An in-memory computing unit and array based on DICE structure SRAM

Abstract

The present invention relates to the field of in-memory computing technology, and more particularly to an in-memory computing unit and array based on a DICE structure SRAM. The in-memory computing unit includes a DICE structure storage unit; a read access circuit C composed of MOS transistors M4, M5, and M6; and a read access circuit D composed of MOS transistors M7, M8, and M9. The in-memory computing array includes a row of standard storage cells based on the DICE structure, n rows and m columns of the in-memory computing units, and m multiplexed logic operation units; the logic operation unit also includes four MOS transistors MM1, MM2, MM3, and MM4. The in-memory computing unit of the present invention can increase the stability of the unit, reduce the impact of read and write interference, and thus improve the stability of the calculation. In addition, by controlling and implementing two different logical operations, the richness of the calculation function is increased.

Description

Technical Field

[0001] The present invention relates to the field of in-memory computing technology, and in particular to an in-memory computing unit and array based on a DICE structure SRAM. Background Art

[0002] The rapid development of neural networks necessitates computing large amounts of data. If memory transfer speeds cannot keep up with CPU performance, computing power will be limited, creating a "memory wall." Furthermore, reading and writing in-memory data consumes hundreds of times more energy than computing on that data, creating a "power wall." To address the high latency and energy consumption inherent in the von Neumann architecture, the concept of integrating storage units with logic operations—in-memory computing—was proposed. Therefore, a highly stable in-memory computing unit or device is needed to improve computing efficiency. Summary of the Invention

[0003] The object of the present invention is to provide an in-memory computing unit and array based on a DICE structure SRAM. The in-memory computing array implements basic logical operations on data by introducing independent read access circuits and logic operation circuits into the memory based on the DICE structure. This avoids the shortcomings of the von Neumann architecture, which require data to be read from the memory through a bus and then sent to the CPU for calculation through the bus. This breaks the "memory wall" and "power consumption wall", effectively reduces the speed of data transfer and calculation, and at the same time reduces the power consumption of its circuit.

[0004] To solve the above technical problems, the present invention provides the following technical solution: an in-memory computing unit based on a DICE structure SRAM, comprising:

[0005] DICE structure storage unit;

[0006] A read access circuit C is composed of a MOS transistor M4, a MOS transistor M5, and a MOS transistor M6. MOS transistor M6 serves as the access transistor of the read access circuit C and enables data output of the DICE structure storage unit via a word line RWL_C connected to its gate. Its drain is connected to the sources of MOS transistors M4 and M5. The gates of MOS transistors M4 and M5 are connected to the QA and QB nodes of the DICE structure storage unit, and their drains serve as readout signal lines BLC and BLCB, respectively, output by the in-memory computing unit.

[0007] A read access circuit D is composed of MOS transistors M7, M8, and M9. MOS transistor M9 serves as the access transistor for the read access circuit D and enables data output of the DICE structure storage unit via a word line RWL_D connected to the gate. Its drain is connected to the sources of MOS transistors M7 and M8. The gates of MOS transistors M7 and M8 are connected to the QC and QD nodes of the DICE structure storage unit, and their drains serve as readout signal lines BLD and BLDB, respectively, output by the in-memory computing unit.

[0008] Preferably, the in-memory computing unit further includes three word lines WL, RWL_C and RWL_D; normal SRAM read and write operations are implemented through the word lines WL and bit lines BL and BLB, and reading and computing operations of in-memory computing weights are implemented through the word lines RWL_C / RWL_D.

[0009] The present invention also provides the following technical solution: an in-memory computing array based on a DICE structure SRAM, comprising: a row of standard storage cells based on the DICE structure, n rows and m columns of in-memory computing units as described above, and m multiplexed logic operation units; wherein the read and write signal lines BL and BLB of the in-memory computing units in each column are interconnected; the read signal lines BLC and BLCB of the read access circuit C in each column are interconnected; the read signal lines BLD and BLDB of the read access circuit D in each row are interconnected; the word lines WL of the in-memory computing units in each row are interconnected; the word lines RWL_C of the read access circuit C in each row are interconnected; and the word lines RWL_D of the read access circuit D in each row are interconnected.

[0010] Preferably, the logic operation unit includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a first output terminal and a second output terminal; the first input terminal is connected to the bit line BLB of the standard storage unit of the DICE structure in the column where the logic operation unit is located, the second input terminal is connected to the bit line BL of the standard storage unit of the DICE structure in the column where the logic operation unit is located, the third input terminal is connected to the read signal line BLC of the read access circuit C of the in-memory computing unit in the column where the logic operation unit is located, the fourth input terminal is connected to the read signal line BLCB of the read access circuit C of the in-memory computing unit in the column where the logic operation unit is located, the fifth input terminal is connected to the read signal line BLD of the read access circuit D in the column where the logic operation unit is located, the first output terminal outputs the result of the logical exclusive OR operation, and the second output terminal outputs the result of the logical OR operation.

[0011] Preferably, the logic operation unit further includes four MOS transistors MM1, MM2, MM3, and MM4, wherein the gate of the MOS transistor MM1 is connected to the word line BLB of the standard memory cell with the DICE structure (as the first input terminal), the source is connected to the read signal line BLC of the read access circuit C (as the third input terminal), and the drain is connected to the drain of the MOS transistor MM2 as the output terminal of the logical exclusive OR operation result; wherein the gate of the MOS transistor MM2 is connected to the bit line BL of the standard memory cell with the DICE structure (as the second input terminal), and the source is connected to the bit line BLCB of the read access circuit C (as the fourth input terminal); wherein the gate of the MOS transistor MM3 is connected to the bit line BLB of the standard memory cell with the DICE structure (as the first input terminal), the source is connected to the read signal line BLD of the read access circuit D (as the fifth input terminal), and the drain is connected to the drain of the MOS transistor MM4 as the output terminal of the logical exclusive OR operation result; wherein the gate and source of the MOS transistor MM4 are interconnected with the bit line BLB of the standard memory cell with the DICE structure.

[0012] Preferably, when the word line RWL_C of the read access circuit C is enabled, the in-memory computing array can realize the logical exclusive OR operation of the row data (the bit) and the pre-stored operation data; when the word line RWL_D of the read access circuit D is enabled, the in-memory computing array can realize the logical exclusive OR operation of the row data (the bit) and the pre-stored operation data; when the word lines of the read access circuit C and the read access circuit D are enabled at the same time, the in-memory computing array can realize the logical exclusive OR and OR operation of the row data (the bit) and the pre-stored operation data.

[0013] Preferably, when performing a logical exclusive-OR operation, the word line RWL_C of the read access circuit C is enabled, the read signal line BLC of the read access circuit C is connected to the third input terminal of the logic operation unit, and the read signal line BLC is connected to the fourth input terminal of the logic operation unit, providing data C for logical operation with pre-stored data. When performing a logical exclusive-OR operation, the word line RWL_D of the read access circuit D is enabled, the read signal line BLD of the read access circuit D is connected to the fifth input terminal of the logic operation unit, providing data D for logical operation with pre-stored data. The logic operation unit uses four MOS transistors, which can implement two logical operations, greatly reducing the complexity of the logical operation part.

[0014] The present invention has the following beneficial effects:

[0015] The present invention improves the reliability of the storage unit by adopting an in-memory computing unit based on the DICE structure SRAM, which can increase the stability of the unit, reduce the impact of read and write interference, and thus improve the stability of the calculation. At the same time, two different logical operations are realized through two read access circuits, which increases the richness of the calculation function, allowing data to be calculated inside the memory, and can significantly reduce the data handling, computing volume and power consumption of applications such as machine learning. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. 4 is a circuit architecture diagram of the overall in-memory computing array of the present invention.

[0017] Figure 2 This is a circuit structure diagram of the in-memory computing unit proposed in the present invention.

[0018] Figure 3 This is a circuit structure diagram of the logic operation unit proposed in the present invention. DETAILED DESCRIPTION

[0019] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0020] like Figure 1-3As shown, an in-memory computing unit and array solution based on a DICE structure SRAM, the in-memory computing array includes an in-memory computing unit based on a DICE structure, a standard storage unit of a DICE structure (a standard DICE structure SRAM unit), and a logic operation unit. When the in-memory computing array based on a DICE structure SRAM is used for a standard SRAM, the two read access circuits C and read access circuit D of the in-memory computing unit are disabled, and the read and write data are normally read or written through the bit lines BL and BLB. The in-memory computing array based on a DICE structure SRAM is equivalent to a normal DICE structure SRAM; when the in-memory computing array based on a DICE structure SRAM is used for in-memory computing, the array is first treated as a standard SRAM, and the word line WL is enabled through an external address encoding module, and the data is stored in the in-memory computing unit of the DICE structure in-memory computing array. When it is necessary to perform During in-memory calculation, the word line WL of the standard storage cell row based on the DICE structure is enabled, and the pre-calculated data is written into the standard storage cell based on the DICE structure in the row through the bit lines BL and BLB. When the address encoding module of the peripheral in-memory calculation receives the address, the address is encoded, and the encoding logic operation is enabled as needed to enable the word line RWL_C of the read access circuit C of the n-th row in-memory calculation unit or the word line RWL_D of the read access circuit D of the n-th row in-memory calculation unit. At the same time, it is necessary to enable the word line WL of the standard storage cell row based on the DICE structure in the array to read out the pre-stored data and participate in the logic operation.

[0021] When a logical exclusive-OR operation is to be implemented, the word line WL of the standard memory cell row based on the DICE structure is first enabled before the logical operation, and the pre-operation data is written into the standard DICE structure SRAM cell of the row through the bit lines BL and BLB. Then, according to the address decoding, the read access circuit C RWL_C of the in-memory computing unit in the nth row is enabled, so that the data of the in-memory computing unit in the nth row is output from the readout signal lines BLC and BLCB as the input signal of the logical operation module, where BLC serves as the third input terminal signal and BLCB serves as the fourth input signal; at the same time, the word line WL of the standard memory cell row based on the DICE structure in the array is enabled, so that the BL and BLB of its standard SRAM cell serve as the input signals of the logical operation module, where BLB serves as the input signal of the first input terminal and BL serves as the input signal of the second input terminal. Finally, the first output terminal of the logical operation module will obtain the logical exclusive-OR operation result of the data in the nth row and the pre-stored data.

[0022] When a logical OR operation is to be implemented, the word line WL of the standard storage cell row based on the DICE structure is first enabled before the logical operation, and the pre-operation data is written into the standard DICE structure SRAM cell of the row through the bit lines BL and BLB. Then, according to the address decoding, the read access circuit D RWL_D of the calculation unit in the n-th row is enabled, so that the data of the calculation unit in the n-th row is output from the read signal lines BLD and BLDB as the input signal of the logical operation module, where BLD serves as the fifth input terminal signal; at the same time, the word line WL of the standard storage cell row based on the DICE structure in the array is enabled, so that the BL and BLB of its standard SRAM cell serve as the input signals of the logical operation module, where BLB serves as the input signal of the first input terminal and BL serves as the input signal of the second input terminal. Finally, the second output terminal of the logical operation module will obtain the logical OR operation result of the data in the n-th row and the pre-stored data.

[0023] When the logical OR and XOR operations are to be implemented simultaneously, the word line WL of the standard storage cell row based on the DICE structure is first enabled before the logical operation, and the pre-operation data is written into the standard DICE structure SRAM cell of the row through the bit lines BL and BLB. Then, the RWL_D of the read access circuit D of the calculation unit in the n-th row of memory is enabled according to the address decoding, so that the data of the calculation unit in the n-th row of memory is output from the read signal lines BLD and BLDB as the input signal of the logical operation module, where BLD serves as the fifth input terminal signal; at the same time, the RWL_C of the read access circuit C of the calculation unit in the h-th row of memory is enabled according to the address decoding, so that the data of the calculation unit in the h ... The data of the calculation unit is output from the readout signal lines BLC and BLCB as the input signal of the logic operation module, wherein BLC is used as the third input terminal signal and BLCB is used as the fourth input terminal signal; at the same time, the word line WL of the standard storage cell row based on the DICE structure in the array makes the BL and BLB of its standard SRAM cell serve as the input signals of the logic operation module, wherein BLB is used as the input signal of the first input terminal and BL is used as the input signal of the second input terminal. Finally, the first output terminal of the logic operation module outputs the logical exclusive OR operation result of the h-th row data and the pre-stored data, and the second output terminal outputs the logical OR operation result of the n-th row data and the pre-stored data.

[0024] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. An in-memory computing unit based on a DICE structure SRAM, characterized in that: include: DICE structure storage unit; Read access circuit C, composed of MOS transistor M4, MOS transistor M5 and MOS transistor M6; The MOS transistor M6 serves as the access transistor of the read access circuit C, and enables the data output of the DICE structure storage unit by connecting to the word line RWL_C at the gate. The drain of the MOS transistor M6 is connected to the source of the MOS transistor M4 and the MOS transistor M5. The gates of the MOS transistor M4 and the MOS transistor M5 are connected to the QA and QB nodes of the DICE structure storage unit, and the drains of the MOS transistor M6 serve as the readout signal lines BLC and BLCB output by the in-memory computing unit, respectively. A read access circuit D is composed of MOS transistors M7, M8, and M9. MOS transistor M9 serves as the access transistor for the read access circuit D and enables data output of the DICE structure storage unit via a word line RWL_D connected to the gate. Its drain is connected to the sources of MOS transistors M7 and M8. The gates of MOS transistors M7 and M8 are connected to the QC and QD nodes of the DICE structure storage unit, and their drains serve as readout signal lines BLD and BLDB, respectively, output by the in-memory computing unit.

2. The in-memory computing unit based on DICE structure SRAM according to claim 1, characterized in that: The in-memory calculation unit also includes three word lines WL, RWL_C and RWL_D; normal SRAM read and write operations are implemented through the word lines WL and bit lines BL and BLB, and the reading and calculation operations of the in-memory calculation weights are implemented through the word lines RWL_C / RWL_D.

3. An in-memory computing array based on DICE structure SRAM, characterized in that: include: A row of standard storage cells based on a DICE structure, n rows and m columns of in-memory computing units according to any one of claims 1 to 2, and m multiplexed logic operation units; wherein the bit lines BL and BLB of the in-memory computing units in each column are interconnected; the read signal lines BLC and BLCB of the read access circuit C in each column are interconnected; the read signal lines BLD and BLDB of the read access circuit D in each row are interconnected; the word lines WL of the in-memory computing units in each row are interconnected; the read word lines RWL_C of the read access circuit C in each row are interconnected; and the read word lines RWL_D of the read access circuit D in each row are interconnected.

4. The in-memory computing array based on DICE structure SRAM according to claim 3, characterized in that: The logic operation unit includes a first input terminal, a second input terminal, a third input terminal, a fourth input terminal, a fifth input terminal, a first output terminal and a second output terminal; the first input terminal is connected to the bit line BLB of the standard storage unit of the DICE structure in the column where the logic operation unit is located, the second input terminal is connected to the bit line BL of the standard storage unit of the DICE structure in the column where the logic operation unit is located, the third input terminal is connected to the read signal line BLC of the read access circuit C of the in-memory computing unit in the column where the logic operation unit is located, the fourth input terminal is connected to the read signal line BLCB of the read access circuit C of the in-memory computing unit in the column where the logic operation unit is located, and the fifth input terminal is connected to the read signal line BLD of the read access circuit D in the column where the logic operation unit is located, the first output terminal outputs the result of a logical exclusive OR operation, and the second output terminal outputs the result of a logical OR operation.

5. The in-memory computing array based on DICE structure SRAM according to claim 4, characterized in that: The logic operation unit also includes four MOS transistors MM1, MM2, MM3, and MM4, wherein the gate of the MOS transistor MM1 is connected to the word line BLB of the standard storage cell with the DICE structure, the source is connected to the read signal line BLC of the read access circuit C, and the drain is connected to the drain of the MOS transistor MM2 as the output end of the logical exclusive OR operation result; the gate of the MOS transistor MM2 is connected to the bit line BL of the standard storage cell with the DICE structure, and the source is connected to the read signal line BLCB of the read access circuit C; the gate of the MOS transistor MM3 is connected to the bit line BLB of the standard storage cell with the DICE structure, the source is connected to the read signal line BLD of the read access circuit D, and the drain is connected to the drain of the MOS transistor MM4 as the output end of the logical OR operation result; the gate and source of the MOS transistor MM4 are interconnected with the bit line BLB of the standard storage cell with the DICE structure.

6. The in-memory computing array based on DICE structure SRAM according to any one of claims 3 to 5, characterized in that: When the word line RWL_C of the read access circuit C is enabled, the in-memory calculation array can realize the logical exclusive OR operation of the row data and the pre-stored calculation data; when the word line RWL_D of the read access circuit D is enabled, the in-memory calculation array can realize the logical OR operation of the row data and the pre-stored calculation data; when the word lines of the read access circuit C and the read access circuit D are enabled at the same time, the in-memory calculation array can realize the logical exclusive OR and OR operation of the row data and the pre-stored calculation data.

7. The in-memory computing array based on DICE structure SRAM according to claim 6, characterized in that: When performing a logical exclusive OR operation, the word line RWL_C of the read access circuit C is enabled, the read signal line BLC of the read access circuit C is connected to the third input terminal of the logical operation unit, and the read signal line BLC is connected to the fourth input terminal of the logical operation unit, providing data C for logical operation with pre-stored data; when performing a logical OR operation, the word line RWL_D of the read access circuit D is enabled, and the read signal line BLD of the read access circuit D is connected to the fifth input terminal of the logical operation unit, providing data D for logical operation with pre-stored data.

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