Driving method for a display panel and display device

Abstract

Embodiments of the present disclosure disclose a driving method and a display device for a display panel. The driving method of the display panel includes: obtaining display data of a current display frame; according to the display data, inputting a data voltage to a data line so that sub-pixels electrically connected to the data line are charged with corresponding data voltages; wherein, the data voltages on the input data line are divided into multiple voltage groups, each voltage group includes at least two adjacent data voltages, and the data voltages in the same voltage group have the same polarity; the data voltages in two adjacent voltage groups input to the same data line have different polarities; and the voltage groups corresponding to adjacent two data lines have different polarities.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a driving method for a display panel and a display device. Background Art

[0002] In a display such as a Liquid Crystal Display (LCD), it generally includes a plurality of pixels. Each pixel may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. By controlling the display data corresponding to each sub-pixel, the display brightness of each sub-pixel is controlled, so as to mix the required displayed colors to display a color image. Summary of the Invention

[0003] The driving method for a display panel provided by an embodiment of the present disclosure includes:

[0004] Obtaining the display data of the current display frame;

[0005] According to the display data, inputting a data voltage to a data line, so that the sub-pixels electrically connected to the data line are charged with corresponding data voltages; wherein, the data voltages input to the data line are divided into a plurality of voltage groups, each voltage group includes at least two adjacent data voltages, and the data voltages in the same voltage group have the same polarity; the data voltages in two adjacent voltage groups input to the same data line have different polarities; the polarities of the voltage groups corresponding to two adjacent data lines are different.

[0006] In some examples, the driving method further includes:

[0007] Inputting a reference voltage before inputting the data voltage to the data line.

[0008] In some examples, the driving method further includes:

[0009] Inputting the reference voltage before inputting the first data voltage of the voltage group to the data line.

[0010] In some examples, the data voltage is formed by dividing the voltage of a first power supply and a second power supply; wherein, the voltage of the first power supply is less than the voltage of the second power supply;

[0011] The reference voltage is the voltage between the first power supply voltage and the second power supply voltage.

[0012] In some examples, the reference voltage is the midpoint voltage between the first power supply voltage and the second power supply voltage.

[0013] In some examples, the driving method further includes:

[0014] When inputting the first data voltage of the voltage group to the data line, a compensation voltage is superimposed on the data line;

[0015] Wherein, when the first data voltage corresponds to a positive polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is greater than the first data voltage;

[0016] When the first data voltage corresponds to a negative polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is less than the first data voltage.

[0017] In some examples, among different voltage groups, the compensation voltages superimposed on the first data voltages corresponding to the same polarity are the same.

[0018] In some examples, the absolute values of the compensation voltages corresponding to each voltage group are the same.

[0019] In some examples, the holding duration of the data voltage loaded on the data line and the holding duration of the sub-pixel corresponding to the data voltage being turned on have a non-overlapping duration;

[0020] In the same voltage group, the first data voltage loaded on the data line has a first non-overlapping duration, and the remaining data voltages loaded on the data line have a second non-overlapping duration; wherein, the first non-overlapping duration is less than the second non-overlapping duration.

[0021] In some examples, the first non-overlapping duration of the first data voltage corresponding to the positive polarity is less than the first non-overlapping duration of the first data voltage corresponding to the negative polarity.

[0022] The display device provided by the embodiments of the present disclosure includes:

[0023] A timing controller, configured to: obtain and output the display data of the current display frame; and generate and output a polarity inversion signal based on the rule that the data voltages input to the data line are divided into multiple voltage groups, each voltage group includes at least two adjacent data voltages, the data voltages in the same voltage group have the same polarity, the data voltages in adjacent two voltage groups input to the same data line have different polarities, and the polarities of the voltage groups corresponding to adjacent two data lines are different;

[0024] A display panel, including a source driver circuit; wherein, the source driver circuit is configured to receive the display data and the polarity inversion signal; and input a data voltage to the data line according to the display data and the polarity inversion signal, so that the sub-pixels electrically connected to the data line are charged with the corresponding data voltage.

[0025] In some examples, the source driver circuit includes: a data processing circuit and a plurality of voltage output circuits; wherein, each of the data lines is electrically connected to the voltage output circuit in a one-to-one correspondence;

[0026] The data processing circuit is configured to receive the display data and output corresponding display data to each of the voltage output circuits according to the display data;

[0027] The voltage output circuit is configured to receive the polarity inversion signal and the display data output by the data processing circuit, and input data voltages to the electrically connected data lines in sequence according to the polarity inversion signal and the display data output by the data processing circuit, so that the sub-pixels electrically connected to the data lines are charged with corresponding data voltages.

[0028] In some examples, the source driver circuit further includes: a first charge sharing circuit;

[0029] The first charge sharing circuit is configured to receive a first reference control signal and input a reference voltage before inputting each of the data voltages to the electrically connected data line under the control of the first reference control signal.

[0030] In some examples, the reference voltage is triggered by a first setting edge of the first reference control signal and input to the corresponding data line;

[0031] The data voltage is triggered by a second setting edge of the first reference control signal and input to the corresponding data line;

[0032] Wherein, the first setting edge is a rising edge and the second setting edge is a falling edge;

[0033] Or, the first setting edge is a falling edge and the second setting edge is a rising edge.

[0034] In some examples, the first charge sharing circuit includes a first switching transistor;

[0035] The gate of the first switching transistor is configured to receive the first reference control signal, the first pole of the first switching transistor is configured to receive the reference voltage, and the second pole of the first switching transistor is electrically connected to the data line.

[0036] In some examples, the source driver circuit further includes: a second charge sharing circuit;

[0037] The second charge sharing circuit is configured to receive a second reference control signal and input the reference voltage before inputting the first data voltage of each voltage group to each of the data lines under the control of the second reference control signal.

[0038] In some examples, the second reference control signal is the polarity inversion signal.

[0039] In some examples, the second charge sharing circuit includes a second switching transistor;

[0040] The gate of the second switching transistor is configured to receive the second reference control signal, the first pole of the second switching transistor is configured to receive the reference voltage, and the second pole of the second switching transistor is electrically connected to the data line.

[0041] In some examples, the voltage output circuit includes a first output circuit and a second output circuit; wherein, each of the data lines is electrically connected to the first output circuit and the second output circuit in a one-to-one correspondence;

[0042] The first output circuit is configured to input a data voltage corresponding to a positive polarity to the electrically connected data line according to the polarity inversion signal and the display data;

[0043] The second output circuit is configured to input a data voltage corresponding to a negative polarity to the electrically connected data line according to the polarity inversion signal and the display data.

[0044] In some examples, the first output circuit includes: a first digital-to-analog conversion circuit and a first amplifier; wherein, there is a midpoint voltage terminal between the first power supply voltage and the second power supply voltage, and the first digital-to-analog conversion circuit is electrically connected between the second power supply voltage and the midpoint voltage terminal;

[0045] The first digital-to-analog conversion circuit is configured to receive the polarity inversion signal and the display data, and according to the polarity inversion signal, perform digital-to-analog conversion on the display data to generate and output a data voltage corresponding to a positive polarity;

[0046] The first amplifier is configured to receive the data voltage output by the first digital-to-analog conversion circuit, and after amplifying the received data voltage, input it to the electrically connected data line.

[0047] In some examples, the second output circuit includes: a second digital-to-analog conversion circuit and a second amplifier; wherein, there is a midpoint voltage terminal between the first power supply voltage and the second power supply voltage, and the second digital-to-analog conversion circuit is electrically connected between the first power supply voltage and the midpoint voltage terminal;

[0048] The second digital-to-analog conversion circuit is configured to receive the polarity inversion signal and the display data, and according to the polarity inversion signal, perform digital-to-analog conversion on the display data to generate and output a data voltage corresponding to a negative polarity;

[0049] The second amplifier is configured to receive the data voltage output by the second digital-to-analog conversion circuit, and after amplifying the received data voltage, input it to the electrically connected data line. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 Some structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0051] Figure 2 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0052] Figure 3 Some other structural schematic diagrams of the display panel in the embodiments of the present disclosure;

[0053] Figure 4 Some signal timing diagrams in the embodiments of the present disclosure;

[0054] Figure 5 Some flowcharts of the driving method of the display panel in the embodiments of the present disclosure;

[0055] Figure 6 Some schematic diagrams of data voltages in the embodiments of the present disclosure;

[0056] Figure 7 Some other schematic diagrams of data voltages in the embodiments of the present disclosure;

[0057] Figure 8 Some other signal timing diagrams in the embodiments of the present disclosure;

[0058] Figure 9 Some structural schematic diagrams of the source driver circuit in the embodiments of the present disclosure;

[0059] Figure 10 Some other signal timing diagrams in the embodiments of the present disclosure;

[0060] Figure 11a Some other signal timing diagrams in the embodiments of the present disclosure;

[0061] Figure 11b Some other signal timing diagrams in the embodiments of the present disclosure;

[0062] Figure 12 Some other signal timing diagrams in the embodiments of the present disclosure;

[0063] Figure 13 Some other structural schematic diagrams of the source driver circuit in the embodiments of the present disclosure;

[0064] Figure 14 Some other signal timing diagrams in the embodiments of the present disclosure;

[0065] Figure 15 Some other structural schematic diagrams of the source driver circuit in the embodiments of the present disclosure;

[0066] Figure 16 Some other signal timing diagrams in the embodiments of the present disclosure;

[0067] Figure 17 Some other signal timing diagrams in the embodiments of the present disclosure;

[0068] Figure 18 Some other signal timing diagrams in the embodiments of the present disclosure. Detailed implementation manners

[0069] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. And, without conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0070] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "including" or "comprising" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0071] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual proportions, and the purpose is only to schematically illustrate the content of the present disclosure. Also, the same or similar reference numerals throughout the drawings denote the same or similar elements or elements having the same or similar functions.

[0072] See Figure 1 And Figure 2, the display device may include a display panel 100 and a timing controller 200. Among them, the display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (for example, GA1, GA2, GA3, GA4), a plurality of data lines DA (for example, DA1, DA2, DA3), a gate driving circuit 110, and a source driving circuit 120. The gate driving circuit 110 is respectively coupled to the gate lines GA1, GA2, GA3, GA4, and the source driving circuit 120 is respectively coupled to the data lines DA1, DA2, DA3. Among them, the timing controller 200 may input a control signal to the gate driving circuit 110 through a level shift circuit, so as to drive the gate lines GA1, GA2, GA3, GA4. The timing controller 200 inputs a signal to the source driving circuit 120, so that the source driving circuit 120 inputs a data voltage to the data line, thereby charging the sub-pixel SPX, enabling the sub-pixel SPX to input a corresponding data voltage, and realizing the function of displaying an image. Exemplarily, the source driving circuit 120 may be set to two, and one of the source driving circuits 120 is connected to half of the data lines, and the other source driving circuit 120 is connected to the other half of the data lines. Of course, the source driving circuit 120 may also be set to three, four, or more, and it can be designed and determined according to the requirements of actual applications, which is not limited herein.

[0073] Exemplarily, each pixel unit includes a plurality of sub-pixels SPX. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed through red, green, and blue to achieve color display. Or, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed through red, green, blue, and white to achieve color display. Of course, in actual applications, the emission color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, which is not limited herein.

[0074] See Figure 2 As shown, each sub-pixel SPX includes a transistor 01 and a pixel electrode 02. Among them, one row of sub-pixels SPX corresponds to one gate line, and one column of sub-pixels SPX corresponds to one data line. The gate of the transistor 01 is electrically connected to the corresponding gate line, the source of the transistor 01 is electrically connected to the corresponding data line, and the drain of the transistor 01 is electrically connected to the pixel electrode 02. It should be noted that the pixel array structure of the present disclosure may also be a double-gate structure, that is, two gate lines are provided between adjacent two rows of pixels. This arrangement can reduce half of the data lines, that is, some of the data lines between adjacent two columns of pixels, and some of the adjacent two columns of pixels do not include data lines. The specific pixel arrangement structure and the arrangement of data lines and scan lines are not limited.

[0075] It should be noted that the display panel in the embodiments of the present disclosure may be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate that are opposed to each other, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate. When displaying an image, since there is a voltage difference between the data voltage applied to the pixel electrode of each sub-pixel SPX and the common electrode voltage applied to the common electrode, this voltage difference can form an electric field, so that the liquid crystal molecules are deflected under the action of this electric field. Since different intensities of the electric field cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixel SPX is different, so that the sub-pixel SPX can achieve different gray-scale brightnesses, and further realize image display.

[0076] In the following, it is assumed that the display panel in the embodiments of the present disclosure is a liquid crystal display panel, and the pixel unit includes a red sub-pixel SPX, a green sub-pixel SPX, and a blue sub-pixel SPX as an example for description. However, readers should know that the colors of the sub-pixels SPX included in the liquid crystal display panel are not limited to this.

[0077] Gray scale generally divides the brightness change area between the darkest and the brightest into several parts for convenient screen brightness control. For example, the displayed image is composed of three colors: red, green, and blue. Each of these colors can show different brightness levels, and different combinations of red, green, and blue with different brightness levels can form different colors. For example, if the gray-scale bit number of the liquid crystal display panel is 6bit, then each of the three colors of red, green, and blue has 64 (i.e., 2 6 ) gray scales, and these 64 gray-scale values are 0 to 63 respectively. If the gray-scale bit number of the liquid crystal display panel is 8bit, then each of the three colors of red, green, and blue has 256 (i.e., 2 8 ) gray scales, and these 256 gray-scale values are 0 to 255 respectively. If the gray-scale bit number of the liquid crystal display panel is 10bit, then each of the three colors of red, green, and blue has 1024 (i.e., 2 10 ) gray scales, and these 1024 gray-scale values are 0 to 1023 respectively. If the gray-scale bit number of the liquid crystal display panel is 12bit, then each of the three colors of red, green, and blue has 4096 (i.e., 2 12 ) gray scales, and these 4096 gray-scale values are 0 to 4093 respectively.

[0078] Exemplarily, taking a sub-pixel SPX as an example, when the data voltage Vda1 input in the pixel electrode of the sub-pixel SPX is greater than the common electrode voltage Vcom, the liquid crystal molecules at the sub-pixel SPX can be made to have a positive polarity, and then the polarity corresponding to the data voltage Vda1 in the sub-pixel SPX is positive. When the data voltage Vda2 input in the pixel electrode of the sub-pixel SPX is less than the common electrode voltage Vcom, the liquid crystal molecules at the sub-pixel SPX can be made to have a negative polarity, and then the polarity corresponding to the data voltage Vda2 in the sub-pixel SPX is negative. For example, the common electrode voltage can be 8.3V. If a data voltage of 8.8V to 16V is input in the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX can be made to have a positive polarity, and then the data voltage of 8.8V to 16V is the data voltage corresponding to the positive polarity. If a data voltage of 0.6V to 7.8V is input in the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX can be made to have a negative polarity, and then the data voltage of 0.6V to 7.8V is the data voltage corresponding to the negative polarity. Exemplarily, taking the 0 to 255 gray levels of 8-bit as an example, when a data voltage of 16V is input in the pixel electrode of the sub-pixel SPX, the sub-pixel SPX can use the data voltage with a positive polarity to achieve the brightness of the maximum gray level value (i.e., 255 gray level value). When a data voltage of 0.6V is input in the pixel electrode of the sub-pixel SPX, the sub-pixel SPX can use the data voltage with a negative polarity to achieve the brightness of the maximum gray level value (i.e., 255 gray level value). It should be noted that there may be a voltage difference between the data voltage of the 0 gray level value and the common electrode voltage. For example, when the common electrode voltage is 8.3V, the data voltage with a positive polarity corresponding to the 0 gray level value can be 8.8V, and the data voltage with a negative polarity corresponding to the 0 gray level value can be 7.8V. Of course, the data voltage of the 0 gray level value and the common electrode voltage can also be the same. In practical applications, it can be determined according to the actual application needs and is not limited here.

[0079] Exemplarily, the data voltage can be formed by dividing the first power supply voltage and the second power supply voltage. Among them, the first power supply voltage VY1 is less than the second power supply voltage VY2. For example, there is a midpoint voltage terminal HAVDD between the first power supply voltage VY1 and the second power supply voltage VY2. The midpoint voltage terminal HAVDD can be an additional voltage signal input through the pin of the chip by an external signal source. And the voltage of the midpoint voltage terminal HAVDD can be 1 / 2*(VY2 - VY1). Or, the voltage of the midpoint voltage terminal HAVDD can also fluctuate within a certain range above and below 1 / 2*(VY2 - VY1), which is not limited here.

[0080] Exemplarily, the data voltage corresponding to the positive polarity can be formed by dividing the voltage of the midpoint voltage terminal HAVDD and the second power supply voltage, and the data voltage corresponding to the negative polarity can be formed by dividing the voltage of the midpoint voltage terminal HAVDD and the first power supply voltage. For example, the data voltage corresponding to the negative polarity that realizes the maximum gray scale value can be the first power supply voltage VY1. For example, the data voltage corresponding to the negative polarity that realizes the maximum gray scale value can also be greater than the first power supply voltage VY1. For example, the data voltage corresponding to the positive polarity that realizes the maximum gray scale value can be the second power supply voltage VY2. For example, the data voltage corresponding to the positive polarity that realizes the maximum gray scale value can also be less than the second power supply voltage VY2. Exemplarily, the first power supply voltage VY1 can be the ground voltage 0V, and the second power supply voltage VY2 can be the high power supply voltage AVDD. The voltage VHAVDD of the midpoint voltage terminal HAVDD can be equal to 1 / 2*AVDD or can fluctuate within a certain range around 1 / 2*AVDD. Also, the data voltage corresponding to the negative polarity of 0.6V to 7.8V can be generated by dividing the voltage between 0V and VHAVDD, and the data voltage corresponding to the positive polarity of 8.8V to 16V can be generated by dividing the voltage between VHAVDD and AVDD. It should be noted that VHAVDD can be the same as Vcom, or there can be a small voltage difference (such as 0.1V, 0.5V) between VHAVDD and Vcom, which is not limited here.

[0081] The following takes the pixel unit including a red sub-pixel, a green sub-pixel, and a blue sub-pixel as an example for illustration. As Figure 3 shown, the red sub-pixel R11, the green sub-pixel G11, and the blue sub-pixel B11 form a pixel unit, and the red sub-pixel R12, the green sub-pixel G12, and the blue sub-pixel B12 form a pixel unit. The red sub-pixel R21, the green sub-pixel G21, and the blue sub-pixel B21 form a pixel unit, and the red sub-pixel R22, the green sub-pixel G22, and the blue sub-pixel B22 form a pixel unit. The red sub-pixel R31, the green sub-pixel G31, and the blue sub-pixel B31 form a pixel unit, and the red sub-pixel R32, the green sub-pixel G32, and the blue sub-pixel B32 form a pixel unit. The red sub-pixel R41, the green sub-pixel G41, and the blue sub-pixel B41 form a pixel unit, and the red sub-pixel R42, the green sub-pixel G42, and the blue sub-pixel B42 form a pixel unit. The red sub-pixel R51, the green sub-pixel G51, and the blue sub-pixel B51 form a pixel unit, and the red sub-pixel R52, the green sub-pixel G52, and the blue sub-pixel B52 form a pixel unit. The red sub-pixel R61, the green sub-pixel G61, and the blue sub-pixel B61 form a pixel unit, and the red sub-pixel R62, the green sub-pixel G62, and the blue sub-pixel B62 form a pixel unit.

[0082] Combined with Figure 3 and Figure 4 As shown, when sub-pixels in regions Q1, Q3, Q4, and Q5 input data voltages of 127 gray levels, and the green sub-pixels in region Q2 input data voltages of 255 gray levels while the remaining sub-pixels input data voltages of 0 gray levels, taking column flipping as an example, the red sub-pixels electrically connected to data line DA1 input data voltages corresponding to the positive polarity, the green sub-pixels electrically connected to data line DA2 input data voltages corresponding to the negative polarity, the blue sub-pixels electrically connected to data line DA3 input data voltages corresponding to the positive polarity, the red sub-pixels electrically connected to data line DA4 input data voltages corresponding to the negative polarity, the green sub-pixels electrically connected to data line DA5 input data voltages corresponding to the positive polarity, and the blue sub-pixels electrically connected to data line DA6 input data voltages corresponding to the negative polarity. The following takes data lines DA2, DA3, DA5, and DA6 and the sub-pixels electrically connected thereto as examples for illustration. In Figure 4 where VDA2 represents the data voltage transmitted on data line DA2, VDA3 represents the data voltage transmitted on data line DA3, VDA5 represents the data voltage transmitted on data line DA5, and VDA6 represents the data voltage transmitted on data line DA6.

[0083] In display frame F01, when GA1 controls the first row of sub-pixels to turn on, the green sub-pixels G11, blue sub-pixels B11, green sub-pixels G12, and blue sub-pixels B12 turn on. The data line DA2 transmits a negative-polarity data voltage Vda11 corresponding to 127 gray levels, so that the green sub-pixel G11 inputs this data voltage Vda11. The data line DA3 transmits a positive-polarity data voltage Vda21 corresponding to 127 gray levels, so that the blue sub-pixel B11 inputs this data voltage Vda21. The data line DA5 transmits a positive-polarity data voltage Vda21 corresponding to 127 gray levels, so that the green sub-pixel G12 inputs this data voltage Vda21. The data line DA6 transmits a negative-polarity data voltage Vda11 corresponding to 127 gray levels, so that the blue sub-pixel B11 inputs this data voltage Vda11.

[0084] When GA2 controls the second row of sub-pixels to turn on, green sub-pixels G21, blue sub-pixels B21, green sub-pixels G22, and blue sub-pixels B22 turn on. A negative data voltage Vda12 corresponding to a 255 gray-scale value is transmitted on data line DA2 to enable green sub-pixel G21 to input this data voltage Vda12. A positive data voltage Vda22 corresponding to a 0 gray-scale value is transmitted on data line DA3 to enable blue sub-pixel B21 to input this data voltage Vda22. A positive data voltage Vda21 corresponding to a 127 gray-scale value is transmitted on data line DA5 to enable green sub-pixel G22 to input this data voltage Vda21. A negative data voltage Vda11 corresponding to a 127 gray-scale value is transmitted on data line DA6 to enable blue sub-pixel B22 to input this data voltage Vda11.

[0085] When GA3 controls the third row of sub-pixels to turn on, green sub-pixels G31, blue sub-pixels B31, green sub-pixels G32, and blue sub-pixels B32 turn on. A negative data voltage Vda12 corresponding to a 255 gray-scale value is transmitted on data line DA2 to enable green sub-pixel G31 to input this data voltage Vda12. A positive data voltage Vda22 corresponding to a 0 gray-scale value is transmitted on data line DA3 to enable blue sub-pixel B31 to input this data voltage Vda22. A positive data voltage Vda21 corresponding to a 127 gray-scale value is transmitted on data line DA5 to enable green sub-pixel G32 to input this data voltage Vda21. A negative data voltage Vda11 corresponding to a 127 gray-scale value is transmitted on data line DA6 to enable blue sub-pixel B32 to input this data voltage Vda11.

[0086] When GA4 controls the fourth row of sub-pixels to turn on, green sub-pixels G41, blue sub-pixels B41, green sub-pixels G42, and blue sub-pixels B42 turn on. A negative data voltage Vda12 corresponding to a 255 gray-scale value is transmitted on data line DA2 to enable green sub-pixel G41 to input this data voltage Vda12. A positive data voltage Vda22 corresponding to a 0 gray-scale value is transmitted on data line DA3 to enable blue sub-pixel B41 to input this data voltage Vda22. A positive data voltage Vda21 corresponding to a 127 gray-scale value is transmitted on data line DA5 to enable green sub-pixel G42 to input this data voltage Vda21. A negative data voltage Vda11 corresponding to a 127 gray-scale value is transmitted on data line DA6 to enable blue sub-pixel B42 to input this data voltage Vda11.

[0087] When GA5 controls the fifth row of sub-pixels to turn on, green sub-pixels G51, blue sub-pixels B51, green sub-pixels G52, and blue sub-pixels B52 turn on. A negative data voltage Vda12 corresponding to a 255 gray-scale value is transmitted on data line DA2 so that the green sub-pixel G51 inputs this data voltage Vda12. A positive data voltage Vda22 corresponding to a 0 gray-scale value is transmitted on data line DA3 so that the blue sub-pixel B51 inputs this data voltage Vda22. A positive data voltage Vda21 corresponding to a 127 gray-scale value is transmitted on data line DA5 so that the green sub-pixel G52 inputs this data voltage Vda21. A negative data voltage Vda11 corresponding to a 127 gray-scale value is transmitted on data line DA6 so that the blue sub-pixel B52 inputs this data voltage Vda11.

[0088] When GA6 controls the sixth row of sub-pixels to turn on, green sub-pixels G61, blue sub-pixels B61, green sub-pixels G62, and blue sub-pixels B62 turn on. A negative data voltage Vda11 corresponding to a 127 gray-scale value is transmitted on data line DA2 so that the green sub-pixel G61 inputs this data voltage Vda11. A positive data voltage Vda21 corresponding to a 127 gray-scale value is transmitted on data line DA3 so that the blue sub-pixel B61 inputs this data voltage Vda21. A positive data voltage Vda21 corresponding to a 127 gray-scale value is transmitted on data line DA5 so that the green sub-pixel G62 inputs this data voltage Vda21. A negative data voltage Vda11 corresponding to a 127 gray-scale value is transmitted on data line DA6 so that the blue sub-pixel B62 inputs this data voltage Vda11.

[0089] Since there is a coupling capacitance between the pixel electrode and its adjacent data line. For example, there is a coupling capacitance Cpd11 between the pixel electrode in the green sub-pixel G11 and data line DA2, and there is a coupling capacitance Cpd12 between the pixel electrode in the green sub-pixel G11 and data line DA3. Combining Figure 4 with the above description, it can be seen that Figure 4VG11 in it represents the actual voltage value on the pixel electrode in the green sub-pixel G11, and VB12 represents the actual voltage value on the pixel electrode in the blue sub-pixel B12. When the data voltage on the data line DA2 jumps from the negative-polarity data voltage Vda11 of 127 gray-scale values to the negative-polarity data voltage Vda12 of 255 gray-scale values, due to the effect of the coupling capacitor Cpd11, the data voltage Vda11 that has been charged on the pixel electrode in the green sub-pixel G11 will be pulled downward, making the voltage after pulling less than Vda11. Moreover, when the data voltage on the data line DA3 jumps from the positive-polarity data voltage Vda21 of 127 gray-scale values to the positive-polarity data voltage Vda22 of 0 gray-scale values, due to the effect of the coupling capacitor Cpd12, the data voltage Vda11 that has been charged on the pixel electrode in the green sub-pixel G11 will also be pulled downward, making the voltage after pulling less than Vda11. Since both of these two pulls on the data voltage on the pixel electrode in the green sub-pixel G11 are downward pulls and their pulling directions are the same and cannot cancel each other out, the voltage on the pixel electrode in the green sub-pixel G11 after being pulled is less than Vda11.

[0090] For example, there is a coupling capacitor Cpd21 between the pixel electrode in the green sub-pixel G12 and the data line DA5, and there is a coupling capacitor Cpd22 between the pixel electrode in the green sub-pixel G12 and the data line DA6. The data voltage on the data line DA5 has always been the positive-polarity data voltage Vda21 of 127 gray-scale values. Although there is a coupling capacitor Cpd21, it will not pull the data voltage Vda11 that has been charged on the pixel electrode in the green sub-pixel G12. Moreover, the data voltage on the data line DA6 has always been the negative-polarity data voltage Vda11 of 127 gray-scale values. Although there is the effect of the coupling capacitor Cpd12, it will not pull the data voltage Vda11 that has been charged on the pixel electrode in the green sub-pixel G12 either. Therefore, the voltage on the pixel electrode in the green sub-pixel G12 can be relatively stable at the data voltage Vda11.

[0091] In summary, the voltage on the pixel electrode in the green sub-pixel G11 in the area Q1 after being pulled is less than Vda11. And the voltage on the pixel electrode in the green sub-pixel G12 in the area Q5 can be relatively stable at the data voltage Vda11. Therefore, the brightness of the green sub-pixel G11 in the area Q1 is different from the brightness of the green sub-pixel G12 in the area Q5, thus causing the problem of color deviation and affecting the display effect.

[0092] The embodiment of the present disclosure provides a driving method for a display panel, as Figure 5 shown, which may include the following steps:

[0093] S100. Obtain the display data of the current display frame. Exemplarily, the display data includes the digital voltage form of the data voltage corresponding to each sub-pixel one by one.

[0094] S200. According to the display data, input data voltages to the data lines so that the sub-pixels electrically connected to the data lines are charged with the corresponding data voltages. Exemplarily, according to the display data, input data voltages to each data line so that the sub-pixels electrically connected to each data line are charged with the corresponding data voltages. For one data line, input data voltages to the data line in sequence so that the sub-pixels electrically connected to the data line can input the corresponding data voltages.

[0095] In the embodiments of the present disclosure, the data voltages on the input data lines are divided into multiple voltage groups, each voltage group includes at least two adjacent data voltages, and the data voltages in the same voltage group have the same polarity; the data voltages in two adjacent voltage groups input to the same data line have different polarities; the voltage groups corresponding to two adjacent data lines have different polarities. Exemplarily, each voltage group may include two adjacent data voltages. Combining Figure 3 with Figure 6 As shown, taking data lines DA2, DA3, DA5, and DA6 as examples, using '+' to represent the positive polarity and '-' to represent the negative polarity, the data voltages VR11-1 corresponding to the red sub-pixel R11, the data voltage VR21-1 corresponding to the red sub-pixel R21, the data voltage VR31-1 corresponding to the red sub-pixel R31, the data voltage VR41-1 corresponding to the red sub-pixel R41, the data voltage VR51-1 corresponding to the red sub-pixel R51, and the data voltage VR61-1 corresponding to the red sub-pixel R61 are sequentially transmitted on the data line DA1. Among them, the data voltage VR11-1 and the data voltage VR21-1 can be used as a voltage group and correspond to the negative polarity, the data voltage VR31-1 and the data voltage VR41-1 can be used as a voltage group and correspond to the positive polarity, and the data voltage VR51-1 and the data voltage VR61-1 can be used as a voltage group and correspond to the negative polarity.

[0096] On data line DA2, data voltages VG11-1 corresponding to green sub-pixel G11, VG21-1 corresponding to green sub-pixel G21, VG31-1 corresponding to green sub-pixel G31, VG41-1 corresponding to green sub-pixel G41, VG51-1 corresponding to green sub-pixel G51, and VG61-1 corresponding to green sub-pixel G61 are transmitted in sequence. Among them, data voltage VG11-1 and data voltage VG21-1 can be regarded as a voltage group and correspond to the positive polarity, data voltage VG31-1 and data voltage VG41-1 can be regarded as a voltage group and correspond to the negative polarity, and data voltage VG51-1 and data voltage VG61-1 can be regarded as a voltage group and correspond to the positive polarity.

[0097] On data line DA3, data voltages VB11-1 corresponding to blue sub-pixel B11, VB21-1 corresponding to blue sub-pixel B21, VB31-1 corresponding to blue sub-pixel B31, VB41-1 corresponding to blue sub-pixel B41, VB51-1 corresponding to blue sub-pixel B51, and VB61-1 corresponding to blue sub-pixel B61 are transmitted in sequence. Among them, data voltage VB11-1 and data voltage VB21-1 can be regarded as a voltage group and correspond to the negative polarity, data voltage VB31-1 and data voltage VB41-1 can be regarded as a voltage group and correspond to the positive polarity, and data voltage VB51-1 and data voltage VB61-1 can be regarded as a voltage group and correspond to the negative polarity.

[0098] On data line DA4, data voltages VR12-1 corresponding to red sub-pixel R12, VR22-1 corresponding to red sub-pixel R22, VR32-1 corresponding to red sub-pixel R32, VR42-1 corresponding to red sub-pixel R42, VR52-1 corresponding to red sub-pixel R52, and VR62-1 corresponding to red sub-pixel R62 are transmitted in sequence. Among them, data voltage VR12-1 and data voltage VR22-1 can be regarded as a voltage group and correspond to the positive polarity, data voltage VR32-1 and data voltage VR42-1 can be regarded as a voltage group and correspond to the negative polarity, and data voltage VR52-1 and data voltage VR62-1 can be regarded as a voltage group and correspond to the positive polarity.

[0099] On the data line DA5, the data voltages VG12-1 corresponding to the green sub-pixel G12, VG22-1 corresponding to the green sub-pixel G22, VG32-1 corresponding to the green sub-pixel G32, VG42-1 corresponding to the green sub-pixel G42, VG52-1 corresponding to the green sub-pixel G52, and VG62-1 corresponding to the green sub-pixel G62 are transmitted in sequence. Among them, the data voltage VG12-1 and the data voltage VG22-1 can be used as a voltage group and correspond to the negative polarity, the data voltage VG32-1 and the data voltage VG42-1 can be used as a voltage group and correspond to the positive polarity, and the data voltage VG52-1 and the data voltage VG62-1 can be used as a voltage group and correspond to the negative polarity.

[0100] On the data line DA6, the data voltages VB12-1 corresponding to the blue sub-pixel B12, VB22-1 corresponding to the blue sub-pixel B22, VB32-1 corresponding to the blue sub-pixel B32, VB42-1 corresponding to the blue sub-pixel B42, VB52-1 corresponding to the blue sub-pixel B52, and VB62-1 corresponding to the blue sub-pixel B62 are transmitted in sequence. Among them, the data voltage VB12-1 and the data voltage VB22-1 can be used as a voltage group and correspond to the positive polarity, the data voltage VB32-1 and the data voltage VB42-1 can be used as a voltage group and correspond to the negative polarity, and the data voltage VB52-1 and the data voltage VB62-1 can be used as a voltage group and correspond to the positive polarity.

[0101] Exemplarily, each voltage group may include three adjacent data voltages. Combining Figure 3 With Figure 7 As shown, taking the data lines DA2, DA3, DA5, and DA6 as examples, using "+" to represent the positive polarity and "-" to represent the negative polarity, on the data line DA1, the data voltages VR11-1 corresponding to the red sub-pixel R11, VR21-1 corresponding to the red sub-pixel R21, VR31-1 corresponding to the red sub-pixel R31, VR41-1 corresponding to the red sub-pixel R41, VR51-1 corresponding to the red sub-pixel R51, and VR61-1 corresponding to the red sub-pixel R61 are transmitted in sequence. Among them, the data voltage VR11-1, the data voltage VR21-1, and the data voltage VR31-1 can be used as a voltage group and correspond to the negative polarity, and the data voltage VR41-1, the data voltage VR51-1, and the data voltage VR61-1 can be used as a voltage group and correspond to the positive polarity.

[0102] On data line DA2, data voltages VG11-1 corresponding to green sub-pixel G11, VG21-1 corresponding to green sub-pixel G21, VG31-1 corresponding to green sub-pixel G31, VG41-1 corresponding to green sub-pixel G41, VG51-1 corresponding to green sub-pixel G51, and VG61-1 corresponding to green sub-pixel G61 are transmitted in sequence. Among them, data voltages VG11-1, VG21-1, and VG31-1 can be regarded as a voltage group and correspond to the positive polarity, and data voltages VG41-1, VG51-1, and VG61-1 can be regarded as a voltage group and correspond to the negative polarity.

[0103] On data line DA3, data voltages VB11-1 corresponding to blue sub-pixel B11, VB21-1 corresponding to blue sub-pixel B21, VB31-1 corresponding to blue sub-pixel B31, VB41-1 corresponding to blue sub-pixel B41, VB51-1 corresponding to blue sub-pixel B51, and VB61-1 corresponding to blue sub-pixel B61 are transmitted in sequence. Among them, data voltages VB11-1, VB21-1, and VB31-1 can be regarded as a voltage group and correspond to the negative polarity, and data voltages VB41-1, VB51-1, and VB61-1 can be regarded as a voltage group and correspond to the positive polarity.

[0104] On data line DA4, data voltages VR12-1 corresponding to red sub-pixel R12, VR22-1 corresponding to red sub-pixel R22, VR32-1 corresponding to red sub-pixel R32, VR42-1 corresponding to red sub-pixel R42, VR52-1 corresponding to red sub-pixel R52, and VR62-1 corresponding to red sub-pixel R62 are transmitted in sequence. Among them, data voltages VR12-1, VR22-1, and VR32-1 can be regarded as a voltage group and correspond to the positive polarity, and data voltages VR42-1, VR52-1, and VR62-1 can be regarded as a voltage group and correspond to the negative polarity.

[0105] On data line DA5, data voltages VG12-1 corresponding to green sub-pixel G12, VG22-1 corresponding to green sub-pixel G22, VG32-1 corresponding to green sub-pixel G32, VG42-1 corresponding to green sub-pixel G42, VG52-1 corresponding to green sub-pixel G52, and VG62-1 corresponding to green sub-pixel G62 are transmitted in sequence. Among them, data voltage VG12-1, data voltage VG22-1, and data voltage VG32-1 can be used as a voltage group and correspond to negative polarity, and data voltage VG42-1, data voltage VG52-1, and data voltage VG62-1 can be used as a voltage group and correspond to positive polarity.

[0106] On data line DA6, data voltages VB12-1 corresponding to blue sub-pixel B12, VB22-1 corresponding to blue sub-pixel B22, VB32-1 corresponding to blue sub-pixel B32, VB42-1 corresponding to blue sub-pixel B42, VB52-1 corresponding to blue sub-pixel B52, and VB62-1 corresponding to blue sub-pixel B62 are transmitted in sequence. Among them, data voltage VB12-1, data voltage VB22-1, and data voltage VB32-1 can be used as a voltage group and correspond to positive polarity, and data voltage VB42-1, data voltage VB52-1, and data voltage VB62-1 can be used as a voltage group and correspond to negative polarity.

[0107] In practical applications, each voltage group can also include four, five or other numbers of adjacent data voltages, which can be determined according to the requirements of practical applications and are not limited herein.

[0108] In the embodiments of the present disclosure, the polarities of the voltage groups corresponding to two adjacent data lines are different, which may refer to the different polarities of the data voltages input to these two data lines simultaneously. For example, the data voltage VR11-1 on the data line DA1, the data voltage VG11-1 on the data line DA2, the data voltage VB11-1 on the data line DA3, the data voltage VR12-1 on the data line DA4, the data voltage VG12-1 on the data line DA5, and the data voltage VB12-1 on the data line DA6 are input simultaneously. Then, the data voltage VR21-1 on the data line DA1, the data voltage VG21-1 on the data line DA2, the data voltage VB21-1 on the data line DA3, the data voltage VR22-1 on the data line DA4, the data voltage VG22-1 on the data line DA5, and the data voltage VB22-1 on the data line DA6 are input simultaneously. Then, the data voltage VR31-1 on the data line DA1, the data voltage VG31-1 on the data line DA2, the data voltage VB31-1 on the data line DA3, the data voltage VR32-1 on the data line DA4, the data voltage VG32-1 on the data line DA5, and the data voltage VB32-1 on the data line DA6 are input simultaneously. Then, the data voltage VR41-1 on the data line DA1, the data voltage VG41-1 on the data line DA2, the data voltage VB41-1 on the data line DA3, the data voltage VR42-1 on the data line DA4, the data voltage VG42-1 on the data line DA5, and the data voltage VB42-1 on the data line DA6 are input simultaneously. Then, the data voltage VR51-1 on the data line DA1, the data voltage VG51-1 on the data line DA2, the data voltage VB51-1 on the data line DA3, the data voltage VR52-1 on the data line DA4, the data voltage VG52-1 on the data line DA5, and the data voltage VB52-1 on the data line DA6 are input simultaneously. Then, the data voltage VR61-1 on the data line DA1, the data voltage VG61-1 on the data line DA2, the data voltage VB61-1 on the data line DA3, the data voltage VR62-1 on the data line DA4, the data voltage VG62-1 on the data line DA5, and the data voltage VB62-1 on the data line DA6 are input simultaneously.

[0109] Exemplarily, in combination with Figure 8As shown, VDA2 represents the data voltage transmitted on data line DA2, VDA3 represents the data voltage transmitted on data line DA3, VDA5 represents the data voltage transmitted on data line DA5, and VDA6 represents the data voltage transmitted on data line DA6. VG11 represents the actual voltage value on the pixel electrode in green sub-pixel G11, and VB12 represents the actual voltage value on the pixel electrode in blue sub-pixel B12. By alternately inputting the negative-polarity voltage groups and positive-polarity voltage groups on data line DA5, and alternately inputting the positive-polarity voltage groups and negative-polarity voltage groups on data line DA6, the data voltage charged into green sub-pixel G12 in region Q5 can be cancelled out between downward pulling and upward pulling, so that the voltage on the pixel electrode can be relatively stable, and further the brightness of green sub-pixel G12 can be relatively stable. Also, by alternately inputting the negative-polarity voltage groups and positive-polarity voltage groups on data line DA2, and alternately inputting the positive-polarity voltage groups and negative-polarity voltage groups on data line DA3, the data voltage charged into green sub-pixel G11 in region Q1 can be alternately changed between downward pulling and upward pulling, so that the brightness of green sub-pixel G11 flashes with alternate complementary colors every time a voltage group passes, which can macroscopically show no color deviation and thus improve the color deviation phenomenon.

[0110] In an embodiment of the present disclosure, the timing controller 200 can acquire the display data of the current display frame F0 and store the display data corresponding to the current display frame in the form of digital voltages. The timing controller 200 can generate a polarity inversion signal POL1 based on the rules that the data voltages on the input data lines are divided into multiple voltage groups, each voltage group includes at least two adjacent data voltages, the data voltages in the same voltage group have the same polarity; the data voltages in two adjacent voltage groups input on the same data line have different polarities; and the voltage groups corresponding to adjacent data lines have different polarities (as Figure 10As shown in). The timing controller 200 sends display data in the form of digital signals and the generated polarity inversion signal POL1 to the source driver circuit 120. The source driver circuit 120 can receive the display data and the polarity inversion signal POL1 sent by the timing controller 200, so that it can input data voltage to the data lines according to the display data, the polarity inversion signal, and the data load signal TP, so that the sub-pixels electrically connected to the data lines are charged with the corresponding data voltage. Exemplarily, the source driver circuit 120 can invert the polarity of the data voltage loaded on the data lines in response to the falling edge of the polarity inversion signal POL1, and load the data voltage on the data lines in response to the falling edge of the data load signal TP. Of course, the source driver circuit 120 can also invert the polarity of the data voltage loaded on the data lines in response to the above-mentioned edge of the polarity inversion signal POL1. The source driver circuit 120 can also load the data voltage on the data lines in response to the rising edge of the data load signal TP. These can be determined according to the requirements of actual applications and are not limited herein.

[0111] In the embodiments of the present disclosure, in combination with Figure 2 with Figure 9 and Figure 10As shown, the source driver circuit 120 may include: a data processing circuit 121 and a plurality of voltage output circuits (such as 122-1, 122-2); wherein, each data line is electrically connected to a voltage output circuit one by one (for example, data line DA1 is electrically connected to voltage output circuit 122-1, and data line DA2 is electrically connected to voltage output circuit 122-2). Moreover, the data processing circuit 121 can receive display data, and according to the display data, output corresponding display data to each voltage output circuit. It can also perform optimization processing on the display data and output the optimized display data to each voltage output circuit. And, the voltage output circuit can receive the polarity inversion signal POL1 and the display data output by the data processing circuit 121, and according to the polarity inversion signal and the display data output by the data processing circuit 121, sequentially input data voltages to the data lines electrically connected thereto, so that the sub-pixels electrically connected to the data lines are filled with corresponding data voltages. For example, the data processing circuit 121 can generate a data loading signal TP according to the display data, and output the data loading signal TP, the polarity inversion signal POL1, and the display data corresponding to the sub-pixels electrically connected to the data line DA1 to the voltage output circuit 122-1. The voltage output circuit 122-1 can control the display data to be loaded on the data line DA1 through the data loading signal TP, and control the polarity inversion of the display data corresponding thereto through the polarity inversion signal POL1. Also, the data processing circuit 121 can generate a data loading signal TP according to the display data, and output the data loading signal TP, the polarity inversion signal POL1, and the display data corresponding to the sub-pixels electrically connected to the data line DA2 to the voltage output circuit 122-2. The voltage output circuit 122-2 can control the display data to be loaded on the data line DA2 through the data loading signal TP, and control the polarity inversion of the display data corresponding thereto through the polarity inversion signal POL1.

[0112] In the embodiments of the present disclosure, in combination with Figure 2 and Figure 9As shown in the figure, the voltage output circuit may include a first output circuit 123 and a second output circuit 124. Each data line is electrically connected to the first output circuit 123 and the second output circuit 124 in a one-to-one correspondence. Moreover, the first output circuit 123 is configured to input a data voltage corresponding to the positive polarity to the electrically connected data line according to the polarity inversion signal and the display data. In addition, the second output circuit 124 is configured to input a data voltage corresponding to the negative polarity to the electrically connected data line according to the polarity inversion signal and the display data. For example, the voltage output circuit 122-1 includes the first output circuit 123 and the second output circuit 124. The first output circuit 123 may input a data voltage corresponding to the positive polarity to the data line DA1 according to the polarity inversion signal POL1 and the display data. Moreover, the second output circuit 124 may input a data voltage corresponding to the negative polarity to the data line DA1 according to the polarity inversion signal POL1 and the display data.

[0113] In the embodiments of the present disclosure, as Figure 9 shown, the first output circuit 123 may include: a first digital-to-analog conversion circuit DAC-P and a second amplifier OP-P. The first digital-to-analog conversion circuit DAC-P is electrically connected between the second power supply voltage and the midpoint voltage HAVDD. Moreover, the first digital-to-analog conversion circuit DAC-P is configured to receive the polarity inversion signal and the display data, perform digital-to-analog conversion on the display data according to the polarity inversion signal, generate a data voltage corresponding to the positive polarity, and output it. In addition, the second amplifier OP-P is configured to receive the data voltage output by the first digital-to-analog conversion circuit DAC-P, perform amplification processing on the received data voltage, and then input it to the electrically connected data line.

[0114] In the embodiments of the present disclosure, as Figure 9 shown, the second output circuit 124 may include: a second digital-to-analog conversion circuit DAC-N and a second amplifier OP-N. The second digital-to-analog conversion circuit DAC-N is electrically connected between the first power supply voltage and the midpoint voltage HAVDD. Moreover, the second digital-to-analog conversion circuit DAC-N is configured to receive the polarity inversion signal and the display data, perform digital-to-analog conversion on the display data according to the polarity inversion signal, generate a data voltage corresponding to the negative polarity, and output it. In addition, the second amplifier OP-N is configured to receive the data voltage output by the second digital-to-analog conversion circuit DAC-N, perform amplification processing on the received data voltage, and then input it to the electrically connected data line.

[0115] Taking the data lines DA1 and DA2 and the sub-pixels electrically connected thereto as an example, in combination with Figure 3 、 Figure 9 and Figure 10The working process of the display panel provided by the embodiments of the present disclosure will be described. ga1 represents the signal loaded on gate line GA1, ga2 represents the signal loaded on gate line GA2, ga3 represents the signal loaded on gate line GA3, ga4 represents the signal loaded on gate line GA4, ga5 represents the signal loaded on gate line GA5, and ga6 represents the signal loaded on gate line GA6. da1 represents the data voltage loaded on data line DA1, and da2 represents the data voltage loaded on data line DA2. Moreover, the high level in signals ga1 to ga6 can be used as a gate turn-on signal to control the conduction of the transistor in the sub-pixel. The gate turn-on signal can be sequentially loaded on gate lines GA1 to GA6.

[0116] In display frame F0, when the signal ga1 on gate line GA1 outputs a high-level gate opening signal, the transistors in red sub-pixel R11 and green sub-pixel G11 are turned on. And in time period T1 corresponding to the high level of signal ga1, data processing circuit 121 outputs the display data corresponding to red sub-pixel R11, data load signal TP, and polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in voltage output circuit 122-1. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to red sub-pixel R11 into an analog voltage data voltage Vr11 through digital-to-analog conversion, control the data voltage Vr11 to be loaded on data line DA1 through data load signal TP, and control the polarity of data voltage Vr11 to be negative through polarity inversion signal POL1. After the data voltage Vr11 is amplified by the second amplifier OP-P, the negative-polarity data voltage Vr11 corresponding to the display data is loaded on data line DA1 to enable red sub-pixel R11 to input data voltage Vr11. Also, data processing circuit 121 outputs the display data corresponding to green sub-pixel G11, data load signal TP, and polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in voltage output circuit 122-2. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to green sub-pixel G11 into an analog voltage data voltage Vg11 through digital-to-analog conversion, control the data voltage Vg11 to be loaded on data line DA2 through data load signal TP, and control the polarity of data voltage Vg11 to be positive through polarity inversion signal POL1. After the data voltage Vg11 is amplified by the second amplifier OP-P, the positive-polarity data voltage Vg11 corresponding to the display data is loaded on data line DA2 to enable green sub-pixel G11 to input data voltage Vg11. And, in time period T1, the signal ga2 on gate line GA2 outputs a high-level gate opening signal, and the transistors in red sub-pixel R21 and green sub-pixel G21 are turned on. The data voltage Vr11 is simultaneously input into red sub-pixel R21 to pre-charge red sub-pixel R21. Also, the data voltage Vg11 is simultaneously input into green sub-pixel G21 to pre-charge green sub-pixel G21. And, in time period T1, the signal ga3 on gate line GA3 outputs a high-level gate opening signal, and the transistors in red sub-pixel R31 and green sub-pixel G31 are turned on. The data voltage Vr11 is simultaneously input into red sub-pixel R31 to pre-charge red sub-pixel R31. Also, the data voltage Vg11 is simultaneously input into green sub-pixel G31 to pre-charge green sub-pixel G31.

[0117] During the time period T2 corresponding to the high level of the signal ga2, the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R21, the data load signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-1. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R21 into an analog voltage data voltage Vr21 through digital-to-analog conversion, control the data voltage Vr21 to be loaded on the data line DA1 through the data load signal TP, and control the polarity of the data voltage Vr21 to be negative through the polarity inversion signal POL1. After the data voltage Vr21 is amplified by the second amplifier OP-P, the negative-polarity data voltage Vr21 corresponding to the display data is loaded on the data line DA1, so that the red sub-pixel R21 is charged with the data voltage Vr21. And, the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G21, the data load signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G21 into an analog voltage data voltage Vg21 through digital-to-analog conversion, control the data voltage Vg21 to be loaded on the data line DA2 through the data load signal TP, and control the polarity of the data voltage Vg21 to be positive through the polarity inversion signal POL1. After the data voltage Vg21 is amplified by the second amplifier OP-P, the positive-polarity data voltage Vg21 corresponding to the display data is loaded on the data line DA2, so that the green sub-pixel G21 is charged with the data voltage Vg21. And, during the time period T2, the gate line GA3 outputs a gate opening signal with a high level, and the transistors in the red sub-pixel R31 and the green sub-pixel G31 are turned on. The data voltage Vr21 is simultaneously input into the red sub-pixel R31 to pre-charge the red sub-pixel R31. And, the data voltage Vg21 is simultaneously input into the green sub-pixel G31 to pre-charge the green sub-pixel G31. And, during the time period T2, the gate line GA4 outputs a gate opening signal with a high level, and the transistors in the red sub-pixel R41 and the green sub-pixel G41 are turned on. The data voltage Vr21 is simultaneously input into the red sub-pixel R41 to pre-charge the red sub-pixel R41. And, the data voltage Vg21 is simultaneously input into the green sub-pixel G41 to pre-charge the green sub-pixel G41.

[0118] In the time period T3 corresponding to the high level of the signal ga3, the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R31, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-1. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R31 into an analog voltage data voltage Vr31 through digital-to-analog conversion, control the data voltage Vr31 to be loaded on the data line DA1 through the data loading signal TP, and control the polarity of the data voltage Vr31 to be positive through the polarity inversion signal POL1. After the data voltage Vr31 is amplified by the second amplifier OP-P, the positive-polarity data voltage Vr31 corresponding to the display data is loaded on the data line DA1, so that the red sub-pixel R31 is charged with the data voltage Vr31. And, the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G31, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G31 into an analog voltage data voltage Vg31 through digital-to-analog conversion, control the data voltage Vg31 to be loaded on the data line DA2 through the data loading signal TP, and control the polarity of the data voltage Vg31 to be negative through the polarity inversion signal POL1. After the data voltage Vg31 is amplified by the second amplifier OP-P, the negative-polarity data voltage Vg31 corresponding to the display data is loaded on the data line DA2, so that the green sub-pixel G31 is charged with the data voltage Vg31. And, in the time period T3, the gate line GA4 outputs a gate opening signal with a high level, and the transistors in the red sub-pixel R41 and the green sub-pixel G41 are turned on. The data voltage Vr31 is simultaneously input into the red sub-pixel R41 to pre-charge the red sub-pixel R41. And, the data voltage Vg31 is simultaneously input into the green sub-pixel G41 to pre-charge the green sub-pixel G41. And, in the time period T3, the gate line GA5 outputs a gate opening signal with a high level, and the transistors in the red sub-pixel R51 and the green sub-pixel G51 are turned on. The data voltage Vr31 is simultaneously input into the red sub-pixel R51 to pre-charge the red sub-pixel R51. And, the data voltage Vg31 is simultaneously input into the green sub-pixel G51 to pre-charge the green sub-pixel G51.

[0119] During the T4 time period corresponding to the high level of signal ga4, the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R41, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-1. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R41 into an analog voltage data voltage Vr41 through digital-to-analog conversion, control the data voltage Vr41 to be loaded on the data line DA1 through the data loading signal TP, and control the polarity of the data voltage Vr41 to be positive through the polarity inversion signal POL1. After the data voltage Vr41 is amplified by the second amplifier OP-P, the positive-polarity data voltage Vr41 corresponding to the display data is loaded on the data line DA1, so that the red sub-pixel R41 is charged with the data voltage Vr41. And, the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G41, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G41 into an analog voltage data voltage Vg41 through digital-to-analog conversion, control the data voltage Vg41 to be loaded on the data line DA2 through the data loading signal TP, and control the polarity of the data voltage Vg41 to be negative through the polarity inversion signal POL1. After the data voltage Vg41 is amplified by the second amplifier OP-P, the negative-polarity data voltage Vg41 corresponding to the display data is loaded on the data line DA2, so that the green sub-pixel G41 is charged with the data voltage Vg41. And, during the T4 time period, the signal ga5 on the gate line GA5 outputs a high-level gate opening signal, and the transistors in the red sub-pixel R51 and the green sub-pixel G51 are turned on. The data voltage Vr41 is simultaneously input into the red sub-pixel R51 to pre-charge the red sub-pixel R51. And, the data voltage Vg41 is simultaneously input into the green sub-pixel G51 to pre-charge the green sub-pixel G51. And, during the T4 time period, the signal ga6 on the gate line GA6 outputs a high-level gate opening signal, and the transistors in the red sub-pixel R61 and the green sub-pixel G61 are turned on. The data voltage Vr41 is simultaneously input into the red sub-pixel R61 to pre-charge the red sub-pixel R61. And, the data voltage Vg41 is simultaneously input into the green sub-pixel G61 to pre-charge the green sub-pixel G61.

[0120] During the T5 time period corresponding to the high level of the signal ga5, the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R51, the data load signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-1. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R51 into an analog voltage data voltage Vr51 through digital-to-analog conversion, control the data voltage Vr51 to be loaded on the data line DA1 through the data load signal TP, and control the polarity of the data voltage Vr51 to be negative through the polarity inversion signal POL1. After the data voltage Vr51 is amplified by the second amplifier OP-P, a negative-polarity data voltage Vr51 corresponding to the display data is loaded on the data line DA1, so that the red sub-pixel R51 is charged with the data voltage Vr51. And, the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G51, the data load signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G51 into an analog voltage data voltage Vg51 through digital-to-analog conversion, control the data voltage Vg51 to be loaded on the data line DA2 through the data load signal TP, and control the polarity of the data voltage Vg51 to be positive through the polarity inversion signal POL1. After the data voltage Vg51 is amplified by the second amplifier OP-P, a positive-polarity data voltage Vg51 corresponding to the display data is loaded on the data line DA2, so that the green sub-pixel G51 is charged with the data voltage Vg51. And, during the T5 time period, the signal ga6 on the gate line GA6 outputs a high-level gate opening signal, and the transistors in the red sub-pixel R61 and the green sub-pixel G61 are turned on. The data voltage Vr51 is simultaneously input to the red sub-pixel R51 to pre-charge the red sub-pixel R51. And, the data voltage Vg51 is simultaneously input to the green sub-pixel G61 to pre-charge the green sub-pixel G61.

[0121] During the T6 time period corresponding to the high level of the signal ga6, the data processing circuit 121 outputs the display data corresponding to the red sub-pixel R61, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-1. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the red sub-pixel R61 into an analog voltage data voltage Vr61 through digital-to-analog conversion, control the data voltage Vr61 to be loaded on the data line DA1 through the data loading signal TP, and control the polarity of the data voltage Vr61 to be negative through the polarity inversion signal POL1. After the data voltage Vr61 is amplified by the second amplifier OP-P, the negative-polarity data voltage Vr61 corresponding to the display data is loaded on the data line DA1, so that the red sub-pixel R61 is charged with the data voltage Vr61. And pre-charge the next red sub-pixel. Moreover, the data processing circuit 121 outputs the display data corresponding to the green sub-pixel G61, the data loading signal TP, and the polarity inversion signal POL1 to the first digital-to-analog conversion circuit DAC-P in the voltage output circuit 122-2. The first digital-to-analog conversion circuit DAC-P can convert the display data corresponding to the green sub-pixel G61 into an analog voltage data voltage Vg61 through digital-to-analog conversion, control the data voltage Vg61 to be loaded on the data line DA2 through the data loading signal TP, and control the polarity of the data voltage Vg61 to be positive through the polarity inversion signal POL1. After the data voltage Vg61 is amplified by the second amplifier OP-P, the positive-polarity data voltage Vg61 corresponding to the display data is loaded on the data line DA2, so that the green sub-pixel G61 is charged with the data voltage Vg61. And pre-charge the next green sub-pixel.

[0122] The implementation manners of the remaining sub-pixels are analogized in turn until the sub-pixels in the entire display panel are charged with the data voltage, which will not be elaborated here.

[0123] In the embodiment of the present disclosure, after loading the data voltage corresponding to a row of sub-pixels on the data line, the adjacent two data lines can be short-circuited to release charges. When the data voltages on the adjacent two data lines are symmetrical, after these two data lines are short-circuited to release charges, the voltages on these two data lines will change to the common electrode voltage Vcom. When the data voltage is loaded on the data line next time, it will change from Vcom to the data voltage to be loaded, so that the data line can be charged evenly. For example, in combination with Figure 10 and Figure 11aAs shown, in the T1 stage, when the data voltage Vr11 loaded on the data line DA1 is 0.6V and the data voltage Vg11 loaded on the data line DA2 is 16V, after loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, and the common electrode voltage Vcom of 8.3V can be obtained on the data line DA1 and the data line DA2. In the T2 stage, when the data voltage Vr21 loaded on the data line DA1 is 0.6V and the data voltage Vg21 loaded on the data line DA2 is 16V, the data line DA1 can change from Vcom to 0.6V, and the data line DA2 can change from Vcom to 16V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, and the common electrode voltage Vcom of 8.3V can be obtained on the data line DA1 and the data line DA2. In the T3 stage, when the data voltage Vr31 loaded on the data line DA1 is 16V and the data voltage Vg31 loaded on the data line DA2 is 0.6V, the data line DA1 can change from Vcom to 16V, and the data line DA2 can change from Vcom to 0.6V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, and the common electrode voltage Vcom of 8.3V can be obtained on the data line DA1 and the data line DA2. In the T4 stage, when the data voltage Vr41 loaded on the data line DA1 is 16V and the data voltage Vg41 loaded on the data line DA2 is 0.6V, the data line DA1 can change from Vcom to 16V, and the data line DA2 can change from Vcom to 0.6V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, and the common electrode voltage Vcom of 8.3V can be obtained on the data line DA1 and the data line DA2. In the T5 stage, when the data voltage Vr51 loaded on the data line DA1 is 0.6V and the data voltage Vg51 loaded on the data line DA2 is 16V, the data line DA1 can change from Vcom to 0.6V, and the data line DA2 can change from Vcom to 16V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, and the common electrode voltage Vcom of 8.3V can be obtained on the data line DA1 and the data line DA2. In the T6 stage, when the data voltage Vr61 loaded on the data line DA1 is 0.6V and the data voltage Vg61 loaded on the data line DA2 is 16V, the data line DA1 can change from Vcom to 0.6V, and the data line DA2 can change from Vcom to 16V.After loading data voltages on data lines DA1 and DA2, short - circuit data lines DA1 and DA2 to release charges, so that the voltages on data lines DA1 and DA2 can be the common electrode voltage Vcom of 8.3V.

[0124] In the embodiments of the present disclosure, when the data voltages loaded on two adjacent data lines are asymmetric, after these two data lines are short - circuited to release charges, the voltages on these two data lines will deviate from the common electrode voltage Vcom. When the data voltages are loaded on the data lines next time, it will change from the voltage deviating from Vcom to the data voltage to be loaded, resulting in uneven charging of the data lines. For example, in combination with Figure 10 and Figure 11bAs shown, in the T1 stage, when the data voltage Vr11 loaded on the data line DA1 is 0.6V and the data voltage Vg11 loaded on the data line DA2 is 12V, after loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, which can make the voltages on the data line DA1 and the data line DA2 be 6.3V, less than the common electrode voltage Vcom. In the T2 stage, when the data voltage Vr21 loaded on the data line DA1 is 0.6V and the data voltage Vg21 loaded on the data line DA2 is 12V, it can make the data line DA1 change from 6.3V less than Vcom to 0.6V, and make the data line DA2 change from 6.3V less than Vcom to 12V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, which can make the voltages on the data line DA1 and the data line DA2 be 6.3V, less than the common electrode voltage Vcom. In the T3 stage, when the data voltage Vr31 loaded on the data line DA1 is 16V and the data voltage Vg31 loaded on the data line DA2 is 4.6V, it can make the data line DA1 change from 6.3V less than Vcom to 16V, and make the data line DA2 change from 6.3V less than Vcom to 4.6V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, which can make the voltages on the data line DA1 and the data line DA2 be 10.3V, greater than the common electrode voltage Vcom. In the T4 stage, when the data voltage Vr31 loaded on the data line DA1 is 16V and the data voltage Vg31 loaded on the data line DA2 is 4.6V, it can make the data line DA1 change from 10.3V greater than Vcom to 16V, and make the data line DA2 change from 10.3V greater than Vcom to 4.6V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, which can make the voltages on the data line DA1 and the data line DA2 be 10.3V, greater than the common electrode voltage Vcom. In the T5 stage, when the data voltage Vr21 loaded on the data line DA1 is 0.6V and the data voltage Vg21 loaded on the data line DA2 is 12V, it can make the data line DA1 change from 10.3V greater than Vcom to 0.6V, and make the data line DA2 change from 10.3V greater than Vcom to 12V. After loading the data voltages on the data line DA1 and the data line DA2, short-circuit the data line DA1 and the data line DA2 to release the charge, which can make the voltages on the data line DA1 and the data line DA2 be 6.3V, less than the common electrode voltage Vcom.In the T6 stage, when the data voltage Vr21 loaded on the data line DA1 is 0.6V and the data voltage Vg21 loaded on the data line DA2 is 12V, the data line DA1 can change from 6.3V less than Vcom to 0.6V, and the data line DA2 can change from 6.3V less than Vcom to 12V. This causes the reference points during the charging of the data line DA1 and the data line DA2 to be sometimes greater than Vcom and sometimes less than Vcom, resulting in the problem of uneven charging.

[0125] To solve this problem, the driving method provided by the embodiments of the present disclosure may further include: inputting a reference voltage before inputting the data voltage to the data line. In this way, it is possible to release the charge on the data line without short - circuiting adjacent data lines. Moreover, each data voltage loaded on the data line can be charged from this reference point of the reference voltage to improve the charging uniformity. Exemplarily, as Figure 12 shown, before the T1 stage, a reference voltage VG is input to the data line DA1, and a reference voltage VG is input to the data line DA2. In the T1 stage, the data voltage Vr11 is loaded on the data line DA1, and the data voltage Vg11 is loaded on the data line DA2. Before the T2 stage, a reference voltage VG is input to the data line DA1, and a reference voltage VG is input to the data line DA2. In the T2 stage, the data voltage Vr21 is loaded on the data line DA1, and the data voltage Vg21 is loaded on the data line DA2. Before the T3 stage, a reference voltage VG is input to the data line DA1, and a reference voltage VG is input to the data line DA2. In the T3 stage, the data voltage Vr31 is loaded on the data line DA1, and the data voltage Vg31 is loaded on the data line DA2. The rest is the same and will not be elaborated here.

[0126] In the embodiments of the present disclosure, the reference voltage is a voltage between the first power supply voltage and the second power supply voltage. In this way, each data voltage loaded on the data line can be charged from this reference point of the reference voltage to improve the charging uniformity.

[0127] In the embodiments of the present disclosure, the reference voltage is the mid - point voltage HAVDD between the first power supply voltage and the second power supply voltage. Since the mid - point voltage HAVDD may be equal to Vcom and may differ little from Vcom, charging the data voltages starting from the mid - point voltage HAVDD can further improve the charging uniformity.

[0128] In the embodiments of the present disclosure, as Figure 13As shown, the source driver circuit may further include: a first charge sharing circuit 125; wherein, the first charge sharing circuit 125 is configured to receive a first reference control signal VS1, and under the control of the first reference control signal VS1, input a reference voltage before inputting each data voltage to the electrically connected data line. Exemplarily, the first charge sharing circuit 125 may include a first switching transistor M1; wherein, the gate of the first switching transistor M1 is configured to receive the first reference control signal VS1, the first pole of the first switching transistor M1 is configured to receive the reference voltage, and the second pole of the first switching transistor M1 is electrically connected to the data line. It should be noted that the first switching transistor M1 may be an N-type transistor or a P-type transistor, and the first pole may be the source, the second pole may be the drain, or the first pole may be the drain and the second pole may be the source.

[0129] In the embodiments of the present disclosure, the reference voltage is triggered by the rising edge of the first reference control signal VS1 and input to the corresponding data line. And, the data voltage is triggered by the falling edge of the first reference control signal VS1 and input to the corresponding data line. For example, the first reference control signal VS1 may be a data loading signal TP. Combining Figure 12 with Figure 13 As shown, before stage T1, triggered by the rising edge of the data loading signal TP, the first switching transistor M1 is turned on, and the reference voltage VG is input to the data line DA1. In stage T1, triggered by the falling edge of the data loading signal TP, the first switching transistor M1 is turned off, and the data voltage Vr11 is loaded on the data line DA1. Before stage T2, triggered by the rising edge of the data loading signal TP, the first switching transistor M1 is turned on, and the reference voltage VG is input to the data line DA1. In stage T2, triggered by the falling edge of the data loading signal TP, the first switching transistor M1 is turned off, and the data voltage Vr21 is loaded on the data line DA1. Before stage T3, triggered by the rising edge of the data loading signal TP, the first switching transistor M1 is turned on, and the reference voltage VG is input to the data line DA1. In stage T3, triggered by the falling edge of the data loading signal TP, the first switching transistor M1 is turned off, and the data voltage Vr31 is loaded on the data line DA1. The rest is the same, and will not be elaborated here.

[0130] In the embodiments of the present disclosure, the reference voltage is triggered by the falling edge of the first reference control signal VS1 and input to the corresponding data line. And, the data voltage is triggered by the rising edge of the first reference control signal VS1 and input to the corresponding data line. Its implementation manner is generally the same as the above, and will not be elaborated here.

[0131] Embodiments of the present disclosure provide other embodiments of the driving method for a display panel, which are modifications of the implementation manners in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0132] In the embodiments of the present disclosure, a reference voltage is input before the first data voltage of the data voltage group is input to the data line. In this way, it is not necessary to short adjacent data lines to release the charge on the data line. Moreover, each voltage group loaded on the data line can be charged from the reference point of the reference voltage to improve the charging uniformity. Exemplarily, as shown in Figure 14 Before the T1 stage, the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2. In the T1 stage, the data voltage Vr11 is loaded on the data line DA1, and the data voltage Vg11 is loaded on the data line DA2. In the T2 stage, the data voltage Vr21 is loaded on the data line DA1, and the data voltage Vg21 is loaded on the data line DA2. Before the T3 stage, the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2. In the T3 stage, the data voltage Vr31 is loaded on the data line DA1, and the data voltage Vg31 is loaded on the data line DA2. The same applies to the rest and will not be elaborated here.

[0133] Exemplarily, taking the voltage group that can include two adjacent data voltages as an example, for the data line DA1, the data voltage VR11-1 is the first data voltage in the voltage group composed of the data voltage VR11-1 and the data voltage VR21-1. The data voltage VR31-1 is the first data voltage in the voltage group composed of the data voltage VR31-1 and the data voltage VR41-1. The data voltage VR51-1 is the first data voltage in the voltage group composed of the data voltage VR51-1 and the data voltage VR61-1. For the data line DA2, the data voltage VG11-1 is the first data voltage in the voltage group composed of the data voltage VG11-1 and the data voltage VG21-1. The data voltage VG31-1 is the first data voltage in the voltage group composed of the data voltage VG31-1 and the data voltage VG41-1. The data voltage VG51-1 is the first data voltage in the voltage group composed of the data voltage VG51-1 and the data voltage VG61-1.

[0134] Exemplarily, taking the case where a voltage group may include three adjacent data voltages as an example, for data line DA1, data voltage VR11-1 serves as the first data voltage in the voltage group composed of data voltage VR11-1, data voltage VR21-1, and data voltage VR31-1. Data voltage VR41-1 serves as the first data voltage in the voltage group composed of data voltage VR41-1, data voltage VR51-1, and data voltage VR61-1. For data line DA2, data voltage VG11-1 serves as the first data voltage in the voltage group composed of data voltage VG11-1, data voltage VG21-1, and data voltage VG31-1. Data voltage VG41-1 serves as the first data voltage in the voltage group composed of data voltage VG41-1, data voltage VG51-1, and data voltage VG61-1.

[0135] In an embodiment of the present disclosure, as Figure 15 shown, the source driving circuit further includes: a second charge sharing circuit 126; wherein, the second charge sharing circuit 126 is configured to receive a second reference control signal VS2, and under the control of the second reference control signal VS2, input a reference voltage before inputting the first data voltage of each voltage group to each data line. Exemplarily, the second charge sharing circuit 126 includes a second switching transistor M2; wherein, the gate of the second switching transistor M2 is configured to receive the second reference control signal VS2, the first pole of the second switching transistor M2 is configured to receive the reference voltage, and the second pole of the second switching transistor M2 is electrically connected to the data line. It should be noted that for the second switching transistor M2, the first pole may be the source electrode and the second pole may be the drain electrode, or the first pole may be the drain electrode and the second pole may be the source electrode.

[0136] In an embodiment of the present disclosure, the reference voltage is triggered by the rising edge of the second reference control signal VS2 and input to the corresponding data line. And, the data voltage is triggered by the falling edge of the data loading signal TP and input to the corresponding data line. For example, the second reference control signal VS2 may be a polarity inversion signal POL1. Combining Figure 14 with Figure 15As shown, before the T1 stage, triggered by the rising edge of the polarity inversion signal POL1, the second switching transistor M2 is turned on, and the reference voltage VG is input to the data line DA1. In the T1 stage, triggered by the rising edge of the polarity inversion signal POL1, the first switching transistor M1 is turned off, and triggered by the falling edge of the data loading signal TP, the data voltage Vr11 is loaded on the data line DA1. In the T2 stage, triggered by the falling edge of the data loading signal TP, the data voltage Vr21 is loaded on the data line DA1. Before the T3 stage, triggered by the rising edge of the polarity inversion signal POL1, the first switching transistor M1 is turned on, and the reference voltage VG is input to the data line DA1. In the T3 stage, triggered by the rising edge of the polarity inversion signal POL1, the first switching transistor M1 is turned off, and triggered by the falling edge of the data loading signal TP, the data voltage Vr31 is loaded on the data line DA1. The rest is the same and will not be elaborated here.

[0137] Embodiments of the present disclosure provide some more embodiments of the driving method of the display panel, which are variations of the implementation manners in the above embodiments. Only the differences between this embodiment and the above embodiments will be described below, and the same parts will not be elaborated here.

[0138] Combined with Figure 10As shown, taking the data line DA1 as an example, in the T1 stage, the data line DA1 is loaded with the negative-polarity Vr11. In the T2 stage, the data line DA1 is loaded with the negative-polarity Vr21. In the T3 stage, the data line DA1 is loaded with the positive-polarity Vr31. In the T4 stage, the data line DA1 is loaded with the positive-polarity Vr41. In the T5 stage, the data line DA1 is loaded with the negative-polarity Vr51. In the T6 stage, the data line DA1 is loaded with the negative-polarity Vr61. Among them, the red sub-pixel R31 is pre-charged with the voltage Vr21, and then needs to be charged with Vr31. When the red sub-pixel R31 switches from Vr21 to Vr31, although it is pre-charged with Vr21, since the negative-polarity Vr21 is switched to the positive-polarity Vr31 and the voltage changes from low to high with too large a change, it is relatively difficult for the red sub-pixel R31 to charge Vr31. The red sub-pixel R41 is pre-charged with the voltage Vr31, and then needs to be charged with Vr41. When the red sub-pixel R41 switches from Vr31 to Vr41, it is pre-charged with Vr31, but since the positive-polarity Vr31 is switched to the positive-polarity Vr41 and the voltage change is not large, it is relatively easy for the red sub-pixel R41 to charge Vr41. The red sub-pixel R51 is pre-charged with the voltage Vr41, and then needs to be charged with Vr51. When the red sub-pixel R51 switches from Vr41 to Vr51, although it is pre-charged with Vr41, since the positive-polarity Vr41 is switched to the negative-polarity Vr51 and the voltage changes from high to low with too large a change, it is relatively difficult for the red sub-pixel R51 to charge Vr51. The red sub-pixel R61 is pre-charged with the voltage Vr51, and then needs to be charged with Vr61. When the red sub-pixel R61 switches from Vr51 to Vr61, it is pre-charged with Vr51, but since the negative-polarity Vr51 is switched to the negative-polarity Vr61 and the voltage change is not large, it is relatively easy for the red sub-pixel R61 to charge Vr61. This results in the charging rate of the red sub-pixel R31 being less than that of the red sub-pixel R41, and the charging rate of the red sub-pixel R51 being less than that of the red sub-pixel R61. Thus, the charging rates of the sub-pixels are uneven.

[0139] In order to improve the uniformity of the charging rates of the sub-pixels, in the embodiments of the present disclosure, the driving method may further include: when inputting the first data voltage of the voltage group to the data line, a compensation voltage is superimposed on the data line. Among them, when the first data voltage corresponds to a positive polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is greater than the first data voltage, and when the first data voltage corresponds to a negative polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is less than the first data voltage. In this way, the uniformity of the charging rates of the sub-pixels can be improved by means of over-driving.

[0140] In the disclosed embodiment, in different voltage groups, the compensation voltages superimposed on the first data voltages of the same polarity are the same. For example, in different voltage groups, the compensation voltages superimposed on the first data voltages of positive polarity are the same. In different voltage groups, the compensation voltages superimposed on the first data voltages of negative polarity are the same. Furthermore, the absolute value of the compensation voltage corresponding to each voltage group is the same.

[0141] For example, in combination Figure 16 As shown, before the T1 stage, the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2. In the T1 stage, the data voltage Vr11 and the compensation voltage VC1 are loaded on the data line DA1, and the data voltage Vg11 and the compensation voltage VC2 are loaded on the data line DA2. In the T2 stage, the data voltage Vr21 is loaded on the data line DA1, and the data voltage Vg21 is loaded on the data line DA2. Before the T3 stage, the reference voltage VG is input to the data line DA1, and the reference voltage VG is input to the data line DA2. In the T3 stage, the data voltage Vr31 and the compensation voltage VC2 are loaded on the data line DA1, and the data voltage Vg31 and the compensation voltage VC1 are loaded on the data line DA2. And, Vr11+VC1<Vr11,Vg11+VC2> Vg11,Vr31+VC2>Vr31,Vg31+VC1 <Vg31,|VC1|=|VC2|。其余同理,在此不作赘述。

[0142] The disclosed embodiments provide some other embodiments of the driving method of the display panel, which are modified with respect to the implementation methods in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are not repeated here.

[0143] In order to improve the uniformity of the charging rate of the sub-pixels, in the embodiment of the present disclosure, Figure 17As shown, there is an overlapping duration between the duration for which the data line loads the data voltage and the duration for which the sub-pixel corresponding to the data voltage remains turned on, and this overlapping duration is the charging duration of the sub-pixel. There is a non-overlapping duration between the duration for which the data line loads the data voltage and the duration for which the sub-pixel corresponding to the data voltage remains turned on. If the non-overlapping duration becomes longer, the overlapping duration becomes shorter, that is, the charging duration of the sub-pixel becomes shorter, which will reduce the charging rate of the sub-pixel. If the non-overlapping duration becomes shorter, the overlapping duration increases, that is, the charging duration of the sub-pixel increases, which will increase the charging rate of the sub-pixel. In specific implementation, in the same voltage group, the first data voltage loaded onto the data line can have a first non-overlapping duration, and the remaining data voltages loaded onto the data line can have a second non-overlapping duration. By making the first non-overlapping duration less than the second non-overlapping duration, the charging rate of the sub-pixel corresponding to the first data voltage can be increased, and the charging rates of the sub-pixels corresponding to the remaining data voltages can be reduced, so as to make the charging rates of different sub-pixels approach each other as much as possible, or even be the same, thereby improving the uniformity of the charging rates of the sub-pixels.

[0144] Exemplarily, the first non-overlapping durations corresponding to each voltage group can be the same, and the second non-overlapping durations corresponding to each voltage group can be the same. Combining Figure 17 As shown, when Vr11 and Vr21 form a voltage group, Vr11 is the first data voltage in this voltage group, and Vr12 is the remaining data voltage in this voltage group. Then, the duration t11 for which Vr11 is loaded onto the data line DA1 and the duration t21 for which the gate turn-on signal corresponding to the red sub-pixel R11 remains on have a first non-overlapping duration GOE1. The duration t12 for which Vr21 is loaded onto the data line DA1 and the duration t22 for which the gate turn-on signal corresponding to the red sub-pixel R21 remains on have a second non-overlapping duration GOE2. And, GOE1 < GOE2, t11 = t12, t21 = t22. Also, when Vg11 and Vg21 form a voltage group, Vg11 is the first data voltage in this voltage group, and Vg12 is the remaining data voltage in this voltage group. Then, the duration t31 for which Vg11 is loaded onto the data line DA2 and the duration t21 for which the gate turn-on signal corresponding to the green sub-pixel G11 remains on have a first non-overlapping duration GOE1. The duration t32 for which Vg21 is loaded onto the data line DA2 and the duration t22 for which the gate turn-on signal corresponding to the green sub-pixel G21 remains on have a second non-overlapping duration GOE2. And, GOE1 < GOE2, t31 = t32.

[0145] In the embodiments of the present disclosure, it is also possible to make the first non-overlap duration of the first data voltage corresponding to the positive polarity less than the first non-overlap duration of the first data voltage corresponding to the negative polarity. In a specific application, switching from a data voltage of positive polarity to a data voltage of negative polarity is equivalent to discharging, which is faster than switching from a data voltage of negative polarity to a data voltage of positive polarity. Therefore, by making the first non-overlap duration of the first data voltage corresponding to the positive polarity less than the first non-overlap duration of the first data voltage corresponding to the negative polarity, the charging rate of the data voltage corresponding to the positive polarity can be made greater than the charging rate of the data voltage corresponding to the negative polarity. Thus, the brightness uniformity can be further improved.

[0146] Exemplarily, as shown in Figure 18 When Vr11 and Vr21 are used as a voltage group, Vr11 is used as the first data voltage in the voltage group, and Vr12 is used as the remaining data voltages in the voltage group. Then, the sustain duration t11 of Vr11 loaded on the data line DA1 and the sustain duration t21 of the gate turn-on signal corresponding to the red sub-pixel R11 have a first non-overlap duration GOE11. When Vg11 and Vg21 are used as a voltage group, Vg11 is used as the first data voltage in the voltage group, and Vg12 is used as the remaining data voltages in the voltage group. Then, the sustain duration t31 of Vg11 loaded on the data line DA2 and the sustain duration t21 of the gate turn-on signal corresponding to the green sub-pixel G11 have a first non-overlap duration GOE21. And, GOE11 < GOE21, t11 = t31, t21 = t22. In this way, the charging rate of the data voltage corresponding to the positive polarity can be made greater than the charging rate of the data voltage corresponding to the negative polarity. Thus, the brightness uniformity can be further improved.

[0147] Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A driving method for a display panel, comprising: Obtaining display data of a current display frame; According to the display data, inputting a data voltage to a data line so that sub-pixels electrically connected to the data line are charged with corresponding data voltages; wherein, the data voltages input to the data line are divided into multiple voltage groups, each of the voltage groups includes at least two adjacent data voltages, and the data voltages in the same voltage group have the same corresponding polarity; the data voltages in two adjacent voltage groups input to the same data line have different corresponding polarities; the voltage groups corresponding to two adjacent data lines have different polarities; When inputting the first data voltage of the voltage group to the data line, superimposing a compensation voltage on the data line; Wherein, when the first data voltage corresponds to a positive polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is greater than the first data voltage; When the first data voltage corresponds to a negative polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is less than the first data voltage; Wherein, the holding duration for which the data line loads the data voltage and the holding duration for which the sub-pixel corresponding to the data voltage is turned on have a non-overlapping duration; In the same voltage group, the first data voltage loaded onto the data line has a first non-overlapping duration, and the remaining data voltages loaded onto the data line have a second non-overlapping duration; wherein, the first non-overlapping duration is less than the second non-overlapping duration.

2. The driving method according to claim 1, wherein, The driving method further comprises: Inputting a reference voltage before inputting the data voltage to the data line.

3. The driving method according to claim 2, wherein, The driving method further comprises: Inputting the reference voltage before inputting the first data voltage of the voltage group to the data line.

4. The driving method according to claim 2 or 3, wherein, The data voltage is formed by dividing a first power supply voltage and a second power supply voltage; wherein, the first power supply voltage is less than the second power supply voltage; The reference voltage is a voltage between the first power supply voltage and the second power supply voltage.

5. The driving method according to claim 4, wherein, The reference voltage is the midpoint voltage HAVDD between the first power supply voltage and the second power supply voltage.

6. The driving method according to claim 1, wherein, In different voltage groups, the compensation voltages superimposed on the first data voltages corresponding to the same polarity are the same.

7. The driving method according to claim 6, wherein, The absolute value of the compensation voltage corresponding to each voltage group is the same.

8. The driving method according to claim 1, wherein, The first non-overlapping duration of the first data voltage corresponding to the positive polarity is less than the first non-overlapping duration of the first data voltage corresponding to the negative polarity.

9. A display device, comprising: A timing controller configured to: obtain and output display data of a current display frame; And generate and output a polarity inversion signal based on the rule that the data voltages input to the data line are divided into multiple voltage groups, each of the voltage groups includes at least two adjacent data voltages, the data voltages in the same voltage group have the same corresponding polarity; the data voltages in two adjacent voltage groups input to the same data line have different corresponding polarities; the voltage groups corresponding to two adjacent data lines have different polarities; A display panel, including a source driver circuit; wherein, the source driver circuit is configured to receive the display data and the polarity inversion signal; according to the display data and the polarity inversion signal, input a data voltage to a data line, so that sub-pixels electrically connected to the data line are charged with corresponding data voltages; The source driver circuit is further configured to superimpose a compensation voltage on the data line when inputting the first data voltage of the voltage group to the data line; Wherein, when the first data voltage corresponds to a positive polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is greater than the first data voltage; When the first data voltage corresponds to a negative polarity, the voltage value after the first data voltage is superimposed with the compensation voltage is less than the first data voltage; Wherein, the maintaining duration for the data line to load the data voltage and the maintaining duration for the sub-pixels corresponding to the data voltage to be turned on have a non-overlapping duration; In the same voltage group, the first data voltage loaded onto the data line has a first non-overlapping duration, and the remaining data voltages loaded onto the data line have a second non-overlapping duration; wherein, the first non-overlapping duration is less than the second non-overlapping duration.

10. The display device according to claim 9, wherein, The source driver circuit includes: a data processing circuit and a plurality of voltage output circuits; wherein, each data line is electrically connected to the voltage output circuit in a one-to-one correspondence; The data processing circuit is configured to receive the display data, and according to the display data, output corresponding display data to each voltage output circuit; The voltage output circuit is configured to receive the polarity inversion signal and the display data output by the data processing circuit, and according to the polarity inversion signal and the display data output by the data processing circuit, input a data voltage to the electrically connected data line, so that sub-pixels electrically connected to the data line are charged with corresponding data voltages.

11. The display device according to claim 10, wherein, The source driver circuit further includes: a first charge sharing circuit; The first charge sharing circuit is configured to receive a first reference control signal, and under the control of the first reference control signal, input a reference voltage before inputting each data voltage to the electrically connected data line.

12. The display device according to claim 11, wherein, The reference voltage is triggered by a first setting edge of the first reference control signal and input to the corresponding data line; The data voltage is triggered by a second setting edge of the first reference control signal and input to the corresponding data line; Wherein, the first setting edge is a rising edge, and the second setting edge is a falling edge; Or, the first setting edge is a falling edge, and the second setting edge is a rising edge.

13. The display device according to claim 12, wherein, The first charge sharing circuit includes a first switching transistor; The gate of the first switching transistor is configured to receive the first reference control signal, the first pole of the first switching transistor is configured to receive the reference voltage, and the second pole of the first switching transistor is electrically connected to the data line.

14. The display device according to claim 10, wherein, The source driver circuit further includes: a second charge sharing circuit; The second charge sharing circuit is configured to receive a second reference control signal, and under the control of the second reference control signal, input a reference voltage before inputting the first data voltage of each voltage group to each data line.

15. The display device according to claim 14, wherein, The second reference control signal is the polarity inversion signal.

16. The display device according to claim 15, wherein, The second charge sharing circuit includes a second switching transistor; The gate of the second switching transistor is configured to receive the second reference control signal, the first pole of the second switching transistor is configured to receive the reference voltage, and the second pole of the second switching transistor is electrically connected to the data line.

17. The display device according to any one of claims 10-16, wherein, The voltage output circuit includes a first output circuit and a second output circuit; wherein, each data line is electrically connected to the first output circuit and the second output circuit in a one-to-one correspondence; The first output circuit is configured to input a data voltage corresponding to the positive polarity to the electrically connected data line according to the polarity inversion signal and the display data; The second output circuit is configured to input a data voltage corresponding to the negative polarity to the electrically connected data line according to the polarity inversion signal and the display data.

18. The display device according to claim 17, wherein, The first output circuit includes: a first digital-to-analog conversion circuit and a second amplifier; wherein, there is a midpoint voltage terminal between the first power supply voltage and the second power supply voltage, and the first digital-to-analog conversion circuit is electrically connected between the second power supply voltage and the midpoint voltage terminal; The first digital-to-analog conversion circuit is configured to receive the polarity inversion signal and the display data, and according to the polarity inversion signal, perform digital-to-analog conversion on the display data to generate and output a data voltage corresponding to the positive polarity; The second amplifier is configured to receive the data voltage output by the first digital-to-analog conversion circuit, and after amplifying the received data voltage, input it to the electrically connected data line.

19. The display device according to claim 18, wherein, The second output circuit includes: a second digital-to-analog conversion circuit and a second amplifier; wherein, there is a midpoint voltage terminal between the first power supply voltage and the second power supply voltage, and the second digital-to-analog conversion circuit is electrically connected between the first power supply voltage and the midpoint voltage terminal; The second digital-to-analog conversion circuit is configured to receive the polarity inversion signal and the display data, and according to the polarity inversion signal, perform digital-to-analog conversion on the display data to generate and output a data voltage corresponding to the negative polarity; The second amplifier is configured to receive the data voltage output by the second digital-to-analog conversion circuit, and after amplifying the received data voltage, input it to the electrically connected data line.

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