storage device

Abstract

Embodiments provide a storage device that can efficiently perform a read operation. The storage device of an embodiment includes a plurality of memory cells, a word line, and a controller. The plurality of memory cells respectively stores five-bit data including first to fifth-bit data according to threshold voltages. The plurality of memory cells stores first to fifth pages respectively including the first to fifth-bit data. The word line is connected to the plurality of memory cells. The controller performs a read operation of reading data from the plurality of memory cells by applying a read voltage to the word line. The controller applies a read voltage to the word line a number of times that is different for each of the first to fifth pages in the read operation, and the number of times is seven, six, six, six, and six, respectively.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-210885 (filed on December 24, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] The implementation method mainly relates to a storage device. Background Technology

[0004] NAND (Not And) type flash memory is known to be able to store data non-volatilely. Summary of the Invention

[0005] The embodiment provides a storage device that can perform read operations more efficiently.

[0006] The storage device of this embodiment includes multiple storage cells, word lines, and a controller. Each of the multiple storage cells stores 5 bits of data, including a first bit, a second bit, a third bit, a fourth bit, and a fifth bit, respectively, based on a threshold voltage. The multiple storage cells store pages 1, 2, 3, 4, and 5, each containing the first, second, third, fourth, and fifth bits of data. Word lines are connected to the multiple storage cells. The controller performs a read operation by applying a read voltage to the word lines to read data from the multiple storage cells. The controller applies different read voltages to the word lines 7 times, 6 times, 6 times, 6 times, and 6 times, respectively, during the read operations for each page (page 1, page 2, page 3, page 4, and page 5). Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of the information processing system according to the first embodiment.

[0008] Figure 2 This is a block diagram illustrating an example of the hardware configuration of the memory controller in the first embodiment.

[0009] Figure 3 This is a block diagram illustrating an example of the hardware configuration of the storage device according to the first embodiment.

[0010] Figure 4 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the memory device of the first embodiment.

[0011] Figure 5 This is a circuit diagram illustrating an example of the circuit configuration of the line decoder module included in the storage device of the first embodiment.

[0012] Figure 6 This is a circuit diagram illustrating an example of the circuit configuration of the sensing amplifier module included in the storage device of the first embodiment.

[0013] Figure 7 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors in the memory device of the first embodiment.

[0014] Figure 8 This is a table indicating the data allocation and readout voltage settings used in the storage device of the first embodiment.

[0015] Figure 9 This is a timing diagram illustrating an example of reading the first page in the memory system of the first embodiment.

[0016] Figure 10 This is a timing diagram illustrating an example of reading the second page in the memory system of the first embodiment.

[0017] Figure 11 This is a timing diagram illustrating an example of reading the third page in the memory system of the first embodiment.

[0018] Figure 12 This is a timing diagram illustrating an example of reading the fourth page in the memory system of the first embodiment.

[0019] Figure 13 This is a timing diagram illustrating an example of reading the 5th page in the memory system of the first embodiment.

[0020] Figure 14 This is a table that represents the data allocation and readout voltage setting for the first variation example.

[0021] Figure 15 This is a waveform diagram showing an example of the voltage applied to the select word line during the readout operation of the first variation example.

[0022] Figure 16 This is a table that represents the data allocation and readout voltage setting for the second variation example.

[0023] Figure 17 This is a waveform diagram showing an example of the voltage applied to the select word line during the readout operation in the second variation example.

[0024] Figure 18 This is a table that represents the data allocation and readout voltage setting for the third variation example.

[0025] Figure 19 This is a waveform diagram showing an example of the voltage applied to the select word line during the readout operation in the third variation example.

[0026] Figure 20This is a table that represents the data allocation and readout voltage setting for the fourth variation example.

[0027] Figure 21 This is a waveform diagram showing an example of the voltage applied to the select word line during the readout operation in the fourth variation example.

[0028] Figure 22 This is a table that represents the data allocation and readout voltage setting for the 5th variation example.

[0029] Figure 23 This is a waveform diagram showing an example of the voltage applied to the select word line during the readout operation in the 5th variation example.

[0030] Figure 24 This is a table that represents the data allocation and readout voltage setting for the 6th variation example.

[0031] Figure 25 This is a table that represents the data allocation and readout voltage setting for the 7th variation example.

[0032] Figure 26 This is a table that represents the data allocation and readout voltage setting for the 8th variation example.

[0033] Figure 27 This is a table that represents the data allocation and readout voltage setting for the 9th variation example.

[0034] Figure 28 This is a table that represents the data allocation and readout voltage setting for the 10th variation example.

[0035] Figure 29 This is a table that represents the data allocation and readout voltage setting for the 11th variation example.

[0036] Figure 30 This is a table that represents the data allocation and readout voltage setting for the 12th variation example.

[0037] Figure 31 This is a table that represents the data allocation and readout voltage setting for the 13th variation example.

[0038] Figure 32 This is a table that represents the data allocation and readout voltage setting for the 14th variation example.

[0039] Figure 33 This is a table that represents the data allocation and readout voltage setting for the 15th variation example.

[0040] Figure 34 This is a table that represents the data allocation and readout voltage setting for the 16th variation example.

[0041] Figure 35 This is a table that represents the data allocation and readout voltage setting for the 17th variation example.

[0042] Figure 36 This is a table that represents the data allocation and readout voltage setting for the 18th variation example.

[0043] Figure 37 This is a table that represents the data allocation and readout voltage setting for the 19th variation example.

[0044] Figure 38 This is a table that represents the data allocation and readout voltage setting for the 20th variation example.

[0045] Figure 39 This is a table that represents the data allocation and readout voltage setting for the 21st variation example.

[0046] Figure 40 This is a table that represents the data allocation and readout voltage setting for the 22nd variation example.

[0047] Figure 41 This is a table that represents the data allocation and readout voltage setting for the 23rd variation example.

[0048] Figure 42 This is a table that represents the data allocation and readout voltage setting for the 24th variation example.

[0049] Figure 43 This is a table that represents the data allocation and readout voltage setting for the 25th variation example.

[0050] Figure 44 This is a table that represents the data allocation and readout voltage setting for the 26th variation example.

[0051] Figure 45 This is a table that represents the data allocation and readout voltage setting for the 27th variation example.

[0052] Figure 46 This is a table that represents the data allocation and readout voltage setting for the 28th variation example.

[0053] Figure 47 This is a table that represents the data allocation and readout voltage setting for the 29th variation example.

[0054] Figure 48 This is a table that represents the data allocation and readout voltage setting for the 30th variation example.

[0055] Figure 49 This is a table that represents the data allocation and readout voltage setting for the 31st variation example.

[0056] Figure 50 This is a table that represents the data allocation and readout voltage setting for the 32nd variation example.

[0057] Figure 51 This is a table that represents the data allocation and readout voltage setting for the 33rd variation example.

[0058] Figure 52 This is a table that represents the data allocation and readout voltage setting for the 34th variation example.

[0059] Figure 53 This is a table that represents the data allocation and readout voltage setting for the 35th variation example.

[0060] Figure 54 This is a table representing the data allocation and readout voltage setting for the 36th variation example.

[0061] Figure 55 This is a table representing the data allocation and readout voltage setting for the 37th variation example.

[0062] Figure 56 This is a table that represents the data allocation and readout voltage setting for the 38th variation example.

[0063] Figure 57 This is a table that represents the data allocation and readout voltage setting for the 39th variation example.

[0064] Figure 58 This is a table that represents the data allocation and readout voltage setting for the 40th variation example.

[0065] Figure 59 This is a table that represents the data allocation and readout voltage setting for the 41st variation example.

[0066] Figure 60 This is a table that represents the data allocation and readout voltage setting for the 42nd variation example.

[0067] Figure 61 This is a table that represents the data allocation and readout voltage setting for the 43rd variation example.

[0068] Figure 62 This is a table that represents the data allocation and readout voltage setting for the 44th variation example.

[0069] Figure 63 This is a table that represents the data allocation and readout voltage setting for the 45th variation example.

[0070] Figure 64 This is a table that represents the data allocation and readout voltage setting for the 46th variation example.

[0071] Figure 65 This is a table that represents the data allocation and readout voltage setting for the 47th variation example.

[0072] Figure 66 This is a table that represents the data allocation and readout voltage setting for the 48th variation example.

[0073] Figure 67This is a table that represents the data allocation and readout voltage setting for the 49th variation example.

[0074] Figure 68 This is a table that represents the data allocation and readout voltage setting for the 50th variation example.

[0075] Figure 69 This is a table that represents the data allocation and readout voltage setting for the 51st variation example.

[0076] Figure 70 This is a table that represents the data allocation and readout voltage setting for the 52nd variation example.

[0077] Figure 71 This is a table that represents the data allocation and readout voltage setting for the 53rd variation example.

[0078] Figure 72 This is a timing diagram illustrating an example of reading the first page in the memory system of the second embodiment.

[0079] Figure 73 This is a timing diagram illustrating an example of sequential reading in the memory system of the third embodiment.

[0080] Figure 74 This is a top view showing an example of the circuit configuration of a comparative storage device.

[0081] Figure 75 This is a top view showing an example of the circuit configuration of the storage device according to the fourth embodiment.

[0082] Figure 76 This is a top view showing an example of the circuit configuration of the storage device in a variation of the fourth embodiment.

[0083] Figure 77 This is a schematic diagram illustrating a first configuration example of the sensing amplifier module in the storage device according to the fourth embodiment.

[0084] Figure 78 This is a schematic diagram illustrating a second configuration example of the sensing amplifier module in the storage device according to the fourth embodiment.

[0085] Figure 79 This is a top view showing an example of the circuit configuration of the storage device according to the fifth embodiment.

[0086] Figure 80 This is a schematic diagram illustrating a first configuration example of the sense amplifier group and latch group in the storage device of the fifth embodiment.

[0087] Figure 81 This is a schematic diagram illustrating a second configuration example of the sensing amplifier group and latch group in the storage device of the fifth embodiment.

[0088] Figure 82 This is a schematic diagram illustrating a third configuration example of the sensing amplifier group and latch group in the storage device of the fifth embodiment.

[0089] Figure 83 This is a schematic diagram illustrating a fourth configuration example of the sensing amplifier group and latch group in the storage device of the fifth embodiment.

[0090] Figure 84 This is a flowchart illustrating an example of the write operation of the memory system in the sixth embodiment.

[0091] Figure 85 This is a flowchart illustrating an example of a buffer write operation in the memory system of the sixth embodiment.

[0092] Figure 86 This is a timing diagram illustrating an example of a multi-value write operation of the storage device in the sixth embodiment.

[0093] Figure 87 This is a threshold voltage distribution diagram illustrating an example of the threshold voltage portion of redundant pages after a multi-value write operation in the storage device of the sixth embodiment.

[0094] Figure 88 This is a flowchart illustrating an example of the compression operation of the memory system in the sixth embodiment.

[0095] Figure 89 This is a timing diagram illustrating an example of the multi-value write operation of the storage device in the sixth embodiment.

[0096] Figure 90 This is a flowchart illustrating the first example of a buffer read operation of the memory system in the sixth embodiment.

[0097] Figure 91 This is a timing diagram illustrating an example of redundant page readout from the storage device of the sixth embodiment.

[0098] Figure 92 This is a flowchart illustrating the second example of the buffer read operation of the memory system in the sixth embodiment.

[0099] Figure 93 This is a flowchart illustrating the third example of the buffer read operation of the memory system in the sixth embodiment.

[0100] Figure 94 This is a timing diagram illustrating an example of reading redundant pages at once from the storage device of the sixth embodiment.

[0101] Figure 95 This is a sequence diagram showing the first example of an instruction sequence for reading redundant pages at once in the storage device of the sixth embodiment.

[0102] Figure 96 This is a sequence diagram of the second example of an instruction sequence for reading redundant pages at once in the storage device of the sixth embodiment.

[0103] Figure 97 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors in the memory device of the seventh embodiment.

[0104] Figure 98 This is a timing diagram illustrating the first example of a multi-value write operation of the storage device in the seventh embodiment.

[0105] Figure 99 This is a timing diagram illustrating the second example of a multi-value write operation of the storage device in the seventh embodiment.

[0106] Figure 100 This is a timing diagram representing the third example of a multi-value write operation of the storage device in the seventh embodiment.

[0107] Figure 101 This is a timing diagram representing the fourth example of a multi-value write operation of the storage device in the seventh embodiment.

[0108] Figure 102 This is a timing diagram representing the fifth example of a multi-value write operation of the storage device in the seventh embodiment.

[0109] Figure 103 This is a block diagram illustrating an example of the configuration of the storage device in the eighth embodiment.

[0110] Figure 104 This is a table representing an example of a combination of states of the memory cell transistors used in the shared encoding of the memory device in the eighth embodiment.

[0111] Figure 105 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors in the memory device of the eighth embodiment.

[0112] Figure 106 This is a timing diagram illustrating the first example of a multi-value write operation of the storage device in the eighth embodiment.

[0113] Figure 107 This is a timing diagram representing the second example of a multi-value write operation of the storage device in the eighth embodiment.

[0114] Figure 108 This is a timing diagram representing the third example of a multi-value write operation of the storage device in the eighth embodiment.

[0115] Figure 109 This is a table representing an example of the combination of states of the memory cell transistors used in the shared encoding of the memory device in the first variation of the eighth embodiment.

[0116] Figure 110 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors in the memory device of the first variation of the eighth embodiment.

[0117] Figure 111 This is a table representing an example of the combination of states of the memory cell transistors used in the shared encoding of the memory device in the second variation of the eighth embodiment.

[0118] Figure 112 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors in the memory device of the second variation of the eighth embodiment.

[0119] Figure 113 This is a table representing an example of the combination of states of the memory cell transistors used in the shared encoding of the memory device in the third variation of the eighth embodiment.

[0120] Figure 114 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors in the memory device of the third variation of the eighth embodiment.

[0121] Figure 115 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the memory device of the ninth embodiment.

[0122] Figure 116 This is a flowchart illustrating an example of a buffer write operation in the memory system of the ninth embodiment.

[0123] Figure 117 This is a timing diagram illustrating the first example of a multi-value write operation of the storage device in the ninth embodiment.

[0124] Figure 118 This is a timing diagram representing the second example of a multi-value write operation of the storage device in the ninth embodiment.

[0125] Figure 119 This is a sequence diagram illustrating an example of an instruction sequence for a multi-value write operation of the storage device according to the ninth embodiment. Detailed Implementation

[0126] The embodiments will now be described with reference to the accompanying drawings. Each embodiment illustrates an apparatus and method for embodying the technical concept of the invention. The drawings are schematic or conceptual. The dimensions and scale of the drawings may not be identical to actual figures. In the following description, constituent elements having substantially the same function and structure are labeled with the same symbols. The numbers following the text constituting the reference numerals are used to distinguish similar elements with the same structure represented by reference numerals containing the same text.

[0127] [1] First Embodiment

[0128] The first embodiment will now be described.

[0129] [1-1] Composition

[0130] [1-1-1] Composition of Information Processing System 1

[0131] Figure 1 This is a block diagram illustrating an example of the configuration of the information processing system 1 according to the first embodiment. For example... Figure 1 As shown, the information processing system 1 includes, for example, a host device HD and a memory system MS. The host device HD is an electronic device such as a personal computer, a portable information terminal, or a server. The memory system MS is a storage medium such as a memory card or an SSD (solid-state drive). The memory system MS includes, for example, a memory controller 10 and a storage device 20.

[0132] The memory controller 10 is, for example, a semiconductor integrated circuit configured as a System-on-a-Chip (SoC). The memory controller 10 is connected to the host device HD via the host bus HB. The memory controller 10 is connected to the storage device 20 via the memory bus MB. The memory controller 10 controls the storage device 20 based on commands received from the host device HD. For example, the memory controller 10 controls the storage device 20 to perform read operations, write operations, erase operations, etc.

[0133] Storage device 20 is a non-volatile semiconductor storage device. Storage device 20 is, for example, a NAND flash memory. In NAND flash memory, the unit for reading and writing data is called a "page". Storage device 20 includes multiple memory cell transistors MT, multiple bit lines BL, and multiple word lines WL. Each memory cell transistor MT is associated with one bit line BL and one word line WL. Column addresses are assigned to each bit line BL. Page addresses are assigned to each word line WL.

[0134] [1-1-2] Hardware configuration of memory controller 10

[0135] Figure 2 This is a block diagram illustrating an example of the hardware configuration of the memory controller 10 in the first embodiment. For example... Figure 2As shown, the memory controller 10 includes, for example, a host interface (host I / F) 11, a memory interface (memory I / F) 12, a CPU (Central Processing Unit) 13, an ECC (Error Correction Code) circuit 14, a ROM (Read Only Memory) 15, a RAM (Random Access Memory) 16, and a buffer memory 17.

[0136] The Host I / F11 is a hardware interface conforming to the interface standard between the host device HD and the memory controller 10. The Host I / F11 is connected to the host device HD via the host bus HB. The Host I / F11 supports, for example, SATA (Serial Advanced Technology Attachment) and PCIe... TM Interface standards such as PCI Express (PCI Express, high-speed peripheral component interconnect) are used.

[0137] The memory I / F12 is a hardware interface conforming to the interface standard between the memory controller 10 and the storage device 20. The memory I / F12 is connected to the storage device 20 via the memory bus MB. The memory I / F12, for example, supports the NAND interface standard.

[0138] CPU 13 is a processor that controls the overall operation of memory controller 10. CPU 13 writes data to storage device 20 via memory I / F 12 according to write requests received via host I / F 11. CPU 13 reads data from storage device 20 via memory I / F 12 according to read requests received via host I / F 11.

[0139] ECC circuit 14 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. ECC circuit 14 encodes the data to be written to storage device 20 and decodes the data to be read from storage device 20.

[0140] ROM15 is non-volatile memory. ROM15 stores programs such as firmware. For example, ROM15 may be an EEPROM. TM (Electrically Erasable Programmable Read-Only Memory). The operation of the memory controller 10 is achieved by using the CPU 13 to execute firmware stored in the ROM 15, etc.

[0141] RAM16 is volatile memory. RAM16 is used as the operating area of ​​CPU13. RAM16 can be DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc.

[0142] The buffer memory 17 is, for example, a volatile memory. The buffer memory 17 temporarily stores data received via the host I / F 11 and data received via the memory I / F 12. The buffer memory 17 is DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), etc.

[0143] [1-1-3] Hardware configuration of storage device 20

[0144] Figure 3 This is a block diagram illustrating an example of the hardware configuration of the storage device 20 according to the first embodiment. Figure 3 As shown, the storage device 20 includes, for example, an input / output circuit 201, a logic controller 202, a register circuit 203, a sequencer 204, a ready / busy controller 205, a driver circuit 206, a memory cell array 207, a line decoder module 208, and a sense amplifier module 209. Signals transmitted or received via the memory bus MB include, for example, input / output signals I / O0 to I / O7, control signals CEn, CLE, ALE, WEn, REn, and WPn, and a ready / busy signal RBn.

[0145] Input / output circuit 201 is an interface circuit responsible for transmitting and receiving input / output signals I / O0 to I / O7. Input / output signals I / O include data DAT, status information STS, address information ADD, and instruction CMD. Input / output circuit 201 can transmit (input or output) data DAT to the sense amplifier module 209. Input / output circuit 201 can transmit (output) the status information STS from register circuit 203 to memory controller 10. Input / output circuit 201 can also transmit the address information ADD and instruction CMD from memory controller 10 to register circuit 203.

[0146] The logic controller 202 controls the input / output circuit 201 and the sequencer 204 based on the control signals CEn, CLE, ALE, WEn, REn, and WPn input from the memory controller 10. The logic controller 202 starts the memory device 20 based on the control signal CEn. Based on the control signals CLE and ALE, the logic controller 202 notifies the input / output circuit 101 that the received input / output signals (I / O) from the memory device 20 are the instruction (CMD) and address information (ADD), respectively. Based on the control signal WEn, the logic controller 202 commands the input / output circuit 201 to input the input / output signals (I / O), and based on the control signal REn, commands the input / output circuit 201 to output the input / output signals (I / O). Based on the control signal WPn, the logic controller 202 puts the memory device 20 into a protection state when the power is switched on or off.

[0147] Register circuit 203 is a circuit that temporarily stores status information STS, address information ADD, and instruction CMD. The status information STS stored in register circuit 203 is updated based on the control of sequencer 204 and transmitted to input / output circuit 201. Address information ADD includes block address, page address, column address, etc. Instruction CMD includes commands related to various operations of storage device 20.

[0148] The sequencer 204 is a controller that controls the overall operation of the storage device 20. Based on the instruction CMD and address information ADD stored in the register circuit 203, the sequencer 204 performs read operations, write operations, erase operations, etc.

[0149] The ready / busy controller 205 is a controller that generates a ready / busy signal RBn based on the control of the sequencer 204. The ready / busy signal RBn is a signal that informs the memory controller 10 whether the storage device 20 is in a ready or busy state. A "ready state" is the state in which the storage device 20 can accept commands from the memory controller 10, and is indicated using a "H" level ready / busy signal RBn. A "busy state" is the state in which the storage device 20 cannot accept commands from the memory controller 10, and is indicated using a "L" level ready / busy signal RBn.

[0150] The driver circuit 206 is a circuit that generates the voltage used in read, write, and erase operations. The driver circuit 206 supplies the generated voltage to the line decoder module 208 and the sense amplifier module 209, etc.

[0151] The memory cell array 207 is a collection of multiple memory cell transistors MT. The memory cell array 207 contains multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). A block address is assigned to each BLK. Each BLK block contains multiple pages. The BLK block is used, for example, as a unit for data erasure. The memory cell array 207 has multiple bit lines BL0 to BLm (m is an integer greater than or equal to 1) and multiple word lines WL.

[0152] The line decoder module 208 is a circuit used to select the block BLK as the action target and to transmit voltage to the word line WL and other wiring. The line decoder module 208 contains multiple line decoders RD0 to RDn. The line decoders RD0 to RDn are associated with blocks BLK0 to BLKn respectively.

[0153] The sense amplifier module 209 is a circuit used to transmit voltage to each bit line BL and read data. The sense amplifier module 209 includes multiple sense amplifier units SAU0 to SAUm. The sense amplifier units SAU0 to SAUm are respectively associated with multiple bit lines BL0 to BLm.

[0154] [1-1-4] Circuit configuration of storage device 20

[0155] (Circuit configuration of memory cell array 207)

[0156] Figure 4 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 207 included in the memory device 20 of the first embodiment. Figure 4 The circuit structure of one BLK block is illustrated in the diagram. (See diagram for example.) Figure 4 As shown, block BLK includes, for example, string cells SU0 to SU4, word lines WL0 to WL7, select gate lines SGD0 to SGD4, select gate line SGS, and source line SL.

[0157] Each string cell SU contains multiple NAND strings NS. The multiple NAND strings NS of each string cell SU are connected to bit lines BL0 to BLm. Each NAND string NS contains memory cell transistors MT0 to MT7, and select transistors ST1 and ST2. Each memory cell transistor MT has a control gate and a charge storage layer, storing data non-volatilely. Select transistors ST1 and ST2 are used to select the string cell SU.

[0158] The drain of select transistor ST1 is connected to the associated bit line BL. The source of select transistor ST1 is connected to the drain of memory cell transistor MT7. Memory cell transistors MT0 to MT7 are connected in series. The source of memory cell transistor MT0 is connected to the drain of select transistor ST2. The source of select transistor ST2 is connected to the source line SL. The source line SL is, for example, shared by multiple blocks BLK. Word lines WL0 to WL7 are respectively connected to memory cell transistors MT0 to MT7 in each NAND string NS. Select gate lines SGD0 to SGD4 are respectively connected to the gates of the multiple select transistors ST1 contained in string cells SU0 to SU4. Select gate line SGS is connected to the gate of select transistor ST2 in each NAND string NS.

[0159] In this specification, a collection of multiple memory cell transistors MT contained in the same string cell SU and connected to the same word line WL is referred to as a "cell set CU". In the storage device 20, each memory cell transistor MT stores 5 bits of data. That is, each cell set CU can store 5 pages of data. In addition, the circuit configuration of the memory cell array 207 can also be other circuit configurations. The number of string cells SU contained in each BLK, and the number of memory cell transistors MT contained in each NAND string NS, as well as the number of each transistor of the selection transistors ST1 and ST2, can be freely designed.

[0160] (Circuit configuration of line decoder module 208)

[0161] Figure 5 This is a circuit diagram illustrating an example of the circuit configuration of the line decoder module 208 included in the storage device 20 of the first embodiment. Figure 5 The diagram illustrates the connection relationships between the line decoder module 208 and the driver circuit 206 and the memory cell array 207, respectively, as well as the detailed circuit configuration of line decoder RD0 among line decoders RD0 to RDn. Figure 5 As shown, each row decoder RD is connected to the driver circuit 206 via signal lines CG0-CG11, SGDD0-SGDD4, SGSD, USGD, and USGS. Each row decoder RD is connected to the associated block BLK via word lines WL0-WL7 and select gate lines SGS and SGD0-SGD4.

[0162] The following section describes the connection relationships between the various elements of the line decoder RD0 and the driver circuit 206 and block BLK0, taking the line decoder RD0 as an example. The line decoder RD0 includes transistors TR0 to TR19, transmission gate lines TG and bTG, and block decoder BD. Transistors TR0 to TR19 are all high-voltage N-type MOS (Metal Oxide Semiconductor) transistors.

[0163] The drain and source of transistor TR0 are connected to signal line SGSD and select gate line SGS, respectively. The drains of transistors TR1 through TR8 are connected to signal lines CG0 through CG7, respectively. The sources of transistors TR1 through TR8 are connected to word lines WL0 through WL7, respectively. The drains of transistors TR9 through TR13 are connected to signal lines SGDD0 through SGDD4, respectively. The sources of transistors TR9 through TR13 are connected to select gate lines SGD0 through SGD4, respectively. The drain and source of transistor TR14 are connected to signal line USGS and select gate line SGS, respectively. The drains of transistors TR15 through TR19 are connected to signal line USGD, respectively. The sources of transistors TR15 through TR19 are connected to select gate lines SGD0 through SGD4, respectively. The gates of transistors TR0 through TR13 are connected to the transmission gate line TG, respectively. The gates of transistors TR14 through TR19 are connected to the transmission gate line bTG, respectively.

[0164] The block decoder (BD) is a decoder that decodes block addresses. Based on the decoding result of the block address, the block decoder (BD) applies specified voltages to the transmit gate lines TG and bTG. Specifically, the block decoder (BD) corresponding to the selected block BLK applies "H" and "L" level voltages to the transmit gate lines TG and bTG, respectively. The block decoder (BD) corresponding to the unselected block BLK applies "L" and "H" level voltages to the transmit gate lines TG and bTG, respectively. Thus, the voltages of signal lines CG0 to CG7 are transmitted to the word lines WL0 to WL7 of the selected block BLK, the voltages of signal lines SGDD0 to SGDD4 and SGSD are transmitted to the select gate lines SGD0 to SGD4 and SGS of the selected block BLK, respectively, and the voltages of signal lines USGD and USGS are transmitted to the select gate lines SGD and SGS of the unselected block BLK, respectively.

[0165] Furthermore, the line decoder module 208 can also be configured with other circuits. For example, the number of transistors TR included in the line decoder module 208 can be varied according to the number of wirings provided in each BLK block. Signal line CG is shared by multiple BLK blocks, and therefore can also be called a "global word line". Word line WL is provided separately for each block, and therefore can also be called a "local word line". Signal lines SGDD and SGSD are shared by multiple BLK blocks, and therefore can also be called "global transmission gate lines". Select gate lines SGD and SGS are provided separately for each block, and therefore can also be called "local transmission gate lines".

[0166] (Circuit configuration of the sensing amplifier module 209)

[0167] Figure 6This is a circuit diagram illustrating an example of the circuit configuration of the sensing amplifier module 209 included in the storage device 20 of the first embodiment. Figure 6 The circuit configuration of a single sense amplifier unit (SAU) is illustrated in the diagram. Figure 6 As shown, the sense amplifier unit SAU includes a sense amplifier section SA, a bit line connection section BLHU, latch circuits SDL, ADL, BDL, CDL, DDL, EDL and XDL, and a bus LBUS. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, DDL, EDL and XDL are configured to transmit and receive data via the bus LBUS.

[0168] The sensing amplifier section SA is a circuit used to determine data based on the voltage of the bit line BL and to apply voltage to the bit line BL. If the control signal STB is active during a readout operation, the sensing amplifier section SA determines whether the data read from the selected memory cell transistor MT is "0" or "1" based on the voltage of the associated bit line BL. The latch circuits SDL, ADL, BDL, CDL, DDL, EDL, and XDL are all circuits that can temporarily store data. The latch circuit XDL is used to input and output data DAT between the sensing amplifier unit SAU and the input / output circuit 201. The latch circuit XDL can also be used as a cache memory. The storage device 20 can be ready as long as at least the latch circuit XDL is idle.

[0169] The sensing amplifier section SA includes transistors T0 to T7, capacitor CP, and nodes ND1, ND2, SEN, and SRC. The bit line connection section BLHU includes transistor T8. The latch circuit SDL includes inverters IV0 and IV1, transistors T10 and T11, and nodes SINV and SLAT. Transistor T0 is a P-type MOS transistor. Transistors T1 to T8, T10, and T11 are all N-type MOS transistors. Transistor T8 is an N-type MOS transistor with a higher voltage rating than the N-type transistors in the sensing amplifier section SA.

[0170] The gate of transistor T0 is connected to node SINV. The source of transistor T0 is connected to the power supply line. The drain of transistor T0 is connected to node ND1. Node ND1 is connected to the drains of transistors T1 and T2 respectively. The sources of transistors T1 and T2 are connected to nodes ND2 and SEN respectively. Nodes ND2 and SEN are connected to the source and drain of transistor T3 respectively. Node ND2 is connected to the drains of transistors T4 and T5 respectively. The source of transistor T5 is connected to node SRC. The gate of transistor T5 is connected to node SINV. Node SEN is connected to the gate of transistor T6 and one electrode of capacitor CP. The source of transistor T6 is grounded. The drain and source of transistor T7 are connected to the bus LBUS and the drain of transistor T6 respectively. The drain of transistor T8 is connected to the source of transistor T4. The source of transistor T8 is connected to the associated bit line BL.

[0171] Apply a power supply voltage VDD to the source of transistor T0, for example. Apply a ground voltage VSS to node SRC, for example. Input control signals BLX, HLL, XXL, BLC, and STB to the gates of transistors T1, T2, T3, T4, and T7, respectively. Input a control signal BLS to the gate of transistor T8. Input a clock signal CLK to the other electrode of capacitor CP.

[0172] The input node of inverter IV0 is connected to node SLAT. The output node of inverter IV0 is connected to node SINV. The input node of inverter IV1 is connected to node SINV. The output node of inverter IV1 is connected to node SLAT. One end of transistor T10 is connected to node SINV. The other end of transistor T10 is connected to the bus LBUS. A control signal STI is input to the gate of transistor T10. One end of transistor T11 is connected to node SLAT. The other end of transistor T11 is connected to the bus LBUS. A control signal STL is input to the gate of transistor T11. The latch circuit SDL stores data at node SLAT and stores the inverted data stored at node SINV.

[0173] The circuit configurations of latch circuits ADL, BDL, CDL, DDL, EDL, and XDL are similar to those of latch circuit SDL. For example, latch circuit ADL stores data at node ALAT and its inverted data at node AINV. Furthermore, control signals ATI and ATL are input to the gate of transistor T10 and T11, respectively, in latch circuit ADL. Latch circuit BDL stores data at node BLAT and its inverted data at node BINV. Control signals BTI and BTL are input to the gate of transistor T10 and T11, respectively, in latch circuit BDL. Latch circuits CDL, DDL, and EDL are similar, therefore their descriptions are omitted.

[0174] Furthermore, control signals BLX, HLL, XXL, BLC, STB, BLS, STI, and STL, as well as the clock signal CLK, are generated by sequencer 204. The sense amplifier module 209 can also be configured with other circuits. For example, each sense amplifier unit SAU may have eight or more latch circuits. The sense amplifier unit SAU may also have an arithmetic circuit capable of performing simple logic operations. In this specification, activating the control signal corresponds to temporarily changing a voltage at the "L" level to the "H" level. When transistor T6 is a P-type transistor, activating the control signal STB corresponds to temporarily changing a voltage at the "H" level to the "L" level. During the readout operation of each page, the sense amplifier module 209 appropriately performs arithmetic processing using the latch circuit, thereby determining the data stored in the memory cell transistor MT.

[0175] [1-1-5] Threshold voltage distribution of memory cell transistor MT

[0176] Figure 7 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors MT in the memory device 20 of the first embodiment. The vertical axis, "NMTs," represents the number of memory cell transistors MT. The horizontal axis, "Vth," represents the threshold voltage of the memory cell transistors MT. Figure 7 As shown, the threshold voltage distribution of the memory cell transistor MT in the memory device 20 can be sequentially formed into states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30 and S31 in order of threshold voltage from low to high.

[0177] Furthermore, in the storage device 20, read voltages R1 to R31 and a read pass voltage VREAD are set for states S0 to S31. Specifically, read voltage R1 is set between states S0 and S1, read voltage R2 is set between states S1 and S2, read voltage R3 is set between states S2 and S3, read voltage R4 is set between states S3 and S4, ..., read voltage R30 is set between states S29 and S30, and read voltage R30 is set between states S30 and S31. The read pass voltage VREAD is set to a voltage higher than that of state S31, which has the highest threshold voltage among states S0 to S31. The storage cell transistor MT with the read pass voltage VREAD applied to its gate is turned on regardless of the data to be stored. Furthermore, verification voltages are set between adjacent states. Specifically, in the write operation, the verification operation (verification read) for each of the states “S1” to “S31” is performed using verification voltages V1 to V31 respectively.

[0178] also, Figure 7 The set of readout voltages R1 to R31 shown can also include negative voltages. A set of readout voltages R1 to R31 can also be a combination of negative voltages, 0V, and positive voltages. That is, within a set of readout voltages R1 to R31, some readout voltages can be negative, while the others can be 0V or positive. For example, readout voltages R1 to R4 could all be negative, readout voltage R5 could be 0V, and readout voltages R6 to R31 could all be positive. Alternatively, a set of readout voltages R1 to R31 could not include 0V, but only include negative and positive voltages.

[0179] Assign any one of the datasets D0 to D31 to each of the states S0 to S31. Datasets D0 to D31 correspond to 32 distinct sets of 5-bit data. Datasets D0 to D31 each contain the 1st to 5th bits of data. The specific data contents of each of datasets D0 to D31 are listed below.

[0180] (Example) Dataset: "1st data point / 2nd data point / 3rd data point / 4th data point / 5th data point"

[0181] D0: "00000"

[0182] D1: "00001"

[0183] D2: "00010"

[0184] D3: "00011"

[0185] D4: "00100"

[0186] D5: "00101"

[0187] D6: "00110"

[0188] D7: "00111"

[0189] D8: "01000"

[0190] D9: "01001"

[0191] D10: "01010"

[0192] D11: "01011"

[0193] D12: "01100"

[0194] D13: "01101"

[0195] D14: "01110"

[0196] D15: "01111"

[0197] D16: "10000"

[0198] D17: "10001"

[0199] D18: "10010"

[0200] D19: "10011"

[0201] D20: "10100"

[0202] D21: "10101"

[0203] D22: "10110"

[0204] D23: "10111"

[0205] D24: "11000"

[0206] D25: "11001"

[0207] D26: "11010"

[0208] D27: "11011"

[0209] D28: "11100"

[0210] D29: "11101"

[0211] D30: "11110"

[0212] D31: "11111".

[0213] [1-1-6] Data Allocation

[0214] Figure 8 This is a table showing the data allocation and readout voltage settings used in the storage device 20 of the first embodiment. The storage device 20 of the first embodiment uses a data allocation of 5 pages of data stored in one unit set (CU), i.e., a 5-bit / unit encoding. Hereinafter, refer to... Figure 8 The data allocation and readout voltage setting of the first embodiment will be explained.

[0215] Furthermore, the "State ID" shown in the accompanying drawings referenced in this specification corresponds to the number following the reference symbol "S" indicating the state. The "Dataset ID" shown in the accompanying drawings referenced in this specification corresponds to the number following the reference symbol "D" indicating the dataset. "Page 1 (Page 1 Data PG1)" corresponds to the group of the first data bit stored in the cell set CU. "Page 2 (Page 2 Data PG2)" corresponds to the group of the second data bit stored in the cell set CU. "Page 3 (Page 3 Data PG3)" corresponds to the group of the third data bit stored in the cell set CU. "Page 4 (Page 4 Data PG4)" corresponds to the group of the fourth data bit stored in the cell set CU. "Page 5 (Page 5 Data PG5)" corresponds to the group of the fifth data bit stored in the cell set CU. Hereinafter, the readout operation targeting pages 1 to 5 will be referred to as page 1 to page 5 readout.

[0216] In the data allocation of the first embodiment, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D9, D1, D3, D19, D23, D21, D20, D4, D12, D14, D10, D2, D0, D16, D17, D25, D29, D13, D5, D7, D6, D22, D18, D26, D27, D11, and D15 are assigned in S30 and S31.

[0217] In the data allocation of the first embodiment, the read voltages used for reading the first page are R4, R8, R12, R18, R22, R26, and R30. In the data allocation of the first embodiment, the read voltages used for reading the second page are R6, R13, R16, R20, R23, and R28. In the data allocation of the first embodiment, the read voltages used for reading the third page are R3, R9, R15, R21, R27, and R31. In the data allocation of the first embodiment, the read voltages used for reading the fourth page are R2, R7, R10, R14, R17, and R24. In the data allocation of the first embodiment, the read voltages used for reading the fifth page are R1, R5, R11, R19, R25, and R29.

[0218] In the first page readout, the data is determined through 7 readouts. In the second, third, fourth, and fifth page readouts, the data is determined through 6 readouts each. This data allocation is, for example, called "7-6-6-6-6 encoding". In the data allocation of the first embodiment, the difference between the maximum and minimum number of readouts set for determining data between pages is "1". Furthermore, in the data allocation of the first embodiment, the minimum interval between the readout voltages of each page is "3" and the maximum is "8".

[0219] Furthermore, in this specification, the "number of reads" for each page's readout operation corresponds to the number of times the control signal STB is activated. In other words, the "number of reads" corresponds to the number of times the operation of determining a threshold voltage using a certain readout voltage is performed. The operation of determining data based on a certain readout voltage during the period when that readout voltage is applied can also be simply referred to as "reading". The "interval between readout voltages" corresponds to the value of an unused readout voltage among two adjacent readout voltages used in the readout operation of a page. In other words, the "interval between readout voltages" corresponds to the number of states configured between adjacent readout voltages in the readout operation of each page. For example, since there are four states S4 to S7 configured between readout voltages R4 and R8, the interval between readout voltages R4 and R8 in the first page readout is "4 (4 states)". Since there are 6 states S12 to S17 between the read voltages R12 and R18, the interval between the read voltages R12 and R18 in the first page readout is "6 (6 states)".

[0220] [1-2] Actions

[0221] The operation of the memory system MS according to the first embodiment will now be described. The selected word line WL will be referred to as "select word line WLsel". The sequencer 204 applies a voltage to the select word line WLsel, corresponding to the voltage applied by the driver circuit 206 via the row decoder module 208 based on the control of the sequencer 204. The address information ADD and instruction CMD received by the memory device 20 are transmitted to the register circuit 203. In the accompanying drawings, "tR" indicates the period (time) during which the memory device 20 is in a busy state based on the instruction of the memory controller 10.

[0222] The details of reading pages 1 to 5 in the first embodiment will be described below. This specification illustrates the case where the voltage of the source line SL is fixed during reading from pages 1 to 5. Furthermore, the accompanying drawings shown below illustrate the case where the voltage of the selection word line WLsel is the ground voltage VSS at the beginning and end of the reading operation. However, this is not a limitation; the voltage of the selection word line WLsel may also be negative at the beginning and end of the reading operation.

[0223] [1-2-1] Read page 1

[0224] Figure 9 This is a timing diagram illustrating an example of reading the first page in the memory system MS of the first embodiment. Figure 9 The transitions of the input / output signals I / O, the ready / busy signal RBn, the select word line WLsel, and the control signal STB during the first page readout of the first embodiment are shown respectively. Below, refer to... Figure 9 The reading of the first page of the first embodiment will be explained.

[0225] When performing a page 1 read, the memory controller 10 sequentially sends instructions "01h", "00h", address "ADD", and "30h" to the memory device 20. Instruction "01h" specifies that the page 1 operation has been selected. Instruction "00h" specifies the read operation. Address "ADD" contains the address of the word line WL to be read. Instruction "30h" indicates the start of the read operation.

[0226] After receiving the instruction "30h", the sequencer 204, based on the instruction and address stored in the register circuit 203, changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 sequentially applies read voltages R4, R8, R12, R18, R22, R26, and R30 to the select word line WLsel. Additionally, during each period of applying read voltages R4, R8, R12, R18, R22, R26, and R30, the sequencer 204 activates the control signal STB. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (judges) the first bit of data read from the memory cell transistor MT connected to the select word line WLsel and stores the determination result in the latch circuit XDL.

[0227] After the sequencer 204 stores the determination result of the first bit of data in the latch circuit XDL, it causes the storage device 20 to change from a busy state to a ready state. Then, based on the fact that the storage device 20 has changed from a busy state to a ready state, the memory controller 10 commands the storage device 20 to output the data DAT (page 1 data PG1) stored in each latch circuit XDL of the sense amplifier module 209. For example, the memory controller 10 can cause the storage device 20 to output the data DAT sequentially by switching the control signal REn. After receiving the page 1 data PG1, the memory controller 10, for example, transmits the page 1 data PG1 to the host device HD and ends the page 1 read.

[0228] [1-2-2] Read from page 2

[0229] Figure 10 This is a timing diagram illustrating an example of reading the second page in the memory system MS of the first embodiment. Figure 10 The transitions of the input / output signals I / O, the ready / busy signal RBn, the select word line WLsel, and the control signal STB during the readout on page 2 of the first embodiment are shown respectively. Below, refer to... Figure 10 The reading of page 2 of the first embodiment will be explained.

[0230] When performing a second page read, the memory controller 10 sequentially sends instructions "02h", "00h", address "ADD", and "30h" to the memory device 20. Instruction "02h" is an instruction that specifies the selection of the second page.

[0231] After receiving the instruction "30h", the sequencer 204, based on the instruction and address stored in the register circuit 203, changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 sequentially applies read voltages R6, R13, R16, R20, R23, and R28 to the select word line WLsel. Additionally, during each period of applying read voltages R6, R13, R16, R20, R23, and R28, the sequencer 204 activates the control signal STB. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (judges) the second bit of data read from the memory cell transistor MT connected to the select word line WLsel, and stores the determination result in the latch circuit XDL.

[0232] After the sequencer 204 stores the determination result of the second bit of data into the latch circuit XDL, it causes the storage device 20 to change from a busy state to a ready state. Then, based on the fact that the storage device 20 has changed from a busy state to a ready state, the memory controller 10 commands the storage device 20 to output the data DAT (page 2 data PG2) stored in each latch circuit XDL of the sense amplifier module 209. After receiving the page 2 data PG2, the memory controller 10, for example, transmits the page 2 data PG2 to the host device HD and ends the page 2 read.

[0233] [1-2-3] Read page 3

[0234] Figure 11 This is a timing diagram illustrating an example of reading the third page in the memory system MS of the first embodiment. Figure 11 The transitions of the input / output signals I / O, the ready / busy signal RBn, the select word line WLsel, and the control signal STB during the readout on page 3 of the first embodiment are shown respectively. Below, refer to... Figure 11 The reading of page 3 of the first embodiment will be explained.

[0235] When performing a page 3 read operation, the memory controller 10 sequentially sends instructions "03h", "00h", address "ADD", and "30h" to the memory device 20. Instruction "03h" is an instruction that specifies the selection of the page 3 operation.

[0236] After receiving the instruction "30h", the sequencer 204, based on the instruction and address stored in the register circuit 203, changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 sequentially applies read voltages R3, R9, R15, R21, R27, and R31 to the select word line WLsel. Additionally, during each period of applying read voltages R3, R9, R15, R21, R27, and R31, the sequencer 204 activates the control signal STB. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (judges) the third bit of data read from the memory cell transistor MT connected to the select word line WLsel, and stores the determination result in the latch circuit XDL.

[0237] After the sequencer 204 stores the determination result of the third bit of data into the latch circuit XDL, it causes the storage device 20 to change from a busy state to a ready state. Then, based on the fact that the storage device 20 has changed from a busy state to a ready state, the memory controller 10 commands the storage device 20 to output the data DAT (page 3 data PG3) stored in each latch circuit XDL of the sense amplifier module 209. After receiving the page 3 data PG3, the memory controller 10, for example, transmits the page 3 data PG3 to the host device HD and ends the page 3 read.

[0238] [1-2-4] Read from page 4

[0239] Figure 12 This is a timing diagram illustrating an example of reading page 4 from the storage device of the first embodiment. Figure 12 The transitions of the input / output signals I / O, the ready / busy signal RBn, the select word line WLsel, and the control signal STB during the readout on page 4 of the first embodiment are shown respectively. Below, refer to... Figure 12 The reading of page 4 of the first embodiment will be explained.

[0240] When performing a page 4 read operation, the memory controller 10 sequentially sends instructions "04h", "00h", address "ADD", and "30h" to the memory device 20. Instruction "04h" is an instruction that specifies the selection of the page 4 operation.

[0241] After receiving the instruction "30h", the sequencer 204, based on the instruction and address stored in the register circuit 203, changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 sequentially applies read voltages R2, R7, R10, R14, R17, and R24 to the select word line WLsel. Additionally, during each period of applying read voltages R2, R7, R10, R14, R17, and R24, the sequencer 204 activates the control signal STB. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (judges) the fourth bit of data read from the storage cell transistor MT connected to the select word line WLsel, and stores the determination result in the latch circuit XDL.

[0242] After the sequencer 204 stores the determination result of the fourth bit of data into the latch circuit XDL, it causes the storage device 20 to change from a busy state to a ready state. Then, based on the fact that the storage device 20 has changed from a busy state to a ready state, the memory controller 10 commands the storage device 20 to output the data DAT (page 4 data PG4) stored in each latch circuit XDL of the sense amplifier module 209. After receiving the page 4 data PG4, the memory controller 10 transmits the page 4 data PG4 to the host device HD, for example, and ends the page 4 read.

[0243] [1-2-5] Read from page 5

[0244] Figure 13 This is a timing diagram illustrating an example of reading page 5 from the storage device of the first embodiment. Figure 13 The transitions of the input / output signals I / O, the ready / busy signal RBn, the select word line WLsel, and the control signal STB during the readout on page 5 of the first embodiment are shown respectively. Below, refer to... Figure 13 The reading of page 5 of the first embodiment will be explained.

[0245] When performing a page 5 read operation, the memory controller 10 sequentially sends instructions "05h", "00h", address "ADD", and "30h" to the memory device 20. Instruction "05h" specifies that the operation of reading page 5 has been selected.

[0246] After receiving the instruction "30h", the sequencer 204, based on the instruction and address stored in the register circuit 203, changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 sequentially applies read voltages R1, R5, R11, R19, R25, and R29 to the select word line WLsel. Additionally, during each period of applying read voltages R1, R5, R11, R19, R25, and R29, the sequencer 204 activates the control signal STB. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (judges) the 5th bit of data read from the memory cell transistor MT connected to the select word line WLsel, and stores the determination result in the latch circuit XDL.

[0247] After the sequencer 204 stores the determination result of the 5th bit data into the latch circuit XDL, it causes the storage device 20 to change from a busy state to a ready state. Then, based on the fact that the storage device 20 has changed from a busy state to a ready state, the memory controller 10 commands the storage device 20 to output the data DAT (page 5 data PG5) stored in each latch circuit XDL of the sense amplifier module 209. After receiving the page 5 data PG5, the memory controller 10 transmits the page 5 data PG5 to the host device HD, for example, and ends the page 5 read.

[0248] [1-3] Effects of the first embodiment

[0249] The storage device 20 according to the first embodiment described above can perform the read operation with better efficiency. The detailed effects of the first embodiment will now be explained.

[0250] In memory-specific data allocation, the 5-bit data allocated to a certain state is set by differing by 1 bit from the 5-bit data allocated to adjacent states. There are over 10 million possible 5-bit / unit codes for memory-specific data allocation without considering page allocation. Even considering page allocation, there are still approximately 100,000 possible 5-bit / unit codes.

[0251] Efficient read voltage distribution preferably involves averaging the number of reads per page and averaging the interval between read voltages per page. Averaging the number of reads per page averages the probability of defects occurring per page. Averaging the interval between read voltages per page reduces read noise and averages the settling time of the read voltage. Furthermore, averaging the settling time shortens the read operation time per page, thus improving the read operation latency of the storage device 20.

[0252] To achieve a 5-bit / unit encoding, ideally, the number of reads should be (PG1, PG2, PG3, PG4, PG5) = (7, 6, 6, 6, 6), with a minimum read voltage interval of "4" between pages, and the maximum interval should be as small as possible. The optimal minimum read voltage interval of "4" is based on the fact that there are 31 possible read voltages in a 5-bit / unit encoding, and dividing "31" by the maximum read count of "7" yields a result close to "4". However, a data allocation with a read count of (PG1, PG2, PG3, PG4, PG5) = (7, 6, 6, 6, 6) and a minimum read voltage interval of "4" between pages does not exist.

[0253] Furthermore, when using the lowest read voltage R1 to determine data, there is a tendency for the upward spread of the lowest state S0, leading to a higher probability of defects. When using the highest read voltage R31 to determine data, there is a tendency for the downward spread of the highest state S31, leading to a higher probability of defects. Pages read 7 times tend to have a higher probability of defects than pages read 6 times. Therefore, in the memory, for pages read 7 times, it is preferable to set the interval of the read voltage evenly and not use the lowest or highest read voltage among the 31 read voltages.

[0254] In contrast, the data allocation in the storage device 20 of the first embodiment is set to conditions close to ideal. Specifically, regarding the data allocation of the first embodiment, the number of reads is (PG1, PG2, PG3, PG4, PG5) = (7, 6, 6, 6, 6), and the interval between the read voltages of each page is at least "3" and at most "8". Moreover, in the first page with 7 reads, the lowest read voltage is R4, and the highest read voltage is R30. That is, in the first page read of the first embodiment, the lowest read voltage R4 is set to be 3 states apart from R1, and the highest read voltage R30 is set to be 1 state apart from R31.

[0255] As a result, in the storage device 20 of the first embodiment, the number of reads per page is averaged, and the probability of defects occurring per page is averaged. By averaging the probability of defects, the storage device 20 can suppress retries during read operations, thereby improving latency. By suppressing the interval of the read voltage to a minimum of "3" and a maximum of "8", the setting time of the read voltage for each page becomes approximately average in the storage device 20. Therefore, the storage device 20 can shorten the read operation time. Therefore, the storage device 20 of the first embodiment can perform read operations more efficiently.

[0256] [1-4] Examples of variations of the first embodiment

[0257] In addition, there are data allocation methods that can perform the read operation more efficiently, similar to the first embodiment. Hereinafter, we will describe the 1st to 17th variations of the data allocation method as variations of the first embodiment.

[0258] (Example 1 of the variations)

[0259] Figure 14 This is a table showing the data allocation and readout voltage settings for the first variation example. See below for reference. Figure 14 The data allocation and readout voltage setting for the first variation example are explained.

[0260] In the data allocation of the first variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D23, D7, D5, D1, D9, D25, D27, D26, D10, D14, D6, D4, D20, D21, and D29 to datasets S30 and S31.

[0261] In the data allocation of the first variation example, the readout voltages used for reading page 1 are R7, R15, R18, R22, R25, and R29. In the data allocation of the first variation example, the readout voltages used for reading page 2 are R4, R8, R13, R21, R27, and R31. In the data allocation of the first variation example, the readout voltages used for reading page 3 are R3, R9, R12, R16, R20, and R26. In the data allocation of the first variation example, the readout voltages used for reading page 4 are R2, R6, R10, R14, R19, R23, and R28. In the data allocation of the first variation example, the readout voltages used for reading page 5 are R1, R5, R11, R17, R24, and R30.

[0262] Figure 15 This is a waveform diagram illustrating an example of the voltage applied to the select word line WLsel during the readout operation of the first variation example (readout waveform). In the readouts on pages 1 to 5 of the first variation example, the sequencer 204 is as follows... Figure 15 As shown, a readout voltage is applied to the select word line WLsel, thereby enabling the desired page data to be read from the cell set CU. Except for the type of readout voltage applied to the select word line WLsel during each page readout, the other operations are the same as in the first embodiment and the first variation.

[0263] (Second variation example)

[0264] Figure 16 This is a table showing the data allocation and readout voltage settings for the second variation example. See below for reference. Figure 16 The data allocation and readout voltage setting for the second variation example will be explained.

[0265] In the data allocation of the second variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D8, D9, D1, D5, D7, D23, D19, D18, D26, D10, D14, D12, D4, D0, D16, D17, D25, D27, D11, D3, D2, D6, D22, D20, D21, D29, D13, and D15 to datasets S30 and S31.

[0266] In the data allocation of the second variation, the readout voltages used for reading page 1 are R4, R9, R13, R18, R22, R26, and R30. In the data allocation of the second variation, the readout voltages used for reading page 2 are R6, R12, R16, R20, R23, and R29. In the data allocation of the second variation, the readout voltages used for reading page 3 are R3, R7, R10, R14, R17, and R25. In the data allocation of the second variation, the readout voltages used for reading page 4 are R2, R8, R15, R21, R27, and R31. In the data allocation of the second variation, the readout voltages used for reading page 5 are R1, R5, R11, R19, R24, and R28.

[0267] Figure 17 This is a waveform diagram illustrating an example of the voltage applied to the select word line WLsel during the readout operation of the second variation (readout waveform). In the readouts on pages 1 to 5 of the second variation, the sequencer 204 is as follows... Figure 17 As shown, a readout voltage is applied to the select word line WLsel, thereby enabling the desired page data to be read from the cell set CU. Except for the type of readout voltage applied to the select word line WLsel during each page readout, the other operations are the same in the first embodiment and the second variation.

[0268] (Example 3)

[0269] Figure 18 This is a table showing the data allocation and readout voltage settings for the third variation example. See below for reference. Figure 18 The data allocation and readout voltage setting for the third variation example are explained.

[0270] In the data allocation of the third variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D16, D17, D19, D23, D7, D15, D13, D12, D4, D0, D2, D18, D26, D27, D11, D3, D1, D5, D21, D20, D22, D6, D14, D10, D8, D9, D25, and D29 to datasets S30 and S31.

[0271] In the data allocation of the third variation, the read voltages used for reading page 1 are R8, R15, R18, R22, R25, and R30. In the data allocation of the third variation, the read voltages used for reading page 2 are R4, R9, R12, R16, R19, and R26. In the data allocation of the third variation, the read voltages used for reading page 3 are R3, R7, R13, R21, R27, and R31. In the data allocation of the third variation, the read voltages used for reading page 4 are R2, R6, R10, R14, R20, R24, and R28. In the data allocation of the third variation, the read voltages used for reading page 5 are R1, R5, R11, R17, R23, and R29.

[0272] Figure 19 This is a waveform diagram illustrating an example of the voltage applied to the select word line WLsel during the readout operation of the third variation (readout waveform). In the readouts on pages 1 to 5 of the third variation, the sequencer 204 is as follows... Figure 19 As shown, a readout voltage is applied to the select word line WLsel, thereby enabling the desired page data to be read from the cell set CU. Except for the type of readout voltage applied to the select word line WLsel during each page readout, the other operations are the same in the first embodiment and the third variation.

[0273] (Example 4)

[0274] Figure 20 This is a table showing the data allocation and readout voltage settings for the fourth variation example. See below for reference. Figure 20 The data allocation and readout voltage setting for the fourth variation example will be explained.

[0275] In the data allocation of the fourth variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D25, D17, D19, D23, D7, D15, D14, D12, D4, D0, D16, D18, D26, D27, D11, D3, D1, D5, D21, D20, D22, D6, D2, D10, D8, D9, D13, and D29 to datasets S30 and S31.

[0276] In the data allocation of the fourth variation, the read voltages used for reading page 1 are R8, R14, R18, R22, R25, and R31. In the data allocation of the fourth variation, the read voltages used for reading page 2 are R5, R9, R12, R16, R19, and R27. In the data allocation of the fourth variation, the read voltages used for reading page 3 are R3, R7, R13, R21, R26, and R30. In the data allocation of the fourth variation, the read voltages used for reading page 4 are R2, R6, R11, R15, R20, R24, and R28. In the data allocation of the fourth variation, the read voltages used for reading page 5 are R1, R4, R10, R17, R23, and R29.

[0277] Figure 21 This is a waveform diagram illustrating an example of the voltage applied to the select word line WLsel during the readout operation of the fourth variation (readout waveform). In the readouts on pages 1-5 of the fourth variation, the sequencer 204 is as follows... Figure 21 As shown, a readout voltage is applied to the select word line WLsel, thereby enabling the desired page data to be read from the cell set CU. Except for the type of readout voltage applied to the select word line WLsel during each page readout, the other operations are the same in the first embodiment and the fourth variation.

[0278] (5th variation example)

[0279] Figure 22 This is a table showing the data allocation and readout voltage settings for the fifth variation example. See below for reference. Figure 22 The data allocation and readout voltage setting for the fifth variation example are explained.

[0280] In the data allocation of the fifth variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D8, D0, D2, D3, D19, D23, D22, D20, D4, D12, D13, D9, D1, D17, D16, D18, D26, D10, D14, D6, D7, D5, D21, D29, D25, D27, D11, and D15 to S30 and S31.

[0281] In the data allocation of the fifth variation, the read voltages used for reading page 1 are R4, R8, R12, R17, R21, R26, and R30. In the data allocation of the fifth variation, the read voltages used for reading page 2 are R5, R13, R16, R20, R23, and R27. In the data allocation of the fifth variation, the read voltages used for reading page 3 are R3, R9, R15, R22, R28, and R31. In the data allocation of the fifth variation, the read voltages used for reading page 4 are R2, R6, R11, R19, R25, and R29. In the data allocation of the fifth variation, the read voltages used for reading page 5 are R1, R7, R10, R14, R18, and R24.

[0282] Figure 23 This is a waveform diagram illustrating an example of the voltage applied to the select word line WLsel during the readout operation of the fifth variation (readout waveform). In the readouts on pages 1 to 5 of the fifth variation, the sequencer 204 is as follows... Figure 23 As shown, a readout voltage is applied to the select word line WLsel, thereby enabling the desired page data to be read from the cell set CU. Except for the type of readout voltage applied to the select word line WLsel during each page readout, the other operations are the same in the first embodiment and the fifth variation.

[0283] (Sixth variation example)

[0284] Figure 24 This is a table showing the data allocation and readout voltage settings for the sixth variation example. See below for reference. Figure 24 The data allocation and readout voltage setting for the sixth variation example are explained.

[0285] In the data allocation of the sixth variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D20, D4, D5, D1, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21, and D29 to datasets S30 and S31.

[0286] In the data allocation of the sixth variation, the readout voltages used for reading page 1 are R7, R15, R18, R22, R25, and R29. In the data allocation of the sixth variation, the readout voltages used for reading page 2 are R4, R8, R13, R21, R27, and R31. In the data allocation of the sixth variation, the readout voltages used for reading page 3 are R3, R9, R12, R16, R20, and R26. In the data allocation of the sixth variation, the readout voltages used for reading page 4 are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the sixth variation, the readout voltages used for reading page 5 are R1, R5, R11, R19, R24, and R28.

[0287] (Seventh variation example)

[0288] Figure 25 This is a table showing the data allocation and readout voltage settings for the 7th variation example. See below for reference. Figure 25 The data allocation and readout voltage setting for the 7th variation example are explained.

[0289] In the data allocation of the 7th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D10, D26, D18, D22, D20, D4, D0, D2, D3, D19, D27, D25, D9, D8, D12, D14, D6, D7, D23, D21, and D29 to datasets S30 and S31.

[0290] In the data allocation of the 7th variation, the read voltages used for reading page 1 are R6, R12, R16, R20, R23, and R29. In the data allocation of the 7th variation, the read voltages used for reading page 2 are R4, R8, R13, R21, R27, and R31. In the data allocation of the 7th variation, the read voltages used for reading page 3 are R3, R7, R10, R14, R17, and R25. In the data allocation of the 7th variation, the read voltages used for reading page 4 are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the 7th variation, the read voltages used for reading page 5 are R1, R5, R11, R19, R24, and R28.

[0291] (8th variation example)

[0292] Figure 26 This is a table showing the data allocation and readout voltage settings for the 8th variation example. See below for reference. Figure 26 The data allocation and readout voltage setting for the 8th variation example are explained.

[0293] In the data allocation of the 8th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S20 are respectively assigned. Assign datasets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D3, D19, D18, D22, D20, D4, D12, D14, D10, D26, D27, D25, D9, D8, D0, D2, D6, D7, D23, D21, and D29 to datasets S30 and S31.

[0294] In the data allocation of the 8th variation, the read voltages used for reading page 1 are R6, R12, R16, R20, R23, and R29. In the data allocation of the 8th variation, the read voltages used for reading page 2 are R4, R8, R11, R17, R25, and R31. In the data allocation of the 8th variation, the read voltages used for reading page 3 are R3, R7, R10, R14, R19, and R27. In the data allocation of the 8th variation, the read voltages used for reading page 4 are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the 8th variation, the read voltages used for reading page 5 are R1, R5, R13, R21, R24, and R28.

[0295] (9th variation example)

[0296] Figure 27 This is a table showing the data allocation and readout voltage settings for the 9th variation example. See below for reference. Figure 27 The data allocation and readout voltage setting for the 9th variation example are explained.

[0297] In the data allocation of the 9th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, and S10 are respectively assigned. Assign datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D5, D1, D0, D2, D18, D22, D20, D4, D12, D8, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21, and D29 to datasets S30 and S31.

[0298] In the data allocation of the 9th variation, the read voltages used for reading page 1 are R7, R15, R18, R22, R25, and R29. In the data allocation of the 9th variation, the read voltages used for reading page 2 are R4, R8, R11, R19, R27, and R31. In the data allocation of the 9th variation, the read voltages used for reading page 3 are R3, R9, R12, R16, R20, and R26. In the data allocation of the 9th variation, the read voltages used for reading page 4 are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the 9th variation, the read voltages used for reading page 5 are R1, R5, R13, R21, R24, and R28.

[0299] (Example 10)

[0300] Figure 28 This is a table showing the data allocation and readout voltage settings for the 10th variation example. See below for reference. Figure 28 The data allocation and readout voltage setting for the 10th variation example are explained.

[0301] In the data allocation for the 10th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D1, D5, D13, D15, D11, D3, D19, D18, D22, D20, D4, D0, D2, D10, D26, D27, D25, D9, D8, D12, D14, D6, D7, D23, D21, and D29 are assigned in S30 and S31.

[0302] In the data allocation of the 10th variation, the readout voltages used for reading page 1 are R6, R12, R16, R20, R23, and R29. In the data allocation of the 10th variation, the readout voltages used for reading page 2 are R4, R8, R11, R19, R27, and R31. In the data allocation of the 10th variation, the readout voltages used for reading page 3 are R3, R7, R10, R14, R17, and R25. In the data allocation of the 10th variation, the readout voltages used for reading page 4 are R2, R9, R15, R18, R22, R26, and R30. In the data allocation of the 10th variation, the readout voltages used for reading page 5 are R1, R5, R13, R21, R24, and R28.

[0303] (Example 11)

[0304] Figure 29 This is a table showing the data allocation and readout voltage settings for the 11th variation example. See below for reference. Figure 29 The data allocation and readout voltage setting for the 11th variation example are explained.

[0305] In the data allocation for the 11th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D5, D1, D17, D19, D18, D22, D20, D4, D12, D8, D9, D25, D27, D26, D10, D14, D6, D7, D23, D21, and D29 are assigned in S30 and S31.

[0306] In the data allocation of the 11th variation, the readout voltages used for reading page 1 are R5, R13, R18, R22, R25, and R29. In the data allocation of the 11th variation, the readout voltages used for reading page 2 are R4, R8, R11, R19, R27, and R31. In the data allocation of the 11th variation, the readout voltages used for reading page 3 are R3, R9, R12, R16, R20, and R26. In the data allocation of the 11th variation, the readout voltages used for reading page 4 are R2, R6, R10, R14, R17, R23, and R30. In the data allocation of the 11th variation, the readout voltages used for reading page 5 are R1, R7, R15, R21, R24, and R28.

[0307] (Example 12)

[0308] Figure 30 This is a table showing the data allocation and readout voltage settings for the 12th variation example. See below for reference. Figure 30 The data allocation and readout voltage setting for the 12th variation example are explained.

[0309] In the data allocation for the 12th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... S30 and S31 assign datasets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D23, D7, D5, D1, D9, D25, D29, D21, D20, D4, D6, D14, D10, D26, and D27.

[0310] In the data allocation of the 12th variation, the read voltages used for reading page 1 are R7, R15, R18, R22, R26, and R30. In the data allocation of the 12th variation, the read voltages used for reading page 2 are R4, R8, R13, R21, R24, and R28. In the data allocation of the 12th variation, the read voltages used for reading page 3 are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the 12th variation, the read voltages used for reading page 4 are R2, R6, R10, R14, R19, and R27. In the data allocation of the 12th variation, the read voltages used for reading page 5 are R1, R5, R11, R17, R25, and R31.

[0311] (Example 13)

[0312] Figure 31 This is a table showing the data allocation and readout voltage settings for the 13th variation example. See below for reference. Figure 31 The data allocation and readout voltage setting for the 13th variation example are explained.

[0313] In the data allocation of the 13th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D5, D1, D17, D19, D18, D22, D20, D4, D12, D8, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26, and D27 are assigned in S30 and S31.

[0314] In the data allocation of the 13th variation, the read voltages used for reading page 1 are R5, R13, R18, R22, R26, and R30. In the data allocation of the 13th variation, the read voltages used for reading page 2 are R4, R8, R11, R19, R24, and R28. In the data allocation of the 13th variation, the read voltages used for reading page 3 are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of the 13th variation, the read voltages used for reading page 4 are R2, R6, R10, R14, R17, and R25. In the data allocation of the 13th variation, the read voltages used for reading page 5 are R1, R7, R15, R21, R27, and R31.

[0315] (Example 14)

[0316] Figure 32 This is a table showing the data allocation and readout voltage settings for the 14th variation example. See below for reference. Figure 32 The data allocation and readout voltage setting for the 14th variation example are explained.

[0317] In the data allocation of the 14th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D12, D8, D0, D2, D18, D22, D20, D4, D5, D1, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26, and D27 are assigned in S30 and S31.

[0318] In the data allocation of Variation 14, the readout voltages used for reading page 1 are R7, R15, R18, R22, R26, and R30. In the data allocation of Variation 14, the readout voltages used for reading page 2 are R4, R8, R13, R21, R24, and R28. In the data allocation of Variation 14, the readout voltages used for reading page 3 are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of Variation 14, the readout voltages used for reading page 4 are R2, R6, R10, R14, R17, and R25. In the data allocation of Variation 14, the readout voltages used for reading page 5 are R1, R5, R11, R19, R27, and R31.

[0319] (Example 15)

[0320] Figure 33 This is a table showing the data allocation and readout voltage settings for the 15th variation example. See below for reference. Figure 33 The data allocation and readout voltage setting for the 15th variation example are explained.

[0321] In the data allocation of the 15th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D19, D3, D11, D15, D13, D5, D1, D0, D2, D18, D22, D20, D4, D12, D8, D9, D25, D29, D21, D23, D7, D6, D14, D10, D26, and D27 are assigned in S30 and S31.

[0322] In the data allocation of Variation 15, the readout voltages used for reading page 1 are R7, R15, R18, R22, R26, and R30. In the data allocation of Variation 15, the readout voltages used for reading page 2 are R4, R8, R11, R19, R24, and R28. In the data allocation of Variation 15, the readout voltages used for reading page 3 are R3, R9, R12, R16, R20, R23, and R29. In the data allocation of Variation 15, the readout voltages used for reading page 4 are R2, R6, R10, R14, R17, and R25. In the data allocation of Variation 15, the readout voltages used for reading page 5 are R1, R5, R13, R21, R27, and R31.

[0323] (Example 16)

[0324] Figure 34 This is a table showing the data allocation and readout voltage settings for the 16th variation example. See below for reference. Figure 34 The data allocation and readout voltage setting for the 16th variation example are explained.

[0325] In the data allocation of the 16th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D10, D14, D6, D22, D20, D21, D29, D13, D12, D4, D0, D16, D17, D19, D23, D7, D5, D1, D9, D25, D27, D26, D18, D2, D3, D11, and D15 are assigned in S30 and S31.

[0326] In the data allocation of the 16th variation, the readout voltages used for reading page 1 are R4, R8, R12, R16, R20, R24, and R28. In the data allocation of the 16th variation, the readout voltages used for reading page 2 are R7, R11, R14, R23, R27, and R30. In the data allocation of the 16th variation, the readout voltages used for reading page 3 are R3, R6, R15, R19, R22, and R31. In the data allocation of the 16th variation, the readout voltages used for reading page 4 are R2, R5, R9, R18, R21, and R25. In the data allocation of the 16th variation, the readout voltages used for reading page 5 are R1, R10, R13, R17, R26, and R29.

[0327] (Example 17)

[0328] Figure 35 This is a table showing the data allocation and readout voltage settings for the 17th variation example. See below for reference. Figure 35 The data allocation and readout voltage setting for the 17th variation example are explained.

[0329] In the data allocation of the 17th variation example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D9, D1, D5, D21, D29, D25, D27, D11, D3, D2, D0, D16, D17, D19, D23, D7, D6, D14, D10, D26, D18, D22, D20, D4, D12, D13, and D15 are assigned in S30 and S31.

[0330] In the data allocation of the 17th variation, the readout voltages used for reading page 1 are R4, R8, R12, R16, R20, R24, and R28. In the data allocation of the 17th variation, the readout voltages used for reading page 2 are R6, R9, R13, R22, R25, and R29. In the data allocation of the 17th variation, the readout voltages used for reading page 3 are R3, R7, R10, R19, R23, and R26. In the data allocation of the 17th variation, the readout voltages used for reading page 4 are R2, R11, R15, R18, R27, and R31. In the data allocation of the 17th variation, the readout voltages used for reading page 5 are R1, R5, R15, R17, R21, and R30.

[0331] (Example 18)

[0332] Figure 36 This is a table showing the data allocation and readout voltage settings for the 18th variation example. See below for reference. Figure 36 The data allocation and readout voltage setting for the 18th variation example are explained.

[0333] In the data allocation of the 18th variation example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D10, D14, D6, D22, D18, D26, D27, D11, D3, D2, D0, D16, D17, D19, D23, D7, D5, D1, D9, D25, D29, D21, D20, D4, D12, D13, and D15 are assigned in S30 and S31.

[0334] In the data allocation of the 18th variation, the readout voltages used for reading page 1 are R8, R12, R16, R20, R24, and R28. In the data allocation of the 18th variation, the readout voltages used for reading page 2 are R4, R7, R10, R13, R23, R26, and R29. In the data allocation of the 18th variation, the readout voltages used for reading page 3 are R3, R6, R9, R19, R22, and R25. In the data allocation of the 18th variation, the readout voltages used for reading page 4 are R2, R5, R15, R18, R21, and R31. In the data allocation of the 18th variation, the readout voltages used for reading page 5 are R1, R11, R14, R17, R27, and R30.

[0335] (Example 19)

[0336] Figure 37 This is a table showing the data allocation and readout voltage settings for the 19th variation example. See below for reference. Figure 37 The data allocation and readout voltage setting for the 19th variation example are explained.

[0337] In the data allocation of the 19th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D27, D11, D3, D2, D0, D16, D20, D22, D6, D14, D10, D26, D18, D19, D23, D7, D5, D4, D12, D8, D9, D1, D17, D21, D29, D13, and D15 are assigned in S30 and S31.

[0338] In the data allocation of Variation 19, the readout voltages used for reading page 1 are R6, R10, R13, R16, R20, R27, and R30. In the data allocation of Variation 19, the readout voltages used for reading page 2 are R7, R14, R17, R23, R26, and R29. In the data allocation of Variation 19, the readout voltages used for reading page 3 are R3, R11, R15, R19, R24, and R28. In the data allocation of Variation 19, the readout voltages used for reading page 4 are R2, R5, R9, R12, R21, and R31. In the data allocation of Variation 19, the readout voltages used for reading page 5 are R1, R4, R8, R18, R22, and R25.

[0339] (20th variation example)

[0340] Figure 38 This is a table showing the data allocation and readout voltage settings for the 20th variation example. See below for reference. Figure 38 The data allocation and readout voltage setting for the 20th variation example are explained.

[0341] In the data allocation of the 20th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D17, D21, D20, D22, D6, D2, D3, D1, D5, D4, D12, D14, D10, D26, D18, D16, D0, D8, D9, D11, D27, D19, D23, D7, D15, D13, and D29 are assigned to S30 and S31.

[0342] In the data allocation of the 20th variation, the read voltages used for reading page 1 are R9, R18, R21, R25, R28, and R31. In the data allocation of the 20th variation, the read voltages used for reading page 2 are R5, R15, R19, R22, R26, and R29. In the data allocation of the 20th variation, the read voltages used for reading page 3 are R3, R6, R10, R13, R17, and R27. In the data allocation of the 20th variation, the read voltages used for reading page 4 are R2, R8, R12, R16, R20, R24, and R30. In the data allocation of the 20th variation, the read voltages used for reading page 5 are R1, R4, R7, R11, R14, and R23.

[0343] (Example 21)

[0344] Figure 39 This is a table showing the data allocation and readout voltage settings for the 21st variation example. See below for reference. Figure 39 The data allocation and readout voltage setting for the 21st variation example are explained.

[0345] In the data allocation of the 21st variation example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D10, D14, D6, D22, D18, D26, D27, D25, D9, D1, D5, D7, D23, D19, D17, D16, D0, D2, D3, D11, D15, D13, D12, D4, D20, D21, and D29 are assigned in S30 and S31.

[0346] In the data allocation of Variation 21, the readout voltages used for reading page 1 are R4, R8, R13, R17, R21, and R29. In the data allocation of Variation 21, the readout voltages used for reading page 2 are R7, R10, R14, R24, R28, and R31. In the data allocation of Variation 21, the readout voltages used for reading page 3 are R3, R6, R9, R15, R18, and R25. In the data allocation of Variation 21, the readout voltages used for reading page 4 are R2, R5, R12, R16, R19, R22, and R26. In the data allocation of Variation 21, the readout voltages used for reading page 5 are R1, R11, R20, R23, R27, and R30.

[0347] (Example 22)

[0348] Figure 40 This is a table showing the data allocation and readout voltage settings for the 22nd variation example. See below for reference. Figure 40 The data allocation and readout voltage setting for the 22nd variation example are explained.

[0349] In the data allocation of the 22nd variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D27, D11, D3, D2, D0, D16, D20, D21, D29, D13, D9, D1, D17, D19, D23, D7, D5, D4, D12, D8, D10, D26, D18, D22, D6, D14, and D15 are assigned in S30 and S31.

[0350] In the data allocation of Variation 22, the readout voltages used for reading page 1 are R6, R10, R14, R17, R20, R26, and R29. In the data allocation of Variation 22, the readout voltages used for reading page 2 are R7, R13, R16, R23, R27, and R30. In the data allocation of Variation 22, the readout voltages used for reading page 3 are R3, R11, R15, R19, R24, and R28. In the data allocation of Variation 22, the readout voltages used for reading page 4 are R2, R5, R9, R18, R21, and R25. In the data allocation of Variation 22, the readout voltages used for reading page 5 are R1, R4, R8, R12, R22, and R31.

[0351] (23rd variation)

[0352] Figure 41 This is a table showing the data allocation and readout voltage settings for the 23rd variation example. See below for reference. Figure 41 The data allocation and readout voltage setting for the 23rd variation example are explained.

[0353] In the data allocation of the 23rd variation example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D17, D19, D18, D26, D10, D14, D12, D4, D5, D1, D3, D2, D6, D22, D20, D16, D0, D8, D9, D13, D29, D21, D23, D7, D15, D11, and D27 are assigned in S30 and S31.

[0354] In the data allocation of Variation 23, the readout voltages used for reading page 1 are R9, R18, R21, R25, R28, and R31. In the data allocation of Variation 23, the readout voltages used for reading page 2 are R5, R8, R12, R22, R26, and R29. In the data allocation of Variation 23, the readout voltages used for reading page 3 are R3, R10, R14, R17, R20, R24, and R30. In the data allocation of Variation 23, the readout voltages used for reading page 4 are R2, R6, R11, R15, R19, and R27. In the data allocation of Variation 23, the readout voltages used for reading page 5 are R1, R4, R7, R13, R16, and R23.

[0355] (Example 24)

[0356] Figure 42 This is a table showing the data allocation and readout voltage settings for the 24th variation example. See below for reference. Figure 42 The data allocation and readout voltage setting for the 24th variation example are explained.

[0357] In the data allocation of the 24th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D17, D21, D20, D22, D6, D2, D3, D1, D9, D8, D10, D26, D18, D16, D0, D4, D12, D14, D15, D11, D27, D19, D23, D7, D5, D13, and D29 are assigned in S30 and S31.

[0358] In the data allocation of Variation 24, the readout voltages used for reading page 1 are R9, R16, R19, R25, R28, and R31. In the data allocation of Variation 24, the readout voltages used for reading page 2 are R5, R13, R17, R21, R26, and R30. In the data allocation of Variation 24, the readout voltages used for reading page 3 are R3, R6, R10, R20, R24, and R27. In the data allocation of Variation 24, the readout voltages used for reading page 4 are R2, R8, R12, R15, R18, R22, and R29. In the data allocation of Variation 24, the readout voltages used for reading page 5 are R1, R4, R7, R11, R14, and R23.

[0359] (Example 25)

[0360] Figure 43 This is a table showing the data allocation and readout voltage settings for the 25th variation example. See below for reference. Figure 43 The data allocation and readout voltage setting for the 25th variation example are explained.

[0361] In the data allocation of the 25th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D18, D22, D6, D14, D12, D13, D29, D25, D17, D1, D5, D7, D15, D11, D9, D8, D0, D4, D20, D21, D23, D19, D3, D2, D10, D26, and D27 are assigned in S30 and S31.

[0362] In the data allocation of Variation 25, the readout voltages used for reading page 1 are R7, R11, R14, R23, R27, and R30. In the data allocation of Variation 25, the readout voltages used for reading page 2 are R4, R8, R13, R17, R21, and R29. In the data allocation of Variation 25, the readout voltages used for reading page 3 are R3, R6, R12, R15, R18, R22, and R26. In the data allocation of Variation 25, the readout voltages used for reading page 4 are R2, R5, R9, R16, R19, and R25. In the data allocation of Variation 25, the readout voltages used for reading page 5 are R1, R10, R20, R24, R28, and R31.

[0363] (Example 26)

[0364] Figure 44 This is a table showing the data allocation and readout voltage settings for the 26th variation example. See below for reference. Figure 44 The data allocation and readout voltage setting for the 26th variation example are explained.

[0365] In the data allocation of the 26th variation example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D2, D3, D11, D15, D13, D29, D21, D20, D22, D18, D26, D10, D14, D6, D7, D23, D19, D17, D1, D5, D4, D12, D8, D9, D25, and D27 are assigned in S30 and S31.

[0366] In the data allocation of Variation 26, the readout voltages used for reading page 1 are R5, R11, R17, R24, and R30. In the data allocation of Variation 26, the readout voltages used for reading page 2 are R4, R8, R12, R16, R19, and R27. In the data allocation of Variation 26, the readout voltages used for reading page 3 are R3, R9, R15, R18, R22, R25, and R28. In the data allocation of Variation 26, the readout voltages used for reading page 4 are R2, R6, R10, R14, R23, and R31. In the data allocation of Variation 26, the readout voltages used for reading page 5 are R1, R7, R13, R20, R26, and R29.

[0367] (Example 27)

[0368] Figure 45 This is a table showing the data allocation and readout voltage settings for the 27th variation example. See below for reference. Figure 45 The data allocation and readout voltage setting for the 27th variation example are explained.

[0369] In the data allocation of the 27th variation example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D0, D4, D20, D22, D23, D7, D5, D1, D9, D25, D27, D19, D3, D2, D6, D14, D12, D13, D29, D21, D17, D16, D18, D26, D10, D11, and D15 are assigned in S30 and S31.

[0370] In the data allocation of Variation 27, the readout voltages used for reading page 1 are R4, R7, R10, R14, R17, R23, and R29. In the data allocation of Variation 27, the readout voltages used for reading page 2 are R5, R13, R16, R20, R24, and R28. In the data allocation of Variation 27, the readout voltages used for reading page 3 are R3, R6, R12, R19, R25, and R31. In the data allocation of Variation 27, the readout voltages used for reading page 4 are R2, R8, R11, R15, R21, and R27. In the data allocation of Variation 27, the readout voltages used for reading page 5 are R1, R9, R18, R22, R26, and R30.

[0371] (Example 28)

[0372] Figure 46 This is a table showing the data allocation and readout voltage settings for the 28th variation example. See below for reference. Figure 46 The data allocation and readout voltage setting for the 28th variation example are explained.

[0373] In the data allocation of the 28th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D23, D19, D27, D25, D9, D8, D10, D26, D18, D22, D6, D14, D12, D13, D29, D21, D20, D4, D0, D2, D3, D11, and D15 are assigned in S30 and S31.

[0374] In the data allocation of Variation 28, the readout voltages used for reading page 1 are R6, R9, R13, R1, R19, R23, and R26. In the data allocation of Variation 28, the readout voltages used for reading page 2 are R4, R11, R17, R20, R24, and R30. In the data allocation of Variation 28, the readout voltages used for reading page 3 are R3, R7, R10, R18, R27, and R31. In the data allocation of Variation 28, the readout voltages used for reading page 4 are R2, R8, R12, R15, R21, and R28. In the data allocation of Variation 28, the readout voltages used for reading page 5 are R1, R5, R14, R22, R25, and R29.

[0375] (Example 29)

[0376] Figure 47 This is a table showing the data allocation and readout voltage settings for the 29th variation example. See below for reference. Figure 47 The data allocation and readout voltage setting for the 29th variation example are explained.

[0377] In the data allocation of the 29th variation example, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D10, D26, D18, D19, D23, D7, D5, D1, D17, D25, and D27 are assigned in S30 and S31.

[0378] In the data allocation of Variation 29, the readout voltages used for reading page 1 are R5, R14, R18, R22, R26, and R29. In the data allocation of Variation 29, the readout voltages used for reading page 2 are R4, R7, R11, R17, R23, and R30. In the data allocation of Variation 29, the readout voltages used for reading page 3 are R3, R6, R10, R13, R19, R25, and R28. In the data allocation of Variation 29, the readout voltages used for reading page 4 are R2, R8, R15, R21, R27, and R31. In the data allocation of Variation 29, the readout voltages used for reading page 5 are R1, R9, R12, R16, R20, and R24.

[0379] (30th variation example)

[0380] Figure 48 This is a table showing the data allocation and readout voltage settings for the 30th variation example. See below for reference. Figure 48 The data allocation and readout voltage setting for the 30th variation example are explained.

[0381] In the data allocation for the 30th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D9, D13, D29, D21, D23, D19, D18, D26, D10, D14, D12, D4, D5, D1, D17, D25, D27, D11, D3, D2, D0, D16, D20, D22, D6, D7, and D15 are assigned in S30 and S31.

[0382] In the data allocation of Variation 30, the readout voltages used for reading page 1 are R4, R7, R13, R19, R22, R26, and R29. In the data allocation of Variation 30, the readout voltages used for reading page 2 are R8, R12, R16, R20, R23, and R31. In the data allocation of Variation 30, the readout voltages used for reading page 3 are R3, R6, R10, R14, R18, and R27. In the data allocation of Variation 30, the readout voltages used for reading page 4 are R2, R9, R15, R21, R25, and R28. In the data allocation of Variation 30, the readout voltages used for reading page 5 are R1, R5, R11, R17, R24, and R30.

[0383] (31st variation example)

[0384] Figure 49 This is a table showing the data allocation and readout voltage settings for the 31st variation example. See below for reference. Figure 49 The data allocation and readout voltage setting for the 31st variation example are explained.

[0385] In the data allocation of the 31st variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D17, D19, D23, D7, D5, D1, D9, D8, D12, D4, D6, D22, D18, D26, D10, D14, D15, D13, D29, D21, D20, D16, D0, D2, D3, D11, and D27 are assigned in S30 and S31.

[0386] In the data allocation of Variation 31, the readout voltages used for reading page 1 are R8, R16, R19, R23, R27, and R31. In the data allocation of Variation 31, the readout voltages used for reading page 2 are R5, R11, R14, R18, R24, and R30. In the data allocation of Variation 31, the readout voltages used for reading page 3 are R3, R7, R10, R13, R17, R20, and R26. In the data allocation of Variation 31, the readout voltages used for reading page 4 are R2, R6, R9, R15, R22, and R28. In the data allocation of Variation 31, the readout voltages used for reading page 5 are R1, R4, R12, R21, R25, and R29.

[0387] (32nd variation)

[0388] Figure 50 This is a table showing the data allocation and readout voltage settings for the 32nd variation example. See below for reference. Figure 50 The data allocation and readout voltage setting for the 32nd variation example are explained.

[0389] In the data allocation of the 32nd variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D29, D21, D23, D19, D3, D11, and D15 are assigned in S30 and S31.

[0390] In the data allocation of Variation 32, the readout voltages used for reading page 1 are R6, R12, R15, R19, R22, R25, and R29. In the data allocation of Variation 32, the readout voltages used for reading page 2 are R4, R10, R17, R23, R26, and R30. In the data allocation of Variation 32, the readout voltages used for reading page 3 are R3, R7, R11, R20, R28, and R31. In the data allocation of Variation 32, the readout voltages used for reading page 4 are R2, R8, R14, R18, R21, and R27. In the data allocation of Variation 32, the readout voltages used for reading page 5 are R1, R5, R9, R13, R16, and R24.

[0391] (33rd variation)

[0392] Figure 51 This is a table showing the data allocation and readout voltage settings for the 33rd variation example. See below for reference. Figure 51 The data allocation and readout voltage setting for the 33rd variation example are explained.

[0393] In the data allocation of the 33rd variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D17, D1, D5, D4, D20, D16, D18, D26, D10, D11, D9, D13, D29, D21, D23, D22, D6, D2, D0, D8, D12, D14, D15, D7, D3, D19, and D27 are assigned in S30 and S31.

[0394] In the data allocation of Variation 33, the readout voltages used for reading page 1 are R6, R9, R13, R17, R21, and R30. In the data allocation of Variation 33, the readout voltages used for reading page 2 are R5, R12, R18, R24, R28, and R31. In the data allocation of Variation 33, the readout voltages used for reading page 3 are R3, R7, R10, R16, R22, R25, and R29. In the data allocation of Variation 33, the readout voltages used for reading page 4 are R2, R11, R15, R19, R23, and R26. In the data allocation of Variation 33, the readout voltages used for reading page 5 are R1, R4, R8, R14, R20, and R27.

[0395] (Example 34)

[0396] Figure 52 This is a table showing the data allocation and readout voltage settings for the 34th variation example. See below for reference. Figure 52 The data allocation and readout voltage setting for the 34th variation example are explained.

[0397] In the data allocation of the 34th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D27, D19, D3, D1, D9, D8, D12, D14, D6, D2, D0, D16, D17, D21, D23, D7, D15, D11, D10, D26, D18, D22, D20, D4, D5, D13, and D29 are assigned in S30 and S31.

[0398] In the data allocation of Variation 34, the readout voltages used for reading page 1 are R7, R16, R20, R24, R28, and R31. In the data allocation of Variation 34, the readout voltages used for reading page 2 are R6, R9, R13, R21, R25, and R30. In the data allocation of Variation 34, the readout voltages used for reading page 3 are R3, R11, R14, R18, R22, and R26. In the data allocation of Variation 34, the readout voltages used for reading page 4 are R2, R5, R8, R12, R15, R19, and R27. In the data allocation of Variation 34, the readout voltages used for reading page 5 are R1, R4, R10, R17, R23, and R29.

[0399] (35th variation)

[0400] Figure 53 This is a table showing the data allocation and readout voltage settings for the 35th variation example. See below for reference. Figure 53 The data allocation and readout voltage setting for the 35th variation example are explained.

[0401] In the data allocation of the 35th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D9, D1, D3, D2, D6, D14, D12, D13, D29, D21, D17, D16, D0, D8, D10, D26, D18, D22, D20, D4, D5, D7, D23, D19, D27, D11, and D15 are assigned in S30 and S31.

[0402] In the data allocation of Variation 35, the readout voltages used for reading page 1 are R5, R13, R17, R20, R24, R27, and R30. In the data allocation of Variation 35, the readout voltages used for reading page 2 are R6, R10, R14, R18, R21, and R29. In the data allocation of Variation 35, the readout voltages used for reading page 3 are R3, R9, R15, R22, R28, and R31. In the data allocation of Variation 35, the readout voltages used for reading page 4 are R2, R7, R11, R19, R23, and R26. In the data allocation of Variation 35, the readout voltages used for reading page 5 are R1, R4, R8, R12, R16, and R25.

[0403] (36th variation example)

[0404] Figure 54 This is a table showing the data allocation and readout voltage settings for the 36th variation example. See below for reference. Figure 54 The data allocation and readout voltage setting for the 36th variation example are explained.

[0405] In the data allocation of the 36th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D27, D11, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D0, D16, D18, D26, D10, D14, D12, D4, D5, D1, D17, D19, D23, D7, and D15 are assigned in S30 and S31.

[0406] In the data allocation of Variation 36, the readout voltages used for reading page 1 are R6, R10, R14, R18, R21, R27, and R30. In the data allocation of Variation 36, the readout voltages used for reading page 2 are R7, R13, R17, R20, R24, and R31. In the data allocation of Variation 36, the readout voltages used for reading page 3 are R3, R9, R15, R22, R26, and R29. In the data allocation of Variation 36, the readout voltages used for reading page 4 are R2, R5, R11, R19, R23, and R28. In the data allocation of Variation 36, the readout voltages used for reading page 5 are R1, R4, R8, R12, R16, and R25.

[0407] (37th variation example)

[0408] Figure 55 This is a table showing the data allocation and readout voltage settings for the 37th variation example. See below for reference. Figure 55 The data allocation and readout voltage setting for the 37th variation example are explained.

[0409] In the data allocation of the 37th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D18, D22, D6, D7, D15, D11, D9, D8, D0, D2, D3, D19, D23, D21, D20, D4, D12, D14, D10, D26, D27, D25, D17, D1, D5, D13, and D29 are assigned in S30 and S31.

[0410] In the data allocation of Variation 37, the readout voltages used for reading page 1 are R7, R16, R20, R24, R28, and R31. In the data allocation of Variation 37, the readout voltages used for reading page 2 are R4, R9, R13, R21, R27, and R30. In the data allocation of Variation 37, the readout voltages used for reading page 3 are R3, R6, R10, R17, R23, and R29. In the data allocation of Variation 37, the readout voltages used for reading page 4 are R2, R5, R11, R14, R18, R22, and R26. In the data allocation of Variation 37, the readout voltages used for reading page 5 are R1, R8, R12, R15, R19, and R25.

[0411] (38th variation example)

[0412] Figure 56 This is a table showing the data allocation and readout voltage settings for the 38th variation example. See below for reference. Figure 56 The data allocation and readout voltage setting for the 38th variation example are explained.

[0413] In the data allocation of the 38th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D17, D1, D3, D2, D6, D22, D20, D16, D0, D8, D9, D13, D29, D21, D23, D19, D18, D26, D10, D14, D12, D4, D5, D7, D15, D1, and D27 are assigned in S30 and S31.

[0414] In the data allocation of Variation 38, the readout voltages used for reading page 1 are R6, R10, R13, R17, R23, and R31. In the data allocation of Variation 38, the readout voltages used for reading page 2 are R5, R14, R18, R22, R26, and R29. In the data allocation of Variation 38, the readout voltages used for reading page 3 are R3, R9, R12, R16, R20, R24, and R30. In the data allocation of Variation 38, the readout voltages used for reading page 4 are R2, R7, R11, R19, R25, and R28. In the data allocation of Variation 38, the readout voltages used for reading page 5 are R1, R4, R8, R15, R21, and R27.

[0415] (39th variation example)

[0416] Figure 57 This is a table showing the data allocation and readout voltage settings for the 39th variation example. See below for reference. Figure 57 The data allocation and readout voltage setting for the 39th variation example are explained.

[0417] In the data allocation of the 39th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D27, D25, D17, D21, D20, D22, D6, D2, D3, D1, D9, D8, D10, D26, D18, D19, D23, D7, D5, D13, and D29 are assigned in S30 and S31.

[0418] In the data allocation of Variation 39, the readout voltages used for reading page 1 are R5, R11, R17, R24, R28, and R31. In the data allocation of Variation 39, the readout voltages used for reading page 2 are R4, R7, R13, R21, R25, and R30. In the data allocation of Variation 39, the readout voltages used for reading page 3 are R3, R6, R10, R14, R18, and R27. In the data allocation of Variation 39, the readout voltages used for reading page 4 are R2, R8, R12, R16, R20, R23, and R29. In the data allocation of Variation 39, the readout voltages used for reading page 5 are R1, R9, R15, R19, R22, and R26.

[0419] (40th variation example)

[0420] Figure 58 This is a table showing the data allocation and readout voltage settings for the 40th variation example. See below for reference. Figure 58 The data allocation and readout voltage setting for the 40th variation example are explained.

[0421] In the data allocation of the 40th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D21, D23, D7, D6, D14, D12, D8, D0, D2, D3, D19, D27, D25, D9, D1, D5, D4, D20, D22, D18, D26, D10, D11, D15, D13, and D29 are assigned in S30 and S31.

[0422] In the data allocation of Variation 40, the readout voltages used for reading page 1 are R8, R16, R19, R23, R27, and R31. In the data allocation of Variation 40, the readout voltages used for reading page 2 are R4, R10, R13, R17, R20, and R26. In the data allocation of Variation 40, the readout voltages used for reading page 3 are R3, R6, R12, R21, R25, and R29. In the data allocation of Variation 40, the readout voltages used for reading page 4 are R2, R7, R11, R14, R18, R24, and R30. In the data allocation of Variation 40, the readout voltages used for reading page 5 are R1, R5, R9, R15, R22, and R28.

[0423] (41st variation example)

[0424] Figure 59 This is a table showing the data allocation and readout voltage settings for the 41st variation example. See below for reference. Figure 59 The data allocation and readout voltage setting for the 41st variation example are explained.

[0425] In the data allocation of the 41st variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D15, D11, D3, D19, D23, D21, and D29 are assigned in S30 and S31.

[0426] In the data allocation of Variation 41, the readout voltages used for reading page 1 are R6, R12, R15, R19, R22, and R28. In the data allocation of Variation 41, the readout voltages used for reading page 2 are R4, R10, R17, R23, R27, and R31. In the data allocation of Variation 41, the readout voltages used for reading page 3 are R3, R7, R11, R20, R26, and R29. In the data allocation of Variation 41, the readout voltages used for reading page 4 are R2, R8, R14, R18, R21, R25, and R30. In the data allocation of Variation 41, the readout voltages used for reading page 5 are R1, R5, R9, R13, R16, and R24.

[0427] (42nd variation)

[0428] Figure 60 This is a table showing the data allocation and readout voltage settings for the 42nd variation example. See below for reference. Figure 60 The data allocation and readout voltage setting for the 42nd variation example are explained.

[0429] In the data allocation of variation example 42, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D27, D19, D3, D7, D15, D14, D12, D8, D0, D2, D6, D22, D23, D21, D17, D1, D9, D11, D10, D26, D18, D16, D20, D4, D5, D13, and D29 are assigned in S30 and S31.

[0430] In the data allocation of Variation 42, the readout voltages used for reading page 1 are R7, R16, R20, R24, R28, and R31. In the data allocation of Variation 42, the readout voltages used for reading page 2 are R6, R9, R13, R21, R25, and R30. In the data allocation of Variation 42, the readout voltages used for reading page 3 are R3, R8, R12, R15, R19, and R27. In the data allocation of Variation 42, the readout voltages used for reading page 4 are R2, R5, R11, R14, R18, R22, and R26. In the data allocation of Variation 42, the readout voltages used for reading page 5 are R1, R4, R10, R17, R23, and R29.

[0431] (43rd variation)

[0432] Figure 61 This is a table showing the data allocation and readout voltage settings for the 43rd variation example. See below for reference. Figure 61 The data allocation and readout voltage setting for the 43rd variation example are explained.

[0433] In the data allocation of the 43rd variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D25, D17, D1, D3, D2, D6, D22, D20, D21, D29, D13, D9, D8, D0, D16, D18, D26, D10, D14, D12, D4, D5, D7, D23, D19, D27, D11, and D15 are assigned in S30 and S31.

[0434] In the data allocation of Variation 43, the readout voltages used for reading page 1 are R6, R10, R14, R18, R21, R27, and R30. In the data allocation of Variation 43, the readout voltages used for reading page 2 are R5, R13, R17, R20, R24, and R29. In the data allocation of Variation 43, the readout voltages used for reading page 3 are R3, R9, R15, R22, R28, and R31. In the data allocation of Variation 43, the readout voltages used for reading page 4 are R2, R7, R11, R19, R23, and R26. In the data allocation of Variation 43, the readout voltages used for reading page 5 are R1, R4, R8, R12, R16, and R25.

[0435] (44th variation example)

[0436] Figure 62 This is a table showing the data allocation and readout voltage settings for the 44th variation example. See below for reference. Figure 62 The data allocation and readout voltage setting for the 44th variation example are explained.

[0437] In the data allocation of the 44th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D21, D5, D7, D15, D11, D10, D8, D0, D4, D20, D22, D23, D19, D3, D1, D9, D25, D27, D26, D18, D2, D6, D14, D12, D13, and D29 are assigned in S30 and S31.

[0438] In the data allocation of Variation 44, the readout voltages used for reading page 1 are R7, R15, R19, R22, R26, and R31. In the data allocation of Variation 44, the readout voltages used for reading page 2 are R4, R9, R13, R21, R25, and R28. In the data allocation of Variation 44, the readout voltages used for reading page 3 are R3, R6, R10, R14, R18, and R27. In the data allocation of Variation 44, the readout voltages used for reading page 4 are R2, R8, R12, R16, R20, R23, and R29. In the data allocation of Variation 44, the readout voltages used for reading page 5 are R1, R5, R11, R17, R24, and R30.

[0439] (45th variation example)

[0440] Figure 63 This is a table showing the data allocation and readout voltage settings for the 45th variation example. See below for reference. Figure 63 The data allocation and readout voltage setting for the 45th variation example are explained.

[0441] In the data allocation of the 45th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D1, D9, D11, D15, D14, D6, D2, D3, D19, D17, D21, D20, D4, D12, D8, D10, D26, D18, D22, D23, D7, D5, D13, D29, D25, and D27 are assigned to S30 and S31.

[0442] In the data allocation of Variation 45, the readout voltages used for reading page 1 are R5, R14, R18, R22, R26, and R29. In the data allocation of Variation 45, the readout voltages used for reading page 2 are R4, R7, R11, R19, R23, and R28. In the data allocation of Variation 45, the readout voltages used for reading page 3 are R3, R9, R12, R16, R20, R24, and R30. In the data allocation of Variation 45, the readout voltages used for reading page 4 are R2, R8, R15, R21, R27, and R31. In the data allocation of Variation 45, the readout voltages used for reading page 5 are R1, R6, R10, R13, R17, and R25.

[0443] (46th variation example)

[0444] Figure 64 This is a table showing the data allocation and readout voltage settings for the 46th variation example. See below for reference. Figure 64 The data allocation and readout voltage setting for the 46th variation example are explained.

[0445] In the data allocation of the 46th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D21, D23, D7, D15, D11, D10, D26, D18, D22, D20, D4, D5, D1, D3, D19, D27, D25, D9, D8, D0, D2, D6, D14, D12, D13, and D29 are assigned in S30 and S31.

[0446] In the data allocation of Variation 46, the readout voltages used for reading page 1 are R8, R12, R16, R20, R23, and R31. In the data allocation of Variation 46, the readout voltages used for reading page 2 are R4, R9, R13, R21, R25, and R28. In the data allocation of Variation 46, the readout voltages used for reading page 3 are R3, R6, R10, R14, R18, and R27. In the data allocation of Variation 46, the readout voltages used for reading page 4 are R2, R7, R15, R19, R22, R26, and R29. In the data allocation of Variation 46, the readout voltages used for reading page 5 are R1, R5, R11, R17, R24, and R30.

[0447] (47th variation example)

[0448] Figure 65 This is a table showing the data allocation and readout voltage settings for the 47th variation example. See below for reference. Figure 65 The data allocation and readout voltage setting for the 47th variation example are explained.

[0449] In the data allocation of the 47th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D4, D12, D14, D15, D11, D3, D2, D6, D22, D20, D21, D17, D1, D9, D8, D10, D26, D18, D19, D23, D7, D5, D13, D29, D25, and D27 are assigned in S30 and S31.

[0450] In the data allocation of Variation 47, the readout voltages used for reading page 1 are R5, R14, R18, R22, R26, and R29. In the data allocation of Variation 47, the readout voltages used for reading page 2 are R4, R7, R11, R19, R23, and R28. In the data allocation of Variation 47, the readout voltages used for reading page 3 are R3, R6, R10, R13, R17, R25, and R30. In the data allocation of Variation 47, the readout voltages used for reading page 4 are R2, R8, R15, R21, R27, and R31. In the data allocation of Variation 47, the readout voltages used for reading page 5 are R1, R9, R12, R16, R20, and R24.

[0451] (48th variation example)

[0452] Figure 66 This is a table showing the data allocation and readout voltage settings for the 48th variation example. See below for reference. Figure 66 The data allocation and readout voltage setting for the 48th variation example are explained.

[0453] In the data allocation of the 48th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D1, D5, D7, D6, D22, D18, D26, D10, D14, D12, D4, D20, D21, D23, D19, D27, D25, D9, D8, D0, D2, D3, D11, D15, D13, and D29 are assigned in S30 and S31.

[0454] In the data allocation of Variation 48, the readout voltages used for reading page 1 are R6, R10, R13, R17, R23, and R31. In the data allocation of Variation 48, the readout voltages used for reading page 2 are R4, R12, R16, R21, R25, and R28. In the data allocation of Variation 48, the readout voltages used for reading page 3 are R3, R7, R11, R14, R20, and R29. In the data allocation of Variation 48, the readout voltages used for reading page 4 are R2, R8, R15, R19, R22, R26, and R30. In the data allocation of Variation 48, the readout voltages used for reading page 5 are R1, R5, R9, R18, R24, and R27.

[0455] (49th variation example)

[0456] Figure 67 This is a table showing the data allocation and readout voltage settings for variation example 49. See below for reference. Figure 67 The data allocation and readout voltage setting for the 49th variation example are explained.

[0457] In the data allocation of variation example 49, states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D0, D2, D10, D26, D27, D25, D17, D21, D23, D7, D6, D14, D12, D8, D9, D1, D5, D4, D20, D22, D18, D19, D3, D11, D15, D13, and D29 are assigned in S30 and S31.

[0458] In the data allocation of Variation 49, the readout voltages used for reading page 1 are R5, R8, R14, R23, R27, and R31. In the data allocation of Variation 49, the readout voltages used for reading page 2 are R4, R7, R11, R16, R20, and R28. In the data allocation of Variation 49, the readout voltages used for reading page 3 are R3, R12, R18, R21, R25, and R29. In the data allocation of Variation 49, the readout voltages used for reading page 4 are R2, R6, R10, R13, R17, R24, and R30. In the data allocation of Variation 49, the readout voltages used for reading page 5 are R1, R9, R15, R19, R22, and R26.

[0459] (50th variation example)

[0460] Figure 68 This is a table showing the data allocation and readout voltage settings for the 50th variation example. See below for reference. Figure 68 The data allocation and readout voltage setting for the 50th variation example are explained.

[0461] In the data allocation of the 50th variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D9, D1, D5, D7, D6, D14, D10, D26, D18, D22, D20, D4, D12, D13, D29, D21, D23, D19, D3, D2, D0, D16, D17, D25, D27, D11, and D15 are assigned in S30 and S31.

[0462] In the data allocation of Variation 50, the readout voltages used for reading page 1 are R4, R12, R16, R19, R23, R26, and R30. In the data allocation of Variation 50, the readout voltages used for reading page 2 are R6, R10, R13, R17, R20, and R28. In the data allocation of Variation 50, the readout voltages used for reading page 3 are R3, R7, R11, R14, R22, and R31. In the data allocation of Variation 50, the readout voltages used for reading page 4 are R2, R8, R15, R21, R25, and R29. In the data allocation of Variation 50, the readout voltages used for reading page 5 are R1, R5, R9, R18, R24, and R27.

[0463] (51st variation)

[0464] Figure 69 This is a table showing the data allocation and readout voltage settings for the 51st variation example. See below for reference. Figure 69 The data allocation and readout voltage setting for the 51st variation example are explained.

[0465] In the data allocation of the 51st variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D0, D2, D6, D14, D12, D13, D9, D25, D27, D19, D3, D1, D5, D4, D20, D22, D23, D7, D15, D11, D10, D26, D18, D16, D17, D21, and D29 are assigned in S30 and S31.

[0466] In the data allocation of Variation 51, the readout voltages used for reading page 1 are R4, R12, R15, R19, R22, and R26. In the data allocation of Variation 51, the readout voltages used for reading page 2 are R5, R8, R14, R23, R27, and R31. In the data allocation of Variation 51, the readout voltages used for reading page 3 are R3, R7, R11, R17, R24, and R30. In the data allocation of Variation 51, the readout voltages used for reading page 4 are R2, R6, R9, R13, R16, R20, and R28. In the data allocation of Variation 51, the readout voltages used for reading page 5 are R1, R10, R18, R21, R25, and R29.

[0467] (52nd variation)

[0468] Figure 70 This is a table showing the data allocation and readout voltage settings for the 52nd variation example. See below for reference. Figure 70 The data allocation and readout voltage setting for the 52nd variation example are explained.

[0469] In the data allocation of the 52nd variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D16, D17, D19, D23, D7, D6, D14, D10, D26, D27, D25, D9, D8, D0, D2, D18, D22, D20, D4, D12, D13, D15, D11, D3, D1, D5, D21, and D29 are assigned in S30 and S31.

[0470] In the data allocation of Variation 52, the readout voltages used for reading page 1 are R8, R12, R15, R19, R22, and R30. In the data allocation of Variation 52, the readout voltages used for reading page 2 are R4, R10, R17, R23, R27, and R31. In the data allocation of Variation 52, the readout voltages used for reading page 3 are R3, R7, R11, R20, R26, and R29. In the data allocation of Variation 52, the readout voltages used for reading page 4 are R2, R6, R14, R18, R21, R25, and R28. In the data allocation of Variation 52, the readout voltages used for reading page 5 are R1, R5, R9, R13, R16, and R24.

[0471] (53rd variation)

[0472] Figure 71 This is a table showing the data allocation and readout voltage settings for the 53rd variation example. See below for reference. Figure 71 The data allocation and readout voltage setting for the 53rd variation are explained.

[0473] In the data allocation of the 53rd variation example, the states S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15, S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, and S29 are respectively... Data sets D31, D30, D28, D24, D8, D9, D13, D29, D21, D20, D22, D6, D2, D0, D16, D17, D25, D27, D11, D3, D1, D5, D4, D12, D14, D10, D26, D18, D19, D23, D7, and D15 are assigned to S30 and S31.

[0474] In the data allocation of Variation 53, the readout voltages used for reading page 1 are R4, R7, R11, R14, R18, R26, and R30. In the data allocation of Variation 53, the readout voltages used for reading page 2 are R8, R16, R19, R23, R27, and R31. In the data allocation of Variation 53, the readout voltages used for reading page 3 are R3, R6, R12, R21, R25, and R29. In the data allocation of Variation 53, the readout voltages used for reading page 4 are R2, R10, R13, R17, R20, and R24. In the data allocation of Variation 53, the readout voltages used for reading page 5 are R1, R5, R9, R15, R22, and R28.

[0475] [1-5] Characteristics of each data allocation

[0476] The data allocation in each of the 1st to 53rd variations is "7-6-6-6-6 encoding". That is, in the data allocation of each of the 1st to 53rd variations, similar to the first embodiment, the difference between the maximum and minimum values ​​of the number of reads set for determining data between pages is "1". In the data allocation of each of the 1st to 15th variations, similar to the first embodiment, the minimum interval of the read voltage between pages is "3" and the maximum is "8". In the data allocation of each of the 16th and 17th variations, the minimum interval of the read voltage between pages is "3" and the maximum is "9". In addition, in the data allocation of each of the 16th and 17th variations, the interval of the read voltage for pages with 7 reads is only "4". In the data allocation of each of the 18th to 25th variations, the minimum interval of the read voltage between pages is "3" and the maximum is "10". In the data allocation of variations 26 to 53, the minimum interval of the readout voltage for each page is “3” and the maximum is “9”.

[0477] The following conditions (1) to (6) are conditions that, in addition to those described in the effects of the implementation method, should be avoided to the extent possible when discussing data allocation.

[0478] (1) The lowest read voltage used in the read operation of a page with 7 reads is only one state apart from the lowest read voltage R1 among the read voltages R1 to R31.

[0479] (2) The highest read voltage used in the read operation of a page with 7 reads is only one state apart from the highest read voltage R31 among the read voltages R1 to R31.

[0480] (3) The minimum interval between multiple read voltages used in the read operation of a page with 7 reads is "3 (i.e. 3 states)".

[0481] (4) The minimum interval between multiple read voltages used in the read operation of the page using the lowest read voltage R1 or the highest read voltage R31 is “3 (i.e., 3 states)”, or the maximum interval is “9 (i.e., 9 states)”.

[0482] (5) There are pages that use both the lowest read voltage R1 and the highest read voltage R31 among the read voltages R1 to R31 for the read operation. In other words, pages 1 to 5 contain pages that use both read voltages R1 and R31 for the read operation.

[0483] (6) The minimum interval of the read voltage used in the read operation of each page is “3 (i.e., 3 states)” and the maximum is “9 (i.e., 9 states)” or more.

[0484] The priority of avoiding each condition is (1), (2) < (3), (4) < (5) < (6). The fewer conditions (1) to (6) are satisfied, the closer the data allocation is to the ideal data allocation. In addition, between satisfying a condition with lower priority and satisfying a condition with higher priority, satisfying the condition with lower priority is closer to the ideal data allocation. Taking conditions (1) to (6) into account, for example, the implementation method and the 1st to 17th variations are divided into groups 1 to 7.

[0485] Group 1 includes the implementation method and variations 1 to 4. The data allocation in Group 1 satisfies one of conditions (1) and (2) in conditions (1) to (6). That is, the data allocation in Group 1 does not satisfy the other of conditions (1) and (2), as well as conditions (3), (4), (5) and (6).

[0486] Group 2 contains the fifth variation. The data allocation in Group 2 satisfies conditions (2) and (4). That is, the data allocation in Group 2 does not satisfy conditions (1), (3), (5) and (6).

[0487] Group 3 contains variations 6 and 7. The data allocation in Group 3 satisfies conditions (1), (2), and (3). That is, the data allocation in Group 3 does not satisfy conditions (4), (5), and (6).

[0488] Group 4 contains the 8th variation. The data allocation in Group 4 satisfies conditions (2), (3), and (4). That is, the data allocation in Group 4 does not satisfy conditions (1), (5), and (6).

[0489] Group 5 contains variations 9 through 11. The data allocation in Group 5 satisfies conditions (1), (2), (3), and (4). That is, the data allocation in Group 5 does not satisfy conditions (5) and (6).

[0490] Group 6 contains variations 12 to 15. The data distribution in Group 6 satisfies conditions (3) and (5). That is, the data distribution in Group 6 does not satisfy conditions (1), (2), (4), and (6).

[0491] Group 7 contains variations 16 and 17. The data allocation in Group 7 satisfies conditions (4) and (6). That is, the data allocation in Group 7 does not satisfy conditions (1), (2), (3), and (5).

[0492] If conditions (1) to (6) are used for scoring, the read efficiency is ranked from best to worst as follows: Group 1, Group 2, Group 3, Group 4, Group 5, Group 6, and Group 7. Furthermore, the data allocation in variations 26 to 53 has the same read efficiency as Group 7. In variations 18 to 25, since the maximum interval of the read voltage for each page is "10", the read efficiency in the data allocation of each example is slightly worse than that of Group 7. Additionally, variations 18, 19, 20, 21, 23, and 24 do not have pages that use both the lowest read voltage R1 and the highest read voltage R31. Therefore, the read efficiency in variations 18, 19, 20, 21, 23, and 24 is higher than that in variations 22 and 25, which use both the lowest read voltage R1 and the highest read voltage R31. The storage device 20 can perform read operations more efficiently even when using data allocation belonging to any group.

[0493] Furthermore, conditions (1) to (6) can be rephrased as conditions (1a) to (6a). Conditions (1a) to (6a) are conditions that are preferably met to the extent possible, in addition to the conditions described in the effects of the implementation method.

[0494] (1a) The lowest read voltage used in the read operation of a page with 7 reads is more than 2 states away from the lowest read voltage R1 among the read voltages R1 to R31.

[0495] (2a) The highest read voltage used in the read operation of a page with 7 reads is more than 2 states away from the highest read voltage R31 among the read voltages R1 to R31.

[0496] (3a) The minimum interval between multiple read voltages used in the read operation of a page with 7 reads is “4 (i.e. 4 states)”.

[0497] (4a) The minimum interval between multiple read voltages used in the read operation of the page using the lowest read voltage R1 or the highest read voltage R31 is “4 (i.e., 4 states)”, or the maximum interval is “8 (i.e., 8 states)”.

[0498] (5a) The lowest read voltage R1 and the highest read voltage R31 among the read voltages R1 to R31 are used for read operations on different pages. In other words, pages 1 to 5 do not include pages where both read voltages R1 and R31 are used for read operations.

[0499] (6a) The minimum interval of the read voltage used in the read operation of each page is “4 (i.e., 4 states)” and the maximum interval is “8 (i.e., 8 states)”.

[0500] The priority of each condition being met is (1a), (2a) > (3a), (4a) > (5a) > (6a). The more conditions (1a) to (6a) are met, the closer the data allocation is to the ideal data allocation. In addition, between meeting a condition with lower priority and meeting a condition with higher priority, meeting the condition with higher priority is closer to the ideal data allocation.

[0501] [2] Second Embodiment

[0502] The information processing system 1 of the second embodiment has the same configuration as the information processing system 1 of the first embodiment. In the second embodiment, the storage device 20 performs page-by-page readout operations by applying a readout voltage from high to low. The differences between the second embodiment and the first embodiment will be described below.

[0503] [2-1] Action

[0504] Figure 72 This is a timing diagram illustrating an example of reading the first page in the memory system MS of the second embodiment. Figure 72 The transitions of the input / output signals I / O, the ready / busy signal RBn, the select word line WLsel, and the control signal STB during the readout of page 1 in the second embodiment are shown respectively. Below, refer to... Figure 72 The reading of page 1 of the second embodiment will be explained.

[0505] When performing a page 1 read, the memory controller 10 sends, for example, the instruction "01h", the instruction "00h", the address "ADD", and the instruction "30h" sequentially to the memory device 20. After receiving the instruction "30h", the sequencer 204, based on the instructions and addresses stored in the register circuit 203, changes the memory device 20 from a ready state to a busy state.

[0506] Subsequently, sequencer 204 sequentially applies readout voltages R30, R26, R22, R18, R12, R8, and R4 to the select word line WLsel. Additionally, during each period of applying readout voltages R30, R26, R22, R18, R12, R8, and R4, sequencer 204 activates the control signal STB. Based on the control of sequencer 204, each sense amplifier unit SAU determines (judges) the first bit of data read from the memory cell transistor MT connected to the select word line WLsel, and stores the determination result in the latch circuit XDL.

[0507] The other operations for reading the first page in the second embodiment are the same as in the first embodiment. This readout operation, which applies the readout voltage from high to low, is called, for example, "reverse readout". The storage device 20 of the second embodiment can perform the readout of pages 2 through 5 respectively by reverse readout, just as it does for reading the first page.

[0508] In addition, Figure 72 In this context, the read voltage is applied to the select word line WLsel after applying the ground voltage VSS, but it is not limited to this. For example, a specified voltage higher than the read voltage can be applied to the select word line WLsel before applying the read voltage. The specified voltage value can be the same as the voltage applied to the unselected word line WL during readout, or it can be a voltage higher than the highest read voltage R31.

[0509] [2-2] Effects of the second embodiment

[0510] As explained above, the storage device 20 of the second embodiment performs a read operation by applying read voltages in the reverse order of the first embodiment. Thus, the data allocation of the first embodiment can be used without being limited by the order in which the read voltages are applied. Furthermore, the reverse read operation described in the second embodiment can also be applied to data allocation in any of the first to 53rd variations.

[0511] [3] Third embodiment

[0512] The information processing system 1 of the third embodiment has the same configuration as the information processing system 1 of the first embodiment. Furthermore, in the third embodiment, the storage device 20 performs a sequential read operation (hereinafter referred to as sequential read) of the five pages of data stored in the unit assembly CU. The differences between the third embodiment and the first embodiment will now be explained.

[0513] [3-1] Action

[0514] Figure 73 This is a timing diagram illustrating an example of sequential reads in the memory system MS of the third embodiment. Figure 73 The transitions of input / output signals I / O, ready / busy signal RBn, select word line WLsel, and control signal STB during sequential readout in the third embodiment are shown respectively. Below, refer to... Figure 73 The sequential reading of the third embodiment will be explained.

[0515] When performing sequential read operations, the memory controller 10 sends, for example, the instruction "xxh", the instruction "00h", the address "ADD", and the instruction "30h" sequentially to the memory device 20. The instruction "xxh" is the instruction that specifies the sequential read operation.

[0516] After receiving the instruction "30h", the sequencer 204, based on the instruction and address stored in the register circuit 203, changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 sequentially applies read voltages R1 to R31 to the select word line WLsel. Additionally, during each period of applying read voltages R1 to R31, the sequencer 204 activates the control signal STB. Based on the control of the sequencer 204, each sense amplifier unit SAU determines (judges) the 1st to 5th bits of data read from the memory cell transistor MT connected to the select word line WLsel, and stores the determination results in the latch circuits ADL, BDL, CDL, DDL, and EDL, respectively.

[0517] For example, after the readout is completed using the readout voltage R24 and the fourth bit of data is determined, the sequencer 204 causes the storage device 20 to change from a busy state to a ready state. Then, based on the fact that the storage device 20 has changed from a busy state to a ready state, the memory controller 10 commands the storage device 20 to output the data DAT (page 4 data PG4) stored in each latch circuit DDL of the sense amplifier module 209, so that the page 4 data PG4 is output to the memory controller 10.

[0518] Additionally, during the period when the data PG4 of page 4 is output to the memory controller 10, the read operation is completed using read voltages R25 to R31, thereby determining the data of pages 1, 2, 3, and 5 respectively. After the memory controller 10 completes receiving the data PG4 of page 4, it commands the storage device 20 to output the data, for example, according to the determined data order (PG2, PG5, PG1, and PG3). After receiving 5 pages of data, the memory controller 10 ends the sequential reading.

[0519] Furthermore, this example illustrates the case where data is output in the order determined by the data, but it is not limited to this. When there are multiple pages with determined data, the order in which the pages are output from the storage device 20 to the memory controller 10 can be freely designed. In the third embodiment, the case where the read voltage is applied from low to high during sequential reading is illustrated, but it is not limited to this. Sequential reading can also be performed by reverse reading as in the second embodiment.

[0520] [3-2] Effects of the third embodiment

[0521] As explained above, the storage device 20 of the third embodiment can read five pages of data stored in the cell set CU at once. The data allocation of the first embodiment can also be applied when performing sequential reads. Furthermore, sequential reads can also be applied to data allocation in any of the first to fifty-third variations. Additionally, the memory system MS of the third embodiment improves latency in sequential reads by sequentially outputting data from the storage device 20 to the memory controller 10, starting from the page where the data has been determined.

[0522] [3-3] Examples of variations in the third embodiment

[0523] Furthermore, by cleverly designing page allocation or utilizing reverse reads, storage device 20 can advance the data output timing during sequential reads. For example, in Figure 8 In the data allocation of the illustrated embodiment, it is possible to swap pages 1 and 2 and perform sequential reading using reverse reading (i.e., reading operations that apply read voltages sequentially starting from the higher read voltage). In this case, the storage device 20 can output the data of page 1 after reading using read voltage R6, and can output the data of page 2 after reading using read voltage R3. This improves the latency of the memory system MS.

[0524] [4] Fourth Embodiment

[0525] The fourth embodiment relates to the circuit configuration of the memory device 20 described in the first to third embodiments. Hereinafter, a comparative example will also be used to describe the memory device 20a of the fourth embodiment. Furthermore, in the following description, the X, Y, and Z directions are intersecting directions. For example, the Z direction is a vertical direction relative to the XY plane formed by the X and Y directions. The XY plane, for example, corresponds to a surface parallel to the surface of the semiconductor substrate used to form the memory device 20a.

[0526] [4-1] Composition of comparative examples

[0527] Figure 74 This is a top view showing an example of the circuit configuration of the comparative storage device 20b. The storage device 20b has a structure in which the storage cell array 207 and the sense amplifier module 209 are adjacent in the Z direction. Figure 74 (A) shows the circuit configuration on the layer containing the memory cell array 207 of the storage device 20b. Figure 74 (B) shows the circuit configuration on the layer of the storage device 20b that includes the sense amplifier module 209.

[0528] The storage device 20b includes, for example, four memory surfaces LUN1 to LUN4, a wiring section 210, and peripheral circuitry 211. Memory surfaces LUN1 and LUN2 are adjacent in the Y direction. Memory surfaces LUN3 and LUN4 are adjacent in the Y direction. Memory surfaces LUN1 and LUN3 are adjacent in the X direction. Memory surfaces LUN2 and LUN4 are adjacent in the X direction. Each memory surface LUN shares the wiring section 210 and peripheral circuitry 211. The wiring section 210 is disposed on the layer containing the memory cell array 207. The wiring section 210 and peripheral circuitry 211 are arranged overlapping in the Z direction. The wiring section 210 is used to connect the peripheral circuitry 211 to multiple pads disposed on the storage device 20b (i.e., pads used to connect the input / output circuitry 201, etc., to the memory controller 10). The peripheral circuitry 211 is disposed on the layer containing the sense amplifier module 209. The peripheral circuit 211 may include input / output circuit 201, logic controller 202, register circuit 203, and sequencer 204, etc. The wiring section 210 and the peripheral circuit 211 are adjacent to a set of memory surfaces LUN1 to LUN4 in the Y direction.

[0529] Each memory plane LUN includes a memory cell array 207, a lead-out area HR, a row decoder module 208, and a sense amplifier module 209. Specifically, memory plane LUN1 includes a memory cell array 207A, lead-out areas HR_A1 and HR_A2, row decoder modules 208_A1 and 208_A2, and a sense amplifier module 209A. Memory plane LUN2 includes a memory cell array 207B, lead-out areas HR_B1 and HR_B2, row decoder modules 208_B1 and 208_B2, and a sense amplifier module 209B. Memory plane LUN3 includes a memory cell array 207C, lead-out areas HR_C1 and HR_C2, row decoder modules 208_C1 and 208_C2, and a sense amplifier module 209C. The memory plane LUN4 includes a memory cell array 207D, lead-out areas HR_D1 and HR_D2, row decoder modules 208_D1 and 208_D2, and a sense amplifier module 209D.

[0530] This section focuses on memory plane LUN1 and describes the specific circuit configuration within LUN1. For example... Figure 74 As shown in (A), the memory cell array 207A is sandwiched between the lead-out regions HR_A1 and HR_A2 in the X direction. Figure 74 As shown in (B), the sensing amplifier module 209A is sandwiched between the line decoder modules 208_A1 and 208_A2 in the X direction. Figure 74As shown in (A) and (B), the memory cell array 207A and the sense amplifier module 209A are arranged overlapping in the Z direction. The lead-out regions HR_A1 and HR_A2 are arranged overlapping in the Z direction with the line decoder modules 208_A1 and 208_A2, respectively. The memory cell array 207A is connected to the line decoder module 208_A1 via multiple wires provided in the lead-out region HR_A1, and to the line decoder module 208_A2 via multiple wires provided in the lead-out region HR_A2. A set of line decoder modules 208_A1 and 208_A2 constitutes, for example, a... Figure 5 The line decoder module 208 described herein.

[0531] The width of each of the lead-out regions HR_A1 and HR_A2 in the Y direction is approximately equal to the width of the memory cell array 207A in the Y direction. The width of each of the line decoder modules 208_A1 and 208_A2 in the Y direction is approximately equal to the width of each of the lead-out regions HR_A1 and HR_A2 in the Y direction. When applying 5-bit / cell encoding to the memory cell array 207A as described in the first embodiment, for example, the width of the sense amplifier module 209A in the Y direction is greater than the width of the memory cell array 207A in the Y direction. This is because, when processing data with a large number of values ​​such as 5 bits / cell, the sense amplifier module 209 requires many latching circuits. Since the widths in the Y direction differ between the memory cell array 207A and the sense amplifier module 209A, remaining regions SP can be formed on the layer where the memory cell array 207A is located and the layer where the sense amplifier module 209A is located, respectively. The configurations of memory surfaces LUN2 to LUN4 are the same as those of memory surface LUN1.

[0532] In the comparative example memory device 20b described above, by making the area of ​​the sense amplifier module 209 larger than the area of ​​the memory cell array 207, the chip area of ​​the memory device 20b can be increased according to the area of ​​the sense amplifier module 209. In particular, in the 5-bit / cell memory cell array 207 and the 4-bit / cell memory cell array 207 as described in the first embodiment, the number of latching circuits in the sense amplifier module 209 is increased, and the circuit area of ​​the sense amplifier module 209 is increased.

[0533] [4-2] Structure of the fourth embodiment

[0534] In contrast, the storage device 20a of the fourth embodiment has a circuit configuration that utilizes at least two types of storage cell arrays 207 with different numbers of bits stored by storage cell transistors MT. For example, the storage device 20a of the fourth embodiment utilizes a storage cell array 207 with a k value (e.g., 4 values ​​(2 bits / cell), where "k" is an integer greater than or equal to 1) and a storage cell array 207 with a l value (e.g., 32 values ​​(5 bits / cell), where "l" is an integer greater than "k"). Hereinafter, the storage cell array 207 containing storage cell transistors MT capable of storing k values ​​will be referred to as "storage cell array 207 with fewer than many values", and the storage cell array 207 containing storage cell transistors MT capable of storing l values ​​will be referred to as "storage cell array 207 with a very high number of values".

[0535] [4-2-1] Circuit Configuration

[0536] Figure 75 This is a top view showing an example of the circuit configuration of the storage device 20a according to the fourth embodiment. Figure 75 (A) shows the circuit configuration on the layer of the storage device 20a that includes the storage cell array 207. Figure 75 (B) shows the circuit configuration on the layer of the storage device 20a that includes the sense amplifier module 209. The circuit configuration of the storage device 20a in the fourth embodiment has a configuration that omits the remaining area SP compared to the circuit configuration of the storage device 20b in the comparative example.

[0537] Specifically, in storage device 20a, memory cell arrays 207A and 207C are both super-multiple-value (SMV) memory cell arrays 207. In storage device 20a, memory cell arrays 207B and 207D are both low-multiple-value (LMV) memory cell arrays 207. That is, adjacent memory cell arrays 207A and 207B in the Y direction are combinations of SMV and LMV arrays 207. Similarly, adjacent memory cell arrays 207C and 207D in the Y direction are combinations of SMV and LMV arrays 207. The circuit configuration of a set of memory planes LUN1 and LUN2 will now be described.

[0538] The width of the sensing amplifier module 209A, which overlaps with the multi-value memory cell array 207A in the Z direction, is larger in the Y direction than that of the memory cell array 207A. Conversely, the width of the sensing amplifier module 209B, which overlaps with the multi-value or less-value memory cell array 207B in the Z direction, is smaller in the Y direction than that of the memory cell array 207B. This is because the number of latching circuits required for the operation of the multi-value or less-value memory cell array 207 is less than the number required for the operation of the multi-value memory cell array 207. Furthermore, in the storage device 20a, the width of the multi-value memory cell array 207A in the Y direction is designed to be smaller than the width of the multi-value or less-value memory cell array 207B in the Y direction.

[0539] As a result, the combined width in the Y direction of memory cell arrays 207A and 207B can be designed to be approximately the same as the combined width in the Y direction of sense amplifier modules 209A and 209B. That is, a set of memory cell arrays 207A and 207B and a set of sense amplifier modules 209A and 209B can be configured with approximately the same area and overlap in the Z direction. Similarly, a set of lead-out regions HR_A1 and HR_B1 and a set of line decoder modules 208_A1 and 208_B1 are configured with approximately the same area and overlap in the Z direction. A set of lead-out regions HR_A2 and HR_B2 and a set of line decoder modules 208_A2 and 208_B2 are configured with approximately the same area and overlap in the Z direction. Therefore, in the fourth embodiment, the remaining region SP can be omitted. The circuit configuration of a set of memory surfaces LUN3 and LUN4 is the same as the circuit configuration of a set of memory surfaces LUN1 and LUN2.

[0540] Furthermore, a portion of the peripheral circuitry may be configured in the area of ​​the sensing amplifier module 209. That is, it may be possible to... Figure 74 and Figure 75 The area of ​​the sense amplifier module 209 in each figure is part of the surrounding circuitry. Therefore, the area relationship between the associated memory cell array 207 and the sense amplifier module 209 is not limited to... Figure 75 An example is shown.

[0541] Figure 76 This is a top view showing another example of the circuit configuration of the storage device 20a in the fourth embodiment. Figure 76 (A) shows the circuit configuration on the layer of the storage device 20a that includes the storage cell array 207. Figure 76 (B) shows the circuit configuration on the layer of the storage device 20a that includes the sense amplifier module 209. Figure 76 The circuit configuration of the storage device 20a shown is relative to Figure 75Regarding the circuit configuration of the storage device 20a shown, the area (size) of the sensing amplifier module 209 is different.

[0542] Specifically, in Figure 76 In one example, the area of ​​the sensing amplifier module 209 associated with the multi-value memory cell array 207 is larger than the area of ​​the multi-value memory cell array 207. Additionally, the area of ​​the sensing amplifier module 209 associated with the super-multi-value memory cell array 207 is smaller than the area of ​​the super-multi-value memory cell array 207. In this case, the combined width in the Y direction of the memory cell arrays 207A and 207B can also be designed to be approximately the same as the combined width in the Y direction of the sensing amplifier modules 209A and 209B. That is, in Figure 76 In one example shown, a set of memory cell arrays 207A and 207B and a set of sense amplifier modules 209A and 209B are also set to have approximately the same area and are arranged to overlap in the Z direction.

[0543] [4-2-2] Example of the configuration of the sensing amplifier module 209

[0544] Hereinafter, in the fourth embodiment, a configuration example combining the circuit configuration of one sense amplifier unit SAU included in the sense amplifier module 209 connected to the multi-value memory cell array 207 and the circuit configuration of one sense amplifier unit SAU included in the sense amplifier module 209 connected to the multi-value-less memory cell array 207 will be described.

[0545] (Example 1)

[0546] Figure 77 This is a schematic diagram illustrating a first configuration example of the sensing amplifier module 209 in the storage device 20a of the fourth embodiment. (As shown...) Figure 77 As shown, in the first configuration example of the fourth embodiment, the sense amplifier unit SAU of the sense amplifier module 209A includes a sense amplifier section SA configured to transmit and receive data via bus LBUS1, latch circuits SDL, ADL, BDL, CDL, and XDL. In the first configuration example of the fourth embodiment, the sense amplifier unit SAU of the sense amplifier module 209B includes a sense amplifier section SA configured to transmit and receive data via bus LBUS2, latch circuits SDL, and XDL. Furthermore, in this example, the number of latch circuits connected to buses LBUS1 and LBUS2 respectively can be appropriately varied depending on the number of bits stored by the memory cell transistor MT of the associated memory cell array 207.

[0547] (Example 2)

[0548] Figure 78This is a schematic diagram illustrating a second configuration example of the sensing amplifier module 209 in the storage device 20a of the fourth embodiment. (See attached diagram.) Figure 78 As shown, the second configuration in the fourth embodiment has a configuration that omits the latch circuit SDL of the sense amplifier unit SAU of the sense amplifier module 209B compared to the first configuration in the fourth embodiment. Depending on the number of bits stored by the memory cell transistor MT in the multi-value or lower memory cell array 207B (for example, in the case of 1 bit), the latch circuit other than the latch circuit XDL may be omitted in the sense amplifier unit SAU of the sense amplifier module 209B, as in the second configuration in the fourth embodiment.

[0549] [4-3] Effects of the fourth embodiment

[0550] As explained above, the memory device 20a of the fourth embodiment combines a memory surface LUN having a memory cell array 207 with a maximum number of values ​​and a memory surface LUN having a memory cell array 207 with fewer than a maximum number of values. Therefore, the memory device 20a of the fourth embodiment can suppress the formation of residual SP regions in one memory surface LUN due to the difference in area between the memory cell array 207 and the sense amplifier module 209. As a result, the memory device 20a of the fourth embodiment can achieve a chip area smaller than that of the comparative example. That is, the memory device 20a of the fourth embodiment can reduce the manufacturing cost of the memory device 20a.

[0551] Furthermore, in the fourth embodiment, when the memory cell arrays 207A and 207C are used as a very large number of value memory cell array 207, and the memory cell arrays 207B and 207D are used as a number less than a number of value memory cell arrays 207, the storage device 20a can enable the four memory surfaces LUN1 to LUN4 to operate in parallel (i.e., all four memory surfaces operate). Additionally, in the fourth embodiment, when all four memory cell arrays 207A, 207B, 207C, and 207D are used as number less than a number of value memory cell arrays 207, the storage device 20a can also enable the four memory surfaces LUN1 to LUN4 to operate in parallel. On the other hand, in the fourth embodiment, when the memory cell arrays 207A and 207C are used as a very large number of value memory cell array 207, the storage cell arrays 207B and 207D cannot be used as a very large number of value memory cell array 207.

[0552] Furthermore, in the storage device 20a of the fourth embodiment, the combination of the number of memory surface LUNs allocated with a large number of values ​​and the number of memory surface LUNs allocated with fewer than a number of values ​​can be arbitrarily designed. For example, in the fourth embodiment, a memory cell array 207 for storing a large number of values ​​can be allocated to 1 LUN, and a memory cell array 207 for storing fewer than a number of values ​​can be allocated to 2 LUNs, or a memory cell array 207 for storing a large number of values ​​can be allocated to 3 LUNs, or a memory cell array 207 for storing fewer than a number of values ​​can be allocated to 6 LUNs, or a memory cell array 207 for storing a large number of values ​​can be allocated to 4 LUNs, or a memory cell array 207 for storing fewer than a number of values ​​can be allocated to 8 LUNs.

[0553] [5] Fifth Embodiment

[0554] The storage device 20c of the fifth embodiment relates to the circuit configuration of the memory system MS described in the first to third embodiments, and has a configuration in which multiple memory cell arrays 207 share a latch circuit. The storage device 20c of the fifth embodiment will now be described.

[0555] [5-1] Structure of the fifth embodiment

[0556] The storage device 20c of the fifth embodiment has a configuration that utilizes a super-multiple-value storage cell array 207 by sharing a latch circuit among multiple memory surfaces (LUNs) and suppressing the area of ​​the latch circuit.

[0557] [5-1-1] Circuit Configuration

[0558] Figure 79 This is a top view showing an example of the circuit configuration of the storage device 20c according to the fifth embodiment. The storage device 20c has a structure in which the storage cell array 207 and the sense amplifier module 209 are adjacent in the Z direction. Figure 79 (A) shows the circuit configuration on the layer of the storage device 20c that includes the storage cell array 207. Figure 79 (B) shows the circuit configuration on the layer of the storage device 20c that includes the sense amplifier module 209.

[0559] The storage device 20c includes, for example, four memory planes LUN1 to LUN4, a wiring section 210, and peripheral circuitry 211. The configuration of the memory planes LUN1 to LUN4 in the fifth embodiment is the same as that of the memory planes LUN1 to LUN4 in the comparative example described in the fourth embodiment. Each memory plane LUN includes a memory cell array 207, an output region HR, a row decoder module 208, and a sense amplifier group SAS. The sense amplifier group SAS includes at least a sense amplifier section SA. For example, two adjacent memory planes LUNs in the Y direction share a latch group LS. The latch group LS, for example, includes at least one latch circuit shared by multiple sense amplifier groups SAS at each row address. A set of sense amplifier groups SAS and latch groups LS can be used in the same way as the sense amplifier module 209 described in the first embodiment.

[0560] Specifically, memory plane LUN1 includes memory cell array 207A, lead-out areas HR_A1 and HR_A2, row decoder modules 208_A1 and 208_A2, and sense amplifier group SAS1. Memory plane LUN2 includes memory cell array 207B, lead-out areas HR_B1 and HR_B2, row decoder modules 208_B1 and 208_B2, and sense amplifier group SAS2. Memory plane LUN3 includes memory cell array 207C, lead-out areas HR_C1 and HR_C2, row decoder modules 208_C1 and 208_C2, and sense amplifier group SAS3. Memory plane LUN4 includes memory cell array 207D, lead-out areas HR_D1 and HR_D2, row decoder modules 208_D1 and 208_D2, and sense amplifier group SAS4. Sense amplifier groups SAS1 and SAS2 share latch group LS1. Sense amplifier groups SAS3 and SAS4 share latch group LS1.

[0561] Here, the specific circuit configuration in memory plane LUN1 is described. For example... Figure 79 As shown in (A), the memory cell array 207A is sandwiched between the lead-out regions HR_A1 and HR_A2 in the X direction. Figure 79 As shown in (B), the sensing amplifier module 209A is sandwiched between the line decoder modules 208_A1 and 208_A2 in the X direction. Figure 79As shown in (A) and (B), the memory cell array 207A and the sense amplifier group SAS1 are arranged overlapping in the Z direction. The lead-out regions HR_A1 and HR_A2 are arranged overlapping in the Z direction with the row decoder modules 208_A1 and 208_A2, respectively. The width of each of the lead-out regions HR_A1 and HR_A2 in the Y direction is approximately equal to the width of the memory cell array 207A in the Y direction. The width of each of the row decoder modules 208_A1 and 208_A2 in the Y direction is approximately equal to the width of each of the lead-out regions HR_A1 and HR_A2 in the Y direction. The width of each of the row decoder modules 208_A1 and 208_A2 in the Y direction is greater than the width of the sense amplifier group SAS1 in the Y direction.

[0562] Memory array LUN2 has a similar circuit configuration to memory array LUN1, except that the sense amplifier group SAS2 is located in a separate section from memory array LUN1. The sense amplifier groups SAS1 and SAS2 sandwich the latch group LS1 in the Y direction. As a result, the combined width in the Y direction of memory cell arrays 207A and 207B can be designed to be approximately the same as the combined width in the Y direction of the sense amplifier groups SAS1 and SAS2 and the latch group LS1. That is, a set of memory cell arrays 207A and 207B can be configured with approximately the same area as a set of sense amplifier groups SAS1 and SAS2 and the latch group LS1, and overlapped in the Z direction. The circuit configuration of memory arrays LUN3 and LUN4 is the same as that of memory arrays LUN1 and LUN2. Furthermore, it is also possible to... Figure 79 The sensing amplifier group SAS is part of the surrounding circuitry configured in the region.

[0563] [5-1-2] Example of the configuration of the sense amplifier group SAS and latch group LS

[0564] The following describes the first to fourth configuration examples of the circuit configuration of the sense amplifier group SAS and the latch group LS1 in the fifth embodiment. Furthermore, in the following description, the circuit configuration included in the sense amplifier group SAS1 and SAS2 and the latch group LS1 corresponding to a set of memory surfaces LUN1 and LU2 will be used as an example.

[0565] (Example 1)

[0566] Figure 80 This is a schematic diagram illustrating a first configuration example of the sense amplifier group SAS and latch group LS in the storage device 20c of the fifth embodiment. Figure 80As shown, in the first configuration example of the fifth embodiment, the sense amplifier group SAS1 includes a sense amplifier section SA configured to transmit and receive data via bus LBUS1 and a latch circuit XDL, and the sense amplifier group SAS2 includes a sense amplifier section SA configured to transmit and receive data via bus LBUS2 and a latch circuit XDL. In the first configuration example of the fifth embodiment, the latch group LS1 includes latch circuits SDL, ADL, BDL, and CDL configured to transmit and receive data via bus SBUS, and switches SW1 and SW2. Switches SW1 and SW2 are, for example, MOS transistors. Switch SW1 is connected between LBUS1 and SBUS. Switch SW2 is connected between LBUS2 and SBUS. Control signals CS1 and CS2 are input to the gates of switches SW1 and SW2, respectively. Switch SW1 operates based on control signal CS1. Switch SW2 operates based on control signal CS2. Control signals CS1 and CS2 are generated, for example, by sequencer 204.

[0567] In the first configuration example of the fifth embodiment, the storage device 20c uses a set of sense amplifier group SAS1 and latch group LS1 when processing multiple values. Specifically, when multiple values ​​are assigned to memory cell array 207A and multiple values ​​are assigned to memory cell array 207B, the sequencer 204 controls the switch SW1 to the on state, thereby electrically connecting LBUS1 and SBUS, and performing multiple value operation on memory cell array 207A (for example, the operation described in embodiments 1 to 3). On the other hand, when processing multiple values, the storage device 20c uses, for example, only sense amplifier group SAS2. Specifically, the sequencer 204 controls the switch SW2 to the off state, thereby disconnecting the resistance between LBUS2 and SBUS, and performing multiple value operation.

[0568] (Example 2)

[0569] Figure 81 This is a schematic diagram illustrating a second configuration example of the sense amplifier group SAS and latch group LS in the storage device 20c of the fifth embodiment. Figure 81As shown, the second configuration in the fifth embodiment has a configuration that omits the latch circuit SDL of the latch group LS1 compared to the first configuration in the fifth embodiment, and one latch circuit SDL is connected to each of the buses LBUS1 and LBUS2. In the second configuration in the fifth embodiment, when using an encoding that allows read and write operations to be performed in one latch circuit, such as 1 bit / cell, read and write operations can be performed using only the sense amplifier group SAS. Specifically, in the second configuration of the fifth embodiment, the memory device 20c can, for example, use a sense amplifier group SAS1 and latch group LS1 used in multi-valued applications, and a sense amplifier group SAS2 used in multi-valued applications, so that the read and write operations of memory surfaces LUN1 and LUN2 are performed in parallel.

[0570] (Example 3)

[0571] Figure 82 This is a schematic diagram illustrating a third configuration example of the sense amplifier group SAS and latch group LS in the storage device 20c of the fifth embodiment. Figure 82 As shown, the third configuration in the fifth embodiment has a configuration that omits the latch circuits XDL of each of the latch groups LS1 and LS2 compared to the first configuration in the fifth embodiment, and only one latch circuit XDL is connected to the bus SBUS. Thus, the sense amplifier group SAS may only include the sense amplifier section SA, and the latch circuits used in both read and write operations may be integrated in the latch group LS1. In this case, the storage device 20c can selectively execute either the operation targeting memory surface LUN1 or the operation targeting memory surface LUN2 in the combined memory surfaces LUN1 and LUN2.

[0572] (Example 4)

[0573] Figure 83 This is a schematic diagram illustrating a fourth configuration example of the sense amplifier group SAS and latch group LS in the storage device 20c of the fifth embodiment. Figure 83 As shown, the fourth configuration in the fifth embodiment has a configuration that omits the latch circuit SDL of the latch group LS1 compared to the third configuration in the fifth embodiment, and has one latch circuit SDL connected to each of the buses LBUS1 and LBUS2. By equipping the sense amplifier group SAS with the latch circuit SDL, the fourth configuration in the fifth embodiment can, for example, perform 1-bit / cell operation and multi-value or multi-value operation in parallel.

[0574] [5-2] Effects of the fifth embodiment

[0575] In the storage device 20c of the fifth embodiment, multiple memory cell arrays 207 (sensor amplifier groups SAS) share a latch group LS. When processing a large number of values, the two memory surface LUNs of the shared latch group LS operate one memory surface LUN at a time. For example, while a write operation is being performed on one memory surface LUN, the other memory surface LUN cannot be used and is instead placed in a standby state. Furthermore, when processing multiple values ​​(or 1 bit / cell), the two memory surface LUNs of the shared latch group LS can operate in parallel.

[0576] In the storage device 20c, one of the two memory surfaces LUNs sharing the latch group LS can be used for super-multi-value and the other for multi-value. By setting the memory cell array 207 to be used in multi-value, the area used to configure the latch circuit can be suppressed. In addition, in the fifth embodiment, a memory cell array 207 with a memory cell transistor MT that stores only 1 bit of data (1 bit / cell memory cell array 207) is provided. For example, in the case where a sense amplifier group SAS and a latch group LS are provided as in the first configuration example, the 1 bit / cell memory cell array 207 can perform read and write operations using the sense amplifier group SAS instead of the latch group LS.

[0577] As explained above, the storage device 20c of the fifth embodiment has a latch group LS, thus reducing the area of ​​the circuitry that functions as the sense amplifier module 209. As a result, the storage device 20c of the fifth embodiment can reduce the chip area, thereby reducing the manufacturing cost of the storage device 20c.

[0578] Furthermore, the storage device 20c of the fifth embodiment can use all of the memory cell arrays 207A, 207B, 207C, and 207D as a super-multiple-value memory cell array 207. When the two memory surfaces LUNs of the shared latch group LS each have a super-multiple-value memory cell array 207, the storage device 20c performs write operations one memory surface LUN at a time. Additionally, when the storage cell arrays 207A and 207C are used as super-multiple-value memory cell arrays 207, and the storage cell arrays 207B and 207D are used as multi-value or lower memory cell arrays 207, the storage device 20c of the fifth embodiment can enable the four memory surfaces LUN1 to LUN4 to operate in parallel. Furthermore, when the storage cell arrays 207A, 207B, 207C, and 207D are all used as multi-value or lower memory cell arrays 207, the storage device 20c of the fifth embodiment can enable the four memory surfaces LUN1 to LUN4 to operate in parallel.

[0579] Furthermore, in the storage device 20c of the fifth embodiment, the combination of the number of memory surfaces LUNs allocated with a large number of values ​​and the number of memory surfaces LUNs allocated with fewer than a number of values ​​can be arbitrarily designed. For example, in the fifth embodiment, a memory cell array 207 for storing a large number of values ​​can be allocated to 1 LUN, and a memory cell array 207 for storing fewer than a number of values ​​can be allocated to 2 LUNs, or a memory cell array 207 for storing a large number of values ​​can be allocated to 3 LUNs, or a memory cell array 207 for storing fewer than a number of values ​​can be allocated to 6 LUNs, or a memory cell array 207 for storing a large number of values ​​can be allocated to 4 LUNs, or a memory cell array 207 for storing fewer than a number of values ​​can be allocated to 8 LUNs.

[0580] [6] 6th Embodiment

[0581] The information processing system 1 of the sixth embodiment has the same configuration as the information processing system 1 of the fourth or fifth embodiment. The sixth embodiment relates to a method for writing a large number of values ​​of data into a memory system MS. Hereinafter, the differences between the memory system MS of the sixth embodiment and those of the first to fifth embodiments will be described.

[0582] [6-1] Action

[0583] In the sixth embodiment, the memory system MS temporarily stores data input from the outside along with a write instruction into a memory cell array 207 with multiple values ​​(k value: "k" is an integer greater than or equal to 1). Then, the memory system MS reads the data stored in the memory cell array 207 with multiple values ​​and stores the read data into a memory cell array 207 with a super-multiple value (l value: "l" is an integer greater than "k"). In other words, the memory controller 10 can copy the data written to the memory cell array 207 with multiple values ​​to the memory cell array 207 with super-multiple values. The write operation of the sixth embodiment will be described below using the case where the memory cell array 207 with multiple values ​​stores data in two values ​​as an example.

[0584] [6-1-1] Summary of the write operation

[0585] Figure 84 This is a flowchart illustrating an example of the write operation of the memory system MS in the sixth embodiment. For example... Figure 84 As shown, firstly, the memory controller 10 receives write commands and data (STP1) from the host device HD. The data received from the host device HD is stored, for example, in the buffer memory 17.

[0586] Then, the memory controller 10 uses the received data to perform a buffer write operation (STP2). The buffer write operation is a high-speed write operation that stores data into a buffer area of ​​the storage device 20. The buffer area is a storage area allocated to the multi-value sub-array 207. That is, during the buffer write operation, the memory controller 10 commands the storage device 20 to write data to the multi-value sub-array 207. Afterwards, the memory controller 10 discards the data written to the buffer area from the buffer memory 17.

[0587] After STP2 is completed, the task based on the command from the host device HD ends, and the memory system MS is switched to an idle state (STP3).

[0588] If the memory system MS transitions to an idle state after a buffered write operation, a compression operation (STP4) is performed regardless of the command from the host device HD. The compression operation includes a buffered read operation and a compressed write operation. The buffered read operation is the operation of reading data written via the buffered write operation. The compressed write operation is the operation of writing data read via the buffered read operation to the super-many-value (SMV) array 207. That is, during the compression operation, the memory controller 10 commands the storage device 20 to write data to the SMV array 207. Furthermore, the compression operation can begin at least after the buffered write operation. The compressed write operation can also be referred to as a "super-many-value write operation."

[0589] In addition, if all pages in a block BLK of the multi-value storage cell array 207 have been written, the memory controller 10 can copy the data written to that block BLK to the multi-value storage cell array 207 and erase the data stored in that block BLK.

[0590] [6-1-2] Buffered Write Operation

[0591] Figure 85 This is a flowchart illustrating an example of a buffer write operation in the memory system MS of the sixth embodiment. For example... Figure 85 As shown, after the buffer write operation begins, the memory controller 10 determines the data write destination (STP11). During the STP11 process, a redundant page set is allocated to each page of data that is the target of the buffer write operation. A "redundant page set" corresponds to a group of multiple pages that have the same page of data written to them during the buffer write operation. In this specification, the pages contained in the redundant page set are referred to as "redundant pages." A "redundant page" corresponds to the set of cells (CU) contained in the block BLK of the buffer region. The following describes the case where the redundant page set consists of M redundant pages ("M" being an integer of 2 or more). These M redundant pages are referred to as the first redundant page, the second redundant page, ..., the Mth redundant page.

[0592] Then, the memory controller 10, using the address of the write destination determined in STP11 as the object, simultaneously writes the same data to the first through kth redundant pages (STP12). In the STP12 process, for example, a write operation is performed on M redundant pages. In this write operation, to achieve high speed, the verification operation can be omitted, and the number of times the programming voltage VPGM (programming pulse) is applied is set to 1. In this case, to improve reliability, the memory system MS stores the same data simultaneously on the first through kth redundant pages for the same page of data.

[0593] After STP12 is completed, the memory controller 10 confirms whether all data received in STP1 has been written (STP13).

[0594] If the writing of all data received in STP1 is not completed (STP13: No), the memory controller 10 proceeds to the processing of STP11. That is, the memory controller 10 performs the writing of the data received in STP1 that has not yet completed the multi-value writing operation.

[0595] If all data received in STP1 has been written (STP13: Yes), the memory controller 10 completes a series of processes for the buffer write operation (returns).

[0596] Furthermore, multiple redundant pages containing the same single page of data can be assigned to cell sets CUs with the same address for word line WL and string unit SU in different block BLKs. However, this is not a limitation; multiple redundant pages containing the same single page of data can also be assigned to cell sets CUs of different string units SU sharing the word line WL in the same BLK, or to cell sets CUs of different block BLKs sharing the bit line BL. Additionally, in multi-value write operations involving multiple redundant pages, verification can be omitted to achieve high speed, and data can be written to multiple redundant pages simultaneously with a single programming pulse.

[0597] (Specific example of a multi-value write operation)

[0598] Figure 86 This is a timing diagram illustrating an example of a multi-value write operation of the storage device 20 in the sixth embodiment. Figure 86The diagram illustrates the ready / busy signal RBn, the voltage applied to the select word line WLsel, the voltage applied to the bit line BLprog (which is to be programmed), and the voltage applied to the bit line BLinh (which is to be disabled for programming). The bit line BLprog (which is to be programmed) corresponds to the bit line BL connected to the memory cell transistor MT (which is to be programmed), i.e., the memory cell transistor MT whose threshold voltage is to be raised. The bit line BLinh (which is to be disabled for programming) corresponds to the bit line BL connected to the memory cell transistor MT (which is to be disabled for programming), i.e., the memory cell transistor MT whose threshold voltage is to be suppressed for rising. Furthermore, in the state before the start of multi-value write operation, the voltages of the select word line WLsel, the bit line BLprog, and the bit line BLinh are, for example, the ground voltage VSS.

[0599] like Figure 86 As shown, after the memory device 20 begins a multi-value write operation, it transitions from a ready state to a busy state. Then, the sequencer 204 applies a programming voltage VGMb to the select word line WLsel, a ground voltage VSS to the bit line BLprog, and a voltage VBLinh to the bit line BLinh. The programming voltage VGMb is a high voltage that raises the threshold voltage of the memory cell transistor MT. VBLinh is a voltage higher than the ground voltage VSS.

[0600] When a programming voltage VPGM is applied to the select word line WLsel, the threshold voltage of the memory cell transistor MT, which is connected to the bit line BLprog, contained in the selected string cell SU, and connected to the select word line WLsel, rises. On the other hand, for example, if a voltage VBLinh is applied to the bit line BLinh, the channel voltage increases, thereby suppressing the rise in the threshold voltage of the memory cell transistor MT, which is disabled for programming.

[0601] After the sequencer 204 applies a programming voltage VGMb (programming pulse) to the select word line WLsel once, it ends the multi-value write operation, causing the memory device 20 to change from a busy state to a ready state. tProg1 in the figure represents the time taken to perform the multi-value write operation.

[0602] Furthermore, within the same BLK, the degradation caused by writing and erasing is similar, therefore it is presumed that the optimal programming voltage VPGMb for multi-value write operations is approximately the same. Therefore, the sequencer 204 can also determine the programming voltage VPGMb based on the results of a typical write sequence for the first page within the BLK. The typical write sequence is similar to the sequence of the super-multi-value write operation described below, and includes a programming cycle. In this case, the sequencer 204 can use the programming voltage VPGMb, which is presumed to be optimal based on the typical write sequence, as the programming voltage VPGMb used for multi-value write operations for other pages of the same BLK.

[0603] (Threshold voltage distribution of redundant pages after multi-value write operation)

[0604] Figure 87 This is a threshold voltage distribution diagram illustrating an example of the threshold voltage portion of redundant pages after a multi-value write operation in the storage device 20 of the sixth embodiment. For example... Figure 87 As shown, after a multi-value write operation is performed, the threshold voltage of the memory cell transistor MT that is the programming target, i.e., the memory cell transistor MT to be written with data "0" (programming target cell), rises. Meanwhile, the threshold voltage of the memory cell transistor MT that is disabled for programming, i.e., the memory cell transistor MT to be written with data "1", remains at a lower level, the erase state.

[0605] The read voltage RV is used to read the data written to the redundant page in this example via a multi-value write operation. The programming voltage VGMb is set so that the threshold voltage of the memory cell transistor MT, which has been written with the data "0" during a multi-value write operation, will not exceed the read pass voltage VREAD. However, if a programming voltage VGMb that does not cause reprogramming is used, and a single programming pulse causes the threshold voltage to rise without performing a verification read, it is possible for the memory cell transistor MT to fail to reach the read voltage RV. Such a memory cell transistor MT will be detected as a failed bit FB.

[0606] [6-1-3] Compression action

[0607] Figure 88 This is a flowchart illustrating an example of the compression operation of the memory system MS in the sixth embodiment. For example... Figure 88 As shown, firstly, the memory controller 10 performs a buffer read operation (STP21). In the buffer read operation, the memory controller 10 reads the data written by the buffer write operation from the storage device 20 and stores it in the buffer memory 17.

[0608] Next, the memory controller 10 confirms whether the data collection operation from the buffer area has been completed (STP21). In the processing of STP21, whether the data collection has been completed is determined, for example, based on whether at least one multi-value write operation can be performed.

[0609] If data collection is incomplete (STP21: No), return to STP21 for processing. If data collection is complete (STP21: Yes), proceed to STP23 for processing.

[0610] In the STP23 process, the memory controller 10 uses the collected data to instruct the storage device 20 to perform a multi-page write operation. The storage device 20 performs the multi-page write operation based on the instruction from the memory controller 10. That is, the storage device 20 writes the multi-page data collected through the STP23 process to the multi-page memory cell array 207. Then, the memory controller 10 discards the multi-page data that has been written to the multi-page memory cell array 207 from the buffer memory 17.

[0611] Next, the memory controller 10 confirms whether the compression operation has been completed (STP24). Specifically, the memory controller 10 confirms whether all data stored in the buffer area has been written to the multi-value memory cell array 207. If the compression operation has not been completed (STP24: No), the memory controller 10 returns to the processing of STP21. If the writing of all data stored in the buffer area to the multi-value memory cell array 207 has been completed (STP24: Yes), the memory controller 10 ends the compression operation (returns).

[0612] (A specific example of a multi-value write operation)

[0613] Figure 89 This is a timing diagram illustrating an example of the multi-value write operation of the storage device 20 in the sixth embodiment. Figure 89 The ready / busy signal RBn and the voltage applied to the select word line WLsel are shown. Furthermore, in the state prior to initiating a multi-value write operation, the voltage on the word line WLsel is, for example, the ground voltage VSS.

[0614] like Figure 89 As shown, after the storage device 20 begins a multi-value write operation, it transitions from a ready state to a busy state. Then, the sequencer 204 executes a programming loop that includes programming and verification operations.

[0615] During the programming process, a programming voltage VPGM is applied to the select word line WLsel. The programming voltage VPGM is a high voltage that raises the threshold voltage of the memory cell transistor MT. After applying the programming voltage VPGM to the select word line WLsel, the threshold voltage of the memory cell transistor MT, which is to be programmed, rises. The rise in the threshold voltage of the memory cell transistor MT, which is to be disabled for programming, is suppressed, for example, by a boost converter technique.

[0616] During the verification process, a read operation using a verification voltage is performed. The type and value of the verification voltage applied to the select word line WLsel during the verification process change appropriately as the programming cycle progresses. For example, in the first programming cycle, a read operation using verification voltage V1 is performed. For each sense amplifier unit (SAU), a verification voltage is set to determine whether the verification has passed, based on the write data to be saved. Then, memory cell transistors (MT) exceeding the set verification voltage are considered to have passed verification.

[0617] The actions described above correspond to one programming cycle. Each time a programming cycle is repeated, the programming voltage VPGM increases, and this increase rises with the number of programming cycles executed. The amount of increase in the programming voltage VPGM can be set to any value. Then, the sequencer 204 repeatedly executes the programming cycle. Once it detects that programming for all states has passed, or that the number of programming cycles has exceeded a specified number, it terminates the write operation, causing the storage device 20 to transition from a busy state to a ready state. tProg2 in the diagram represents the time taken to perform the multi-value write operation. tProg2 is longer than tProg1.

[0618] [6-1-4] The first example of a buffered readout action

[0619] Figure 90 This is a flowchart illustrating the first example of a buffer read operation in the memory system MS according to the sixth embodiment. Furthermore, the "k" used in this first example of the buffer read operation is a variable processed by the memory controller 10. Figure 90 As shown, after the memory controller 10 starts the buffer read operation of the first example, it first executes the "k=1" process (STP100).

[0620] Next, the memory controller 10 performs a k-th redundant page read (STP101). In this example, the k-th redundant page read corresponds to a read operation performed using the read voltage RV, targeting the k-th redundant page in a group of redundant pages that store the same 1 page of data. The data read through the redundant page read is, for example, stored in any latch circuit of the sense amplifier unit SAU.

[0621] Next, the memory controller 10 verifies whether "k = M" (STP102) is satisfied. That is, the memory controller 10 verifies whether the data read of all redundant pages contained in the group containing a certain redundant page has been completed.

[0622] In the processing of STP102, if "k = M" is not satisfied, the memory controller 10 carries over "k" (STP103). In other words, in the processing of STP103, the memory controller 10 adds "1" to the number "k". Then, the memory controller 10 proceeds to the processing of STP101. That is, the memory controller 10 performs a read operation to select the next redundant page contained in the group containing a certain redundant page.

[0623] In the processing of STP103, if "k = M" is satisfied, the memory controller 10 instructs the storage device 20 to perform majority decision processing (STP104). In majority decision processing, for example, the sense amplifier unit SAU determines the most frequent read result (data "1" or data "0") as the data associated with the sense amplifier unit SAU based on the read results of multiple redundant pages stored in multiple latch circuits. The determined data is output to the memory controller 10.

[0624] After processing by STP104, the memory controller 10 saves the result of STP104 as data associated with that page to, for example, buffer memory 17 (STP105). Then, the memory controller 10 completes a series of processes (returns) for the buffer read operation of that page.

[0625] Furthermore, within the same BLK, the degradation caused by writing and erasing is similar. Therefore, it is presumed that the optimal read voltage for word line WL is approximately the same during multi-value read operations. Thus, sequencer 204 can also determine the optimal read voltage for word line WL during a normal read operation for the first page within the BLK, and determine the read voltage for other word lines WL based on the result.

[0626] Alternatively, in the first example of the buffered read operation, the read result of the redundant page read can also be output to the memory controller 10. In this case, the memory controller 10 performs majority decision processing based on the read results of multiple redundant page reads to determine the data to be read. The series of actions of the buffered read operation can also be executed based on a single instruction from the memory controller 10. The order in which the redundant page reads are performed via STP100 to STP103 can also be other orders.

[0627] (Specific example of reading redundant pages)

[0628] Figure 91 This is a timing diagram illustrating an example of redundant page readout in the storage device 20 of the sixth embodiment. Figure 91This illustration shows an example of the voltages of the selected word lines WLsel and WLusel, nodes BLX, BLC, HHL and XXL, bit line BL, sense node SEN, and control signal STB during redundant page readout. The non-selected word line WLusel represents the unselected word line WL. Hereinafter, the memory cell transistor MT, contained in the selected block BLK, contained in the selected string cell SU, and connected to the selected word line WLsel, will also be referred to as "MTsel".

[0629] like Figure 91 As shown, before the redundant page readout begins, the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL and XXL, bit line BL, and sensing node SEN are, for example, VSS. At this time, in each sensing amplifier unit SAU, transistors T1 to T4, whose gates are subject to VSS, are all in the off state. After the sequencer 204 starts the redundant page readout, it sequentially executes the processing at times t1 to t6.

[0630] At time t1, sequencer 204 applies a read voltage RV to the select word line WLsel and a read voltage VREAD to the non-select word line WLusel. By applying the read voltage RV to the select word line WLsel, the selected memory cell transistor MTsel is turned on or off, and by applying VREAD to the non-select word line WLusel, the unselected memory cell transistor MT is turned on. Furthermore, since the number of binary reads is relatively small, VREAD can be set higher.

[0631] Additionally, at time t1, VBLX is applied to node BLX, VBLC to node BLC, and VHHL to node HHL. VBLX, VBLC, and VHHL are all voltages higher than VSS. Transistors T1 (with VBLX applied to its gate), T4 (with VBLC applied to its gate), and T2 (with VHHL applied to its gate) are all turned on. Therefore, the bit line BL is charged using the current flowing through transistors T0, T1, T4, and T8, causing its voltage to rise from VSS to VPCH. The sensing node SEN is charged using the current flowing through transistors T0 and T2, causing its voltage to rise from VSS to VSEN.

[0632] At time t2, sequencer 204 applies VSS to node HHL. Consequently, transistor T2, whose gate has been VSS applied, becomes off, and the current path between node ND1 and sensing node SEN is blocked. At this time, sensing node SEN is in a floating state, maintaining the voltage reached after charging at times t1-t2.

[0633] At time t3, sequencer 204 applies VXXL to node XXL. VXXL is a voltage higher than VSS. Transistor T3, whose gate is applied with VXXL, becomes ON. Thus, the voltage of sensing node SEN decreases from VSEN or remains constant depending on the state of the associated memory cell transistor MTsel. Specifically, when memory cell transistor MTsel, to which the read voltage RV is applied, is ON, the voltage of sensing node SEN decreases ( Figure 91 When the memory cell transistor MTsel (ON) is off, and the readout voltage RV is applied, the voltage of the sensing node SEN remains unchanged. Figure 91 MTsel(OFF, off). Furthermore, when the memory cell transistor MTsel is on, the rate of voltage drop at the sensing node SEN may change depending on the relationship between the threshold voltage of the memory cell transistor MTsel and the applied readout voltage RV.

[0634] At time t4, sequencer 204 applies VSS to node XXL. Consequently, transistor T3, whose gate has been VSS applied, becomes off, and the current path between sensing node SEN and node ND2 is blocked. At this time, sensing node SEN is in a floating state, maintaining the voltage reached after the discharge between times t3 and t4.

[0635] At time t5, sequencer 204 activates the control signal STB. In other words, sequencer 204 temporarily changes the control signal STB from an "L" level to an "H" level, and causes the sense amplifier unit SAU to determine the threshold voltage of the memory cell transistor MTsel. Specifically, transistor T7, whose gate is applied with an "H" level voltage, becomes ON, and the pre-charged bus LBUS voltage decreases or remains unchanged depending on the state of transistor T6. For example, if the voltage of sense node SEN is above the threshold voltage of transistor T6, transistor T6 is ON, and the bus LBUS voltage decreases. If the voltage of sense node SEN is less than the threshold voltage of transistor T6, transistor T6 is OFF, and the bus LBUS voltage remains unchanged. Then, sequencer 204 saves the data based on the bus LBUS voltage to the designated latch circuit.

[0636] At time t6, sequencer 204 restores the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL and XXL, and bit line BLprog to their states before the verification operation began. Afterward, sequencer 204 terminates the redundant page readout.

[0637] [6-1-5] Example 2 of buffered readout action

[0638] Figure 92 This is a flowchart illustrating the second example of the buffer read operation of the memory system MS in the sixth embodiment. Figure 92 The example illustrates the case where two unit sets (CUs) are allocated as redundant pages for storing the same 1 page of data (M=2).

[0639] like Figure 92 As shown, after the memory controller 10 begins the buffer read operation of the second example, it first performs a first redundant page read (STP111). The result of the first redundant page read is, for example, saved to any latch circuit of each sense amplifier unit (SAU). Subsequently, the memory controller 10 performs a second redundant page read (STP112). The result of the second redundant page read is, for example, saved to any latch circuit of each sense amplifier unit (SAU).

[0640] Then, the memory controller 10 instructs the storage device 20 to perform a determination process (STP113). In this determination process, the sense amplifier unit (SAU) determines the data as "0" if a set of first and second redundant bits contains the data "0", and as "1" if it does not contain the data "0". The redundant bits correspond to the readout results stored in the latch circuits of each sense amplifier unit (SAU) read through redundant page readout. The first redundant bit corresponds to the result read from the first redundant page. The second redundant bit corresponds to the result read from the second redundant page. The determined data is then output to the memory controller 10.

[0641] After processing by STP114, the memory controller 10 saves the determination result of STP113 as data associated with that page to the buffer memory 17 (STP114). Then, the memory controller 10 completes a series of processes (returns) for the buffer read operation of that page.

[0642] As explained above, in the second example of the buffered read operation, if after reading the data of two memory cell transistors MT associated with redundant pages, one or more memory cell transistors MT are data "0", then the data associated with the sense amplifier unit SAU is treated as data "0". Specifically, if, when reading the first redundant page and the second redundant page respectively, the read results of the first redundant page and the second redundant page having the same column address are one or more data "0", then the data at that same column address is treated as data "0".

[0643] For example, the probability that data written to a memory cell transistor MT that has been written with data "0" will be read as a failure bit FB is as small as 0.5% to 1%. If the error probability of a single memory cell transistor MT is 1%, then if two memory cell transistor MTs are used for the determination, the error probability becomes 1% × 1% = 0.01%. Similarly, if the error probability of a single memory cell transistor MT is 0.5%, then if two memory cell transistor MTs are used for the determination, the error probability becomes 0.5% × 0.5% = 0.0025%.

[0644] Furthermore, if, when reading redundant pages 1 to M, the read results of pages 1 to M with the same column address contain more than one data "0", then the data at that same column address can also be treated as data "0". For example, if the error probability of one memory cell transistor MT is 1% and M = 3, using three memory cell transistors MT reduces the error probability to 1% × 1% × 1% = 0.0001%. Similarly, if the error probability of one memory cell transistor MT is 5%, using three memory cell transistors MT reduces the error probability to 5% × 5% × 5% = 0.0125%. Thus, the second example of buffered read operation reduces the error probability by using multiple memory cell transistors MT to determine the data.

[0645] Furthermore, in the second example of the buffered read operation, the read result of the redundant page read can also be output to the memory controller 10. In this case, the memory controller 10 performs the STP113 processing based on the read results of multiple redundant page reads to determine the data to be read. The series of actions of the buffered read operation can also be executed based on a single instruction from the memory controller 10.

[0646] [6-1-6] The third example of a buffered readout action

[0647] Figure 93 This is a flowchart illustrating the third example of the buffer read operation of the memory system MS in the sixth embodiment. For example... Figure 93 As shown, after the memory controller 10 starts the buffer read operation of the third example, it first performs a read operation (STP121) targeting the first to Mth redundant pages. In the STP121 process, the data of the first to Mth redundant pages is read out to the sense amplifier module 209 all at once. The details of the method for reading out the data of the first to Mth redundant pages all at once (hereinafter referred to as "redundant page one-time read") will be described below.

[0648] After the processing of STP121, the memory controller 10 saves the determination result of STP123 as data associated with the page, for example, to the buffer memory 17 (STP122). Then, the memory controller 10 completes a series of processes for the buffer read operation of the page (returns).

[0649] (A specific example of reading redundant pages at once)

[0650] Figure 94 This is a timing diagram illustrating an example of the one-time reading of redundant pages in the storage device 20 of the sixth embodiment. Figure 94 This example illustrates a redundant page readout at once, showing the voltages of the word lines WLsel and WLusel, nodes BLX, BLC, HHL and XXL, bit line BL, sense node SEN, and control signal STB. In this example, two cell sets CU are allocated as redundant pages for storing the same single page of data (M=2). In a redundant page readout at once, compared to using… Figure 91 Regarding the redundant page readout described, the number of word lines WLsel selected simultaneously differs from the sensing level. Furthermore, the "sensing level" corresponds, for example, to the threshold voltage of transistor T6, which is used to determine the voltage of the sensing node SEN.

[0651] like Figure 94 As shown, before the redundant page readout begins, the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL and XXL, bit line BL, and sensing node SEN are, for example, VSS. After the sequencer 204 begins the redundant page readout, it sequentially executes the processing at times t1 to t6.

[0652] At time t1, sequencer 204 simultaneously selects two blocks BLK containing redundant pages from multiple blocks BLK sharing a common bit line BL. Then, within the selected blocks BLK, sequencer 204 applies a read voltage RV to the select word line WLsel and VREAD to the non-select word line WLusel. Additionally, at time t1, VBLX is applied to node BLX, VBLC to node BLC, and VHHL to node HHL. Consequently, the voltage of bit line BL rises from VSS to VPCH, and the voltage of sensing node SEN rises from VSS to VSEN.

[0653] At time t2, sequencer 204 applies VSS to node HHL. Thus, the sensing node SEN maintains the voltage reached after charging at times t1 to t2.

[0654] At time t3, sequencer 204 applies VXXL to node XXL. Thus, the voltage of the sensing node SEN decreases from VSEN or remains constant depending on the states of the associated memory cell transistors MTsel. Specifically, when the two memory cell transistors MTsel on the common bit line BL are in the ON state, the voltage of the sensing node SEN decreases significantly ( Figure 94 When only one of the two memory cell transistors MTsel (2 cells_on) is on in the on state along the shared bit line BL, the voltage of the sensing node SEN drops slightly. Figure 94 When MTsel (only one cell is turned on) is off, the voltage of the sensing node SEN remains unchanged. Figure 94 MTsel(2 units_disconnected)).

[0655] At time t4, sequencer 204 applies VSS to node XXL. Consequently, transistor T3, whose gate has been subjected to VSS, becomes off, and the current path between sensing node SEN and node ND2 is blocked. At this time, sensing node SEN is in a floating state, maintaining the voltage reached after the discharge between times t3 and t4. As a result, the voltage of sensing node SEN remains at different levels depending on the number of memory cell transistors MTsel that become on due to the applied readout voltage RV.

[0656] At time t5, sequencer 204 activates the control signal STB. In other words, sequencer 204 temporarily changes the control signal STB from an "L" level to an "H" level, and causes the sense amplifier unit SAU to determine the threshold voltage of the memory cell transistor MTsel. The sense level used to determine this threshold voltage is set between the voltage of the sense node SEN corresponding to MTsel (only one cell is on) and the voltage of the sense node SEN corresponding to MTsel (both cells are off). Then, sequencer 204 saves the voltage data based on the bus LBUS to the designated latch circuit.

[0657] At time t6, sequencer 204 restores the voltages of word lines WLsel and WLusel, nodes BLX, BLC, HHL and XXL, and bit line BLprog to their states before the verification operation began. Afterward, sequencer 204 completes the one-time read of redundant pages.

[0658] As explained above, in the third example of the buffered read operation, k memory cell transistors MT are read simultaneously in a single read operation. Then, the sensing level is adjusted; if it is above the sensing level, it is determined to be data "0"; if it is below the sensing level, it is determined to be data "1". In other words, if, when reading both the first redundant page and the second redundant page at once, the memory device 20 determines, based on the sensing level, that there are more than one data "0" in the read results of pages with the same column address assigned to them, it treats them as data "0". Therefore, the third example of the buffered read operation can shorten the time required for reading multiple redundant pages.

[0659] [6-2] Instruction sequence for reading redundant pages at once

[0660] Figure 95 This is a sequence diagram illustrating the first example of an instruction sequence for reading redundant pages at once in the storage device 20 of the sixth embodiment. For example... Figure 95 As shown, when performing a one-time redundant page read, the memory controller 10 sends "yyh", "00h", "ADD(1)", "ADD(2)", ..., "ADD(k) (k is an integer greater than or equal to 2)", and "30h" sequentially to the memory device 20. "yyh" is the instruction specifying the one-time redundant page read. "ADD(1)", "ADD(2)", ..., "ADD(k)" are the addresses of the redundant page set selected as the objects of the one-time redundant page read. ADD(1), ADD(2), ..., ADD(k) are associated with the redundant pages PG(1), PG(2), ..., PG(k) respectively. After receiving the instruction "30h", the sequencer 204, based on the instruction and addresses ADD(1), ..., ADD(k) stored in the register circuit 203, changes the memory device 20 from the ready state to the busy state. Then, the sequencer 204 uses the addresses ADD(1), ..., ADD(k) as objects, for example, to execute... Figure 94 The redundant pages shown are processed in a series of steps when read out at once.

[0661] In addition, the memory controller 10 may also instruct the storage device 20 to perform a one-time read of redundant pages using only the addresses of representative redundant pages within the multiple redundant pages contained in the redundant page set. Figure 96 This is a sequence diagram of the second example of an instruction sequence for reading redundant pages at once in the storage device 20 of the sixth embodiment. For example... Figure 96As shown, in this example, the memory controller 10 sends "yyh", "00h", "ADD(1)", and "30h" sequentially to the storage device 20. After receiving the instruction "30h", the sequencer 204, based on the instruction stored in the register circuit 203 and the address ADD(1) of the redundant page PG(1), changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 treats the address ADD(1) and the addresses ADD(2), ..., ADD(k) associated with the address ADD(1) as objects and performs a series of processes to read the redundant page at once.

[0662] [6-3] Effects of the sixth embodiment

[0663] One performance requirement for SSDs and other storage systems is the speed of sequential write operations. Sequential write is the continuous writing of data received from the host device by the storage system. One method to improve the speed of sequential write operations is to have the SSD write the data received from the host device to a storage cell array 207 with fewer than a few values. However, the data recording density of the storage cell array 207 with fewer than a few values ​​is relatively low.

[0664] Therefore, the memory system MS in the sixth embodiment first writes data through a high-speed multi-value write operation (buffered write operation). Then, the memory system MS reads the data written to the buffer area and performs a high-density super-multi-value write operation (compression operation). Thus, the memory system MS in the sixth embodiment can suppress the decrease in sequential write speed and increase the storage capacity of the memory system MS.

[0665] Furthermore, in the memory system MS of the sixth embodiment, when writing to the binary memory cell array 207, a programming pulse is applied to the select word line WLsel, and the verification operation is omitted. Therefore, the memory system MS of the sixth embodiment can speed up the buffer write operation. However, on the other hand, the omission of the verification operation can lead to an expansion of the threshold voltage distribution, which may result in an increase in the number of invalid bits FB.

[0666] To address this, in the buffer write operation, the memory system MS of the sixth embodiment writes the same page of data to multiple redundant pages. Then, in the buffer read operation, the memory system MS determines the page of data based on the results of read operations targeting multiple redundant pages (examples 1 to 3 of the buffer read operation). As a result, the memory system MS of the sixth embodiment can suppress the probability of errors occurring in the buffer read operation, thereby improving data reliability.

[0667] Furthermore, in the sixth embodiment, the example of performing a multi-value write operation on a binary memory cell array 207 is given, but the embodiment is not limited to this. A multi-value write operation, omitting the verification operation, can also be performed on a memory cell array 207 with more than two values. In this case, the number of programming pulses applied depends, for example, on the type of data to be written to the memory cell transistor MTsel. During a buffered read operation on a memory cell array 207 with more than two values, the type and value of the read voltage to be used can be set according to the number of states formed by the multi-value write operation.

[0668] Furthermore, in the sixth embodiment, an example is shown where the memory system MS omits the verification operation (verification read) after simultaneously writing the same data to the 1st to kth redundant pages, but it is not limited to this. The memory system MS may also perform a verification read after simultaneously writing the same data to the 1st to kth redundant pages, and if there are cells that have not reached a specified threshold, perform an additional write operation. The verification read in the sixth embodiment is, for example, performed simultaneously on the 1st to kth redundant pages. Alternatively, if, during the verification read, one page of data in the 1st to kth redundant pages is not sufficiently written, the memory system MS may simultaneously perform an additional write to the 1st to kth redundant pages. However, the additional write operation also applies to the memory cell transistors MT in the 1st to kth redundant pages that have reached the verification level (the threshold voltage of the target state). Therefore, these memory cell transistors MT may be repeatedly programmed. If this problem exists, the memory system MS may also perform a verification read independently page by page on the 1st to kth redundant pages. Subsequently, the memory system MS can also independently append write operations to cells that have not reached the verification level, page by page.

[0669] Furthermore, in the sixth embodiment, such as Figure 84 The illustration shows a case where a compression operation (a write operation for the multi-value storage cell array 207) is performed after a buffered write operation (a write operation for the multi-value storage cell array 207), but it is not limited to this. For example, when writing data that is frequently used or requires high-speed reading, the storage device 20 may omit the compression operation after the buffered write operation and leave the data in the buffer area (multi-value storage cell array 207). The read operation for the buffer area can read the data faster than the read operation for the multi-value storage cell array 207. Therefore, by leaving frequently used or high-speed read data in the buffer area, the storage device 20 can reduce the latency when reading the data.

[0670] [7] 7th Embodiment

[0671] The information processing system 1 of the seventh embodiment has the same configuration as the information processing system 1 of the sixth embodiment. The seventh embodiment relates to a specific example of the multi-value write operation described in the sixth embodiment. Hereinafter, the differences between the memory system MS of the seventh embodiment and those of the first to sixth embodiments will be described.

[0672] [7-1] Threshold voltage distribution of memory cell transistor MT

[0673] Figure 97 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors MT in the memory device 20 of the seventh embodiment. The vertical axis “NMTs” represents the number of memory cell transistors MT. The horizontal axis “Vth” represents the threshold voltage of the memory cell transistors MT. Figure 97 The example shown illustrates a buffer region consisting of a 4-value (2 bits / cell) memory cell array 207. Specifically, the threshold voltage distribution of the memory cell transistor MT in this example can form four states: S0, S1, S2, and S3. When performing a read operation on this memory cell array 207, read voltages R1 to R3 and a read pass voltage VREAD are used.

[0674] The following describes the first to fourth examples of multi-value write operations when the buffer region is composed of a 4-value (2 bits / cell) memory cell array 207. The programming voltage set for writing data corresponding to state S1 will be referred to as "VPGM(S1)". The programming voltage set for writing data corresponding to state S2 will be referred to as "VPGM(S2)". The programming voltage set for writing data corresponding to state S3 will be referred to as "VPGM(S3)". The magnitude of each programming voltage is set in the manner that "VPGM(S1) < VPGM(S2) < VPGM(S3)". The bit line BL connected to the sense amplifier unit SAU assigned to write data corresponding to state S1 will be referred to as "BLprog(S1)". The bit line BL connected to the sense amplifier unit SAU assigned to write data corresponding to state S2 will be referred to as "BLprog(S2)". The bit line BL connected to the sense amplifier unit SAU assigned to write data corresponding to state S3 will be referred to as "BLprog(S3)".

[0675] [7-2] The first example of a multi-value write operation

[0676] Figure 98 This is a timing diagram illustrating the first example of a multi-value write operation of the storage device 20 in the seventh embodiment. For example... Figure 98 As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state. Before the write operation begins, the voltage of each bit line BL and each word line WL is the ground voltage VSS.

[0677] Then, with a ground voltage VSS applied to bit line BLprog (S1) and a voltage VBLinh applied to bit lines BLprog (S2), BLprog (S3), and BLinh respectively, sequencer 204 applies a programming voltage VPGM (S1) to the select word line WLsel. This causes the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S1) and select word line WLsel to rise. The rise in the threshold voltage of the memory cell transistor MT connected to any of bit lines BLprog (S2), BLprog (S3), and BLinh, and the select word line WLsel, is suppressed.

[0678] Next, sequencer 204 applies a programming voltage VPGM (S2) to the select word line WLsel while applying a ground voltage VSS to bit line BLprog (S2) and a voltage VBLinh to bit lines BLprog (S1), BLprog (S3), and BLinh respectively. This causes the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S2) and select word line WLsel to rise. The rise in the threshold voltage of the memory cell transistor MT connected to any of bit lines BLprog (S1), BLprog (S3), and BLinh, and the select word line WLsel, is suppressed.

[0679] Next, sequencer 204 applies a programming voltage VPGM (S3) to the select word line WLsel while applying a ground voltage VSS to bit line BLprog (S3) and a voltage VBLinh to bit lines BLprog (S1), BLprog (S2), and BLinh respectively. This causes the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S3) and select word line WLsel to rise. The rise in the threshold voltage of the memory cell transistor MT connected to any of the bit lines BLprog (S1), BLprog (S2), and BLinh, and the select word line WLsel, is suppressed.

[0680] The sequencer 204, based on the three programming voltages VPGM(S1), VPGM(S2), and VPGM(S3) applied to the select word line WLsel as described above, terminates the multi-value write operation, causing the storage device 20 to change from a busy state to a ready state. Thus, the first example of the multi-value write operation in the seventh embodiment can form, in the unit set CU that is the programming target, as shown... Figure 97 The threshold voltage distribution for the four states is shown. Furthermore, tProg3 in the illustration represents the time taken to perform the first example of the multi-value write operation in the seventh embodiment. tProg3 is longer than tProg1 and shorter than tProg2.

[0681] Furthermore, in the first example of the multi-value write operation in the seventh embodiment, it is also possible to write during the writing process of state S1 (i.e., during the period when the programming voltage VPGM(S1) is applied to the select word line WLsel), such as Figure 98 As shown by the dashed lines, a ground voltage VSS is applied to either or both of the bit lines BLprog (S2) and BLprog (S3). In this case, when the programming voltage VPGM (S1) is applied to the select word line WLsel, not only does the threshold voltage of the memory cell transistor MT written to state S1 rise, but the threshold voltage of the memory cell transistor MT written to state S2 or S3 also rises. Similarly, during the writing process of state S2 (i.e., during the period when the programming voltage VPGM (S2) is applied to the select word line WLsel), as... Figure 98 As shown by the dashed line, a ground voltage VSS is applied to the bit line BLprog (S3). In this case, when the programming voltage VPGM (S2) is applied to the select word line WLsel, not only does the threshold voltage of the memory cell transistor MT written to state S2 increase, but the threshold voltage of the memory cell transistor MT written to state S3 also increases.

[0682] [7-3] Example 2 of a multi-value write operation

[0683] Figure 99 This is a timing diagram illustrating a second example of a multi-value write operation of the storage device 20 in the seventh embodiment. For example... Figure 99 As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state.

[0684] Then, with a ground voltage VSS applied to bit line BLprog (S2), an intermediate voltage VBLm applied to bit line BLprog (S1), and voltages VBLinh applied to bit lines BLprog (S3) and BLinh respectively, sequencer 204 applies programming voltage VPGM (S2) to select word line WLsel. As a result, the threshold voltages of the memory cell transistors MT connected to bit lines BLprog (S1) and WLsel, and the memory cell transistors MT connected to bit lines BLprog (S2) and WLsel respectively, rise. The rise in threshold voltage of the memory cell transistor MT connected to bit line BLprog (S2) is greater than that of the memory cell transistor MT connected to bit line BLprog (S1).

[0685] Next, with a ground voltage VSS applied to bit line BLprog (S3) and a voltage VBLinh applied to bit lines BLprog (S1), BLprog (S2), and BLinh respectively, sequencer 204 applies a programming voltage VPGM (S2) to the select word line WLsel. This causes the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S3) and select word line WLsel to rise.

[0686] Other detailed operations are the same as in the first example of the multi-value write operation in the 7th embodiment. The sequencer 204, based on the fact that two programming voltages VPGM(S2) and VPGM(S3) have been applied to the select word line WLsel as described above, ends the multi-value write operation, causing the storage device 20 to change from a busy state to a ready state. Thus, in the second example of the multi-value write operation of the 7th embodiment, the unit set CU, which is the programming target, can be formed as follows: Figure 97 The threshold voltage distribution for the four states is shown. Furthermore, tProg4 in the diagram represents the time taken to perform the second example of the multi-value write operation in the seventh embodiment. tProg4 is longer than tProg1 but shorter than tProg3.

[0687] Furthermore, in the second example of the multi-value write operation in the seventh embodiment, it is also possible to write during the write process in states S1 and S2 (i.e., during the period when the programming voltage VPGM (S2) is applied to the select word line WLsel), such as Figure 99 As shown by the dashed line, a ground voltage VSS is applied to the bit line BLprog (S3). In this case, when the programming voltage VPGM (S2) is applied to the select word line WLsel, not only does the threshold voltage of the memory cell transistor MT written to state S1 or S2 increase, but the threshold voltage of the memory cell transistor MT written to state S3 also increases.

[0688] [7-4] The third example of a multi-value write operation

[0689] Figure 100 This is a timing diagram illustrating a third example of a multi-value write operation of the storage device 20 in the seventh embodiment. (As shown...) Figure 100 As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state.

[0690] Then, with a ground voltage VSS applied to bit line BLprog (S1) and a voltage VBLinh applied to bit lines BLprog (S2), BLprog (S3), and BLinh respectively, sequencer 204 applies a programming voltage VPGM (S1) to the select word line WLsel. This causes the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S1) and select word line WLsel to rise.

[0691] Next, sequencer 204 applies a programming voltage VPGM (S3) to the select word line WLsel while applying a ground voltage VSS to bit line BLprog (S3), an intermediate voltage VBLm to bit line BLprog (S2), and voltage VBLinh to bit lines BLprog (S1) and BLinh respectively. As a result, the threshold voltages of the memory cell transistors MT connected to bit line BLprog (S2) and select word line WLsel, and the threshold voltages of the memory cell transistors MT connected to bit line BLprog (S3) and select word line WLsel, respectively, increase. The increase in the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S3) is greater than that of the memory cell transistor MT connected to bit line BLprog (S2).

[0692] Other detailed operations are the same as in the first example of the multi-value write operation in the 7th embodiment. The sequencer 204, based on the fact that two programming voltages VPGM(S1) and VPGM(S3) have been applied to the select word line WLsel as described above, ends the multi-value write operation, causing the storage device 20 to change from a busy state to a ready state. Thus, the third example of the multi-value write operation in the 7th embodiment can form, in the unit set CU that is the programming target, as shown... Figure 97 The threshold voltage distribution for the four states is shown. The duration of the third example of performing the multi-value write operation in the seventh embodiment is tProg4.

[0693] Furthermore, in the third example of the multi-value write operation in the seventh embodiment, it is also possible to write during the writing process of state S1 (i.e., during the period when the programming voltage VPGM(S1) is applied to the select word line WLsel), such as Figure 100 As shown by the dashed lines, a ground voltage VSS is applied to either or both of the bit lines BLprog(S2) and BLprog(S3). In this case, when the programming voltage VPGM(S1) is applied to the select word line WLsel, not only does the threshold voltage of the memory cell transistor MT written to state S1 increase, but the threshold voltage of the memory cell transistor MT written to state S2 or S3 also increases.

[0694] [7-5] Example 4 of a multi-value write operation

[0695] Figure 101 This is a timing diagram illustrating the fourth example of a multi-value write operation of the storage device 20 in the seventh embodiment. For example... Figure 101 As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state.

[0696] Then, sequencer 204 applies a programming voltage VPGM (S3) to the select word line WLsel while applying a ground voltage VSS to bit line BLprog (S3), an intermediate voltage VBLm1 to bit line BLprog (S1), an intermediate voltage VBLm2 to bit line BLprog (S2), and a voltage VBLinh to BLinh. VBLm2 is a voltage higher than VSS. VBLm1 is the voltage between VBLm2 and VBLinh. Thus, the threshold voltage of the memory cell transistor MT connected to any of the bit lines BLprog (S1), BLprog (S2), and BLprog (S3), as well as the select word line WLsel, rises. The threshold voltage rise of the memory cell transistor MT connected to bit line BLProg (S2) is greater than that of the memory cell transistor MT connected to bit line BLprog (S1), and the threshold voltage rise of the memory cell transistor MT connected to bit line BLProg (S3) is greater than that of the memory cell transistor MT connected to bit line BLprog (S2).

[0697] Other detailed operations are the same as in the first example of the multi-value write operation in the 7th embodiment. The sequencer 204, based on the fact that a programming voltage VPGM (S3) has been applied to the select word line WLsel as described above, ends the multi-value write operation, causing the storage device 20 to change from a busy state to a ready state. Thus, the fourth example of the multi-value write operation in the 7th embodiment can form, in the unit set CU that is the programming target, as shown... Figure 97 The threshold voltage distribution for the four states is shown. The duration of the third example of performing the multi-value write operation in the seventh embodiment is tProg1.

[0698] [7-6] The 5th example of a multi-value write operation

[0699] exist Figure 99 , Figure 100 and Figure 101 The examples illustrate how applying an intermediate voltage to the bit line BL according to the data to be written adjusts the rise in the threshold voltage of the memory cell transistor MT, which is the object of programming, but are not limited to this.

[0700] Figure 102 This is a timing diagram illustrating the fifth example of a multi-value write operation of the storage device 20 in the seventh embodiment. For example... Figure 102 As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state.

[0701] Then, with the ground voltage VSS applied to bit lines BLprog(S1), BLprog(S2), and BLprog(S3) respectively, and the voltage VBLinh applied to bit line BLinh, sequencer 204 applies programming voltage VPGM(S3) to select word line WLsel. Afterwards, during a first time interval after the programming voltage VPGM(S3) has been applied, sequencer 204 raises the voltage of bit line BLprog(S1) from VSS to VBLinh. Next, during a second time interval after the programming voltage VPGM(S3) has been applied for a period longer than the first time, sequencer 204 raises the voltage of bit line BLprog(S2) from VSS to VBLinh. Afterwards, after a specified time interval after the programming voltage VPGM(S3) has been applied, sequencer 204 sets the voltage of select word line WLsel and each bit line BL to VSS. Other detailed operations are the same as in the first example of the multi-value write operation in the seventh embodiment. The duration of the fifth example of performing the multi-value write operation in the seventh embodiment is, for example, tProg1.

[0702] As explained above, the memory system MS can also temporarily apply a ground voltage VSS to the bit line BL, and then change the voltage of the bit line BL to the voltage VBLinh of the bit line BLinh that is disabled for writing during the write operation, thereby changing the write time. In this case, the memory system MS can also adjust the rise in the threshold voltage of the memory cell transistor MT that is being programmed. That is, the memory system MS of the seventh embodiment can form, through the fifth example of the multi-value write operation, a set of cells CU that is being programmed, such as Figure 97 The threshold voltage distribution for the four states is shown.

[0703] [7-7] Effects of the 7th embodiment

[0704] As explained above, the memory system MS in the seventh embodiment can also perform multi-value write operations that omit the verification operation when there are 3 or more values. In addition, when the memory system MS applies a programming voltage VPGM to the multiple memory cell transistors MT that are to be programmed during the write operation, it can apply any of the first to Kth voltages (K is the value of the memory cell transistor MT used for data storage) to the multiple bit lines BL according to the data to be written and the magnitude of the programming voltage VPGM.

[0705] As a result, the memory system MS, like the second, third, or fourth examples of multi-value write operations, can perform writes of multiple states at once by applying a single programming voltage VPGM. That is, by applying the programming voltage VPGM in three or more different ways to the bit line BL, depending on the data to be written and the magnitude of the programming voltage VPGM, the memory system MS can reduce the number of programming pulses applied. Therefore, the memory system MS of the seventh embodiment can shorten the time of the buffered write operation.

[0706] Additionally, in multi-value write operations that omit the verification step, such as Figure 97 As shown, there is a risk of overlapping threshold voltage distributions in adjacent states. In this case, the memory system MS of the seventh embodiment can still improve data reliability by combining it with that of the sixth embodiment. That is, the memory system MS of the seventh embodiment can also simultaneously write to multiple memory cell transistors MT as shown in the sixth embodiment, read out multiple memory cell transistors MT during reading, and perform majority decisions on the read data, etc.

[0707] [8] 8th Embodiment

[0708] The storage device 20 of the eighth embodiment stores multiple bits of data based on the threshold voltages of the two storage cell transistors MT. The differences between the memory system MS of the eighth embodiment and those of the first to seventh embodiments will be explained below.

[0709] [8-1] Configuration of storage device 20

[0710] Figure 103 This is a block diagram illustrating an example of the configuration of the storage device 20 in the eighth embodiment. For example... Figure 103 As shown, the storage device 20 of the eighth embodiment has a function for using... Figure 3 The configuration of the storage device 20 described herein is obtained by adding logic circuit 220. The storage cell array 207 in the eighth embodiment includes a first storage cell transistor MTa and a second storage cell transistor MTb.

[0711] In the eighth embodiment, multiple bits of data are stored through various combinations of threshold voltages of the memory cell transistors MTa and MTb. This data storage method is referred to hereafter as "shared encoding." The combined memory cell transistors MTa and MTb can be connected to a common word line WL or to different word lines WL. The multiple bit lines BL in the eighth embodiment include bit lines BLa and BLb, respectively connected to the memory cell transistors MTa and MTb. The sense amplifier module 209 in the eighth embodiment includes sense amplifier units SAUa and SAUb, respectively connected to the bit lines BLa and BLb.

[0712] The logic circuit 220 transmits and receives data DAT with the input / output circuit 201. Additionally, the logic circuit 220 performs specified encoding processing on the write data transmitted from the input / output circuit 201 and sends the encoded write data to at least one of the sense amplifier units SAUa and SAUb. Furthermore, the logic circuit 220 performs specified decoding processing on the read results transmitted from at least one of the sense amplifier units SAUa and SAUb and sends the decoded data as read data to the input / output circuit 201. The logic circuit 220 may also omit the encoding and decoding processes depending on the data to be input / output.

[0713] The data DTa stored in the first memory cell transistor MTa is read out by the sense amplifier unit SAUa and transmitted to the logic circuit 220 via the data bus BUSa. The data DATb stored in the second memory cell transistor MTb is read out by the sense amplifier unit SAUb and transmitted to the logic circuit 220 via the data bus BUSb. Furthermore, the logic circuit 220 can use the data DTa read from the memory cell transistor MTa and the data DATb read from the memory cell transistor MTb to perform decoding processing, and output the decoded data DAT to the memory controller 10 via the input / output circuit 201.

[0714] The other configurations of the information communication system 1 in the eighth embodiment are the same as those in the first embodiment. Hereinafter, the case where the first storage cell transistor MTa and the second storage cell transistor MTb store data DAT1 and DAT2 in 3-bit form will be described. In this case, a set of first storage cell transistors MTa and second storage cell transistors MTb can store 3 bits of data.

[0715] [8-2] Regarding shared coding

[0716] Figure 104 This is a table showing an example of a combination of states of the memory cell transistor MT used in the shared encoding of the storage device 20 in the eighth embodiment. For example... Figure 104 As shown, in the storage device 20 of the eighth embodiment, there are nine combinations of the three states S0 to S2 applicable to the first storage cell transistor MTa and the three states S0 to S2 applicable to the second storage cell transistor MTb. Three bits of data can be represented by eight (2 to the power of three) combinations. Therefore, in this example, no data is allocated for one combination.

[0717] exist Figure 104In this example, "○" indicates an example of a combination of states of memory cell transistors MTa and MTb that are allocated data, and "-" indicates an example of a combination of states of memory cell transistors MTa and MTb that are not allocated data. Specifically, in this example, no data is allocated to the combination of state S1 of the first memory cell transistor MTa and state S1 of the second memory cell transistor MTb. Different 3-bit data is allocated to the other combinations. In this case, in the cell set CU containing combinations of memory cell transistors MTa and MTb, the number of memory cell transistors MT distributed in state S1 is reduced to a certain extent, corresponding to the combination where state S1 of each memory cell transistor MTa and MTb is not used. For example, the number of memory cell transistors MT distributed in state S1 is two-thirds of the number of memory cell transistors MT distributed in other states.

[0718] Figure 105 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistors MT in the memory device 20 of the eighth embodiment. The vertical axis "NMTs" represents the number of memory cell transistors MTa and MTb. The horizontal axis "Vth" represents the threshold voltage of the memory cell transistors MTa and MTb. Figure 105 As shown, the threshold voltage distribution of the memory cell transistor MT in this example can form three states: S0, S1, and S2. Furthermore, as mentioned above, the number of memory cell transistors MT distributed in state S1 is reduced, therefore the difference in threshold voltage among the memory cell transistors MT distributed in state S1 is smaller. Specifically, the difference in threshold voltage among the memory cell transistors MT distributed in state S1 can be smaller than the difference in threshold voltage among the memory cell transistors MT distributed in state S2. In this case, the memory system MS can make the interval between read voltages R1 and R2 smaller than that between... Figure 97 The threshold voltage distribution shown is set relatively small compared to the case where the number of memory cell transistors MT in each state is set to be approximately uniform.

[0719] [8-3] The first example of a multi-value write operation

[0720] Figure 106 This is a timing diagram illustrating the first example of a multi-value write operation of the storage device 20 in the eighth embodiment. For example... Figure 106 As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state.

[0721] Then, with a ground voltage VSS applied to bit line BLprog (S1) and a voltage VBLinh applied to bit lines BLprog (S2) and BLinh respectively, sequencer 204 applies a programming voltage VPGM (S1) to the select word line WLsel. This causes the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S1) and select word line WLsel to rise. The rise in the threshold voltage of the memory cell transistor MT connected to either bit line BLprog (S2) or BLinh, and to select word line WLsel, is suppressed.

[0722] Next, sequencer 204 applies a programming voltage VPGM (S2) to the select word line WLsel while applying a ground voltage VSS to bit line BLprog (S2) and a voltage VBLinh to bit lines BLprog (S1) and BLinh respectively. This causes the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S2) and word line WLsel to rise. However, the rise in the threshold voltage of the memory cell transistor MT connected to either bit line BLprog (S1) or BLinh, as well as the select word line WLsel, is suppressed.

[0723] The sequencer 204, based on the fact that two programming voltages, VPGM(S1) and VPGM(S2), have been applied to the select word line WLsel as described above, terminates the multi-value write operation, causing the memory device 20 to change from a busy state to a ready state. Thus, the first example of the multi-value write operation in the eighth embodiment can form, in the unit set CU that is the programming target, as shown... Figure 105 The threshold voltage distribution for the three states is shown. The duration of the first example of performing the multi-value write operation in the eighth embodiment is tProg4.

[0724] Furthermore, in the first example of the multi-value write operation in the eighth embodiment, it is also possible to write during the writing process of state S1 (i.e., during the period when the programming voltage VPGM(S1) is applied to the select word line WLsel), such as Figure 106 As shown by the dashed line, a ground voltage VSS is applied to the bit line BLprog (S2). In this case, when the programming voltage VPGM (S1) is applied to the select word line WLsel, not only does the threshold voltage of the memory cell transistor MT written to state S1 increase, but the threshold voltage of the memory cell transistor MT written to state S2 also increases.

[0725] [8-4] Example 2 of a multi-value write operation

[0726] Figure 107 This is a timing diagram illustrating a second example of a multi-value write operation of the storage device 20 in the eighth embodiment. For example... Figure 107As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state.

[0727] Then, with a ground voltage VSS applied to bit line BLprog (S2), an intermediate voltage VBLm applied to bit line BLprog (S1), and a voltage VBLinh applied to bit line BLinh, sequencer 204 applies a programming voltage VPGM (S2) to the select word line WLsel. This causes the threshold voltages of the memory cell transistors MT connected to bit lines BLprog (S1) and WLsel, and the memory cell transistors MT connected to bit lines BLprog (S2) and WLsel to rise. The rise in the threshold voltage of the memory cell transistor MT connected to bit line BLprog (S2) is greater than that of the memory cell transistor MT connected to bit line BLprog (S1). On the other hand, the rise in the threshold voltage of the memory cell transistor MT connected to bit lines BLinh and WLsel is suppressed.

[0728] The sequencer 204, based on the fact that a programming voltage VPGM (S2) has been applied to the select word line WLsel as described above, terminates the multi-value write operation, causing the storage device 20 to change from a busy state to a ready state. Thus, the second example of the multi-value write operation in the eighth embodiment can form, in the unit set CU that is the programming target, as shown... Figure 105 The threshold voltage distribution for the three states is shown. The duration of the second example of performing the multi-value write operation in the eighth embodiment is tProg1.

[0729] [8-5] The third example of a multi-value write operation

[0730] exist Figure 107 The example illustrates a case where an intermediate voltage is applied to the bit line BL according to the data to be written, thereby adjusting the rise in the threshold voltage of the memory cell transistor MT, which is the object of programming, but it is not limited to this.

[0731] Figure 108 This is a timing diagram illustrating the third example of a multi-value write operation of the storage device in the eighth embodiment. For example... Figure 108 As shown, after the storage device 20 starts a multi-value write operation, it changes from a ready state to a busy state.

[0732] Then, with the ground voltage VSS applied to bit lines BLprog(S1) and BLprog(S2) respectively, and the voltage VBLinh applied to bit line BLinh, sequencer 204 applies programming voltage VPGM(S2) to select word line WLsel. Afterwards, while the programming voltage VPGM(S2) has been applied for a specified time, sequencer 204 causes the voltage of bit line BLprog(S1) to rise from VSS to VBLinh. Then, after applying programming voltage VPGM(S2) again for a specified time, sequencer 204 causes the voltage of select word line WLsel and each bit line BL to both be VSS. Other detailed operations are the same as in the first example of the multi-value write operation in the eighth embodiment. The execution time of the fifth example of the multi-value write operation in the eighth embodiment is, for example, tProg1.

[0733] As explained above, the memory system MS can also temporarily apply a ground voltage VSS to the bit line BL, and then change the voltage of the bit line BL to the voltage VBLinh of the bit line BLinh that is disabled for writing during the write operation, thereby changing the write time. In this case, the memory system MS can also adjust the rise in the threshold voltage of the memory cell transistor MT that is being programmed. That is, the memory system MS of the eighth embodiment can form, through the third example of the multi-value write operation, a set of cells CU that is being programmed, such as Figure 105 The threshold voltage distribution for the three states is shown.

[0734] [8-6] Effects of the 8th embodiment

[0735] As explained above, the write operation of writing data to the memory cell transistor MT with a 3-value is performed in the same manner as in the 7th embodiment, and the verification operation can be omitted. Therefore, the memory system MS in the 8th embodiment, like that in the 7th embodiment, can shorten the write operation time.

[0736] Furthermore, when writing data to the memory cell transistor MT with a 3-value, shared coding can be utilized. Shared coding reduces the number of reads per page, thus enabling faster read operations. Moreover, in shared coding, a combination of unused states can exist between the first memory cell transistor MTa and the second memory cell transistor MTb. For example, in... Figure 105 In one example, the number of memory cell transistors MT distributed in state S1 is two-thirds that in other states. In this case, the memory system MS can set the width of state S1 to be smaller than the width of other states.

[0737] As a result, the storage device 20 can reduce the overlap of adjacent states within the threshold voltage range of the storage cell transistor MT used for writing data. Therefore, the storage device 20 of the eighth embodiment can reduce the probability of error bits occurring during read operations.

[0738] [8-7] Examples of variations in the eighth embodiment

[0739] Hereinafter, the first to third variations of the eighth embodiment will be described.

[0740] [8-7-1] First variation of the eighth embodiment

[0741] In shared coding, combinations of unused states can also be other combinations.

[0742] Figure 109 This is a table showing an example of a combination of states of the memory cell transistor MT used in the shared encoding of the memory device 20 in the first variation of the eighth embodiment. For example... Figure 109 As shown, in this example, no data is allocated to the combination of state S2 of the first memory cell transistor MTa and state S2 of the second memory cell transistor MTb. However, different 3-bit data is allocated to other combinations. In this case, in the cell set CU containing combinations of memory cell transistors MTa and MTb, the number of memory cell transistors MT distributed in state S1 decreases to a certain extent, corresponding to the combination where state S2 of each memory cell transistor MTa and MTb is not used.

[0743] Figure 110 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistor MT in the memory device 20 of the first variation of the eighth embodiment. For example... Figure 110 As shown, the threshold voltage distribution of the memory cell transistor MT in this example can form three states, S0, S1, and S2. Furthermore, as described above, the number of memory cell transistors MT distributed in state S2 is reduced, thus the difference in threshold voltage among the memory cell transistors MT distributed in state S2 is smaller. Specifically, the difference in threshold voltage among the memory cell transistors MT distributed in state S2 can be smaller than the difference in threshold voltage among the memory cell transistors MT distributed in state S1. The effects of programming crosstalk and data retention are greater in states with higher threshold voltages than in states with lower threshold voltages. Therefore, the memory device 20 of the first variation of the eighth embodiment can reduce the probability of error bits occurring during read operations by reducing the number of memory cell transistors MT distributed in a specific state (e.g., state S2) where the effects of programming crosstalk and data retention are greater.

[0744] Furthermore, as described in the 8th embodiment Figure 104 and Figure 105This corresponds to the case where the number of memory cell transistors MT distributed in state S1 is two-thirds of that in other states. This is described in the first variation of the eighth embodiment. Figure 109 and Figure 110 This corresponds to the case where the number of memory cell transistors MT distributed in state S2 is two-thirds of that in other states. However, it is not limited to this; the memory system MS can make any state two-thirds, and the interval between two states in between can be set to be small.

[0745] [8-7-2] Second variation of the eighth embodiment

[0746] In shared coding, the number of states assigned to the first memory cell transistor MTa and the second memory cell transistor MTb can also be other numbers. For example, shared coding can also utilize the two memory cell transistors MTa and MTb with 6 values ​​respectively, and enable the two memory cell transistors MTa and MTb to store 5 bits of data.

[0747] Figure 111 This is a table showing an example of a combination of states of the memory cell transistor MT used in the shared encoding of the memory device 20 in the second variation of the eighth embodiment. For example... Figure 111 As shown, in the second variation of the eighth embodiment, there are 36 combinations of the six states S0 to S5 applicable to the first memory cell transistor MTa and the five states S0 to S5 applicable to the second memory cell transistor MTb. Five bits of data can be represented by 32 (2 to the power of 5) combinations. Therefore, in this example, no data is allocated for four combinations. For example, no data is allocated for combinations of state S2 of the first memory cell transistor MTa with states S2 and S3 of the second memory cell transistor MTb, and for combinations of state S3 of the first memory cell transistor MTa with states S2 and S3 of the second memory cell transistor MTb. Different 5-bit data are allocated for the other combinations. In this case, in the cell set CU containing combinations of memory cell transistors MTa and MTb, the number of memory cell transistors MT distributed in states S2 and S3 decreases to a lesser extent than the data allocation for states S2 and S3 of each of the memory cell transistors MTa and MTb.

[0748] Figure 112 This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistor MT in the memory device 20 of the second variation of the eighth embodiment. For example... Figure 112As shown, the threshold voltage distribution of the memory cell transistor MT in this example can form six states: S0, S1, S2, S3, S4, and S5. Furthermore, as described above, the number of memory cell transistors MT distributed in states S2 and S3 is reduced, thus the differences in threshold voltages of the memory cell transistors MT distributed in state S2 and in state S3 are smaller. Specifically, the difference in threshold voltages of the memory cell transistors MT distributed in states S2 or S3 can be smaller than the difference in threshold voltages of the memory cell transistors MT distributed in any of states S0, S1, S4, and S5. Moreover, in the second variation of the eighth embodiment, the widths of states S2 and S3 can be set smaller than the widths of the other states. In other words, the memory system MS can also set the interval RLD2 between read voltages R2 and R3 (or read voltages R3 and R4) to be smaller than the interval RLD1 between read voltages R1 and R2 (or read voltages R4 and R5).

[0749] As a result, the storage device 20 of the second variation of the eighth embodiment can reduce the overlap of adjacent states within the threshold voltage range of the storage cell transistor MT used for writing data. Therefore, the storage device 20 of the second variation of the eighth embodiment can reduce the probability of error bits occurring during read operations.

[0750] [8-7-3] Third variation of the eighth embodiment

[0751] The combination of states used in the shared encoding that enables the two memory cell transistors MTa and MTb to store 5 bits of data is not limited to the second variation of the eighth embodiment.

[0752] Figure 113 This is a table showing an example of a combination of states of the memory cell transistor MT used in the shared encoding of the storage device 20 in the third variation of the eighth embodiment. For example... Figure 113 As shown, in the third variation of the eighth embodiment, no data is allocated for the combinations of state S4 of the first memory cell transistor MTa with states S4 and S5 of the second memory cell transistor MTb, and for the combinations of state S5 of the first memory cell transistor MTa with states S4 and S5 of the second memory cell transistor MTb. Instead, different 5-bit data is allocated to other combinations. In this case, in the cell set CU containing combinations of memory cell transistors MTa and MTb, the number of memory cell transistors MT distributed in states S4 and S5 decreases to a lesser extent than the data allocation for states S4 and S5 of each of the memory cell transistors MTa and MTb.

[0753] Figure 114This is a schematic diagram illustrating an example of the threshold voltage distribution of the memory cell transistor MT in the memory device 20 of the third variation of the eighth embodiment. For example... Figure 114 As shown, the threshold voltage distribution of the memory cell transistor MT in this example can form six states: S0, S1, S2, S3, S4, and S5. Furthermore, as described above, the number of memory cell transistors MT distributed in states S4 and S5 is reduced, thus the difference in threshold voltage between the memory cell transistors MT distributed in states S4 and S5 is smaller. Specifically, the difference in threshold voltage between the memory cell transistors MT distributed in state S4 can be smaller than the difference in threshold voltage between the memory cell transistors MT distributed in state S1. Moreover, in the third variation of the eighth embodiment, the width of state S4 can be set to be smaller than the width of the other states. In other words, the memory system MS can also set the interval RLD2 between read voltages R4 and R5 to be smaller than the interval RLD1 between each of read voltages R1 and R2, read voltages R2 and R3, and read voltages R3 and R4.

[0754] Therefore, the storage device 20 of the third variation of the eighth embodiment can achieve the same effect as the second variation of the eighth embodiment. In addition, the storage device 20 of the third variation of the eighth embodiment can reduce the probability of error bits occurring during read operations by reducing the number of storage cell transistors MT distributed in designated states (e.g., states S4 and S5) where the effects of programming crosstalk and data retention are greater.

[0755] Furthermore, as described in the second variation of the eighth embodiment... Figure 111 and Figure 112 This corresponds to the case where the number of memory cell transistors MT distributed in states S2 and S3 is two-thirds of that in other states. This is described in the third variation of the eighth embodiment. Figure 113 and Figure 114 This corresponds to the case where the number of memory cell transistors MT distributed in states S4 and S5 is two-thirds of that in other states. However, it is not limited to this; the memory system MS can make any two-thirds of the states, and the interval between two states between these states can be set to be small.

[0756] Furthermore, the storage device 20 in the eighth embodiment and its variations can be embodied as shown below. The storage device 20 includes: a plurality of first storage cells forming a threshold voltage distribution having K states (K being an integer of 3 or more); and a plurality of second storage cells forming a threshold voltage distribution having K states. Moreover, N bits (N being an integer of 1 or more) of data less than K^2 are stored based on combinations of the K states of the plurality of first storage cells and the K states of the plurality of second storage cells. In both the plurality of first and second storage cells, the distribution width of states that are not used to store N bits of data can be set to be smaller than the distribution width of states used to store N bits of data.

[0757] [9] 9th Embodiment

[0758] The information processing system 1 of the ninth embodiment has the same configuration as the information processing system 1 of the sixth embodiment. The ninth embodiment relates to a method for writing multiple pages of data at once in a multi-value write operation. Hereinafter, the differences between the memory system MS of the ninth embodiment and those of the first to eighth embodiments will be described.

[0759] [9-1] Circuit configuration of memory cell array

[0760] Figure 115 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array 207 included in the memory device 20 of the ninth embodiment. Figure 115 The multiple string units (SU) contained in the buffer region are extracted for illustration. For example... Figure 115 As shown, the buffer region contains multiple string units SU(1) to SU(h) (h is an integer greater than or equal to 2). At least one redundant page set is allocated to a set of string units SU(1) to SU(h). Figure 115 In the text, the multiple wirings (word lines WL, etc.) of the NAND string NS connected to the string unit SU(1) are marked with “(1)”, ..., and the multiple wirings of the NAND string NS connected to the string unit SU(h) are marked with “(h)”.

[0761] [9-2] Flowchart of buffer write operation

[0762] Figure 116 This is a flowchart illustrating an example of a buffer write operation in the memory system MS of the ninth embodiment. For example... Figure 116 As shown, after the memory controller 10 starts the buffer write operation of the first example, it first determines the write destination (STP21) of the data of pages 1 to h.

[0763] Next, the memory controller 10 instructs the storage device 20 to perform a multi-value write operation (STP22) of the data of pages 1 to h. Then, the storage device 20 starts the multi-value write operation based on the received data of pages 1 to h and the instructions.

[0764] After the storage device 20 starts a multi-value write operation, it first charges the channel of the NAND string NS, which is the write destination, based on the first page of data (STP23). That is, the channel of the associated NAND string NS is set with the first page of data.

[0765] Next, the storage device 20 charges the channel of the NAND string NS, which is the write destination, based on the second page data (STP24). That is, the second page data is set for the channel of the associated NAND string NS.

[0766] Similarly, based on the data to be written, the channels of the NAND string NS, which are the respective write destinations for pages 3 to (h-1) of the data, are charged. Then, the channels of the NAND string NS, which are the write destinations, are charged based on the h-th page of data (STP25). That is, pages 3 to h of data are set for the channels of the associated NAND string NS.

[0767] Next, the storage device 20 applies a programming voltage VPGM (STP26) to the select word lines WLsel corresponding to the write destinations of the data for pages 1 to h. Furthermore, the number of select word lines WLsel to which the programming voltage VPGM is applied during the STP26 process can vary depending on the number and configuration of redundant pages allocated to the redundant page set, or the number and configuration of pages being written simultaneously.

[0768] After applying the programming voltage VPGM to the select word line WLsel, the memory device 20 completes a series of processes for the multi-value write operation. Then, the memory controller 10 detects that the memory device 20 has completed the multi-value write operation, thereby completing a series of processes for the buffer write operation (returning).

[0769] [9-3] The first example of a multi-value write operation

[0770] Figure 117 This is a timing diagram illustrating the first example of a multi-value write operation of the storage device 20 in the ninth embodiment. For example... Figure 117 As shown, after the storage device 20 begins a multi-value write operation, it changes from a ready state to a busy state. Before the write operation begins, the voltage of each bit line BL and each word line WL is, for example, the ground voltage VSS. Furthermore, the word line WL selected by the serial unit SU(i) (where "i" is a natural number less than or equal to h) will be referred to as the selected word line WLsel(i). Additionally, the voltage of the bit line BL is controlled as shown by the solid line when it corresponds to the bit line BL being programmed. Figure 117The “Program” is controlled as shown by the dashed line when it corresponds to the bit line BL that is prohibited from programming. Figure 117 (The "Inhibit").

[0771] Then, at time t(1), sequencer 204 applies voltage VSG to the select gate line SGD(1), and according to the data in PG(1) on page 1, applies ground voltage VSS to the bit line BL that is to be programmed, applies voltage VBLinh to the bit line BL that is not to be programmed, and applies ground voltage VSS to the other select gate lines SGD and select word lines WLsel. Voltage VSG is higher than ground voltage VSS, which makes select transistor ST1 turn on. Then, in string cell SU(1), the channel of NAND string NS connected to the bit line BL that is not to be programmed is charged to voltage VBLinh via the select transistor ST1 that is in the on state. On the other hand, in string cell SU(1), the channel of NAND string NS connected to the bit line BL that is to be programmed is charged to ground voltage VSS. In addition, since select transistor ST1 is in the off state, the NAND string NS of string cell SU other than string cell SU(1) is not charged. Then, sequencer 204 lowers the voltage of the select gate line SGD(1) from VSG to VSS and fixes the channel voltage of each NAND string NS of the string unit SU(1). In other words, sequencer 204 sets the data of page 1 PG(1) for each NAND string NS of the string unit SU(1) through processing at time t(1).

[0772] Next, at time t(2), sequencer 204 applies voltage VSG to the select gate line SGD(2), and according to the data in PG(2) on page 2, applies ground voltage VSS to the bit line BL that is to be programmed, applies voltage VBLinh to the bit line BL that is not to be programmed, and applies ground voltage VSS to the other select gate lines SGD and select word lines WLsel. Then, in the string cell SU(2), the channel of the NAND string NS connected to the bit line BL that is to be programmed is charged to voltage VBLinh via the select transistor ST1 which is in the on state. On the other hand, in the string cell SU(2), the channel of the NAND string NS connected to the bit line BL that is not to be programmed is charged to ground voltage VSS. In addition, since the select transistor ST1 is in the off state, the NAND string NS of the string cell SU other than the string cell SU(2) is not charged. Then, sequencer 204 lowers the voltage of the select gate line SGD(2) from VSG to VSS and fixes the channel voltage of each NAND string NS of the string unit SU(2). In other words, sequencer 204 sets the data of page 2 PG(2) for each NAND string NS of the string unit SU(2) through the processing at time t(2).

[0773] Then, sequencer 204 changes the string unit SU that is the object of the setting data and performs the same processing as at times t(1) and t(2). Through times t(3) to t(h), sequencer 204 sets the data of page 3 PG(3) to page h PG(h) for each NAND string NS of string units SU(3) to SU(h).

[0774] Next, at time t(h+1), sequencer 204 applies programming voltage VPGM to select word line WLsel while the select gate lines SGD(1) to SGD(h) are respectively grounded with voltage VSS. The select word lines WL(1) to WLsel(h) corresponding to PG(1) on page 1 to PG(h) on page h can be associated with different word lines WL or with the same word line WL. Thus, the threshold voltage of the memory cell transistor MT to which programming voltage VPGM is applied either rises or remains constant depending on the set data (channel voltage). Specifically, in memory cell transistor MT where the channel voltage is maintained at voltage VSS, the threshold voltage rises. However, in memory cell transistor MT where the channel voltage rises based on voltage VBLinh, the rise in threshold voltage is suppressed.

[0775] The sequencer 204, having completed processing from time t(1) to time t(h+1), terminates the multi-value write operation, causing the storage device 20 to transition from a busy state to a ready state. Thus, the first example of the multi-value write operation in the ninth embodiment can write all the unit sets (CUs) of the programming object page set at once. Furthermore, tProg5 in the illustration represents the time taken to execute the first example of the multi-value write operation in the ninth embodiment. tProg5, for example, is shorter than the total time for executing h multi-value write operations.

[0776] [9-4] Example 2 of a multi-value write operation

[0777] Figure 118 This is a timing diagram illustrating a second example of a multi-value write operation of the storage device 20 in the ninth embodiment. For example... Figure 118 As shown, after the storage device 20 begins a multi-value write operation, it transitions from a ready state to a busy state. Before the write operation begins, the voltage of each bit line BL and each word line WL is, for example, the ground voltage VSS. Furthermore, the voltage of the bit line BL is controlled as shown by the solid line when it corresponds to the bit line BL being programmed. Figure 118 The “Program” is controlled as shown by the dashed line when it corresponds to the bit line BL that is prohibited from programming. Figure 118 (The "Inhibit").

[0778] Then, at time t(0), sequencer 204, with ground voltage VSS applied to the select gate lines SGD(1) to SGD(h) respectively, applies write pass voltage VPASS to the word lines WLsel(1) to WLsel(h) respectively. The write pass voltage VPASS is a voltage higher than the ground voltage VSS and lower than the programming voltage VPGM. As a result, the channel voltage of each NAND string NS of the string cell SU(1) to SU(h) increases based on the voltage of the select word line WLsel. In addition, the write pass voltage VPASS can also be applied to the word lines WL other than the select word line WLsel at time t(0).

[0779] Then, at time t(1), sequencer 204 applies voltage VSG to the select gate line SGD(1), and according to the data on page 1, applies ground voltage VSS to the bit line BL that is to be programmed, applies voltage VBLinh to the bit line BL that is to be disabled for programming, and applies ground voltage VSS to the other select gate lines SGD and select word lines WLsel. Then, in the serial cell SU(1), the channel of the NAND string NS connected to the bit line BL that is to be programmed is discharged via the select transistor ST1 which is in the on state. On the other hand, in the serial cell SU(1), the discharge of the channel voltage of the NAND string NS connected to the bit line BL that is to be disabled for programming is suppressed by applying voltage VBLinh to the bit line BL. In addition, since the select transistor ST1 is in the off state, the NAND string NS of the serial cell SU other than the serial cell SU(1) will not be discharged. Then, sequencer 204 lowers the voltage of the select gate line SGD(1) from VSG to VSS and fixes the channel voltage of each NAND string NS of the serial unit SU(1). Thus, through processing at time t(1), sequencer 204 can set the data of the first redundant page PG1 for each NAND string NS of the serial unit SU(1).

[0780] Subsequently, sequencer 204 performs the processing at times (2) to (h+1) in the same manner as the first example of the multi-value write operation in the 9th embodiment. In this case, the second example of the multi-value write operation in the 9th embodiment is also able to write multiple pages to multiple unit sets CU at one time, just like the first example of the multi-value write operation in the 9th embodiment.

[0781] [9-5] Instruction sequence for multi-value write operation

[0782] Figure 119 This is a sequence diagram illustrating an example of the instruction sequence for a multi-value write operation of the storage device 20 in the ninth embodiment. For example... Figure 119As shown, when the memory controller 10 commands the storage device 20 to perform a multi-value write operation, it sends, for example, “zzh”, “80h”, “ADD(1)”, “DAT(1)”, “ADD(2)”, “DAT(2)”, …, “ADD(h) (h is an integer greater than or equal to 2)”, “DAT(h)”, and “10h” to the storage device 20 in sequence. “zzh” is an instruction that specifies a multi-value write operation that is performed at one time, targeting multiple pages. “ADD(1)”, “ADD(2)”, …, “ADD(h)” are the addresses of the redundant page set selected as the target of the write operation. A set of ADD(1) and DAT(1), a set of ADD(2) and DAT(2), …, a set of ADD(h) and DAT(h) are associated with the redundant pages PG(1), PG(2), …, PG(h) respectively.

[0783] After receiving the instruction "10h", the sequencer 204, based on the instructions and addresses ADD(1), ..., ADD(h) stored in the register circuit 203, changes the storage device 20 from a ready state to a busy state. Then, the sequencer 204 executes, for example, the following... Figure 117 and Figure 118 The series of processes for multi-value write operations shown in any of the figures. Then, the data DAT(1) to DAT(h) are written to multiple cell sets CUs associated with addresses ADD(1), ..., ADD(h), respectively.

[0784] [9-6] Effects of the 9th embodiment

[0785] As explained above, the storage device 20 of the ninth embodiment can write multiple pages at once (simultaneously). As a result, the storage device 20 of the ninth embodiment can achieve high-speed writing operations. In addition, the ninth embodiment, in combination with the sixth embodiment, can improve data reliability. That is, the memory system MS of the ninth embodiment can also, in combination with the sixth embodiment, write multiple pages (h pages) × redundant pages (k) of data to the storage device 20 at once (simultaneously). Furthermore, the ninth embodiment can also be combined with any of the first to eighth embodiments.

[0786] Furthermore, in the ninth embodiment, an example is shown where the memory system MS omits the verification operation (verification read) after simultaneously writing the same data to multiple pages, but it is not limited to this. The memory system MS may also perform a verification read after simultaneously writing data to multiple pages, and if there are cells that do not reach a specified threshold, perform an additional write operation. The verification read in the ninth embodiment is, for example, performed independently page by page for the data written simultaneously to multiple pages. Afterwards, the memory system MS may also independently set the channel voltage (set data) of the NAND string NS for each page of the memory cell transistor MT that did not reach the verification level during the verification read, and perform an additional write operation.

[0787]

[10] Other

[0788] In the data allocation described in the above embodiment, the data allocation for each page can also be swapped between pages. The instructions used in the above embodiment are ultimately just one example. For example, the instructions “01h” to “05h”, “xxh”, “yyh”, and “zzh” can all be replaced with any instruction. Instructions such as “01h” to “05h” that specify the page to be read can also be omitted by making the address “ADD” contain page information. The address “ADD” can also be sent in multiple cycles. The instruction sequence described in the above embodiment is ultimately just one example. Other instruction sequences can also be used as long as they can instruct the actions described in the above embodiment. In the read operation of the first embodiment, the sequencer 204 can also change the storage device 20 from a busy state to a ready state based on the data being determined. In this case, after the memory controller 10 determines the result of the command to the storage device 20 to transmit data to the latch circuit XDL, it commands the storage device 20 to output the determined page data.

[0789] In embodiments 4 and 5, multiple memory plane LUNs operate in parallel, but this is not limited to the case where the start time of each operation is the same. The start times of each operation can be different as long as they overlap within a certain period. For example, when four memory planes LUN1 to LUN4 operate in parallel, they can be executed in the following order: LUN1 starts operating, LUN2 starts operating, LUN3 starts operating, LUN4 starts operating, LUN1 ends operating, LUN2 ends operating, LUN3 ends operating, and LUN4 ends operating. Alternatively, in this example, the start of LUN4's operation and the end of LUN1's operation can be executed in the reverse order.

[0790] In embodiments 4 and 5, the storage device 20 is illustrated as having four memory surface LUNs, but it is not limited to this. Embodiments 4 and 5 can also be applied to cases where the storage device 20 has at least a plurality of memory surface LUNs. In embodiments 4 and 5, when the multi-value or less memory cell array 207 is combined with the super-multi-value memory cell array 207, the multi-value or less memory cell array 207 is used, for example, as a buffer region to speed up operation. That is, by combining the multi-value or less memory cell array 207 with the super-multi-value memory cell array 207, embodiments 4 and 5 enable high-speed operation of the storage device 20.

[0791] The redundant page readout and redundant page one-time readout operations in embodiments 6 to 9 are ultimately just one example. The detailed operations of redundant page readout and redundant page one-time readout can be appropriately modified according to the circuit configuration of the sense amplifier unit SAU.

[0792] The voltage applied to the select word line WLsel during the readout operation is, for example, the same voltage as the signal line CG supplied by the driver circuit 206 to the line decoder module 208. The magnitude of the voltage applied to each line and the duration of the applied voltage can be roughly determined by observing the voltage of the corresponding signal line CG. When estimating the voltages of the select gate line and word line based on the voltages of each signal line connected to the driver circuit 206, the voltage drop of the transistor TR included in the line decoder RD can also be taken into account. In this case, the voltages of the select gate line and word line are lower than the voltages applied to the corresponding signal lines by a degree corresponding to the voltage drop of the transistor TR.

[0793] In this specification, "connected" means electrically connected, but does not exclude cases where other components are in between. "On state" means that the gate of the corresponding transistor is subjected to a voltage greater than or equal to the transistor's threshold voltage ("H" level voltage). "Off state" means that the gate of the corresponding transistor is subjected to a voltage less than or equal to the transistor's threshold voltage ("L" level voltage). Even in the off state, a small amount of current, such as leakage current, may flow through the transistor. "Readout voltage" can also be called "readout level". "Lowest readout voltage" refers to the lowest readout voltage in the specified group. "Highest readout voltage" refers to the highest readout voltage in the specified group.

[0794] Furthermore, some or all of the embodiments described may also be described as follows, but are not limited to the following:

[0795] [Postscript 1]

[0796] A storage device comprising:

[0797] The first storage cell array group has storage cells that store data through a threshold value of K (K is an integer greater than or equal to 1), and has a (a is an integer greater than or equal to 1) first storage cell arrays;

[0798] The second storage cell array group has storage cells that store data using a threshold value L (L is an integer greater than K), and has b (b is an integer greater than 1) second storage cell arrays; and

[0799] Sequencer; and

[0800] The sequencer simultaneously performs writes of data with values ​​below K to c (c is less than or equal to a) of the first storage cell array and writes of data with values ​​below L to d (d is less than or equal to b) of the second storage cell array.

[0801] [Postscript 2]

[0802] The storage device according to Appendix 1 further comprises:

[0803] The first sensing amplifier unit is connected to the memory cells of the first memory cell array; and

[0804] The second sensing amplifier unit is connected to the memory cells of the second memory cell array; and

[0805] The second sensing amplifier unit contains more latching circuits than the first sensing amplifier unit.

[0806] [Postscript 3]

[0807] A storage device comprising:

[0808] The first storage cell array group has storage cells that can be selected to store data by a threshold value of K (K is an integer greater than or equal to 1) or L (L is an integer greater than K), and has a (a is an integer greater than or equal to 1) first storage cell arrays.

[0809] The second storage cell array group has storage cells that can be selected to store data based on a threshold value of K (K is an integer greater than or equal to 1) or L (L is an integer greater than K), and has b (b is an integer greater than or equal to 1) second storage cell arrays; and

[0810] Sequencer; and

[0811] The sequencer simultaneously performs writes of data with values ​​below K to c (c is less than or equal to a) of the first storage cell array and writes of data with values ​​below L to d (d is less than or equal to b) of the second storage cell array.

[0812] [Postscript 4]

[0813] The storage device according to Appendix 3 further comprises:

[0814] The first sensing amplifier group is connected to the memory cells of the first memory cell array;

[0815] The second sensing amplifier group is connected to the memory cells of the second memory cell array;

[0816] A latching circuit is connected to the first sensing amplifier group and the second sensing amplifier group; and

[0817] Sequencer; and

[0818] When the sequencer writes data with a value less than L to the storage cells of the first storage cell array group, it drives both the first sensing amplifier group and the latch circuit mentioned above. When it writes data with a value less than L to the storage cells of the second storage cell array group, it drives both the second sensing amplifier group and the latch circuit mentioned above.

[0819] [Postscript 5]

[0820] According to the storage device described in Appendix 1 or 3, wherein

[0821] The start time of writing data to the first storage cell array is different from that of writing data to the second storage cell array.

[0822] [Postscript 6]

[0823] According to the storage device described in Appendix 1 or 3, wherein

[0824] The start time of writing data to the first storage cell array is approximately the same as that of writing data to the second storage cell array.

[0825] [Postscript 7]

[0826] A storage device comprising:

[0827] The first memory cell array has multiple pages containing multiple memory cell transistors capable of storing a value K (K being an integer greater than or equal to 1); and

[0828] Controller; and

[0829] The controller writes data to the first and second pages, which are included in the plurality of pages of the first storage cell array, without performing a verification read.

[0830] [Postscript 8]

[0831] According to the storage device described in Appendix 7, wherein

[0832] The value of K is 2, 3, or 4.

[0833] [Postscript 9]

[0834] According to the storage device described in Appendix 7, wherein

[0835] If, when reading the first page and the second page respectively, the controller reads out more than one data "0" for the same column address in the first page and the second page respectively, then the data with the same column address will be treated as data "0".

[0836] [Postscript 10]

[0837] According to the storage device described in Appendix 7, wherein

[0838] If, when the controller reads both the first page and the second page at once, there are more than one data "0" in the read results of the first page and the second page that are assigned the same column address, based on the sensing level, then the controller will treat it as data "0".

[0839] [Postscript 11]

[0840] A memory system comprising a memory device according to Appendix 7, further comprising a second memory cell array, and a memory controller for controlling the memory device, the second memory cell array having multiple pages including multiple memory cell transistors capable of storing a value L (L being an integer greater than K); and the memory controller copying data written to the first memory cell array into the second memory cell array.

[0841] [Postscript 12]

[0842] A storage device comprising:

[0843] The first memory cell array has multiple pages containing multiple memory cell transistors capable of storing a value K (K being an integer greater than or equal to 1); and

[0844] Controller; and

[0845] The controller writes data to the first and second pages, which are included in the plurality of pages of the first storage unit array, without performing a verification read.

[0846] [Postscript 13]

[0847] According to the storage device described in Appendix 12, wherein

[0848] When the controller performs a read operation, it reads the data from the first and second pages respectively, performs a majority decision on the read data from the first and second pages, and uses the result of the majority decision as the read result.

[0849] [Postscript 14]

[0850] According to the storage device described in Appendix 12, wherein

[0851] The controller writes da...

Claims

1. A storage device comprising: Multiple storage units, each storing 5 bits of data including the first, second, third, fourth, and fifth bits of data according to a threshold voltage; Word lines connect to the plurality of storage units; and The controller performs a read operation to read data from the plurality of memory cells by applying a read voltage to the word lines; and The plurality of storage units store pages 1, 2, 3, 4, and 5, respectively, containing the first bit of data, the second bit of data, the third bit of data, the fourth bit of data, and the fifth bit of data. The controller applies different readout voltages to the word lines 7 times, 6 times, 6 times, 6 times, and 6 times respectively during the readout operations of pages 1, 2, 3, 4, and 5. The 5-bit data is any one of multiple datasets consisting of distinct datasets 1 through 32. The threshold voltage of the memory cell includes any of the different states from state 1 to state 32, and The multiple datasets are assigned to states 1 through 32, with adjacent states differing by only one bit. The distinct first to 31st readout voltages are set to correspond to adjacent states among the first to 32 states, and The interval between the readout voltage applied to the word line by the controller during the readout operation of each of the pages 1 to 5 is a minimum of 3 states and a maximum of 8 states.

2. The storage device according to claim 1, wherein If either condition 1 or condition 2 is met, The first condition refers to the fact that the lowest read voltage used in the read operation of the first page is separated from the lowest read voltage among the first read voltage to the 31st read voltage by one state. The second condition refers to the fact that the uppermost read voltage used in the read operation of the first page is separated from the uppermost of the 31st read voltage among the first read voltage to the 31st read voltage by one state.

3. The storage device according to claim 2, wherein If the first condition and the other of the second condition, as well as each of the third, fourth, and fifth conditions are not satisfied, The third condition refers to the fact that the minimum interval between the multiple readout voltages used in the readout operation of the first page is three states. The fourth condition refers to the fact that the minimum interval between the multiple read voltages used in the read operation of a page using the first read voltage or the 31st read voltage is three states. The fifth condition refers to the fact that pages 1 to 5 include pages in which both the first readout voltage and the 31st readout voltage are used for the readout operation.

4. The storage device according to claim 1, wherein Each of the conditions satisfying conditions 2 and 4, The second condition refers to the fact that the uppermost read voltage used in the read operation of the first page is separated from the uppermost of the 31st read voltages among the first read voltages to the 31st read voltages by one state. The fourth condition refers to the minimum interval between multiple read voltages used in the read operation of a page using the first read voltage or the 31st read voltage being 3 states.

5. The storage device according to claim 4, wherein Each of the conditions that are not met (conditions 1, 3, and 5) The first condition refers to the fact that the lowest read voltage used in the read operation of the first page is separated from the lowest read voltage among the first read voltage to the 31st read voltage by one state. The third condition refers to the fact that the minimum interval between the multiple readout voltages used in the readout operation of the first page is three states. The fifth condition refers to the fact that pages 1 to 5 include pages in which both the first readout voltage and the 31st readout voltage are used for the readout operation.

6. The storage device according to claim 1, wherein Each of the conditions satisfying conditions 1, 2, and 3, The first condition refers to the fact that the lowest read voltage used in the read operation of the first page is separated from the lowest read voltage among the first read voltage to the 31st read voltage by one state. The second condition refers to the fact that the uppermost read voltage used in the read operation of the first page is separated from the uppermost of the 31st read voltages among the first read voltages to the 31st read voltages by one state. The third condition refers to the fact that the minimum interval between the multiple readout voltages used in the readout action of the first page is three states.

7. The storage device according to claim 6, wherein Each one that does not meet conditions 4 and 5 The fourth condition refers to the fact that the minimum interval between the multiple read voltages used in the read operation of a page using the first read voltage or the 31st read voltage is three states. The fifth condition refers to the fact that pages 1 to 5 include pages in which both the first readout voltage and the 31st readout voltage are used for the readout operation.

8. The storage device according to claim 1, wherein Each of the conditions satisfying conditions 2, 3, and 4, The second condition refers to the fact that the uppermost read voltage used in the read operation of the first page is separated from the uppermost of the 31st read voltages among the first read voltages to the 31st read voltages by one state. The third condition refers to the fact that the minimum interval between the multiple readout voltages used in the readout operation of the first page is three states. The fourth condition refers to the minimum interval between multiple read voltages used in the read operation of a page using the first read voltage or the 31st read voltage being 3 states.

9. The storage device according to claim 8, wherein Each one that does not meet conditions 1 and 5 The first condition refers to the fact that the lowest read voltage used in the read operation of the first page is separated from the lowest read voltage among the first read voltage to the 31st read voltage by one state. The fifth condition refers to the fact that pages 1 to 5 include pages in which both the first readout voltage and the 31st readout voltage are used for the readout operation.

10. The storage device according to claim 1, wherein Each of the conditions 1, 2, 3, and 4 is satisfied. The first condition refers to the fact that the lowest read voltage used in the read operation of the first page is separated from the lowest read voltage among the first read voltage to the 31st read voltage by one state. The second condition refers to the fact that the uppermost read voltage used in the read operation of the first page is separated from the uppermost of the 31st read voltages among the first read voltages to the 31st read voltages by one state. The third condition refers to the fact that the minimum interval between the multiple readout voltages used in the readout operation of the first page is three states. The fourth condition refers to the minimum interval between multiple read voltages used in the read operation of a page using the first read voltage or the 31st read voltage being 3 states.

11. The storage device according to claim 10, wherein Condition 5 is not met. The fifth condition refers to the fact that pages 1 to 5 include pages in which both the first readout voltage and the 31st readout voltage are used for the readout operation.

12. The storage device according to claim 1, wherein Each one that satisfies conditions 3 and 5. The third condition refers to the fact that the minimum interval between the multiple readout voltages used in the readout operation of the first page is three states. The fifth condition refers to the fact that pages 1 to 5 include pages in which both the first readout voltage and the 31st readout voltage are used for the readout operation.

13. The storage device according to claim 12, wherein Each of the conditions that are not met (conditions 1, 2, and 4) The first condition refers to the fact that the lowest read voltage used in the read operation of the first page is separated from the lowest read voltage among the first read voltage to the 31st read voltage by one state. The second condition refers to the fact that the uppermost read voltage used in the read operation of the first page is separated from the uppermost of the 31st read voltages among the first read voltages to the 31st read voltages by one state. The fourth condition refers to the minimum interval between multiple read voltages used in the read operation of a page using the first read voltage or the 31st read voltage being 3 states.

14. A storage device comprising: Multiple storage units, each storing 5 bits of data including the first, second, third, fourth, and fifth bits of data according to a threshold voltage; Word lines connect to the plurality of storage units; and The controller performs a read operation to read data from the plurality of memory cells by applying a read voltage to the word lines; and The plurality of storage units store pages 1, 2, 3, 4, and 5, respectively, containing the first bit of data, the second bit of data, the third bit of data, the fourth bit of data, and the fifth bit of data. The controller applies different readout voltages to the word lines 7 times, 6 times, 6 times, 6 times, and 6 times respectively during the readout operations of pages 1, 2, 3, 4, and 5. The 5-bit data is any one of multiple datasets consisting of distinct datasets 1 through 32. The threshold voltage of the memory cell includes any of the different states from state 1 to state 32, and The multiple datasets are assigned to states 1 through 32, with adjacent states differing by only one bit. The distinct first to 31st readout voltages are set to correspond to adjacent states among the first to 32 states, and The interval between the readout voltage applied to the word line by the controller during the readout operation of each of the pages 1 to 5 is a minimum of 3 states and a maximum of 9 states.

15. The storage device according to claim 14, wherein The interval of the readout voltage in the readout action of the first page consists of only 4 states.

16. A storage device comprising: Multiple storage units, each storing 5 bits of data, including the first to fifth bits, according to a threshold voltage; Word lines, connected to the plurality of memory cells; and The controller performs the read operation; and The plurality of storage units respectively store pages 1 to 5 corresponding to the 1st to 5th bits of data. The threshold voltage of the memory cell includes any of the different states from state 1 to state 32. Each of the 1st to 32nd states is assigned a distinct 5-bit data. Corresponding to the adjacent states between states 1 to 32, the first readout voltage to the 31st readout voltage are set sequentially in ascending order of voltage. The controller In the readout operation of the first page, seven readouts are performed, applying the fourth, eighth, twelfth, eighteenth, twenty-second, twenty-sixth, and thirtyth readout voltages to the word lines respectively. In the readout operation of the second page, six readouts are performed, applying the 6th readout voltage, the 13th readout voltage, the 16th readout voltage, the 20th readout voltage, the 23rd readout voltage, and the 28th readout voltage to the word line respectively. In the readout operation of the third page, six readouts are performed, applying the third readout voltage, the ninth readout voltage, the fifteenth readout voltage, the twenty-first readout voltage, the twenty-seventh readout voltage, and the thirty-first readout voltage to the word line respectively. In the readout operation on page 4, six readouts are performed, applying the second, seventh, tenth, fourteenth, seventeenth, and twenty-fourth readout voltages to the word lines respectively. In the readout operation on page 5, six readouts are performed, applying the first readout voltage, the fifth readout voltage, the eleventh readout voltage, the nineteenth readout voltage, the twenty-fifth readout voltage, and the twenty-ninth readout voltage to the word line respectively.

17. The storage device according to claim 16, wherein Both the first readout voltage and the second readout voltage are negative voltages.

18. The storage device according to claim 16, wherein During the readout operation of the first page, the controller sequentially applies the 30th readout voltage, the 26th readout voltage, the 22nd readout voltage, the 18th readout voltage, the 12th readout voltage, the 8th readout voltage, and the 4th readout voltage to the word line.

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