Memory and memory repair method

Abstract

The application discloses a memory, comprising a storage area, a failure record area and a repair circuit; the storage area is provided with redundant bits; the failure record area is provided with multi-state bits, the multi-state bits are used for recording position information of failure bits in the storage area; and the repair circuit is used for repairing the failure bits through the redundant bits according to the position information. Since the multi-state bits represent ternary or other systems, more information can be stored by using the multi-state bits to store information compared with traditional binary, so that the repair bits used in repair are less than those in a traditional repair mode, the repair efficiency is high, resource consumption is low, and meanwhile, instant repair can be carried out in the working process of a chip, and the reliability of the chip is improved. The application further provides a memory repair method, which also has the beneficial effects.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a memory and a memory repair method. Background Technology

[0002] In integrated circuits, to improve the yield of memory chips, some internal space is used as a redundant storage bit area when designing the memory. When a faulty bit is detected, the redundant storage bit can be used to replace the faulty bit for repair.

[0003] Currently, memory repair typically employs redundant circuitry. However, the structure of row redundancy circuitry is relatively complex. Adding row redundancy to the redundant storage bits of the memory would significantly increase the memory area. Moreover, the number of repair groups is usually small, often involving the repair of an entire row or column, resulting in low repair efficiency. Therefore, providing a memory with higher repair efficiency is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a memory with high repair efficiency; another purpose of this invention is to provide a memory repair method with high repair efficiency.

[0005] To solve the above-mentioned technical problems, the present invention provides a memory, including a storage area, a failure record area, and a repair circuit;

[0006] The storage area is equipped with redundant bits;

[0007] The failure record area is provided with polymorphic bits, which are used to record the position information of the failure bits in the storage area;

[0008] The repair circuit is used to repair the failed bit using the redundant bit according to the location information.

[0009] Optionally, the repair circuit is specifically used for:

[0010] Based on the location information, redundant bits are used to replace the faulty bits corresponding to the location information in order to repair the storage area.

[0011] Optionally, the polymorphic bit is a tri-state bit.

[0012] Optionally, each byte in the storage area is provided with the redundant bits.

[0013] Optionally, it also includes an ECC repair circuit, and the storage area further includes an ECC data area; the ECC data area includes ECC bits, which are used to store ECC information corresponding to the failed bits in the storage area; the ECC repair circuit is used to repair the failed bits according to the ECC information.

[0014] Optionally, the polymorphic bit is also used to record the location information of the failed bit in the ECC data area.

[0015] Optional features also include registers, an internal self-test module, and a failure monitoring module;

[0016] The failure detection module is used to store the failure address of the corresponding failure bit generated in the ECC data area into the register;

[0017] The internal self-test module is used for:

[0018] Write the failure address and the corresponding ECC information into the register;

[0019] The location information corresponding to the failure address is written into the polymorphic bit, so that the failure bit can be repaired by the repair circuit according to the location information through the redundant bit;

[0020] After repairing the faulty bit, data is written to the repaired bit according to the faulty address and ECC information stored in the register.

[0021] The present invention also provides a memory repair method, comprising:

[0022] Obtain memory repair instructions;

[0023] The memory repair instruction calls the repair circuit, and the faulty bits in the storage area are repaired by using redundant bits according to the location information; the location information is the location information of the faulty bits in the storage area recorded in the polymorphic bits, and the polymorphic bits are the polymorphic bits set in the fault record area; the redundant bits are the redundant bits set in the storage area.

[0024] Optionally, the step of invoking the repair circuit according to the memory repair instruction and repairing the failed bits in the memory area using redundant bits based on the location information includes:

[0025] The memory repair instruction invokes the repair circuit, and based on the location information, redundant bits are used to replace the faulty bits corresponding to the location information in order to repair the memory area.

[0026] Optionally, after obtaining the memory repair instruction, the method further includes:

[0027] Detect the failure information recorded in the failure record area;

[0028] The step of invoking the repair circuit according to the memory repair instruction, and repairing the failed bits in the memory area using redundant bits based on the location information, includes:

[0029] When the failure information indicates that the failed bits in the storage area need to be repaired, the repair circuit is invoked, and the failed bits in the storage area are repaired using redundant bits based on the location information.

[0030] Optionally, after detecting the failure information recorded in the failure record area, the method further includes:

[0031] When the failure information does not indicate that the failed bits in the storage area need to be repaired, detect whether there are failed bits in the storage area;

[0032] When a faulty bit exists in the storage area, it is detected whether there is a storable polymorphic bit in the fault record area;

[0033] When there are storable polymorphic bits in the failure record area, the position information corresponding to the failure bit is stored in the storable polymorphic bit.

[0034] Optional, also includes:

[0035] Obtain the failure record area detection command;

[0036] According to the failure record area detection instruction, the failure bits in the failure record area are burned to the failure state.

[0037] The present invention provides a memory comprising a storage area, a failure recording area, and a repair circuit. The storage area is provided with redundant bits; the failure recording area is provided with polymorphic bits, which are used to record the position information of the failure bits in the storage area; the repair circuit is used to repair the failure bits according to the position information using the redundant bits. Since the polymorphic bits represent ternary or other bases, storing information using polymorphic bits can store more information than traditional binary data, thus requiring fewer repair bits during repair, resulting in higher repair efficiency and lower resource consumption. Furthermore, real-time repair can be performed during chip operation, improving chip reliability.

[0038] The present invention also provides a memory repair method, which has the same beneficial effects as described above, and will not be described in detail here. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic diagram of a redundant bit repair method;

[0042] Figure 3 This is a schematic diagram of another method for repairing redundant bits;

[0043] Figure 4 This is a schematic diagram of a specific memory structure provided in an embodiment of the present invention;

[0044] Figure 5 This is a schematic diagram of another specific memory structure provided in an embodiment of the present invention;

[0045] Figure 6 A flowchart of a memory repair method provided in an embodiment of the present invention;

[0046] Figure 7 This is a flowchart of a specific memory repair method provided in an embodiment of the present invention.

[0047] In the diagram: 1. Repair circuit, 2. Failure monitoring module, 3. Register, 4. Internal self-test module. Detailed Implementation

[0048] The core of this invention is to provide a memory. In the prior art, memory generally uses redundant circuits for repair, but the structure of row redundancy circuits is relatively complex. If row redundancy is added to the redundant storage bits of the memory, it will cause a large increase in memory area; moreover, the number of repair groups is usually small, and usually an entire row or column is repaired, resulting in low repair efficiency.

[0049] The present invention provides a memory comprising a storage area, a failure recording area, and a repair circuit. The storage area is provided with redundant bits; the failure recording area is provided with polymorphic bits, which are used to record the position information of the failure bits in the storage area; the repair circuit is used to repair the failure bits according to the position information using the redundant bits. Since the polymorphic bits represent ternary or other bases, storing information using polymorphic bits can store more information than traditional binary data, thus requiring fewer repair bits during repair, resulting in higher repair efficiency and lower resource consumption. Furthermore, real-time repair can be performed during chip operation, improving chip reliability.

[0050] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Please refer to Figures 1 to 3 , Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a redundant bit repair method; Figure 3 This is a schematic diagram of another method for repairing redundant bits.

[0052] See Figure 1 In this embodiment of the invention, the memory includes a storage area, a failure record area, and a repair circuit 1; the storage area is provided with redundant bits; the failure record area is provided with polymorphic bits, which are used to record the position information of the failure bits in the storage area; the repair circuit 1 is used to repair the failure bits according to the position information through the redundant bits.

[0053] The aforementioned storage area is used to store regular data. This storage area typically has multiple bytes, and each byte includes multiple bits. In this embodiment of the invention, the storage area is provided with redundant bits, which are used to repair failed bits, i.e., faulty bits. In this embodiment of the invention, the aforementioned faulty bits typically include hard faulty bits and bad bits. Generally, each byte in the aforementioned storage area needs to be provided with redundant bits to ensure that faulty bits in each byte of the storage area can be repaired in a timely manner.

[0054] The aforementioned failure record area is used to record the location information of failed bits in the storage area. This failure record area specifically contains polymorphic bits, which are used to record the location information of failed bits in the storage area. Specifically, in this embodiment of the invention, the polymorphic bit is typically a tri-state bit, but other polymorphic bits are also possible, depending on the specific situation. The aforementioned polymorphic bit can be a high-resistance state, a low-resistance state, a breakdown state, or other states as tri-state or more states. Since the polymorphic bit represents ternary or other bases, it stores more information than traditional methods, and fewer bits can be used to repair failed bits compared to traditional binary methods.

[0055] The aforementioned repair circuit 1 is used to repair failed bits based on the location information recorded in the failure record area using redundant bits set in the storage area. Specifically, in this embodiment of the invention, the repair circuit 1 is specifically used to: replace the failed bits corresponding to the location information with redundant bits according to the location information, so as to repair the storage area. That is, in this embodiment of the invention, the failed bits are located using the location information recorded in the polymorphic bits, and then the failed bits are replaced with redundant bits, i.e., the storage area is repaired. Specifically, in this embodiment of the invention, the failure record area may be provided with one or more sets of polymorphic bits, and each set of polymorphic bits may record failed bits of one or more storage areas.

[0056] In this embodiment of the invention, two alternative methods are specifically provided, both of which can replace the failed bit. See also Figure 2 The first method is redundancy replacement, which uses redundant bits to directly replace invalid bits, while the positions of the remaining bits remain unchanged; see also Figure 3 The second method is to remove bad bits by shifting and replacing them. This involves removing the faulty bits and then shifting other bits in the storage area, usually other bits in the same byte, to fill the gaps created when removing the faulty bits. After the shift, the beginning of the byte will usually be empty. Finally, redundant bits are filled into the gaps after the shift, usually at the beginning of the byte where the faulty bits are located.

[0057] Specifically, the aforementioned repair circuit 1 can locate the failed bit based on the position information recorded in the failure record area and mark the IO of the failed bit. Then, when writing data again, the repair circuit 1 will select the IO of the unmarked bit and the IO of the redundant bit, and rearrange the selected IO. The repair circuit 1 will rearrange the selected IO to form a new storage bit by means of the aforementioned redundancy replacement or bad point removal shift replacement repair method. Finally, the written data will be written to the corresponding bit according to the selected IO to complete the repair of the failed bit and realize the data storage.

[0058] In this embodiment of the invention, taking a tri-state bit as a multi-state bit as an example, assuming that the storage area is set with 8 bits of regular bits + 1 bit of redundant bits, and the failure record area is two tri-state bits, the truth table of the failure record area is shown in Table 1 below:

[0059] Table 1. Truth Table for Failure Record Area

[0060]

[0061]

[0062] Compared with existing ECC (Error Correcting Code) repair technologies, the resources used by the repair structure disclosed in this embodiment of the invention and the resources used by ECC repair are compared in Table 2 for 8-bit data storage:

[0063] Table 2. Comparison of 8-bit data storage bit repair capability and required resources

[0064] Repair capabilities Resources required for this application Resources required for ECC repair 1 bit 3bit 4bit 2bit 7bit 10-bit 3bit 13-bit or 16-bit >16bit

[0065] The comparison of 64-bit data storage bits is shown in Table 3 below:

[0066] Table 3. Comparison of 64-bit data storage bit repair capability and required resources

[0067] Repair capabilities Resources required for this application Resources required for ECC repair 1 bit 5bit 7bit 2bit 12bit 14bit 3bit 19-bit or 24-bit >24bit

[0068] Obviously, the memory provided in this embodiment of the invention can repair faulty bits using fewer resources.

[0069] The present invention provides a memory comprising a storage area, a failure recording area, and a repair circuit 1. The storage area is provided with redundant bits; the failure recording area is provided with polymorphic bits, which are used to record the position information of the failure bits in the storage area; the repair circuit 1 is used to repair the failure bits according to the position information using the redundant bits. Since the polymorphic bits represent ternary or other bases, storing information using polymorphic bits can store more information than traditional binary numbers, thus requiring fewer repair bits during repair, resulting in higher repair efficiency and lower resource consumption. Furthermore, real-time repair can be performed during chip operation, improving chip reliability.

[0070] The specific details of the memory provided by this invention will be described in detail in the following embodiments.

[0071] Please refer to Figure 4 as well as Figure 5 , Figure 4This is a schematic diagram of a specific memory structure provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another specific memory structure provided in an embodiment of the present invention.

[0072] See Figure 4 In this embodiment of the invention, an ECC repair circuit is also included, and the storage area further includes an ECC data area; the ECC data area includes ECC bits, which are used to store ECC information corresponding to the failed bits in the storage area; the ECC repair circuit is used to repair the failed bits according to the ECC information.

[0073] In this embodiment of the invention, ECC repair technology can be applied simultaneously, with an ECC data area and an ECC repair circuit set up in the memory. The ECC data area includes ECC bits, which are used to store ECC information of the failed bits in the corresponding memory area. This ECC information is typically an ECC error correction code. The aforementioned ECC repair circuit is used to repair the failed bits in the memory area based on the ECC information. This ECC repair circuit is a circuit specifically designed for ECC repair technology and is not equivalent to the repair circuit 1 involved in the above embodiment. The specific content of this ECC repair circuit and the aforementioned ECC information can be found in existing technology and will not be elaborated further here.

[0074] It should be noted that, at present, failed bits typically include hard failed bits and defective bits. Hard failed bits are irreversible and remain in a failed state forever after failure. Defective bits are random failures that can be recovered to a normal state. The repair technology provided in the above-described embodiments is more suitable for repairing hard failed bits, while ECC repair technology is more suitable for repairing defective bits. Therefore, when a failed bit is detected in the storage area, the type of the failed bit can be further determined. When the failed bit is specifically a hard failed bit, it can be repaired using the method provided in the above-described embodiments; when the failed bit is specifically a defective bit, it can be repaired using ECC repair technology, based on the ECC data area and ECC repair circuit. Correspondingly, when all the above-described redundant bits have been used, only the failed bit can be repaired using ECC repair technology.

[0075] Furthermore, in this embodiment of the invention, the polymorphic bits are also used to record the location information of failed bits in the ECC data area. That is, in this embodiment of the invention, the aforementioned failure record area, combined with the redundant bit repair technology, can specifically repair failed bits in the ECC data area. Specifically, when a failed bit exists in the ECC data area, the location information corresponding to the failed bit can also be stored in the polymorphic bits of the failure record area. Then, the repair circuit 1 can use redundant bits to replace the failed bits in the ECC data area according to the aforementioned location information to complete the repair of the failed bits in the ECC data area. The repair process for failed bits in the ECC data area can be referred to the repair process for failed bits in the storage area in the above embodiments of the invention, and will not be repeated here.

[0076] See Figure 5 Specifically, in this embodiment of the invention, the memory may further include a register 3, an internal self-test module 4, and a failure monitoring module 2; the failure monitoring module is used to store the failure address of the corresponding failure bit generated by the ECC data area into the register 3; the internal self-test module 4 is used to: write the failure address and the ECC information corresponding to the failure address into the register 3; write the position information corresponding to the failure address into the polymorphic bit, so that the repair circuit 1 can repair the failure bit according to the position information through the redundant bit; after repairing the failure bit, write data into the repaired bit according to the failure address and the ECC information stored in the register 3.

[0077] The aforementioned failure monitoring module 2, also known as the failure monitoring circuit, in this embodiment of the invention, when a bit failure occurs in the storage area, generating a failed bit, the ECC data area can record the address of the failed bit, i.e., the failure address. This failed bit can be a failed bit generated after a regular storage bit in the storage area fails, or it can be a failed bit generated after a bit in the ECC data area fails. Accordingly, the failure address of the corresponding failed bit generated by the failure monitoring module's ECC data area can be stored in register 3. Specifically, in this embodiment of the invention, the aforementioned failure monitoring module 2 can be triggered by an ECC repair code or other methods. After being triggered, the failure monitoring module 2 saves the address of the failed bit in register 3.

[0078] The aforementioned internal self-test module 4, also known as the BIST module, can initiate the memory repair process when the memory or chip is idle, or under other conditions. Specifically, after the internal self-test module 4 is started, it can obtain the failure address from register 3, store the data stored in the failure bit corresponding to the failure address, and store the ECC information stored in the ECC data area into register 3.

[0079] Subsequently, the internal self-test module 4 can write the location information corresponding to the failure address into polymorphic bits, so as to repair the failure bits through the repair circuit 1. Specifically, the failure bits are replaced with redundant bits according to the aforementioned location information to achieve repair. Specifically, in this embodiment of the invention, the location information stored in the failure record area can be updated through the aforementioned failure monitoring module 2.

[0080] After repairing the faulty bits, the data stored in register 3, along with the ECC information, is written to the repaired bits to complete the data storage. Then, the internal self-test module 4 can clear the contents of register 3 and exit the current mode.

[0081] The memory provided in this embodiment of the invention can repair the ECC data area and can be used in conjunction with traditional ECC repair technology to achieve comprehensive repair of failed bits.

[0082] The following describes a memory repair method provided by an embodiment of the present invention. The memory repair method described below can be referred to in correspondence with the memory described above.

[0083] Please refer to Figure 6 , Figure 6 This is a flowchart of a memory repair method provided in an embodiment of the present invention.

[0084] The memory repair methods described in the two embodiments below can be applied to the aforementioned internal self-test module 4 or other controllers to achieve comprehensive memory repair. See also Figure 6 Memory repair methods include:

[0085] S101: Obtain memory repair instructions.

[0086] For details regarding the memory repair instruction, please refer to existing technologies; it will not be elaborated upon here. This memory repair instruction is primarily used to trigger the following process for repairing faulty bits.

[0087] S102: The repair circuit is invoked according to the memory repair instruction, and the faulty bits in the memory area are repaired by using redundant bits according to the location information.

[0088] In this embodiment of the invention, the location information is the location information of the failed bit in the storage area recorded in the polymorphic bit, and the polymorphic bit is the polymorphic bit set in the failed record area; the redundant bit is the redundant bit set in the storage area. The specific structure of the memory and the functions of its various parts have been described in detail in the above embodiments of the invention, and will not be repeated here.

[0089] In this step, repair circuit 1 is invoked according to the aforementioned memory repair instruction. Repair circuit 1 then repairs the faulty bits in the memory area based on the location information stored in the polymorphic bits and redundant bits. The specific repair process has been described in detail in the above embodiments and will not be repeated here. Specifically, this step may include: invoking repair circuit 1 according to the memory repair instruction; and replacing the faulty bits corresponding to the location information with redundant bits to repair the memory area. That is, this step typically repairs the memory area by replacing faulty bits with redundant bits.

[0090] The memory repair method provided in this embodiment of the invention uses polymorphic bits to store information. Since polymorphic bits represent ternary or other bases, more information can be stored using polymorphic bits compared to traditional binary systems. Therefore, fewer repair bits are used during repair, resulting in higher repair efficiency and lower resource consumption. Furthermore, real-time repair can be performed during chip operation, improving chip reliability.

[0091] The specific details of the memory repair method provided by this invention will be described in detail in the following embodiments.

[0092] Please refer to Figure 7 , Figure 7 This is a flowchart of a specific memory repair method provided in an embodiment of the present invention.

[0093] See Figure 7 In this embodiment of the invention, the memory repair method includes:

[0094] S201: Obtain memory repair instructions.

[0095] This step is basically the same as S101 above. For details, please refer to the above embodiments of the invention. It will not be repeated here.

[0096] S202: Detect the failure information recorded in the failure record area.

[0097] The failure information must at least include the aforementioned location information. Typically, this failure information is equivalent to the location information; that is, as long as the failure record area stores the location information, the repair circuit 1 can be invoked to repair the failed bits based on that location information. Of course, the failure information may also include other information, which is not specifically limited here.

[0098] S203: When the failure information indicates that the failed bits in the storage area need to be repaired, the repair circuit is invoked, and the failed bits in the storage area are repaired using redundant bits according to the location information.

[0099] When the failure information indicates that the failed bits in the storage area need to be repaired, for example when the failure record area stores location information, the repair circuit 1 is called again, and the failed bits in the storage area are repaired according to the location information through redundant bits.

[0100] S204: When the failure information does not indicate that the failed bits in the storage area need to be repaired, check whether there are failed bits in the storage area.

[0101] In this step, when the failure information indicates that the failed bits in the storage area do not need to be repaired, for example when the failure record area does not store location information, the system will further check whether there are failed bits in the storage area.

[0102] S205: When there are faulty bits in the storage area, check whether there are storable polymorphic bits in the fault record area.

[0103] In this step, when a faulty bit is detected in the storage area, the fault record area is further checked to see if there is a storable polymorphic bit, which is used to record the location information corresponding to the newly detected faulty bit.

[0104] If no faulty bits are detected in the memory area, it indicates that the memory does not need to be repaired at present, and the process will end.

[0105] S206: When there are storable polymorphic bits in the failure record area, store the position information corresponding to the failure bit into the storable polymorphic bit.

[0106] In this step, when there are storable polymorphic bits in the failure record area, the location information corresponding to the newly detected failure bit is stored in the polymorphic bit to repair the failure bit. After this step, the process can repeat step S203, or wait for the next retrieval of information recorded in the failure record area before repairing the failure bit.

[0107] Specifically, when there are no storable polymorphic bits in the failure record area, it indicates that the memory has failed, and the process needs to be terminated and an alarm needs to be issued.

[0108] S207: Obtain the failure record area detection command.

[0109] For details regarding the failure record area detection command, please refer to existing technologies; it will not be elaborated upon here. This failure record area detection command is primarily used to trigger the following process for detecting the failure record area.

[0110] It should be noted that the faulty record area detection instruction and the aforementioned memory repair instruction can be the same instruction, in order to detect the faulty record area. Accordingly, S208 below can be executed in parallel with any of the above steps or before or after any of the above steps, depending on the specific circumstances, and no specific limitation is made here.

[0111] S208: According to the failure record area detection command, the failure bits in the failure record area are burned to the failure state.

[0112] In this step, the first step is to check if there are any fault bits in the failure record area, including whether there are hard fault bits and defective bits. Then, in this step, the fault bits in the failure record area are programmed into a fault state. Specifically, defective bits are programmed into a fault state, while hard fault bits remain in a fault state, so that all fault bits in the failure record area are in a fault state.

[0113] When no failure bit exists in the failure record area, other failure types in the failure record area can be programmed to logic "1" or other states to initialize the failure types in the failure record area. After this step, you can continue to execute the above-mentioned S204 to check whether there is a failure bit in the memory area and execute subsequent steps, or you can end the process so that it can be used for the next memory repair. It depends on the specific situation, and no specific limitation is made here.

[0114] The memory repair method provided in this embodiment of the invention uses polymorphic bits to store information. Since polymorphic bits represent ternary or other bases, more information can be stored using polymorphic bits compared to traditional binary systems. Therefore, fewer repair bits are used during repair, resulting in higher repair efficiency and lower resource consumption. Furthermore, real-time repair can be performed during chip operation, improving chip reliability.

[0115] The various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0116] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0117] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0118] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0119] The present invention has been described in detail above as a memory and a memory repair method. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A memory, characterized in that, Includes a storage area, a failure record area, and a repair circuit; The storage area is equipped with redundant bits; The failure record area is provided with polymorphic bits, which are used to record the position information of the failure bits in the storage area; The repair circuit is used to repair the failed bit using the redundant bit according to the location information; Each byte in the storage area is provided with the redundant bits; The repair circuit is specifically used for: Based on the location information, redundant bits are used to replace the faulty bits corresponding to the location information in order to repair the storage area; The repair circuit is specifically used for: Redundant bits are used to directly replace invalid bits, while the positions of the remaining bits remain unchanged. Alternatively, remove the invalid bits, then shift the other bits in the same byte in the storage area to fill the gap created when the invalid bits were removed. After the shift, the beginning of the byte will be empty; fill the gap at the beginning of the shifted byte with redundant bits.

2. The memory according to claim 1, characterized in that, The polymorphic bit is a trimorphic bit.

3. The memory according to claim 1, characterized in that, It also includes an ECC repair circuit, and the storage area further includes an ECC data area; the ECC data area includes ECC bits, which are used to store ECC information corresponding to the failed bits in the storage area; the ECC repair circuit is used to repair the failed bits according to the ECC information.

4. The memory according to claim 3, characterized in that, The polymorphic bits are also used to record the location information of the failed bits in the ECC data area.

5. The memory according to claim 4, characterized in that, It also includes registers, an internal self-test module, and a failure monitoring module; The failure monitoring module is used to store the failure address of the corresponding failure bit generated in the ECC data area into the register; The internal self-test module is used for: Write the failure address and the corresponding ECC information into the register; The location information corresponding to the failed address is written into the polymorphic bit, so that the failed bit can be repaired by the repair circuit according to the location information through the redundant bit; After repairing the faulty bit, data is written to the repaired bit according to the faulty address and ECC information stored in the register.

6. A memory repair method, characterized in that, include: Obtain memory repair instructions; The memory repair instruction calls the repair circuit, and the faulty bits in the memory area are repaired using redundant bits based on the location information. The location information is the location information of the failed bit in the storage area recorded in the polymorphic bit, and the polymorphic bit is the polymorphic bit set in the failed record area; the redundant bit is the redundant bit set in the storage area; Each byte in the storage area is provided with the redundant bits; The step of repairing faulty bits in the storage area using redundant bits based on location information includes: Based on the location information, redundant bits are used to replace the faulty bits corresponding to the location information in order to repair the storage area; The step of replacing the faulty bits corresponding to the location information with redundant bits to repair the storage area includes: Redundant bits are used to directly replace invalid bits, while the positions of the remaining bits remain unchanged. Alternatively, remove the invalid bits, then shift the other bits in the same byte in the storage area to fill the gap created when the invalid bits were removed. After the shift, the beginning of the byte will be empty; fill the gap at the beginning of the shifted byte with redundant bits.

7. The method according to claim 6, characterized in that, Following the acquisition of the memory repair instruction, the following is also included: Detect the failure information recorded in the failure record area; The step of invoking the repair circuit according to the memory repair instruction, and repairing the failed bits in the memory area using redundant bits based on the location information, includes: When the failure information indicates that the failed bits in the storage area need to be repaired, the repair circuit is invoked, and the failed bits in the storage area are repaired using redundant bits based on the location information.

8. The method according to claim 7, characterized in that, After detecting the failure information recorded in the failure record area, the method further includes: When the failure information does not indicate that the failed bits in the storage area need to be repaired, detect whether there are failed bits in the storage area; When a faulty bit exists in the storage area, it is detected whether there is a storable polymorphic bit in the fault record area; When there are storable polymorphic bits in the failure record area, the position information corresponding to the failure bit is stored in the storable polymorphic bit.

9. The method according to claim 8, characterized in that, Also includes: Obtain the failure record area detection command; According to the failure record area detection instruction, the failure bits in the failure record area are burned to the failure state.

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