Heterojunction bipolar transistor and method of manufacturing the same

Abstract

The application provides a heterojunction bipolar transistor and a manufacturing method thereof, which comprises a collector region layer, a base region layer and an emitter region layer which are stacked in sequence, the base region layer comprises a gallium arsenide containing energy band layer, the energy band of the gallium arsenide containing energy band layer is lower than that of a gallium arsenide material, so that the energy band of the heterojunction bipolar transistor can be reduced; further, the base region layer further comprises a first gallium arsenide containing transition layer, the lattice constant transition is realized through the first gallium arsenide containing transition layer, so that the lattice mismatch between the collector region layer and the base region layer can be avoided; further, the base region layer further comprises a second gallium arsenide layer, the lattice matching between the emitter region layer and the base region layer can be realized through the second gallium arsenide layer. In the heterojunction bipolar transistor and the manufacturing method thereof provided by the application, a low-energy-band and high-quality heterojunction bipolar transistor can be obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a heterojunction bipolar transistor and a manufacturing method thereof. BACKGROUND

[0002] A heterojunction bipolar transistor (HBT) is a transistor structure formed by replacing a homogenous emitter junction of a bipolar junction transistor (BJT) with a heterojunction, i.e., replacing a homogenous emitter junction of a BJT with a heterojunction, and has advantages of high speed and low power consumption.

[0003] Please refer to Figure 1 A conventional HBT device includes, from bottom to top, a gallium arsenide substrate 100, an n-type gallium arsenide collector region layer 102, a P-type gallium arsenide base region layer 104, and an n-type indium gallium phosphide emitter region layer 106. The conventional HBT device has a high energy band, and those skilled in the art have been trying to reduce the energy band of the HBT device to further improve the performance of the device. SUMMARY

[0004] The present application aims to provide a heterojunction bipolar transistor and a manufacturing method thereof to solve the problem of high energy band of the heterojunction bipolar transistor in the prior art.

[0005] To solve the above technical problem, the present application provides a heterojunction bipolar transistor, which includes, from bottom to top, a gallium arsenide substrate, a collector region layer, a base region layer, an energy band layer containing arsenic gallium, a second gallium arsenide layer, and an emitter region layer.

[0006] The gallium arsenide substrate;

[0007] The collector region layer includes a first gallium arsenide layer, which is of a first conductivity type.

[0008] The base region layer includes:

[0009] A first transition layer containing arsenic gallium, which is of the first conductivity type or a second conductivity type, to realize a transition of lattice constant;

[0010] An energy band layer containing arsenic gallium, which is of the second conductivity type, and has an energy band lower than that of the gallium arsenide material; and

[0011] A second gallium arsenide layer, which is of the second conductivity type; and

[0012] The emitter region layer includes an indium gallium phosphide layer, which is of the first conductivity type.

[0013] Optionally, in the heterojunction bipolar transistor, the base region layer further comprises: a second arsenic-gallium-containing transition layer, a third gallium arsenide layer and a third arsenic-gallium-containing transition layer between the arsenic-gallium-containing band gap layer and the second gallium arsenide layer, the second arsenic-gallium-containing transition layer, the third gallium arsenide layer and the third arsenic-gallium-containing transition layer are of the second conductivity type.

[0014] Optionally, in the heterojunction bipolar transistor, the arsenic-gallium-containing band gap layer, the second arsenic-gallium-containing transition layer, the third gallium arsenide layer and the third arsenic-gallium-containing transition layer are periodically grown, and the growth period is between 5 layers and 20 layers.

[0015] Optionally, in the heterojunction bipolar transistor, the materials of the first arsenic-gallium-containing transition layer, the second arsenic-gallium-containing transition layer, the third arsenic-gallium-containing transition layer and the arsenic-gallium-containing band gap layer are at least one selected from GaAsSb x , In y GaAsSb x , In y GaAs and Al z GaAs, wherein the values of x, y and z are between 0 and 1.

[0016] Optionally, in the heterojunction bipolar transistor, the material of the first arsenic-gallium-containing transition layer is GaAsSb x1 , and the subscript x1 increases from 0 to 1 from the bottom surface to the top surface; the material of the second arsenic-gallium-containing transition layer is GaAsSb x2 , and the subscript x2 decreases from 1 to 0 from the bottom surface to the top surface; the material of the third arsenic-gallium-containing transition layer is GaAsSb x3 , and the subscript x3 increases from 0 to 1 from the bottom surface to the top surface; and the material of the arsenic-gallium-containing band gap layer is GaAsSb x4 , and the subscript X4 is 1 from the bottom surface to the top surface.

[0017] Optionally, in the heterojunction bipolar transistor, the total thickness ratio of the arsenic-gallium-containing band gap layer and the third gallium arsenide layer is between (1.5:1) and (10:1).

[0018] Optionally, in the heterojunction bipolar transistor, thickness of the first transition layer containing gallium arsenide is between 5 nm and 5000 nm, thickness of each of the band gap layers containing gallium arsenide is between 1 nm and 10 nm, thickness of each of the second transition layers containing gallium arsenide is between 1 nm and 10 nm, thickness of each of the third gallium arsenide layers is between 1 nm and 10 nm, thickness of each of the third transition layers containing gallium arsenide is between 1 nm and 10 nm, and thickness of the second gallium arsenide layer is between 1 nm and 10 nm.

[0019] Optionally, in the heterojunction bipolar transistor, the heterojunction bipolar transistor further comprises a gallium arsenide buffer layer, an indium gallium phosphide transition layer and an indium gallium phosphide cap layer which are sequentially stacked on the emitter layer.

[0020] The present application also provides a manufacturing method of a heterojunction bipolar transistor, the manufacturing method of the heterojunction bipolar transistor comprising:

[0021] providing a gallium arsenide substrate;

[0022] forming a collector layer on the gallium arsenide substrate, the collector layer comprising a first gallium arsenide layer, the first gallium arsenide layer being of a first conductivity type;

[0023] forming a base layer on the collector layer, the base layer comprising:

[0024] a first transition layer containing gallium arsenide, the first transition layer containing gallium arsenide being of the first conductivity type or a second conductivity type to realize a transition of lattice constant;

[0025] a band gap layer containing gallium arsenide, the band gap layer containing gallium arsenide being of the second conductivity type, and the band gap layer containing gallium arsenide having a band gap lower than that of gallium arsenide material; and

[0026] a second gallium arsenide layer, the second gallium arsenide layer being of the second conductivity type; and

[0027] forming an emitter layer on the base layer, the emitter layer comprising an indium gallium phosphide layer, the indium gallium phosphide layer being of the first conductivity type.

[0028] Optionally, in the manufacturing method of the heterojunction bipolar transistor, a process temperature for forming the base layer is between 500 ℃ and 800 ℃, and a process pressure for forming the base layer is between 50 mbar and 200 mbar.

[0029] In the heterojunction bipolar transistor and the manufacturing method thereof provided by the application, the collector region layer, the base region layer and the emitter region layer are sequentially stacked, the base region layer comprises a gallium arsenide energy band layer, the energy band of the gallium arsenide energy band layer is lower than that of the gallium arsenide material, so that the energy band of the heterojunction bipolar transistor can be reduced; further, the base region layer further comprises a first gallium arsenide transition layer, the lattice constant transition is realized through the first gallium arsenide transition layer, so that the lattice mismatch between the collector region layer and the base region layer can be avoided; further, the base region layer further comprises a second gallium arsenide layer, the lattice matching between the base region layer and the emitter region layer can be realized through the second gallium arsenide layer. In the heterojunction bipolar transistor and the manufacturing method thereof provided by the application, the heterojunction bipolar transistor with low energy band and high quality can be obtained. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 is a structure schematic diagram of an existing HBT device.

[0031] Figure 2 is a structure schematic diagram of the heterojunction bipolar transistor of an embodiment of the application.

[0032] Figure 3 is a structure schematic diagram of the heterojunction bipolar transistor of another embodiment of the application.

[0033] In the drawings, the reference signs are explained as follows:

[0034] 100-gallium arsenide substrate; 102-n-type gallium arsenide collector region layer; 104-P-type gallium arsenide base region layer; 106-n-type indium gallium phosphide emitter region layer.

[0035] 200-gallium arsenide substrate; 210-collector region layer; 211-first gallium arsenide layer; 220-base region layer; 221-first gallium arsenide transition layer; 222-gallium arsenide energy band layer; 223-second gallium arsenide layer; 224-second gallium arsenide transition layer; 225-third gallium arsenide layer; 226-third gallium arsenide transition layer; 230-emitter region layer; 231-indium gallium phosphide layer; 240-gallium arsenide buffer layer; 250-indium gallium phosphide transition layer; 260-indium gallium phosphide cap layer. DETAILED DESCRIPTION

[0036] The heterojunction bipolar transistor and the manufacturing method thereof provided by the application are further described in detail below in combination with the drawings and specific embodiments. According to the following description, the advantages and features of the application will be more apparent. It should be noted that the drawings are all very simplified and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application.

[0037] The terminology used by the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, all terms of art used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the application. As used herein, the articles "a", "an", "the" and "at least one" are intended to mean that there is one or more of the items. The use of the term "about" in relation to a reference number can indicate that the value of the reference number can vary by ±10%. The use of the term "substantially" can indicate that the indicated condition is met for substantially all of the relevant time. The use of the term "comprising" (or "comprises") is intended to mean that the item listed after the term is inclusive - meaning that other items not specifically mentioned are not excluded. The use of the term "consisting essentially of" is intended to mean that the item listed after the term is inclusive - meaning that other items not specifically mentioned are not excluded - but only if the other items do not materially change the basic and novel characteristics of the claimed application. Unless otherwise specified, "or" means "and / or" and "singular" means "one or more". Unless otherwise specified, "coupled" encompasses "directly coupled" and "indirectly coupled" via devices that are not intended to be part of the claimed application. The use of any and all examples, or exemplary language (e.g. "such as") provided herein, is intended merely to better illuminate the application and does not pose a limitation on the scope of the application unless otherwise claimed. No language is intended to indicate that the application will necessarily encompass one or more specific examples, or that the application will necessarily exhibit one or more specific characteristics.

[0038] The core idea of the present application is to provide a heterojunction bipolar transistor and a manufacturing method thereof, comprising a collector region layer, a base region layer and an emitter region layer which are stacked in sequence, the base region layer comprises a gallium arsenide containing energy band layer, the energy band of the gallium arsenide containing energy band layer is lower than that of gallium arsenide material, thereby the energy band of the heterojunction bipolar transistor can be reduced; further, the base region layer further comprises a first gallium arsenide containing transition layer, the transition of lattice constant can be realized through the first gallium arsenide containing transition layer, thereby the lattice mismatch between the collector region layer and the base region layer can be avoided; further, the base region layer further comprises a second gallium arsenide layer, the lattice matching between the emitter region layer and the base region layer can be realized through the second gallium arsenide layer. In the heterojunction bipolar transistor and the manufacturing method thereof provided by the present application, the heterojunction bipolar transistor with low energy band and high quality can be obtained.

[0039] Specifically, please refer to Figure 2 which is a structure schematic diagram of the heterojunction bipolar transistor of an embodiment of the present application. As shown in Figure 2 in the present application, the heterojunction bipolar transistor comprises, from bottom to top, a gallium arsenide substrate 200, a collector region layer 210, a base region layer 220 and an emitter region layer 230 which are stacked in sequence, the collector region layer 210 comprises a first gallium arsenide layer 211 which is of a first conductive type, the base region layer 220, and the emitter region layer 230 comprises an indium gallium phosphide layer 231 which is of the first conductive type.

[0040] The base region layer 220 comprises: a first arsenic-gallium-containing transition layer 221, which is of a first conductive type or a second conductive type to realize a transition of a lattice constant; an arsenic-gallium-containing band gap layer 222, which is of the second conductive type and has a band gap lower than that of a gallium arsenide material; and a second gallium arsenide layer 223, which is of the second conductive type.

[0041] In the embodiments of the present application, the first conductive type is N type and the second conductive type is P type; in other embodiments of the present application, the first conductive type can be P type and the second conductive type can be N type.

[0042] The first arsenic-gallium-containing transition layer 221 is located on the first gallium arsenide layer 211 and is in contact with the first gallium arsenide layer 211. Here, the first arsenic-gallium-containing transition layer 221 can be of P type or N type, i.e., the first arsenic-gallium-containing transition layer 221 can be of the same conductive type as the collector region layer 210 or of a different conductive type.

[0043] Please continue to refer to Figure 2 In the embodiments of the present application, the base region layer 220 further comprises: a second arsenic-gallium-containing transition layer 224 located on the arsenic-gallium-containing band gap layer 222, a third gallium arsenide layer 225 located on the second arsenic-gallium-containing transition layer 224, and a third arsenic-gallium-containing transition layer 226 located on the third gallium arsenide layer 225, and the second gallium arsenide layer 223 is located on the third arsenic-gallium-containing transition layer 226. Here, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, and the third arsenic-gallium-containing transition layer 226 are all of the second conductive type. Here, the first arsenic-gallium-containing transition layer 221, the arsenic-gallium-containing band gap layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, the third arsenic-gallium-containing transition layer 226, and the second gallium arsenide layer 222 are in contact with each other in sequence.

[0044] Further, the arsenic-gallium-containing band gap layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, and the third arsenic-gallium-containing transition layer 226 can be periodically grown. For example, the arsenic-gallium-containing band gap layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, and the third arsenic-gallium-containing transition layer 226 can be periodically grown in a manner of 2-2-2-2. Figure 3As shown, the base region layer 220 can include: the first arsenic-gallium-containing transition layer 221, the arsenic-gallium-containing band layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, the third arsenic-gallium-containing transition layer 226, the arsenic-gallium-containing band layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, the third arsenic-gallium-containing transition layer 226, …, the arsenic-gallium-containing band layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, the third arsenic-gallium-containing transition layer 226, and the second gallium arsenide layer 222 are sequentially connected. That is, the arsenic-gallium-containing band layer 222 of the first layer is connected with the first arsenic-gallium-containing transition layer 221, and the arsenic-gallium-containing band layer 222 of the second layer to the last layer is connected with the third arsenic-gallium-containing transition layer 226 of the previous layer.

[0045] Preferably, the growth cycle is between 5 layers and 20 layers, for example, can include 5 layers, 6 layers, 7 layers, or more layers of the arsenic-gallium-containing band layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, and the third arsenic-gallium-containing transition layer 226 are sequentially grown. In the embodiment of the present application, the arsenic-gallium-containing band layer 222, the second arsenic-gallium-containing transition layer 224, the third gallium arsenide layer 225, and the third arsenic-gallium-containing transition layer 226 grown by cycle can relieve the stress of the base region layer 220, thereby obtaining a high-quality and high-reliability heterojunction bipolar transistor; further, the energy band of the arsenic-gallium-containing band layer 222 is lower than that of the gallium arsenide material, which can significantly reduce the energy band of the heterojunction bipolar transistor and improve the performance of the heterojunction bipolar transistor compared with the prior art.

[0046] The materials of the first arsenic-gallium-containing transition layer 221, the second arsenic-gallium-containing transition layer 224, the third arsenic-gallium-containing transition layer 226, and the arsenic-gallium-containing band layer 222 are respectively selected from GaAsSb x , In y GaAsSb x , In y GaAs and Al zGaAs, wherein x, y and z are each between 0 and 1. Specifically, the materials of the first arsenic-gallium-containing transition layer 221, the second arsenic-gallium-containing transition layer 224, the third arsenic-gallium-containing transition layer 226 and the arsenic-gallium-containing band layer 222 can be the same or different. For example, the materials of the first arsenic-gallium-containing transition layer 221, the second arsenic-gallium-containing transition layer 224, the third arsenic-gallium-containing transition layer 226 and the arsenic-gallium-containing band layer 222 can each contain arsenic-gallium-antimony; or for example, the materials of the first arsenic-gallium-containing transition layer 221, the arsenic-gallium-containing band layer 222 and the second arsenic-gallium-containing transition layer 224 can each contain arsenic-gallium-antimony, and the material of the third arsenic-gallium-containing transition layer 226 can contain arsenic-gallium-indium.

[0047] In the embodiments of the present application, the materials of the first arsenic-gallium-containing transition layer 221, the second arsenic-gallium-containing transition layer 224, the third arsenic-gallium-containing transition layer 226 and the arsenic-gallium-containing band layer 222 each contain arsenic-gallium-antimony, and the specific proportions can be the same or different. Here, mainly, the number of atoms of antimony contained in the materials of the first arsenic-gallium-containing transition layer 221, the second arsenic-gallium-containing transition layer 224, the third arsenic-gallium-containing transition layer 226 and the arsenic-gallium-containing band layer 222 can be the same or different. Specifically, the material of the first arsenic-gallium-containing transition layer 221 is GaAsSbx1 x1 , the material of the second arsenic-gallium-containing transition layer 224 is GaAsSbx2 x2 , the material of the third arsenic-gallium-containing transition layer 226 is GaAsSbx3 x3 , and the material of the arsenic-gallium-containing band layer 222 is GaAsSbx4 x4 , wherein the subscripts x1, x2, x3 and x4 can be the same or different.

[0048] Please continue to refer to Figure 2 In the embodiments of the present application, the material of the first arsenic-gallium-containing transition layer 221 is GaAsSbx1 x1 , and from the bottom surface to the top surface, the value of the subscript x1 increases from 0 to 1, that is, from bottom to top, the value of the subscript x1 increases from 0 to 1. For example, the material of the bottom of the first arsenic-gallium-containing transition layer 221 is GaAs, that is, the value of x1 is 0; then, the material of the first arsenic-gallium-containing transition layer 221 can be GaAsSbx1 0.01 , for example; further up, the material of the first arsenic-gallium-containing transition layer 221 can be GaAsSbx1 0.02 , for example; further up, the material of the first arsenic-gallium-containing transition layer 221 can be GaAsSbx1 0.03…to the top of the first arsenic-containing gallium transition layer 221, which is GaAsSb. Here, the subscript x1 can increase linearly, in a broken line, or in a curve from the bottom surface to the top surface.

[0049] The first arsenic-containing gallium transition layer 221 can realize a transition of the lattice constant, gradually transitioning to GaAsSb with a large lattice constant, thereby avoiding lattice mismatch and improving the quality and reliability between the film layers.

[0050] In the embodiments of the present application, the material of the second arsenic-containing gallium transition layer 224 is GaAsSb x2 , and the subscript x2 decreases from 1 to 0 from the bottom surface to the top surface. For example, the material of the bottom of the second arsenic-containing gallium transition layer 224 is GaAsSb, and then the material of the second arsenic-containing gallium transition layer 224 can be GaAsSb 0.09 , and then the material of the second arsenic-containing gallium transition layer 224 can be GaAsSb 0.08 , and then the material of the second arsenic-containing gallium transition layer 224 can be GaAsSb 0.07 …to the top of the second arsenic-containing gallium transition layer 224, which is GaAs, i.e., x2 is 0. Here, the subscript x2 can increase linearly, in a broken line, or in a curve from the bottom surface to the top surface.

[0051] The second arsenic-containing gallium transition layer 224 can improve the crystal quality, thereby improving the quality and reliability of the formed heterojunction bipolar transistor.

[0052] Further, the material of the third arsenic-containing gallium transition layer 226 is GaAsSb x3 , and the subscript x3 increases from 0 to 1 from the bottom surface to the top surface. For example, the material of the bottom of the third arsenic-containing gallium transition layer 226 is GaAs, i.e., x3 is 0; then the material of the third arsenic-containing gallium transition layer 226 can be GaAsSb 0.01 ; then the material of the third arsenic-containing gallium transition layer 226 can be GaAsSb 0.02 ; then the material of the third arsenic-containing gallium transition layer 226 can be GaAsSb 0.03 …to the top of the third arsenic-containing gallium transition layer 226, which is GaAsSb. Here, the subscript x3 can increase linearly, in a broken line, or in a curve from the bottom surface to the top surface. Further, the increasing manner of the subscript x3 can be the same as or different from that of the subscript x1.

[0053] The third arsenic-gallium containing transition layer 226 can release the existing lattice constant mismatch, improve the crystal quality, and thus improve the quality and reliability of the formed heterojunction bipolar transistor.

[0054] The material of the arsenic-gallium containing band layer 222 is GaAsSb x4 , and subscript X4 is 1 from the bottom surface to the top surface, i.e. the material of the arsenic-gallium containing band layer 222 is GaAsSb. The energy band of the arsenic-gallium containing band layer 222 is lower than that of the gallium arsenide material, so as to reduce the energy band of the formed heterojunction bipolar transistor, and further improve the device performance.

[0055] As can be seen from the above, in the embodiments of the present application, the arsenic-gallium containing band layer 222 can reduce the energy band of the heterojunction bipolar transistor; further, the first arsenic-gallium containing transition layer 221 can realize the transition of the lattice constant, so as to avoid the lattice mismatch between the collector region layer 210; further, the second gallium arsenide layer 223 can realize the lattice matching between the emitter region layer 230. In the heterojunction bipolar transistor and the manufacturing method thereof provided in the embodiments of the present application, the heterojunction bipolar transistor with low energy band and high quality can be obtained.

[0056] In the embodiments of the present application, the thickness of the first arsenic-gallium containing transition layer 221 is between 5 nm and 5000 nm, the thickness of each layer of the arsenic-gallium containing band layer 222 is between 1 nm and 10 nm, the thickness of each layer of the second arsenic-gallium containing transition layer 224 is between 1 nm and 10 nm, the thickness of each layer of the third gallium arsenide layer 225 is between 1 nm and 10 nm, the thickness of each layer of the third arsenic-gallium containing transition layer 226 is between 1 nm and 10 nm, and the thickness of the second gallium arsenide layer 223 is between 1 nm and 10 nm.

[0057] Preferably, the arsenic-gallium containing band layer 222, the second arsenic-gallium containing transition layer 224, the third gallium arsenide layer 225 and the third arsenic-gallium containing transition layer 226 are periodically grown, and the growth period is between 5 layers and 20 layers.

[0058] For example, the growth period of the arsenic-gallium containing band layer 222, the second arsenic-gallium containing transition layer 224, the third gallium arsenide layer 225 and the third arsenic-gallium containing transition layer 226 is 5 layers, and correspondingly, the total thickness of the arsenic-gallium containing band layer 222 is between 5 nm and 50 nm, the total thickness of the second arsenic-gallium containing transition layer 224 is between 5 nm and 50 nm, the total thickness of the third gallium arsenide layer 225 is between 5 nm and 50 nm, and the total thickness of the third arsenic-gallium containing transition layer 226 is between 5 nm and 50 nm.

[0059] In this way, the overall stress effect of the device can be reduced, the lattice mismatch can be reduced, and the overall mobility of the device can be improved by periodically growing the thin layers.

[0060] Preferably, the ratio of the total thickness of the gallium arsenide containing energy band layer 222 and the third gallium arsenide layer 225 is between (1.5:1) and (10:1). For example, the ratio of the total thickness of the gallium arsenide containing energy band layer 222 and the third gallium arsenide layer 225 is 1.5:1, 2:1, 3:1, 5:1 or 10:1, etc. In this way, the total thickness of the gallium arsenide containing energy band layer 222 is greater than the total thickness of the third gallium arsenide layer 225, but the thickness ratio is between (1.5:1) and (10:1), so that the energy band of the heterojunction bipolar transistor formed can be well reduced, and the lattice mismatch can be effectively reduced, and the overall mobility of the device can be improved.

[0061] Please continue to refer to Figure 2 Or Figure 3 Further, the heterojunction bipolar transistor further comprises a gallium arsenide buffer layer 240, an indium gallium phosphide transition layer 250 and an indium gallium phosphide cap layer 260 which are sequentially stacked on the emitter region layer 230, so as to achieve good ohmic contact and improve the electrical performance of the device.

[0062] Correspondingly, the embodiment of the present application also provides a manufacturing method of a heterojunction bipolar transistor, and the manufacturing method comprises the following steps:

[0063] Providing a gallium arsenide substrate;

[0064] Forming a collector region layer on the gallium arsenide substrate, wherein the collector region layer comprises a first gallium arsenide layer, and the first gallium arsenide layer is of a first conductivity type;

[0065] Forming a base region layer on the collector region layer, wherein the base region layer comprises:

[0066] A first gallium arsenide containing transition layer, wherein the first gallium arsenide containing transition layer is of the first conductivity type or a second conductivity type, so as to realize the transition of the lattice constant;

[0067] A gallium arsenide containing energy band layer, wherein the gallium arsenide containing energy band layer is of the second conductivity type, and the energy band of the gallium arsenide containing energy band layer is lower than the energy band of the gallium arsenide material; and

[0068] A second gallium arsenide layer, wherein the second gallium arsenide layer is of the second conductivity type; and

[0069] Forming an emitter region layer on the base region layer, wherein the emitter region layer comprises an indium gallium phosphide layer, and the indium gallium phosphide layer is of the first conductivity type.

[0070] Specifically, please refer to Figure 2 OrFigure 3 Firstly, a gallium arsenide substrate 200 is provided, which can be formed by a growth process. Preferably, the gallium arsenide substrate 200 is formed by a growth process with a process temperature of 500-800 °C and a process pressure of 50-200 mbar. Preferably, the thickness of the gallium arsenide substrate 200 is 100-300 nm.

[0071] Next, a collector region layer 210 is formed on the gallium arsenide substrate 200, which comprises a first gallium arsenide layer 211, which is of a first conductivity type. In the embodiment, the first gallium arsenide layer 211 is formed by a growth process with a process temperature of 500-800 °C and a process pressure of 50-200 mbar. Preferably, the thickness of the first gallium arsenide layer 211 is 5-5000 nm, and the first gallium arsenide layer 211 is of N type, wherein the doping ions are, for example, Si, Te, etc.

[0072] In the embodiment, a first gallium arsenide containing transition layer 221 is then formed on the first gallium arsenide layer 211, which is of the first conductivity type or the second conductivity type, to realize the transition of the lattice constant. In the embodiment, the first gallium arsenide containing transition layer 221 is formed by a growth process with a process temperature of 500-800 °C and a process pressure of 50-200 mbar. Preferably, the thickness of the first gallium arsenide containing transition layer 221 is 5-5000 nm, and the first gallium arsenide containing transition layer 221 is of N type or P type, wherein the doping ions are, for example, Si, Te, or Mg, C, etc.

[0073] Next, a gallium arsenide containing band layer 222 is formed on the first gallium arsenide containing transition layer 221, which is of the second conductivity type, and the energy band of the gallium arsenide containing band layer 222 is lower than that of the gallium arsenide material. In the embodiment, the gallium arsenide containing band layer 222 is formed by a growth process with a process temperature of 500-800 °C and a process pressure of 50-200 mbar. Preferably, the thickness of the gallium arsenide containing band layer 222 is 1-10 nm, and the gallium arsenide containing band layer 222 is of P type, wherein the doping ions are, for example, Mg, C, etc.

[0074] In this embodiment, a second gallium arsenide-containing transition layer 224 is then formed on the gallium arsenide-containing bandgap layer 222. This second gallium arsenide-containing transition layer 224 is a second conductive layer. Specifically, the second gallium arsenide-containing transition layer 224 can be formed using a growth process with a process temperature of 500°C to 800°C and a process pressure of 50 mbar to 200 mbar. Preferably, the thickness of the second gallium arsenide-containing transition layer 224 is 1 nm to 10 nm. Here, the second gallium arsenide-containing transition layer 224 is p-type, and the doping ions are, for example, Mg, C, etc.

[0075] Next, a third gallium arsenide layer 225 is formed on the second gallium arsenide-containing transition layer 224, wherein the third gallium arsenide layer 225 is a second conductive layer. Specifically, the third gallium arsenide layer 225 can be formed using a growth process with a process temperature of 500℃ to 800℃ and a process pressure of 50 mbar to 200 mbar. Preferably, the thickness of the third gallium arsenide layer 225 is 1 nm to 10 nm, and here, the third gallium arsenide layer 225 is p-type, wherein the doping ions are, for example, Mg, C, etc.

[0076] like Figure 2 or Figure 3 As shown, next, a third gallium arsenide-containing transition layer 226 is formed on the third gallium arsenide layer 225. This third gallium arsenide-containing transition layer 226 is of the second conductive layer type. Specifically, the third gallium arsenide-containing transition layer 226 can be formed using a growth process with a process temperature of 500°C to 800°C and a process pressure of 50 mbar to 200 mbar. Preferably, the thickness of the third gallium arsenide-containing transition layer 226 is 1 nm to 10 nm. Here, the third gallium arsenide-containing transition layer 226 is p-type, wherein the doping ions are, for example, Mg, C, etc.

[0077] like Figure 2 As shown, a second gallium arsenide layer 223 can then be formed on the third gallium arsenide-containing transition layer 226. The second gallium arsenide layer 223 is a second conductive layer. Specifically, the second gallium arsenide layer 223 can be formed using a growth process with a process temperature of 500°C to 800°C and a process pressure of 50 mbar to 200 mbar. Preferably, the thickness of the second gallium arsenide layer 223 is 1 nm to 10 nm. Here, the second gallium arsenide layer 223 is p-type, and the doping ions are, for example, Mg, C, etc.

[0078] Preferred, such as Figure 3As shown, after forming the third arsenic-gallium containing transition layer 226 of the first layer, then, the arsenic-gallium containing band layer 222 of the second layer is formed, the arsenic-gallium containing band layer 222 is of the second conductive layer type, and the energy band of the arsenic-gallium containing band layer 222 is lower than that of the gallium arsenide material. Specifically, the arsenic-gallium containing band layer 222 is formed by using a growth process with a process temperature of 500-800°C and a process pressure of 50-200 mbar. Preferably, the thickness of the arsenic-gallium containing band layer 222 is 1-10 nm, and the arsenic-gallium containing band layer 222 is P-type, wherein the doping ions are, for example, Mg, C, etc.

[0079] Then, the second arsenic-gallium containing transition layer 224 of the second layer, the third gallium arsenide layer 225 of the second layer, and the third arsenic-gallium containing transition layer 226 of the second layer are sequentially formed. Then, the arsenic-gallium containing band layer 222 of the third layer, the second arsenic-gallium containing transition layer 224 of the third layer, the third gallium arsenide layer 225 of the third layer, and the third arsenic-gallium containing transition layer 226 of the third layer are formed on the third arsenic-gallium containing transition layer 226 of the second layer. In this way, preferably, 5-20 layers of the arsenic-gallium containing band layer 222, the second arsenic-gallium containing transition layer 224, the third gallium arsenide layer 225, and the third arsenic-gallium containing transition layer 226 are periodically formed.

[0080] Please continue to refer to Figure 3 Then, the second gallium arsenide layer 223 is formed on the third arsenic-gallium containing transition layer 226 of the last layer (i.e., the uppermost layer), and the second gallium arsenide layer 223 is of the second conductive layer type. Specifically, the second gallium arsenide layer 223 is formed by using a growth process with a process temperature of 500-800°C and a process pressure of 50-200 mbar. Preferably, the thickness of the second gallium arsenide layer 223 is 1-10 nm, and the second gallium arsenide layer 223 is P-type, wherein the doping ions are, for example, Mg, C, etc.

[0081] Please refer to Figure 2 Or Figure 3 In the embodiments of the present application, then, the indium-gallium phosphide layer 231, the gallium arsenide buffer layer 240, the indium-gallium phosphide transition layer 250, and the indium-gallium phosphide cap layer 260 are sequentially formed on the second gallium arsenide layer 223.

[0082] In summary, in the embodiment of the present application, the energy band layer 222 containing arsenic gallium can reduce the energy band of the heterojunction bipolar transistor; further, the first transition layer 221 containing arsenic gallium can realize the transition of the lattice constant, so that the lattice mismatch between the collector region layer 210 can be avoided; further, the second gallium arsenide layer 223 can realize the lattice matching between the emitter region layer 230. Further, the heterojunction bipolar transistor of the embodiment of the present application has better half width and intensity, and better overall mobility.

[0083] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any modification or change made by a person of ordinary skill in the art based on the above disclosure is within the protection scope of the claims.

Claims

1. A heterojunction bipolar transistor, characterized by, The heterojunction bipolar transistor comprises, from bottom to top, in sequence: a gallium arsenide substrate; a collector region layer comprising a first gallium arsenide layer, the first gallium arsenide layer being of a first conductivity type; a base region layer comprising: a first arsenic-containing gallium transition layer, the first arsenic-containing gallium transition layer being of the first conductivity type or a second conductivity type to realize a transition of lattice constant; an arsenic-containing gallium energy band layer, the arsenic-containing gallium energy band layer being of the second conductivity type, the energy band of the arsenic-containing gallium energy band layer being lower than that of a gallium arsenide material; and a second gallium arsenide layer, the second gallium arsenide layer being of the second conductivity type; and an emitter region layer comprising an indium gallium phosphide layer, the indium gallium phosphide layer being of the first conductivity type; the base region layer further comprises: a second arsenic-containing gallium transition layer, a third gallium arsenide layer, and a third arsenic-containing gallium transition layer between the arsenic-containing gallium energy band layer and the second gallium arsenide layer, the second arsenic-containing gallium transition layer, the third gallium arsenide layer, and the third arsenic-containing gallium transition layer all being of the second conductivity type; the arsenic-containing gallium energy band layer, the second arsenic-containing gallium transition layer, the third gallium arsenide layer, and the third arsenic-containing gallium transition layer are periodically grown, and the growth period is between 5 and 20.

2. The heterojunction bipolar transistor of claim 1, wherein the base region is formed of a material having a bandgap larger than that of the emitter region. The material of the first arsenic-gallium-containing transition layer, the second arsenic-gallium-containing transition layer, the third arsenic-gallium-containing transition layer and the arsenic-gallium-containing band gap layer is respectively selected from GaAsSb x , In y GaAsSb x , In y GaAs and Al z GaAs, wherein the values of x, y and z are all between 0 and 1.

3. The heterojunction bipolar transistor of claim 2, wherein the base region is formed of a material having a bandgap larger than that of the emitter region. The material of the first arsenic-containing gallium transition layer is GaAsSb x1 And from the bottom surface to the top surface, the subscript x1 increases from 0 to 1; the material of the second arsenic-containing gallium transition layer is GaAsSb x2 And from the bottom surface to the top surface, the subscript x2 decreases from 1 to 0; the material of the third arsenic-containing gallium transition layer is GaAsSb x3 And from the bottom surface to the top surface, the subscript x3 increases from 0 to 1; the material of the arsenic-containing gallium band layer is GaAsSb x4 And from the bottom surface to the top surface, the subscript X4 is 1.

4. The heterojunction bipolar transistor of claim 3, wherein the base region is formed of a material having a band gap larger than that of the emitter region. The ratio of the total thickness of the arsenic-containing gallium energy band layer and the third gallium arsenide layer is between (1.5:1) and (10:1).

5. The heterojunction bipolar transistor of claim 3, wherein the base region is formed of a material having a band gap larger than that of the emitter region. The thickness of the first arsenic-containing gallium transition layer is between 5 nm and 5000 nm, the thickness of each layer of the arsenic-containing gallium energy band layer is between 1 nm and 10 nm, the thickness of each layer of the second arsenic-containing gallium transition layer is between 1 nm and 10 nm, the thickness of each layer of the third gallium arsenide layer is between 1 nm and 10 nm, the thickness of each layer of the third arsenic-containing gallium transition layer is between 1 nm and 10 nm, and the thickness of the second gallium arsenide layer is between 1 nm and 10 nm.

6. The heterojunction bipolar transistor according to any one of claims 1 to 5, wherein the base layer is made of a material having a band gap larger than that of the emitter layer. The heterojunction bipolar transistor further comprises, in sequence, a gallium arsenide buffer layer, an indium gallium phosphide transition layer, and an indium gallium phosphide cap layer stacked on the emitter region layer.

7. A method of manufacturing a heterojunction bipolar transistor, characterized by, The manufacturing method of the heterojunction bipolar transistor comprises: providing a gallium arsenide substrate; forming a collector region layer on the gallium arsenide substrate, the collector region layer comprising a first gallium arsenide layer, the first gallium arsenide layer being of a first conductivity type; forming a base region layer on the collector region layer, the base region layer comprising: a first arsenic-containing gallium transition layer, the first arsenic-containing gallium transition layer being of the first conductivity type or a second conductivity type to realize a transition of lattice constant; an arsenic-containing gallium energy band layer, the arsenic-containing gallium energy band layer being of the second conductivity type, the energy band of the arsenic-containing gallium energy band layer being lower than that of a gallium arsenide material; and a second gallium arsenide layer, the second gallium arsenide layer being of the second conductivity type; and forming an emitter region layer on the base region layer, the emitter region layer comprising an indium gallium phosphide layer, the indium gallium phosphide layer being of the first conductivity type; The base region layer further comprises: a second arsenic-gallium-containing transition layer, a third gallium arsenide layer and a third arsenic-gallium-containing transition layer between the arsenic-gallium-containing band gap layer and the second gallium arsenide layer, wherein the second arsenic-gallium-containing transition layer, the third gallium arsenide layer and the third arsenic-gallium-containing transition layer are of the second conductivity type; The arsenic-gallium-containing band gap layer, the second arsenic-gallium-containing transition layer, the third gallium arsenide layer and the third arsenic-gallium-containing transition layer are periodically grown, and the growth period is between 5 and 20.

8. The method of manufacturing a heterojunction bipolar transistor according to claim 7, wherein The process temperature for forming the base region layer is between 500 DEG C and 800 DEG C, and the process pressure for forming the base region layer is between 50 mbar and 200 mbar.

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