Phase multiplexed series stacked dc-dc converter

Abstract

A power converter circuit. In one aspect, the power converter circuit includes a first buck converter coupled in series to a second buck converter at a junction, and a control circuit coupled to each of the first and second buck converters. In another aspect, the control circuit is arranged to sense a voltage at the junction, compare the sensed voltage to a first threshold voltage, and in response to the sensed voltage being at a voltage lower than the first threshold voltage, the control circuit operates the first buck converter and disables the second buck converter. In yet another aspect, the control circuit is arranged to compare the sensed voltage to a second threshold voltage, and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter and disables the first buck converter.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to the following commonly assigned U.S. provisional patent applications: No. 63 / 265,823, filed December 21, 2021, entitled "Phase Multiplexed Series Stacked DC-DC Converter," and No. 63 / 265,611, filed December 17, 2021, entitled "Systems and Methods for Stable Intermediate Node Operation in Series Stacked Phase DC-DC Converters," the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The described embodiments generally relate to power converters, and more specifically, this embodiment relates to a DC-DC power converter circuit with phase-multiplexed series stacking. Background Technology

[0004] Today, consumers have access to a wide variety of electronic devices. Many of these devices feature integrated circuits powered by regulated low-voltage DC power supplies. These low-voltage supplies are typically generated by dedicated power converter circuits that use a higher voltage input from a battery or other power source. In some applications, the dedicated power converter circuit can be one of the largest power dissipation components in an electronic device, and sometimes it consumes more space than the integrated circuit that powers it. As electronic devices become more complex and compact, there is a growing need for more efficient power converter circuits. Summary of the Invention

[0005] In some embodiments, a power converter circuit is disclosed. The power converter circuit includes: a first buck converter having a first switch and a second switch, the first switch having a first gate terminal, a first drain terminal, and a first source terminal, the second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; and a second buck converter having a third switch and a fourth switch, the third switch having a third gate terminal, a third drain terminal, and a third source terminal, the fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is series-coupled to the first buck converter at a junction, such that... A third drain terminal is coupled to the second source terminal; an input terminal is coupled to the first drain terminal; an output terminal is coupled to the first and second switching nodes; and control circuitry is coupled to each of the first and second buck converters, wherein the control circuitry is arranged to: sense a voltage at the junction; compare the sensed voltage with a first threshold voltage, and in response to the sensed voltage being below the first threshold voltage, operate the first buck converter and deactivate the second buck converter; and compare the sensed voltage with a second threshold voltage, and in response to the sensed voltage being above the second threshold voltage, operate the second buck converter and deactivate the first buck converter.

[0006] In some embodiments, the first and second buck converters are arranged to produce an output voltage at the output terminal that is lower than the input voltage at the input terminal.

[0007] In some embodiments, the first and second buck converters are arranged to control power delivery from the input terminal to the output terminal.

[0008] In some embodiments, the control circuit includes a window comparator, which includes a first comparator and a second comparator.

[0009] In some embodiments, the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

[0010] In some embodiments, the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

[0011] In some embodiments, the output terminal is coupled to the first switching node via a first inductor.

[0012] In some embodiments, the output terminal is coupled to the second switching node via a second inductor.

[0013] In some embodiments, the first inductor is coupled to the first switching node via a first capacitor.

[0014] In some embodiments, the second capacitor is coupled to the junction at its first terminal and to ground at its second terminal.

[0015] In some embodiments, a method of operating a power converter circuit is disclosed. The method includes: providing a first buck converter including a first switch and a second switch, the first switch having a first gate terminal, a first drain terminal, and a first source terminal, the second switch having a second gate terminal, a second drain terminal, and a second source terminal, the first source terminal being coupled to the second drain terminal at a first switch node; providing a second buck converter including a third switch and a fourth switch, the third switch having a third gate terminal, a third drain terminal, and a third source terminal, the fourth switch having a fourth gate terminal, a fourth drain terminal, and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is series-coupled to the first buck converter at a junction such that the third drain terminal... The circuit includes: a second source terminal coupled to the second source terminal; an input terminal coupled to the first drain terminal; an output terminal coupled to the first and second switching nodes; and a control circuit coupled to each of the first and second buck converters. The control circuit senses a voltage at the junction; the control circuit compares the sensed voltage with a first threshold voltage; in response to the sensed voltage being below the first threshold voltage, the control circuit operates the first buck converter and disables the second buck converter; the control circuit compares the sensed voltage with a second threshold voltage; and in response to the sensed voltage being above the second threshold voltage, the control circuit operates the second buck converter and disables the first buck converter.

[0016] In some embodiments, the method further includes the first and second buck converters generating an output voltage at the output terminal that is lower than the input voltage at the input terminal.

[0017] In some embodiments, the method further includes controlling the power transfer from the input terminal to the output terminal by the first and second buck converters.

[0018] In some embodiments, a circuit is disclosed. The circuit includes: a first buck converter having a first switching node; a second buck converter having a second switching node and series-coupled to the first buck converter at a junction; an input terminal coupled to the first buck converter; an output terminal coupled to the first and second switching nodes; and control circuitry coupled to each of the first and second buck converters, wherein the control circuitry is arranged to: sense a voltage at the junction; compare the sensed voltage to a first threshold voltage, and in response to the sensed voltage being below the first threshold voltage, operate the first buck converter and deactivate the second buck converter; and compare the sensed voltage to a second threshold voltage, and in response to the sensed voltage being above the second threshold voltage, operate the second buck converter and deactivate the first buck converter. Attached Figure Description

[0019] Figure 1 This illustrates a DC-DC power converter circuit with phase multiplexing series stacking according to an embodiment of the present disclosure; and

[0020] Figure 2 Examples of embodiments of the present disclosure are shown for use in Figure 1 The switching sequence and timing diagram of the DC-DC power converter circuit. Detailed Implementation

[0021] The circuits and related technologies disclosed herein generally relate to power converters. More specifically, the circuits, apparatuses, and related technologies disclosed herein relate to phase-multiplexed series-stacked DC-DC power converters. In some embodiments, the phase-multiplexed series-stacked DC-DC power converter may comprise a top-phase buck converter and a bottom-phase buck converter. Under light load conditions, or when the power converter operates at a relatively high voltage at its input and there is a relatively low nominal output current and a fixed switching frequency, such as in battery-powered IoT applications, the top and bottom phases can be alternately switched on and off, thus operating only one phase at a time. Furthermore, the voltage at the node where the top phase connects to the bottom phase can be sensed and regulated. This can significantly reduce voltage fluctuations on the output voltage of the power converter, as voltage fluctuations at the output terminals can be shifted to internal nodes of the power converter.

[0022] Embodiments of this disclosure allow phase-multiplexed series-stacked DC-DC power converters to operate in burst mode while significantly reducing output voltage ripple, as the output voltage ripple shifts to the internal nodes of the power converter. Furthermore, the disclosed phase-multiplexed series-stacked DC-DC power converters can have an improved electromagnetic interference (EMI) spectrum when operating in burst mode. Additionally, embodiments of this disclosure enable reduced inductor losses at low nominal loads. Various inventive embodiments, including methods, processes, systems, apparatuses, etc., are described herein.

[0023] The following description, with reference to the accompanying drawings, forms part of this invention. The following description is merely illustrative and is not intended to limit the scope, applicability, or configuration of this disclosure. In fact, the following description of the embodiments will provide an enlightening description for those skilled in the art to implement one or more embodiments. It should be understood that various changes can be made to the function and arrangement of elements without departing from the spirit and scope of this disclosure. In the following description, specific details are set forth for purposes of explanation in order to provide a thorough understanding of certain inventive embodiments. However, it will be apparent, however, that various embodiments can be practiced without these specific details. The drawings and descriptions are not intended to be limiting. The terms “example” or “exemplary” are used herein to mean “serving as an example, illustration, or description.” Any embodiment or design described herein as “exemplary” or “example” should not be construed as preferred or advantageous relative to other embodiments or designs.

[0024] Current methods of series-stacking DC-DC power converters can exhibit relatively low efficiency in systems operating at relatively high input voltages (VIN), with relatively low nominal output currents, and fixed switching frequencies, such as those used in battery-powered IoT applications. In current methods, the equivalent series resistance (ESR) of the inductors can increase significantly because the AC ripple current flowing through the high-impedance sheath of the inductors is relatively large compared to the DC current. Furthermore, current methods can exhibit undesirable electromagnetic interference (EMI) spectra when the power converter operates in burst mode.

[0025] Figure 1 A phase-multiplexed series-stacked DC-DC power converter circuit 100 is shown according to an embodiment of the present disclosure. Figure 1As shown, the phase-multiplexed series-stacked DC-DC power converter circuit 100 may include a top phase 109 (buck converter stage) and a bottom phase 111 (buck converter stage). In the illustrated embodiment, the top phase 109 and bottom phase 111 buck converter stages may be arranged in a series-stacked configuration. The top phase 109 may be connected to the bottom phase 111 at a node 107 having a voltage VM. The top phase 109 buck converter stage may include a first switch 102 and a second switch 104 connected in series. The bottom phase 111 buck converter stage may include a third switch 106 and a fourth switch 108 connected in series.

[0026] The phase-multiplexed series-stacked DC-DC power converter circuit 100 may include a flying capacitor 112 coupled to node 103. Node 107 may be connected to capacitor 115. The phase-multiplexed series-stacked DC-DC power converter circuit 100 may have an input terminal 110 with voltage Vin and may be coupled to ground 120. The phase-multiplexed series-stacked DC-DC power converter circuit 100 may provide an output voltage VOUT at output terminal 118. Output terminal 118 may be coupled to load capacitor 131 and load 135. The output voltage VOUT may be lower than the input voltage Vin at input terminal 110. The phase-multiplexed series-stacked DC-DC power converter circuit 100 may include a first inductor 114 connected between the flying capacitor 112 and output terminal 118. The circuit 100 may also include a second inductor 116 connected between node 117 and output terminal 118.

[0027] The phase-multiplexed series-stacked DC-DC power converter circuit 100 may further include a first clock generator 142 that generates a first clock Φ1 146 and a second clock generator 144 that generates a second clock Φ2 148. Logic and control circuitry 158 may be arranged to generate control signals for controlling the top-phase 109 and bottom-phase 111 buck converter stages. In some embodiments, the top-phase 109 and bottom-phase 111 buck converter stages may be alternately turned on and off by the logic and control circuitry 158. In various embodiments, the control circuitry 158 is arranged to operate the top-phase 109 buck converter and disable the bottom-phase 111 buck converter. In one embodiment, the logic and control circuitry 158 may include a window comparator 128 and a set-reset (S / R) latch 141. The window comparator 128 may compare the voltage (VM) at node 107 with a preset threshold and maintain the voltage (VM) at node 107 within a preset window, for example, within 100mV above or below an ideal value for VM. As will be understood by those skilled in the art to which this disclosure pertains, the value of the preset window can be set to any suitable value. In some embodiments, the ideal value for VM is Vin / 2.

[0028] Window comparator 128 may include a first comparator 151 and a second comparator 153. The outputs of the first comparator 151 and the second comparator 153 may be coupled to a set / reset latch (S / R latch) 141, and the S / R latch 141 may be toggled to alternately enable the operation of the top phase 109 or the bottom phase 111. A first input of the first comparator 151 may be connected to node 107. A second input 124 of the first comparator 151 may be connected to a first reference voltage set to a preset threshold, such as an ideal value of VM plus 100mV. A first input of the second comparator 153 may be connected to node 107. A second input 126 of the second comparator 153 may be connected to a second reference voltage set to a preset threshold, such as an ideal value of VM minus 100mV. In this way, node 107 can be kept within a preset window, for example, within ±100mV of the ideal value of VM. When the voltage at node 107 rises above a preset threshold, for example, above 100mV, the bottom phase 111 starts working until the voltage VM at node 107 drops below the preset threshold, for example, below 100mV, at which point the top phase 109 starts working.

[0029] S / R latch 141 can generate a signal HiZ at its output node 130. Signal HiZ can enable / disable the operation of top phase 109. The inversion of signal HiZ can be generated by inverter 159. The inversion of signal HiZ at node 136 can enable / disable the operation of bottom phase 111. A first clock 146 can be applied to the gate of first switch 102 via first OR gate 132, and the inversion of first clock 146 can be applied to the gate of second switch 104 via first AND gate 134. A second clock 148 can be applied to the gate of third switch 106 via second OR gate 138, and the inversion of second clock 148 can be applied to the gate of fourth switch 108 via second AND gate 140. Although a particular control circuit and algorithm have been discussed above, those skilled in the art to which this disclosure pertains will understand that other control circuit architectures and control algorithms can be used in the phase-multiplexed series-stacked DC-DC power converter circuit 100 and are within the scope of this disclosure.

[0030] Now refer to Figure 1 and 2 This illustrates an embodiment of the switching sequence and timing diagram of circuit 100. Figure 2The waveforms of the signal on the gate of the second switch 104 (inverted Φ1Gate), the signal on the gate of the fourth switch 108 (inverted Φ2Gate), the preset threshold window (Vin / 2 ± 100mV) of the (VM) node 107, the signal HiZ at node 130, and the output voltage at output terminal 118 are shown. During the first time period, referred to in Figure 208 as the "top phase switch" period, the signal HiZ is high, so the top phase 109 can operate for several cycles, as shown in Figure 202, where the inverted Φ1Gate is switching, while the bottom phase 111 is off, as shown in Figure 204, where the inverted Φ2Gate is off. During the "top phase switch" period, the voltage at the (VM) node 107 increases until it reaches, for example, 100mV higher than Vin / 2, as shown in Figure 206. Then, the window comparator 128 switches the S / R latch 141. This causes the "top phase switch" period to end and the "bottom phase switch" period to begin.

[0031] During the second time period, referred to as the “bottom phase switching” period in Figure 208, signal HiZ is low, so bottom phase 111 can operate for several cycles, during which the inverting Φ2 Gate is switching, while top phase 109 is off, during which the inverting Φ1 Gate is off. During the “bottom phase switching” period, the voltage at node 107 (VM) decreases until it reaches, for example, 100mV lower than Vin / 2. Then, window comparator 128 switches S / R latch 141. This causes the “bottom phase switching” period to end and a new “top phase switching” period to begin. As will be understood by those skilled in the art to which this disclosure pertains, the acceptable value of voltage fluctuation at node 107 (VM) can be set based on the power converter specification. The voltage fluctuation at node 107 (VM) can be set to the number of switching cycles that can be performed continuously for each phase. Figure 210 shows the voltage (VOUT) at output terminal 118. As can be seen in Figure 210, the VOUT ripple is relatively small compared to the ripple (VM) at node 107. For example, the value of VOUT ripple can be less than a few mV. Compared to current methods where the output voltage ripple can have a frequency equal to the burst mode operating frequency, the ripple at output terminal 118 has a frequency equal to the switching frequency of the DC-DC power converter.

[0032] The rate of change of the voltage VM at node 107 can be set by the size of capacitor 115, flying capacitor 112, and the current through inductor 114. In various embodiments, the capacitance value of capacitor 115 at node 107 can be increased independently of other power converter operating parameters. As will be appreciated by those skilled in the art to which this disclosure pertains, phase multiplexing can be performed using other feedback loops of voltage and / or current at other nodes within the DC-DC power converter circuit 100 based on phase multiplexing series stacking. Furthermore, phase multiplexing can be achieved in a series-stacked DC-DC converter using open-loop operation. Those skilled in the art will understand that alternative methods exist for controlling the switches in circuit 100 to achieve phase multiplexing of the switches, thereby enabling overall loop control, and such methods are within the scope of this disclosure. Those skilled in the art will further understand that alternative methods for controlling the switches in circuit 100 can be utilized to optimize light-load efficiency, or minimize area, and / or minimize electromagnetic interference (EMI), and such methods are within the scope of this disclosure.

[0033] Although this document describes and illustrates a particular configuration of a phase-multiplexed series-stacked DC-DC power converter circuit, embodiments of this disclosure are suitable for use with other configurations of DC-DC power converters.

[0034] In some embodiments, the described switch may be formed of silicon or any other suitable semiconductor material. In various embodiments, the described switch may be a transistor. In some embodiments, the described switch may be a metal-oxide-semiconductor field-effect transistor (MOSFET). In various embodiments, the disclosed MOSFET may be entirely formed within a single die well. In some embodiments, the disclosed phase-multiplexed series-stacked DC-DC power converter circuit (including transistors and control circuitry) may be integrally integrated onto a single die. In various embodiments, the top-phase and bottom-phase stages may be formed on separate single dies. In some embodiments, the top-phase, bottom-phase, and logic and control circuitry, and any combination thereof, may be formed in groups on individual dies; for example, the top-phase and bottom-phase may be formed on a single die, and the logic and control circuitry may be formed on a single die, or the top-phase and bottom-phase may be formed on the same die as the logic and control circuitry. In various embodiments, the top-phase, bottom-phase, and logic and control circuitry may be entirely integrated into an electronic package, such as, but not limited to, a square flat no-lead (QFN) package, a dual flat no-lead (DFN) package, or a ball grid array (BGA) package. In some embodiments, the top and bottom phases may be packaged separately in an electronic package. In various embodiments, controller circuitry and / or control logic circuitry, as well as the disclosed phase-multiplexed cascaded phase DC-DC converters, may be integrated into a single die.

[0035] In the foregoing description, embodiments of this disclosure have been described with reference to numerous specific details, which may vary depending on the implementation. Therefore, the description and drawings are to be considered illustrative rather than restrictive. The unique and exclusive reference to the scope of this disclosure, and what the applicant intends to be the scope of this disclosure, is the literal and equivalent scope of the set of claims published in this application, including any subsequent amendments in the specific form of such claims. Specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments of this disclosure.

[0036] Additionally, spatially relative terms such as “bottom” or “top” may be used to describe the relationship between an element and / or feature and another element and / or feature, as shown in the figures, for example. It will be understood that, in addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device during use and / or operation. For example, if the device in the figures is flipped, an element described as the “bottom” surface may be oriented “above” other elements or features. The device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0037] As used herein, the terms “and,” “or,” and “and / or” may have a variety of meanings, which are expected to depend at least in part on the context in which such terms are used. Generally, when used in relation to a list such as A, B, or C, “or” is intended to mean A, B, and C, used here in an inclusive sense; and A, B, or C, used here in an exclusive sense. Additionally, the term “one or more” as used herein may be used to describe any feature, structure, or property in the singular, or to describe a combination of features, structures, or properties. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. Furthermore, when used in relation to a list such as A, B, or C, the term “at least one of…” may be interpreted as meaning any combination of A, B, and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0038] Throughout this specification, references to “an example,” “an instance,” “some instances,” or “exemplary embodiments” mean that a particular feature, structure, or characteristic described in conjunction with a feature and / or instance may be included in at least one feature and / or instance of the claimed subject matter. Therefore, the appearance of the phrases “in an example,” “an instance,” “in some instances,” or “in some embodiments,” or other similar phrases throughout this specification does not necessarily refer to the same feature, instance, and / or limitation. Furthermore, a particular feature, structure, or characteristic may be combined in one or more instances and / or features.

[0039] In the preceding detailed description, numerous specific details have been set forth to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods and apparatus known to those of ordinary skill have not been described in detail to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter be limited to the specific instances disclosed, but rather that it may also include all aspects falling within the scope of the appended claims and their equivalents.

Claims

1. A power converter circuit, comprising: A first buck converter includes a first switch and a second switch. The first switch has a first gate terminal, a first drain terminal and a first source terminal. The second switch has a second gate terminal, a second drain terminal and a second source terminal. The first source terminal is coupled to the second drain terminal at a first switch node. The second buck converter includes a third switch and a fourth switch. The third switch has a third gate terminal, a third drain terminal, and a third source terminal. The fourth switch has a fourth gate terminal, a fourth drain terminal, and a fourth source terminal. The third source terminal is coupled to the fourth drain terminal at a second switch node. The second buck converter is coupled in series to the first buck converter at a junction, such that the third drain terminal is coupled to the second source terminal. An input terminal, which is coupled to the first drain terminal; An output terminal, which is coupled to the first and second switching nodes; as well as Control circuitry coupled to each of the first and second buck converters, wherein the control circuitry is arranged as follows: Sensing the voltage at the junction; The sensed voltage is compared with a first threshold voltage, and in response to the sensed voltage being below the first threshold voltage, the control circuit operates the first buck converter and disables the second buck converter; as well as The sensed voltage is compared with a second threshold voltage, and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter and disables the first buck converter.

2. The power converter circuit of claim 1, wherein the first and second buck converters are arranged to generate an output voltage at the output terminal that is lower than the input voltage at the input terminal.

3. The power converter circuit of claim 1, wherein the first and second buck converters are arranged to control power transfer from the input terminal to the output terminal.

4. The power converter circuit according to claim 1, wherein the control circuit includes a window comparator, the window comparator comprising a first comparator and a second comparator.

5. The power converter circuit of claim 4, wherein the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

6. The power converter circuit of claim 5, wherein the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

7. The power converter circuit according to claim 5, wherein the output terminal is coupled to the first switching node via a first inductor.

8. The power converter circuit according to claim 5, wherein the output terminal is coupled to the second switching node via a second inductor.

9. The power converter circuit of claim 7, wherein the first inductor is coupled to the first switching node via a first capacitor.

10. The power converter circuit of claim 9, wherein the second capacitor is coupled to the junction at its first terminal and to ground at its second terminal.

11. A method of operating a power converter circuit, the method comprising: A first buck converter is provided, comprising a first switch and a second switch, the first switch having a first gate terminal, a first drain terminal and a first source terminal, and the second switch having a second gate terminal, a second drain terminal and a second source terminal, wherein the first source terminal is coupled to the second drain terminal at a first switch node; A second buck converter is provided, comprising a third switch and a fourth switch, the third switch having a third gate terminal, a third drain terminal and a third source terminal, the fourth switch having a fourth gate terminal, a fourth drain terminal and a fourth source terminal, the third source terminal being coupled to the fourth drain terminal at a second switch node, wherein the second buck converter is coupled in series to the first buck converter at a junction such that the third drain terminal is coupled to the second source terminal; Provides an input terminal coupled to the first drain terminal; Provide output terminals coupled to the first and second switching nodes; as well as A control circuit is provided coupled to each of the first and second buck converters; The voltage at the junction is sensed by the control circuit; The control circuit compares the sensed voltage with the first threshold voltage. In response to the sensed voltage being below the first threshold voltage, the control circuit operates the first buck converter and disables the second buck converter; The control circuit compares the sensed voltage with the second threshold voltage. as well as In response to the sensed voltage being above the second threshold voltage, the control circuit operates the second buck converter and disables the first buck converter.

12. The method of claim 11, further comprising generating an output voltage at the output terminal that is lower than the input voltage at the input terminal by the first and second buck converters.

13. The method of claim 11, further comprising controlling the power transfer from the input terminal to the output terminal by the first and second buck converters.

14. The method of claim 11, wherein the control circuitry includes a window comparator, the window comparator comprising a first comparator and a second comparator.

15. The method of claim 14, wherein the first comparator is arranged to receive the voltage at the junction and to receive the first threshold voltage.

16. The method of claim 15, wherein the second comparator is arranged to receive the voltage at the junction and to receive the second threshold voltage.

17. A circuit comprising: A first buck converter having a first switching node; A second buck converter has a second switching node and is coupled in series to the first buck converter at a junction; The input terminal is coupled to the first buck converter; An output terminal, which is coupled to the first and second switching nodes; as well as Control circuitry coupled to each of the first and second buck converters, wherein the control circuitry is arranged as follows: Sensing the voltage at the junction; The sensed voltage is compared with a first threshold voltage, and in response to the sensed voltage being below the first threshold voltage, the control circuit operates the first buck converter and disables the second buck converter; as well as The sensed voltage is compared with a second threshold voltage, and in response to the sensed voltage being at a voltage higher than the second threshold voltage, the control circuit operates the second buck converter and disables the first buck converter.

18. The circuit of claim 17, wherein the first and second buck converters are arranged to generate an output voltage at the output terminal that is lower than the input voltage at the input terminal.

19. The circuit of claim 17, wherein the first and second buck converters are arranged to control power delivery from the input terminal to the output terminal.

20. The circuit of claim 17, wherein the control circuit includes a window comparator, the window comparator comprising a first comparator and a second comparator.

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