Semiconductor Process Defect Identification Method Based on Adaptive Linknet Structure

Abstract

The present invention relates to a semiconductor process defect recognition method based on an adaptive Linknet structure. Based on the Linknet structure, the input semiconductor chip image is successively subjected to multiple feature extractions, maximum pooling sampling processing, and interpolation upsampling processing. Then, the feature map after the interpolation upsampling processing is spliced with the corresponding extracted semiconductor chip feature map to obtain a first spliced feature map. After that, the first spliced feature map is subjected to interpolation upsampling processing and spliced with other feature maps. Finally, a 1×1 convolution is used to perform convolution processing on the finally spliced feature map to reduce the number of channels of the third spliced feature map to 1, and the feature map after the convolution processing is used as the recognized output semiconductor process defect segmentation map, avoiding manual observation and analysis of semiconductor process defect data, realizing automatic recognition and processing of semiconductor process defect data, and thus being more suitable for the huge task volume recognition requirements during large-scale mass production.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor process defect identification, and particularly to a semiconductor process defect identification method based on an adaptive Linknet structure. Background Art

[0002] In the manufacturing process of semiconductor chips, several basic semiconductor processes such as lithography, grinding, etching, cleaning, and deposition usually need to be repeated hundreds or even thousands of times. During the repetition of the above basic semiconductor processes, defects in any link may greatly reduce the final yield of semiconductor chips.

[0003] During the manufacturing process of semiconductor chips, defects such as particles, scratches, and contamination may occur in each layer or each process step. In the manufacturing industry, yield / defect management engineers are usually responsible for counting and analyzing pictures of semiconductor chips with defects, obtaining relevant defect data, and feeding back the defect data to the manufacturing department. In the work of defect management and statistics, engineers often face a large amount of picture data. Such picture data for semiconductor process defects is difficult to automatically analyze like digital data. Engineers must continuously count key information such as the number of defects, the area of defects, and the types of defects to complete manual semiconductor process defect identification, resulting in the inability of existing semiconductor process defect identification to perform fast and efficient identification of large-scale semiconductor process defects. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a semiconductor process defect identification method based on an adaptive Linknet structure for the above-mentioned existing technology.

[0005] The technical solution adopted by the present invention to solve the above technical problem is: a semiconductor process defect identification method based on an adaptive Linknet structure, which is characterized by at least including a first-way semiconductor process defect identification process, and this first-way semiconductor process defect identification process includes the following steps 1 to 12:

[0006] Step 1, take the input semiconductor chip picture as the first-layer input feature map of the Linknet structure, and perform feature extraction processing on this first-layer input feature map for a first preset number of times to obtain a semiconductor chip feature map after primary extraction;

[0007] Step 2, perform maximum pooling sampling processing on the semiconductor chip feature map after primary extraction to obtain the second-layer input feature map of the Linknet structure;

[0008] Step 3, perform feature extraction processing on the obtained second-layer input feature map for a second preset number of times to obtain a semiconductor chip feature map after secondary extraction;

[0009] Step 4: Perform max-pooling sampling on the semiconductor chip feature map after secondary extraction to obtain the input feature map of the third layer of the Linknet structure;

[0010] Step 5: Perform feature extraction on the obtained input feature map of the third layer for a third preset number of times to obtain the semiconductor chip feature map after tertiary extraction;

[0011] Step 6: Perform max-pooling sampling on the semiconductor chip feature map after tertiary extraction to obtain the input feature map of the fourth layer of the Linknet structure;

[0012] Step 7: Perform feature extraction on the obtained input feature map of the fourth layer for a fourth preset number of times to obtain the semiconductor chip feature map after quaternary extraction;

[0013] Step 8: Perform max-pooling sampling on the semiconductor chip feature map after quaternary extraction, and perform interpolation upsampling on the feature map after this max-pooling sampling;

[0014] Step 9: Perform splicing on the feature map after interpolation upsampling in Step 8 and the semiconductor chip feature map after tertiary extraction to obtain the first spliced feature map;

[0015] Step 10: Perform interpolation upsampling on the first spliced feature map, and perform splicing on the feature map after this interpolation upsampling and the semiconductor chip feature map after secondary extraction to obtain the second spliced feature map;

[0016] Step 11: Perform interpolation upsampling on the second spliced feature map, and perform splicing on the feature map after this interpolation upsampling and the semiconductor chip feature map after primary extraction to obtain the third spliced feature map;

[0017] Step 12: Perform convolution on the third spliced feature map using a 1×1 convolution to reduce the number of channels of this third spliced feature map to 1, and use the feature map after this convolution as the semiconductor process defect segmentation map output after recognition.

[0018] To improve the accuracy of semiconductor process defect recognition, preferably, the semiconductor process defect recognition method based on the adaptive Linknet structure in the present invention further includes:

[0019] Respectively execute a second semiconductor process defect recognition process, a third semiconductor process defect recognition process, and a fourth semiconductor process defect recognition process that are the same as the first semiconductor process defect recognition process, and correspondingly obtain the semiconductor process defect segmentation maps corresponding to each semiconductor process defect recognition process;

[0020] Assign corresponding contribution weights to the recognition results of each semiconductor process defect recognition process;

[0021] Stitch the semiconductor process defect segmentation diagrams according to their respective corresponding contribution weights to form a stitched feature map;

[0022] Use a 1×1 convolution to perform convolution processing on the stitched feature map obtained by stitching to reduce the number of channels of the stitched feature map to 1, and use the feature map after this convolution processing as the semiconductor process defect segmentation map finally output after recognition.

[0023] Furthermore, in the semiconductor process defect recognition method based on the adaptive Linknet structure, the Linknet structure in the first-way semiconductor process defect recognition process is the LinkNet18 structure, the first preset number of times is 2, the second preset number of times is 2, the third preset number of times is 2, and the fourth preset number of times is 2;

[0024] The Linknet structure in the second-way semiconductor process defect recognition process is the LinkNet34 structure, the first preset number of times is 3, the second preset number of times is 4, the third preset number of times is 6, and the fourth preset number of times is 3;

[0025] The Linknet structure in the third-way semiconductor process defect recognition process is the LinkNet50 structure, the first preset number of times is 3, the second preset number of times is 4, the third preset number of times is 6, and the fourth preset number of times is 3;

[0026] The Linknet structure in the fourth-way semiconductor process defect recognition process is the LinkNet101 structure, the first preset number of times is 3, the second preset number of times is 4, the third preset number of times is 23, and the fourth preset number of times is 3.

[0027] Further improvement, in the semiconductor process defect recognition method based on the adaptive Linknet structure, each feature extraction process adopted in the first-way semiconductor process defect recognition process and the second-way semiconductor process defect recognition process uses a preset basic feature extraction method; wherein, the preset basic feature extraction method includes the following steps a1 to a5:

[0028] Step a1, use a first group of 3×3 convolutions to perform convolution processing on the input picture to be extracted to obtain a picture after the first-level convolution processing;

[0029] Step a2, perform picture pixel normalization processing on the picture after the first-level convolution processing to obtain a picture after the first-level normalization processing, and use an activation function to perform activation processing on the picture after the first-level normalization processing to obtain a picture after the first-level activation processing;

[0030] Step a3: Perform convolution processing on the picture after the first-level activation processing using a second group of 3×3 convolutions to obtain a picture after the second-level convolution processing;

[0031] Step a4: Perform picture pixel normalization processing on the picture after the second-level convolution processing to obtain a picture after the second-level normalization processing, and perform activation processing on the picture after the second-level normalization processing using an activation function to obtain a picture after the second-level activation processing;

[0032] Step a5: Perform addition processing on the obtained picture after the second-level activation processing and the input picture to be extracted to obtain a picture after the addition processing; wherein, the picture after the addition processing is the output feature map of the basic feature extraction method.

[0033] Preferably, in the semiconductor process defect recognition method based on the adaptive Linknet structure, the activation function adopted by the basic feature extraction method is the y = max(0, x) function.

[0034] Further improvement: In the semiconductor process defect recognition method based on the adaptive Linknet structure, each feature extraction process adopted in the third path semiconductor process defect recognition process and the fourth path semiconductor process defect recognition process uses a preset bottleneck feature extraction method; wherein, the preset bottleneck feature extraction method includes the following steps b1 to b7:

[0035] Step b1: Perform convolution processing on the input picture to be extracted using a first group of 1×1 convolutions to obtain a picture after the first-level convolution processing;

[0036] Step b2: Perform picture pixel normalization processing on the picture after the first-level convolution processing to obtain a picture after the first-level normalization processing, and perform activation processing on the picture after the first-level normalization processing using an activation function to obtain a picture after the first-level activation processing;

[0037] Step b3: Perform convolution processing on the picture after the first-level activation processing using 3×3 convolutions to obtain a picture after the second-level convolution processing;

[0038] Step b4: Perform picture pixel normalization processing on the picture after the second-level convolution processing to obtain a picture after the second-level normalization processing, and perform activation processing on the picture after the second-level normalization processing using an activation function to obtain a picture after the second-level activation processing;

[0039] Step b5: Perform convolution processing on the picture after the second-level activation processing using a second group of 1×1 convolutions to obtain a picture after the third-level convolution processing;

[0040] Step b6: Perform image pixel normalization on the image after the three-level convolution process to obtain the image after the three-level normalization process, and use an activation function to perform activation processing on the image after the three-level normalization process to obtain the image after the three-level activation processing;

[0041] Step b7: Perform an addition process on the obtained image after the three-level activation processing and the input image to be extracted to obtain the image after the addition process; wherein, the image after the addition process is the output feature map of the bottleneck feature extraction method.

[0042] Furthermore, in the semiconductor process defect recognition method based on the adaptive Linknet structure, the activation function adopted by the bottleneck feature extraction method is the y = max(0, x) function.

[0043] Compared with the prior art, the advantages of the present invention are as follows:

[0044] First of all, in the conductor process defect recognition method of the present invention, based on the Linknet structure, the input semiconductor chip image is successively subjected to multiple feature extractions, maximum pooling sampling processes, and interpolation upsampling processes, and then the feature map after the interpolation upsampling process is spliced with the corresponding extracted semiconductor chip feature map to obtain the first spliced feature map. Then, after performing interpolation upsampling processing on the first spliced feature map and splicing it with other feature maps, finally, 1×1 convolution is used to perform convolution processing on the finally spliced feature map to reduce the number of channels of the third spliced feature map to 1, and the feature map after the convolution processing is used as the semiconductor process defect segmentation map output after recognition, avoiding manual observation and analysis of semiconductor process defect data, and realizing automatic recognition processing of semiconductor process defect data, so as to better meet the recognition requirements of the huge task volume during large-scale mass production.

[0045] Secondly, by further enabling the four-way semiconductor process defect recognition process to be executed in parallel, that is, corresponding to four basic LinkNet structures, the shallow model and the deep model are coordinated to segment the defect images, and an adaptive module is constructed to realize the coordinated work of the four structures. This method can ensure rapid and accurate recognition and segmentation of semiconductor chip process defects. Description of the Drawings

[0046] Figure 1 It is a schematic flowchart of the semiconductor process defect recognition method based on the adaptive Linknet structure in the embodiment of the present invention. Detailed Embodiment

[0047] The present invention will be further described in detail below in conjunction with the embodiments of the drawings.

[0048] This embodiment provides a semiconductor process defect recognition method based on an adaptive Linknet structure. Refer to Figure 1 As shown in the figure, the semiconductor process defect recognition method based on the adaptive Linknet structure at least includes the first path of semiconductor process defect recognition process, and this first path of semiconductor process defect recognition process includes the following steps 1 to 12:

[0049] Step 1: Take the input semiconductor chip image as the first-layer input feature map of the Linknet structure, and perform the first preset number of feature extraction processes on this first-layer input feature map to obtain the semiconductor chip feature map after the first-level extraction; where, in this embodiment, the input semiconductor chip image here is marked as P_00, and the semiconductor chip feature map after the first-level extraction is marked as P_01;

[0050] Step 2: Perform a maximum pooling sampling process on the semiconductor chip feature map after the first-level extraction to obtain the second-layer input feature map of the Linknet structure; where, the maximum pooling sampling process is an existing and mature maximum pooling sampling method; after processing, the obtained second-layer input feature map of the Linknet structure is marked as P_10;

[0051] Step 3: Perform the second preset number of feature extraction processes on the obtained second-layer input feature map to obtain the semiconductor chip feature map after the second-level extraction; where, the semiconductor chip feature map after the second-level extraction is marked as P_11;

[0052] Step 4: Perform a maximum pooling sampling process on the semiconductor chip feature map after the second-level extraction to obtain the third-layer input feature map of the Linknet structure; where, the third-layer input feature map of the Linknet structure is marked as P_20;

[0053] Step 5: Perform the third preset number of feature extraction processes on the obtained third-layer input feature map to obtain the semiconductor chip feature map after the third-level extraction; where, the semiconductor chip feature map after the third-level extraction of the Linknet structure is marked as P_21;

[0054] Step 6: Perform a maximum pooling sampling process on the semiconductor chip feature map after the third-level extraction to obtain the fourth-layer input feature map of the Linknet structure; where, the fourth-layer input feature map of the Linknet structure is marked as P_30;

[0055] Step 7: Perform the fourth preset number of feature extraction processes on the obtained fourth-layer input feature map to obtain the semiconductor chip feature map after the fourth-level extraction; where, the semiconductor chip feature map after the fourth-level extraction is marked as P_31;

[0056] Step 8, perform max-pooling sampling on the semiconductor chip feature map after four-level extraction, and perform interpolation upsampling on the feature map after the max-pooling sampling;

[0057] Step 9, splice the feature map after the interpolation upsampling in Step 8 with the semiconductor chip feature map after three-level extraction to obtain a first spliced feature map; among them, in this embodiment, an existing mature splicing method is used for splicing;

[0058] Step 10, perform interpolation upsampling on the first spliced feature map, and splice the feature map after the interpolation upsampling with the semiconductor chip feature map after two-level extraction to obtain a second spliced feature map; among them, the interpolation upsampling here uses an existing mature interpolation upsampling method;

[0059] Step 11, perform interpolation upsampling on the second spliced feature map, and splice the feature map after the interpolation upsampling with the semiconductor chip feature map after one-level extraction to obtain a third spliced feature map;

[0060] Step 12, perform convolution on the third spliced feature map using 1×1 convolution to reduce the number of channels of the third spliced feature map to 1, and use the feature map after the convolution as the semiconductor process defect segmentation map output after recognition.

[0061] In order to improve the recognition accuracy of semiconductor process defects, this embodiment also takes the following measures, that is, the semiconductor process defect recognition method based on the adaptive Linknet structure in this embodiment further includes:

[0062] Step S1, respectively execute the second semiconductor process defect recognition process, the third semiconductor process defect recognition process, and the fourth semiconductor process defect recognition process that are the same as the first semiconductor process defect recognition process, and correspondingly obtain the semiconductor process defect segmentation maps corresponding to each semiconductor process defect recognition process; among them:

[0063] For the first semiconductor process defect recognition process, the Linknet structure in the first semiconductor process defect recognition process is the LinkNet18 structure, the first preset number of times is 2, the second preset number of times is 2, the third preset number of times is 2, and the fourth preset number of times is 2;

[0064] For the second semiconductor process defect recognition process, the Linknet structure in the second semiconductor process defect recognition process is the LinkNet34 structure, the first preset number of times is 3, the second preset number of times is 4, the third preset number of times is 6, and the fourth preset number of times is 3;

[0065] For the third semiconductor process defect recognition process, the Linknet structure in this third semiconductor process defect recognition process is the LinkNet50 structure, the first preset number of times is 3, the second preset number of times is 4, the third preset number of times is 6, and the fourth preset number of times is 3;

[0066] For the fourth semiconductor process defect recognition process, the Linknet structure in this fourth semiconductor process defect recognition process is the LinkNet101 structure, the first preset number of times is 3, the second preset number of times is 4, the third preset number of times is 23, and the fourth preset number of times is 3;

[0067] Step S2, assign corresponding contribution weights to the recognition results of each semiconductor process defect recognition process;

[0068] Step S3, splice the semiconductor process defect segmentation maps according to their respective corresponding contribution weights to splice them into a spliced feature map;

[0069] Step S4, perform convolution processing on the spliced feature map obtained by splicing using 1×1 convolution to reduce the number of channels of the spliced feature map to 1, and use the feature map after this convolution processing as the semiconductor process defect segmentation map finally output after recognition.

[0070] Specifically in this embodiment, each feature extraction process adopted in the above first semiconductor process defect recognition process and the second semiconductor process defect recognition process uses a preset basic feature extraction method; wherein, the preset basic feature extraction method includes the following steps a1 to a5:

[0071] Step a1, perform convolution processing on the input picture to be extracted using the first group of 3×3 convolution to obtain a picture after the first-level convolution processing;

[0072] Step a2, perform picture pixel normalization processing on the picture after the first-level convolution processing to obtain a picture after the first-level normalization processing, and perform activation processing on the picture after the first-level normalization processing using an activation function to obtain a picture after the first-level activation processing;

[0073] Step a3, perform convolution processing on the picture after the first-level activation processing using the second group of 3×3 convolution to obtain a picture after the second-level convolution processing;

[0074] Step a4, perform picture pixel normalization processing on the picture after the second-level convolution processing to obtain a picture after the second-level normalization processing, and perform activation processing on the picture after the second-level normalization processing using an activation function to obtain a picture after the second-level activation processing;

[0075] Step a5: Add the obtained second-level activation-processed image to the input image to be extracted to obtain an added image; wherein, the added image is the output feature map of the basic feature extraction method. In the basic feature extraction method of this embodiment, the activation functions used are all y = max(0, x) functions.

[0076] In addition, specifically in this embodiment, each feature extraction process in the above-mentioned third-path semiconductor process defect recognition process and the fourth-path semiconductor process defect recognition process adopts a preset bottleneck feature extraction method; wherein, the preset bottleneck feature extraction method includes the following steps b1 to b7:

[0077] Step b1: Perform convolution processing on the input image to be extracted using the first group of 1×1 convolutions to obtain a first-level convolution-processed image;

[0078] Step b2: Perform image pixel normalization processing on the first-level convolution-processed image to obtain a first-level normalized image, and perform activation processing on the first-level normalized image using an activation function to obtain a first-level activation-processed image;

[0079] Step b3: Perform convolution processing on the first-level activation-processed image using 3×3 convolutions to obtain a second-level convolution-processed image;

[0080] Step b4: Perform image pixel normalization processing on the second-level convolution-processed image to obtain a second-level normalized image, and perform activation processing on the second-level normalized image using an activation function to obtain a second-level activation-processed image;

[0081] Step b5: Perform convolution processing on the second-level activation-processed image using the second group of 1×1 convolutions to obtain a third-level convolution-processed image;

[0082] Step b6: Perform image pixel normalization processing on the third-level convolution-processed image to obtain a third-level normalized image, and perform activation processing on the third-level normalized image using an activation function to obtain a third-level activation-processed image;

[0083] Step b7: Add the obtained third-level activation-processed image to the input image to be extracted to obtain an added image; wherein, the added image is the output feature map of the bottleneck feature extraction method. Among them, in the bottleneck feature extraction method of this embodiment, the activation functions used for activation processing are all y = max(0, x) functions.

[0084] Although the preferred embodiments of the present invention have been described in detail above, it should be clearly understood that various changes and modifications can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor process defect identification method based on an adaptive Linknet structure, characterized in that At least including the first path of semiconductor process defect recognition process, and this first path of semiconductor process defect recognition process includes the following steps 1 to 12: Step 1: Take the input semiconductor chip image as the first-layer input feature map of the Linknet structure, and perform the first preset number of feature extraction processes on this first-layer input feature map to obtain the semiconductor chip feature map after the first-level extraction; Step 2: Perform maximum pooling sampling on the semiconductor chip feature map after the first-level extraction to obtain the second-layer input feature map of the Linknet structure; Step 3: Perform the second preset number of feature extraction processes on the obtained second-layer input feature map to obtain the semiconductor chip feature map after the second-level extraction; Step 4: Perform maximum pooling sampling on the semiconductor chip feature map after the second-level extraction to obtain the third-layer input feature map of the Linknet structure; Step 5: Perform the third preset number of feature extraction processes on the obtained third-layer input feature map to obtain the semiconductor chip feature map after the third-level extraction; Step 6: Perform maximum pooling sampling on the semiconductor chip feature map after the third-level extraction to obtain the fourth-layer input feature map of the Linknet structure; Step 7: Perform the fourth preset number of feature extraction processes on the obtained fourth-layer input feature map to obtain the semiconductor chip feature map after the fourth-level extraction; Step 8: Perform maximum pooling sampling on the semiconductor chip feature map after the fourth-level extraction, and perform interpolation upsampling on the feature map after this maximum pooling sampling; Step 9: Perform splicing on the feature map after the interpolation upsampling in Step 8 and the semiconductor chip feature map after the third-level extraction to obtain the first spliced feature map; Step 10: Perform interpolation upsampling on the first spliced feature map, and perform splicing on the feature map after this interpolation upsampling and the semiconductor chip feature map after the second-level extraction to obtain the second spliced feature map; Step 11: Perform interpolation upsampling on the second spliced feature map, and perform splicing on the feature map after this interpolation upsampling and the semiconductor chip feature map after the first-level extraction to obtain the third spliced feature map; Step 12: Use a 1×1 convolution to perform convolution on the third spliced feature map to reduce the number of channels of this third spliced feature map to 1, and use the feature map after this convolution as the semiconductor process defect segmentation map output after recognition; Among them, this semiconductor process defect recognition method based on the adaptive Linknet structure further includes: Respectively execute the second path of semiconductor process defect recognition process, the third path of semiconductor process defect recognition process, and the fourth path of semiconductor process defect recognition process that are the same as the first path of semiconductor process defect recognition process, and correspondingly obtain the semiconductor process defect segmentation maps corresponding to each semiconductor process defect recognition process; Assign corresponding contribution weights to the recognition results of each path of semiconductor process defect recognition process; Perform splicing on each semiconductor process defect segmentation map according to its corresponding contribution weight to splice them into a spliced feature map; Perform convolution processing on the spliced feature map obtained by splicing using a 1×1 convolution to reduce the number of channels of the spliced feature map to 1, and use the feature map after the convolution processing as the semiconductor process defect segmentation map finally output after recognition; Wherein: The Linknet structure in the first-way semiconductor process defect recognition process is the LinkNet18 structure, the first preset number is 2, the second preset number is 2, the third preset number is 2, and the fourth preset number is 2; The Linknet structure in the second-way semiconductor process defect recognition process is the LinkNet34 structure, the first preset number is 3, the second preset number is 4, the third preset number is 6, and the fourth preset number is 3; The Linknet structure in the third-way semiconductor process defect recognition process is the LinkNet50 structure, the first preset number is 3, the second preset number is 4, the third preset number is 6, and the fourth preset number is 3; The Linknet structure in the fourth-way semiconductor process defect recognition process is the LinkNet101 structure, the first preset number is 3, the second preset number is 4, the third preset number is 23, and the fourth preset number is 3.

2. The semiconductor process defect identification method based on the adaptive Linknet structure according to claim 1, wherein All feature extraction processes in the first-way semiconductor process defect recognition process and the second-way semiconductor process defect recognition process adopt a preset basic feature extraction method; wherein, the preset basic feature extraction method includes the following steps a1~a5: Step a1, perform convolution processing on the input picture to be extracted using a first group of 3×3 convolutions to obtain a picture after the first-level convolution processing; Step a2, perform picture pixel normalization processing on the picture after the first-level convolution processing to obtain a picture after the first-level normalization processing, and perform activation processing on the picture after the first-level normalization processing using an activation function to obtain a picture after the first-level activation processing; Step a3, perform convolution processing on the picture after the first-level activation processing using a second group of 3×3 convolutions to obtain a picture after the second-level convolution processing; Step a4, perform picture pixel normalization processing on the picture after the second-level convolution processing to obtain a picture after the second-level normalization processing, and perform activation processing on the picture after the second-level normalization processing using an activation function to obtain a picture after the second-level activation processing; Step a5, perform addition processing on the obtained picture after the second-level activation processing and the input picture to be extracted to obtain a picture after the addition processing; wherein, the picture after the addition processing is the output feature map of the basic feature extraction method.

3. The semiconductor process defect identification method based on the adaptive Linknet structure according to claim 2, characterized in that The activation function adopted by the basic feature extraction method is the y=max(0,x) function.

4. The semiconductor process defect identification method based on the adaptive Linknet structure according to claim 2 or 3, characterized in that All feature extraction processes in the third-way semiconductor process defect recognition process and the fourth-way semiconductor process defect recognition process adopt a preset bottleneck feature extraction method; wherein, the preset bottleneck feature extraction method includes the following steps b1~b7: Step b1, perform convolution processing on the input picture to be extracted using a first group of 1×1 convolutions to obtain a picture after the first-level convolution processing; Step b2: Perform image pixel normalization on the image after the first-level convolution to obtain the image after the first-level normalization, and then perform activation processing on the image after the first-level normalization using an activation function to obtain the image after the first-level activation processing; Step b3: Perform convolution processing on the image after the first-level activation processing using a 3×3 convolution to obtain the image after the second-level convolution processing; Step b4: Perform image pixel normalization on the image after the second-level convolution processing to obtain the image after the second-level normalization, and then perform activation processing on the image after the second-level normalization using an activation function to obtain the image after the second-level activation processing; Step b5: Perform convolution processing on the image after the second-level activation processing using the second group of 1×1 convolutions to obtain the image after the third-level convolution processing; Step b6: Perform image pixel normalization on the image after the third-level convolution processing to obtain the image after the third-level normalization, and then perform activation processing on the image after the third-level normalization using an activation function to obtain the image after the third-level activation processing; Step b7: Add the obtained image after the third-level activation processing to the input image to be extracted to obtain the image after the addition processing; wherein, the image after the addition processing is the output feature map of the bottleneck feature extraction method.

5. The semiconductor process defect recognition method based on the adaptive Linknet structure according to claim 4, wherein, The activation function used in the bottleneck feature extraction method is the y = max(0, x) function.

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