Row driving circuit, display panel, and driving method

Abstract

The present application discloses a row driving circuit, a display panel, and a driving method. When the output terminal of the (n - 2)-th stage gate driving signal in the row driving circuit outputs a first level signal, the first pull-down module pulls down the voltage of the second node; when the output terminal of the (n - 1)-th stage gate driving signal outputs a first level signal, the charging module is started to pre-charge the first node to control the driving module to start, and a (n)-th stage gate driving signal is generated and output according to the clock signal corresponding to the (n)-th stage gate driving signal; when the output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal, the first power supply module outputs the first level signal, and the first pull-down module and the second pull-down module pull down the voltage of the first node. The present application sets the first control module, the first pull-down circuit, and the second pull-down circuit to control the voltages of the first node and the second node, improve the charging ability of the charging module for the first node, reduce leakage, and avoid the generation of horizontal stripes caused by leakage.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a row driving circuit, a display panel, and a driving method. Background Art

[0002] The current GDL circuit (Gate Driver Less for array substrate row driving) is applied to ultra-high definition large-size products. However, due to the changes in customer consumption demands, the progress of factory technical requirements, and process capabilities, it is a trend to improve the screen resolution, display quality, and increase the screen-to-body ratio.

[0003] The currently used GDL circuits usually have post-stage pull-down. However, after the period of the clock signal is determined, the post-stage gate driving signal is also limited, resulting in a limited pull-down time. It is troublesome to design and control the corresponding transistors to conduct and turn off in the timing control circuit, and there are too many restrictions. The post-stage signal is prone to fluctuations, causing problems in the conduction and turn-off of the transistors. The control terminals of the transistors that turn on the gate driving signal often have leakage, resulting in a decrease in display quality. Summary of the Invention

[0004] The objective of the present application is to provide a row driving circuit, a display panel, and a driving method, aiming to improve the charging ability of the control terminals of the transistors that turn on the gate driving signal, reduce leakage, and improve the horizontal stripe phenomenon caused by leakage.

[0005] The present application discloses a row driving circuit. The row driving circuit includes a plurality of cascaded row driving units. Each of the row driving units corresponding to each gate line after the (n - 1)-th gate line includes a charging module, a driving module, a first control module, a first pull-down module, and a second pull-down module. The control end of the charging module is connected to the output end of the (n - 1)-th stage gate driving signal, the input end is connected to the first level signal output end, and the output end is connected to the first node. The control end of the driving module is connected to the first node, the input end is connected to the clock signal corresponding to the n-th stage gate driving signal, and the output end outputs the n-th stage gate driving signal. The control end of the first control module is connected to the first node, the input end is connected to the output end of the first power supply module, and the output end is connected to the second level signal output end through the second node. The first control end of the first pull-down module is connected to the output end of the (n - 2)-th stage gate driving signal, the second control end is connected to the second node, the input end is connected to the first node, and the output end is connected to the second level signal output end. The control end of the second pull-down module is connected to the output end of the (n + 1)-th stage gate driving signal, the input end is connected to the first node, and the output end is connected to the second level signal output end. Wherein, n is a natural number greater than or equal to 3. When the output end of the (n - 2)-th stage gate driving signal outputs a first level signal, the first pull-down module pulls down the voltage of the second node. When the output end of the (n + 1)-th stage gate driving signal outputs a first level signal, the first power supply module outputs the first level signal, and the first pull-down module and the second pull-down module pull down the voltage of the first node.

[0006] Optionally, the charging module includes a first transistor, the second pull-down module includes a second transistor, the first pull-down module includes a third transistor and a fourth transistor, the first control module includes a fifth transistor, and the driving module includes a sixth transistor; a control end of the first transistor is connected to an output end of an (n-1)-th stage gate driving signal, an input end is connected to the first level signal output end, and an output end is connected to the first node; a control end of the second transistor receives an (n+1)-th stage gate driving signal, an input end is connected to the first node, and an output end is connected to the second level signal output end; a control end of the third transistor is connected to an output end of an (n-2)-th stage gate driving signal, an input end is connected to a control end of the fourth transistor, and an output end is connected to the second level signal output end; a control end of the fourth transistor is connected to the second node, an input end is connected to the first node, and an output end is connected to the second level signal output end; a control end of the fifth transistor is connected to the first node, an input end is connected to the first power supply module, and an output end is connected to the second level signal output end; a control end of the sixth transistor is connected to the first node, an input end is connected to a clock signal, and an output end outputs an n-th stage gate driving signal; the first power supply module includes a seventh transistor, and an eighth transistor is further disposed between the output end of the (n-2)-th stage gate driving signal and the third transistor; a control end and an input end of the seventh transistor receive a control voltage signal, and an output end is connected to an input end of the fifth transistor; a control end and an input end of the eighth transistor receive the (n-2)-th stage gate driving signal, and an output end is connected to the control end of the third transistor.

[0007] Optionally, the row driving circuit further includes a second control module and a third pull-down module; a control end of the second control module is connected to the first node, an input end is connected to an output end of a second power supply module, and an output end is connected to a second level signal output end; a third control end of the third pull-down module is connected to an output end of an (n-2)th stage gate driving signal, a fourth control end is connected to the third node, an input end is connected to the first node, and an output end is connected to the second level signal output end; wherein, the third pull-down module includes a ninth transistor and a tenth transistor, and the second control module includes an eleventh transistor; a control end of the ninth transistor is connected to the output end of the (n-2)th stage gate driving signal, an input end is connected to a control end of the tenth transistor, and an output end is connected to the second level signal output end; a control end of the tenth transistor is connected to the third node, an input end is connected to the first node, and an output end is connected to the second level signal output end; a control end of the eleventh transistor is connected to the first node, an input end is connected to the second power supply module, and an output end is connected to the second level signal output end; a first power supply module connected to the first control module and a second power supply module connected to the second control module respectively input opposite control voltages to the first control module and the second control module; the second power supply module includes a twelfth transistor, a control end and an input end of the twelfth transistor receive a control voltage signal, and an output end is connected to the input end of the eleventh transistor.

[0008] Optionally, a threshold voltage of the fifth transistor is less than a threshold voltage of the seventh transistor.

[0009] Optionally, each row driving circuit includes a thirteenth transistor, a control end of the thirteenth transistor is connected to a reset signal, an input end of the thirteenth transistor is connected to an output end of the first transistor, and an output end of the thirteenth transistor is connected to the second level signal output end.

[0010] Optionally, a fourteenth transistor is further disposed between an output end of the (n-3)th stage gate driving signal and the third transistor; a control end and an input end of the fourteenth transistor receive the (n-3)th stage gate driving signal, and an output end is connected to a control end of the first pull-down module.

[0011] The present application further discloses a display panel, the display panel includes the row driving circuit as described in any one of the above, and the row driving circuit is used for driving and displaying of the display panel.

[0012] The present application further discloses a driving method for driving the row driving circuit as described in any one of the above, and the driving method includes the steps:

[0013] An output end of the (n-2)th stage gate driving signal outputs a first level signal, starting the first pull-down module to control the voltage of the second node to be pulled down;

[0014] The output terminal of the (n - 1)-th stage gate driving signal outputs a first level signal, starting a charging module to pre-charge a first node to control the start of a driving module, generating and outputting an n-th stage gate driving signal according to a clock signal CKn corresponding to the n-th stage gate driving signal; and

[0015] The output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal, starting a second pull-down module to pull down the voltage of the first node; a first control module receives a first level signal output by a first power supply module, a second node receives the first level signal for charging, starting a first pull-down module to pull down the voltage of the first node;

[0016] where n is a natural number greater than or equal to 3.

[0017] Optionally, the step that the output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal, starting a second pull-down module to pull down the voltage of the first node; a first control module receives a first level signal output by a first power supply module, a second node receives the first level signal for charging, starting a first pull-down module to pull down the voltage of the first node includes:

[0018] When the display panel displays the current frame, the output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal, starting a second pull-down module to pull down the voltage of the first node; a first control module receives a first level signal output by a first power supply module, a second node receives the first level signal for charging, starting a first pull-down module to pull down the voltage of the first node; when the display panel displays the next frame of the current frame, the output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal, starting a second pull-down module to pull down the voltage of the first node; a second control module receives a first level signal output by a second power supply module, starting a third pull-down module to pull down the voltage of the first node;

[0019] where when the first control module receives a first level signal output by the first power supply module, the second control module receives a second level signal output by the second power supply module; when the first control module receives a second level signal output by the first power supply module, the second control module receives a first level signal output by the second power supply module.

[0020] Optionally, the period of the first level signal of the gate driving signal corresponding to each gate line is T, and the interval time between the rising edges of the first level signals of the gate driving signals corresponding to two adjacent row driving units is any value between 1 / 6 and 1 / 3 of the high level period T.

[0021] Compared with using the upper gate signal as the switching control signal and charging voltage of the charging module, in this application, the (n - 1)th signal is only used as the switching control signal of the control terminal of the charging module, and the external DC voltage VGH is used as the input signal of the charging module. This greatly improves the response speed and driving ability of the charging module. In addition, this application also sets up a first control module and a second pull - down circuit. By controlling the voltages of the first node and the second node, the charging ability of the charging module for the first node is improved, and the first node is pre - charged to raise the voltage of the first node to a higher voltage, reducing leakage and avoiding the generation of horizontal stripes due to leakage. Moreover, when the first - level gate line outputs a first - level signal, due to the capacitive coupling effect of the parasitic capacitance, the first node is coupled to a higher potential, the driving module opens more fully, and the first - level gate line is charged to a high level faster, further improving the driving ability of the row driving circuit, improving the horizontal stripes and other display defects caused by the leakage of TFT devices, and improving the image quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings included are used to provide a further understanding of the embodiments of the present application, which form a part of the specification, illustrate the implementation manners of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings. In the drawings:

[0023] Figure 1 is a schematic structural diagram of a row driving circuit according to the first embodiment of the present application;

[0024] Figure 2 is an equivalent circuit schematic diagram of the row driving circuit according to the first embodiment of the present application;

[0025] Figure 3 is a circuit schematic diagram of the row driving circuit according to the second embodiment of the present application;

[0026] Figure 4 is a schematic structural diagram of a row driving circuit according to the third embodiment of the present application;

[0027] Figure 5 is an equivalent circuit schematic diagram of the row driving circuit according to the third embodiment of the present application;

[0028] Figure 6 is a voltage signal waveform diagram according to the third embodiment of the present application;

[0029] Figure 7 is a Q - point voltage change diagram according to the third embodiment of the present application;

[0030] Figure 8It is a schematic circuit diagram of the row driving circuit according to the fourth embodiment of the present application;

[0031] Figure 9 It is a diagram showing the change of the Q-point voltage according to the fourth embodiment of the present application;

[0032] Figure 10 It is a schematic circuit diagram of the row driving circuit according to the fifth embodiment of the present application;

[0033] Figure 11 It is a schematic diagram of the structure of the display panel according to the sixth embodiment of the present application;

[0034] Figure 12 It is a flowchart of the driving method according to the seventh embodiment of the present application.

[0035] Among them, 100, row driving circuit; 110, charging module; 120, driving module; 130, first control module; 140, power supply voltage output module; 141, first power supply module; 142, second power supply module; 150, first pull-down module; 160, second pull-down module; 170, second control module; 180, third pull-down module; 200, display panel; 210, scanning line; 220, timing control module; 230, clock signal output module;

[0036] Gn+1 - the (n + 1)th stage; Gn - the nth stage; Gn-1 - the (n - 1)th stage; Gn-2 - the (n - 2)th stage; Gn-3 - the (n - 3)th stage; Q1 - the first node; QB1 - the second node; QB2 - the third node; T1 - the first transistor; T2 - the second transistor; T3 - the third transistor; T4 - the fourth transistor; T5 - the fifth transistor; T6 - the sixth transistor; T7 - the seventh transistor; T8 - the eighth transistor; T9 - the ninth transistor; T10 - the tenth transistor; T11 - the eleventh transistor; T12 - the twelfth transistor; T13 - the thirteenth transistor; T14 - the fourteenth transistor. Detailed implementation manners

[0037] It should be understood that the terms, specific structures and functional details disclosed here are only for describing specific embodiments and are representative, but the present application can be specifically implemented in many alternative forms and should not be construed as being limited only to the embodiments set forth herein.

[0038] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating relative importance or implicitly indicating the quantity of the indicated technical features. Thus, unless otherwise specified, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features; the meaning of "a plurality" is two or more. The term "comprising" and any variations thereof mean inclusive inclusion, and there may be or be added one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0039] In addition, terms indicating orientation or positional relationships such as "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are described based on the orientation or relative positional relationship shown in the drawings, and are only for the convenience of simplifying the description of the present application, rather than indicating that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0040] Furthermore, unless otherwise clearly specified and defined, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, or the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0041] The present application will be described in detail below with reference to the drawings and optional embodiments.

[0042] As the first embodiment of the present application, a row driving circuit 100 is disclosed. Refer to Figures 1 to 2As shown, the row driving circuit 100 includes a plurality of cascaded row driving units. Each row driving unit corresponding to each gate line after the (n - 1)-th gate line includes a charging module 110, a driving module 120, a first control module 130, a first pull-down module 150, and a second pull-down module 160. The control end of the charging module 110 is connected to the output end of the (n - 1)-th stage gate driving signal, the input end is connected to the first level signal output end, and the output end is connected to the first node Q. The control end of the driving module 120 is connected to the first node Q, the input end is connected to the clock signal CKn corresponding to the n-th stage gate driving signal, and the output end outputs the n-th stage gate driving signal. The control end of the first control module 130 is connected to the first node Q, the input end is connected to the output end of the first power supply module 141, and the output end is connected to the second level signal output end through the second node QB. The first control end of the first pull-down module 150 is connected to the output end of the (n - 2)-th stage gate driving signal, the second control end is connected to the second node QB1, the input end is connected to the first node Q, and the output end is connected to a second level signal output end. The control end of the second pull-down module 160 is connected to the output end of the (n + 1)-th stage gate driving signal, the input end is connected to the first node Q, and the output end is connected to a second level signal output end. Here, n is a natural number greater than or equal to 3.

[0043] Generally, the first level signal can be a high-level signal, and the second level signal can be a low-level signal, and vice versa. Taking the first level signal as a high-level signal and the second level signal as a low level as an example for illustration, when the output terminal of the (n - 2)-th stage gate driving signal outputs a high level, the first pull-down module 150 pulls down the voltage of the second node QB1. When the output terminal of the (n + 1)-th stage gate driving signal outputs a high level, the first pull-down module 150 and the second pull-down module 160 pull down the voltage of the first node Q. When the output terminal of the (n - 2)-th stage gate driving signal outputs a high level, the first pull-down module 150 is started to control the pulling down of the voltage of the second node QB1. When the output terminal of the (n - 1)-th stage gate driving signal outputs a high level, the charging module is started to pre-charge the first node Q to control the start of the driving module 120, and the n-th stage gate driving signal is generated and output according to the clock signal CKn corresponding to the n-th stage gate driving signal. When the output terminal of the (n + 1)-th stage gate driving signal outputs a high level, the second pull-down module 160 is started to pull down the voltage of the first node Q. The first control module 130 receives the high level output by the first power supply module 141 and starts the first pull-down module 150 to pull down the voltage of the first node Q. The first control module 130 and the second pull-down module 160 improve the charging ability of the charging module 110 for the first node Q by controlling the voltages of the second node QB1 and the first node Q, so that the pre-charging voltage of the Q point is raised to a higher voltage, reducing leakage current, avoiding the generation of horizontal stripes caused by leakage current, and when the n-th stage gate driving signal outputs a high level, due to the capacitive coupling effect of the parasitic capacitance, the Q point is coupled to a higher potential, the driving module 120 is opened more fully, the n-th stage gate driving signal is charged to a high level faster, further improving the driving ability, improving the horizontal stripes and other display defects caused by the leakage of the TFT device, and improving the image quality.

[0044] Specifically, the charging module 110 includes a first transistor T1, the second pull-down module 160 includes a second transistor T2, the first pull-down module 150 includes a third transistor T3 and a fourth transistor T4, the first control module 130 includes a fifth transistor T5, and the driving module 120 includes a sixth transistor T6. The control terminal of the first transistor T1 receives the (n - 1)-th stage gate driving signal output from the output terminal connected to the (n - 1)-th stage gate driver signal, the input terminal receives the first level signal VGH output from the first level signal output terminal, and the output terminal is connected to the first node Q. The control terminal of the second transistor T2 receives the (n + 1)-th stage gate driving signal, the input terminal is connected to the first node Q, and the output terminal is connected to the second level signal VSS. The control terminal of the third transistor T3 receives the (n - 2)-th stage gate driving signal, the input terminal is connected to the control terminal of the fourth transistor T4, and the output terminal is connected to the second level signal VSS. The control terminal of the fourth transistor T4 is connected to the second node QB1, the input terminal is connected to the first node Q, and the output terminal is connected to the second level signal VSS. The control terminal of the fifth transistor T5 is connected to the first node Q, the input terminal is connected to the first power supply module 141, and the output terminal is connected to the second level signal VSS. The control terminal of the sixth transistor T6 is connected to the first node Q, the input terminal is connected to the clock signal, and the output terminal outputs the n-th stage gate driving signal.

[0045] Further, as Figure 3 shown, as the second embodiment of the present application, considering that the fifth transistor T5 and the third transistor T3 directly receive voltage signals, which will cause loss of the transistor and affect the service life, the first power supply module 141 includes a seventh transistor T7. By setting the seventh transistor T7, the high-level signal output by the first power supply module 141 is regulated. An eighth transistor T8 is further provided between the output terminal of the (n - 2)-th stage gate driving signal and the third transistor T3. By setting the eighth transistor T8, the high-level signal output from the output terminal of the (n - 2)-th stage gate driving signal is regulated. The control terminal and the input terminal of the seventh transistor T7 receive the first level signal, and the output terminal is connected to the input terminal of the fifth transistor T5. The control terminal and the input terminal of the eighth transistor T8 receive the level signal output from the output terminal of the (n - 2)-th stage gate driving output, and the output terminal is connected to the control terminal of the third transistor T3. When the output terminal of the (n - 2)-th stage gate driving signal outputs a high level, the eighth transistor T8 is turned on, and then the third transistor T3 is turned on. The second node QB1 is pulled down through the third transistor, so that the fourth transistor T4 is in the off state, thereby improving the charging ability of the first node Q and reducing leakage.

[0046] To make the sixth transistor T6 turn on more fully, when the first node Q is at a high voltage and the second node QB1 is at a low voltage, the level signal output from the (n - 2)-th stage gate driving output terminal is capacitively coupled by the parasitic capacitances of the first node Q and the second node QB1. The first node Q is coupled to a higher voltage level, and the sixth transistor T6 turns on more fully, and the Gn row gate line is charged to a high potential faster; when the first node Q is at a high level, the fifth transistor T5 turns on. The output terminal of the fifth transistor T5 receives the second level signal, and the input terminal receives the first level signal output from the first power supply module. The first level signal is at a high level. At this time, the second node QB1 must be in a low level state. Therefore, the threshold voltage of the fifth transistor is less than the threshold voltage of the seventh transistor to ensure that the second node QB1 is in a low level state.

[0047] As Figure 4 and Figure 5 shown, as the third embodiment of the present application, it is a further refinement and improvement of the above first embodiment. The row driving circuit 100 further includes a second control module 170 and a third pull-down module 180; the control terminal of the second control module 170 is connected to the first node Q, the input terminal is connected to the output terminal of the second power supply module 140, and the output terminal is connected to the second level signal output terminal; the third control terminal of the third pull-down module 180 is connected to the output terminal of the (n - 2)-th stage gate driving signal, the fourth control terminal is connected to the third node QB2, the input terminal is connected to the first node Q, and the output terminal is connected to a second level signal output terminal; wherein, the first power supply module 141 and the second power supply module 142 connected to the first control module 130 and the second control module 170 respectively input opposite control voltages to the first control module 130 and the second control module 170.

[0048] Specifically, the third pull-down module 180 includes a ninth transistor T9 and a tenth transistor T10, the second control module 170 includes an eleventh transistor T11, the control terminal of the ninth transistor T9 receives the (n - 2)-th stage gate driving signal, the input terminal is connected to the third node QB2, and the output terminal is connected to the second-level signal VSS; the control terminal of the eleventh transistor T11 is connected to the first node Q, the input terminal is connected to the second power supply module 142, and the output terminal is connected to the second-level signal VSS; the second power supply module 142 further includes a twelfth transistor T12, the control terminal and the input terminal of the twelfth transistor T12 receive a control voltage signal, and the output terminal is connected to the input terminal of the eleventh transistor T11; wherein, the seventh transistor T7 and the twelfth transistor T12 receive a set of voltage signals with opposite waveforms. When the (n + 1)-th level is high, the control voltage signal of the seventh transistor T7 is high, the control voltage signal of the twelfth transistor T12 is low, the control voltage signal of the seventh transistor T7 is low, and the control voltage signal of the twelfth transistor T12 is high. Two control circuits and pull-down circuits corresponding to the two control circuits are provided, and the two sets of circuits can be used alternately, so as to extend the service life of the corresponding transistors and reduce the occurrence of aging.

[0049] Reference Figures 4 to 7 As shown, the (n - 1)-th signal is only used as the gate switch signal of T1, and the external DC voltage VGH is used as the input signal of T1, which greatly improves the response speed and driving ability of T1. At the same time, a TFT device switch T8 is further provided, the output terminal of the (n - 2)-th stage gate driving signal is used as the control terminal and the input terminal of the eighth transistor T8, the high-level period of the gate driving signal corresponding to each gate line is T, and the interval time between the rising edges of the high levels of the gate driving signals corresponding to two adjacent row driving units is any value between 1 / 6 and 1 / 3 of the high-level period T; its working principle is as Figure 6As shown, taking the timing diagram of the driving circuit of 6 CK signals as an example, the time difference between each adjacent CK is one H time (the square wave width in each CK waveform is 6 H). At time t2 in the timing diagram, the output potential of CK2 at the (n - 2)th is at high level, T8, T3, and T9 are turned on, and the potential at the QB point is pulled low, remaining at low potential for one H time within the time period from t2 to t3. At time t3, CK3 is at high level, and its output potential at the (n - 1)th is at high level. When starting to pre-charge the Q point, the (n - 2)th row has pulled down the QB1 and QB2 points for one H time, ensuring that QB1 and QB2 are at low potential, and T4 and T10 are in a completely off state. At this time, the pre-charge voltage of the Q point is raised to V1, and there will be no leakage phenomenon. The Q point is charged to the high voltage V1 in the time period from t3 to t4, and remains at the high voltage V1 in the time period from t4 to t5. T6 is in the on state. At time t4, CK4 is at high level, and the (n)th row outputs high level. Due to the capacitive coupling effect of the parasitic capacitance, the Q point is coupled to a higher potential V2 (V2 > V1), T6 is turned on more fully, and the Gn row gate line corresponding to the gate driving signal of the (n)th row is charged to high level faster, remaining at high level at time t5. Since the QB point is pulled down one H time earlier before pre-charging the Q point, T4 and T10 can be in a completely off state, improving the charging ability of T1 to Q, reducing the leakage of the Q point, enhancing the driving ability, thereby improving the horizontal stripes and other display defects caused by the leakage of the TFT device and improving the image quality.

[0050] Figure 8 As shown, as the fourth embodiment of the present application, a fourteenth transistor T14 is added at the position between the output end of the (n - 3)th stage gate driving signal and the output end of the eighth transistor T8. The output end of the (n - 3)th stage gate driving signal serves as the control end and input end of T14. The implementation method is the same as that of the second embodiment. The difference is that the QB point is pulled down in the time period from t1 to t2, and the potential of the QB point is as Figure 9 shown. That is, the QB point is pulled down 2 H times earlier before pre-charging the Q point. After pulling down for one H time, the (n - 2)th row pulls down for another H time simultaneously, which can make T4 and T10 in a completely off state, improving the charging ability of T1 to the Q point.

[0051] Figure 10As shown, as the fifth embodiment of the present application, it is a further refinement and improvement of any of the above embodiments. Each of the row driving circuits 100 includes a thirteenth transistor T13. The control terminal of the thirteenth transistor T13 is connected to a reset signal. The input terminal of the thirteenth transistor T13 is connected to the output terminal of the first transistor T1. The output terminal of the thirteenth transistor is connected to the second level signal. The thirteenth transistor T13 is set to conduct after the end of a frame to clear the potential of point Q on the row driving circuit 100 again.

[0052] As Figure 11 As shown, as the sixth embodiment of the present application, a display panel 200 is disclosed. The display panel 200 includes the row driving circuit 100 described in any of the above embodiments. The power supply modules connected to the first control module 130 and the second control module 170 of the row driving circuit 100 respectively input opposite control voltages to the first control module 130 and the second control module 170. The control voltages with opposite waveforms input to the first control module 130 and the second control module 170 are generated by the power supply voltage output module 140 in the timing control chip 220. The power supply voltage output module 140 includes a first power supply module and a second power supply module. The first power supply module 141 is connected to the first control module 130, and the second power supply module 142 is connected to the second control module 170. The voltage output by the first power supply module 141 can be output to the second control module 170 after passing through an inverter. In this way, the power supply voltage output module 140 only needs one voltage signal. In the entire display panel, there are multiple row driving circuits 100 corresponding to the scanning lines 210 of the display panel. Each row driving circuit 100 turns on the corresponding transistor through the clock signal of the control clock signal module 230 to output the corresponding gate driving signal to the scanning line 210. The row driving circuit in any of the above embodiments is described. There are multiple GDL circuits, and the multiple GDL circuits are cascaded to ensure the normal output of the GDL circuit. On the premise of ensuring the performance and reliability of the GDL circuit, the number of TFTs is relatively small, the risk of short-circuit failure can be reduced during the process manufacturing, and a narrower border can be achieved, which is suitable for the design of narrow-border and high-resolution models.

[0053] As Figure 12 As shown, as the seventh embodiment of the present application, the present application also discloses a driving method for driving the row driving circuit described in any of the above. The driving method includes the steps:

[0054] S1: The output terminal of the (n - 2)-th stage gate driving signal outputs a first level signal to start the first pull-down module and control the voltage of the second node to be pulled down;

[0055] S2: The output terminal of the (n - 1)-th level gate driving signal outputs a first level signal to start the charging module, pre-charge the first node to control the start of the driving module, generate and output the n-th level gate driving signal according to the clock signal CKn corresponding to the n-th level gate driving signal; and

[0056] S3: The output terminal of the (n + 1)-th level gate driving signal outputs a first level signal to start the second pull-down module to control the pull-down of the voltage of the first node; the first control module receives the first level signal output by the first power supply module, the second node receives the first level signal for charging, starts the first pull-down module to control the pull-down of the voltage of the first node;

[0057] where n is a natural number greater than or equal to 3.

[0058] Generally, the period of the first level signal of the gate driving signal corresponding to each gate line is T, and the interval time between the rising edges of the first level signals of the gate driving signals corresponding to two adjacent row driving units is any value between 1 / 6 and 1 / 3 of the period T of the first level signal; taking the high level period T = 6H of the gate driving signal as an example, the interval time between the rising edges of the high levels of the gate driving signals corresponding to two adjacent row driving units is H for illustration, refer to Figure 5 and Figure 6 , at time t2, the output potential Gn - 2 of CK2 is at a high level, T8, T3, and T9 are turned on, the potential of point QB is pulled down, and it remains at a low potential for a time of one H from t2 to t3. At time t3, CK3 is at a high level, its output potential Gn - 1 is at a high level, when starting to pre-charge point Q, the row of Gn - 2 has pulled down points QB1 and QB2 for a time of one H, ensuring that QB1 and QB2 are at a low potential, and T4 and T10 are in a completely off state. At this time, the pre-charge voltage of point Q is raised to V1, and there will be no leakage phenomenon. Point Q is charged to the high voltage V1 in the time period from t3 to t4, and remains at the high voltage V1 in the time period from t4 to t5. T6 is in an on state. At time t4, CK4 is at a high level, the n-th level outputs a high level. Due to the capacitive coupling effect of the parasitic capacitance, point Q is coupled to a higher potential V2 (V2 > V1), T6 is opened more fully, and Gn is charged to a high level faster, and remains at a high level at time t5. Since points QB are pulled down one H time in advance before pre-charging point Q, T4 and T10 can be in a completely off state, improving the charging ability of T1 to Q and reducing the leakage of point Q.

[0059] Step S3 further includes:

[0060] When the display panel displays the current frame, the output terminal of the (n + 1)-th level gate driving signal outputs a high level to activate the second pull-down module to pull down the voltage of the first node Q; the first control module receives the first level signal output by the first power supply module, the second node receives the first level signal for charging, and the first pull-down module is activated to pull down the voltage of the first node Q; when the display panel displays the next frame of the current frame, the output terminal of the (n + 1)-th level gate driving signal outputs the first level signal to activate the second pull-down module to pull down the voltage of the first node Q; the second control module receives the first level signal output by the second power supply module and activates the third pull-down module to pull down the voltage of the first node Q.

[0061] Wherein, when the first control module receives the first level signal output by the first power supply module, the second control module receives the second level signal output by the second power supply module; when the first control module receives the second level signal output by the first power supply module, the second control module receives the first level signal output by the second power supply module, that is, when the first control module receives a high level, the second control module receives a low level; the first control module and the second control module are provided, and a first pull-down circuit is provided corresponding to the first control module, and a third pull-down circuit is provided corresponding to the second control module. The two groups of circuits can be used alternately, so that the service life of the corresponding transistors can be extended and the occurrence of aging can be reduced; in addition, the high-level time of the (n + 1)-th level gate driving signal can also be evenly divided. It is also possible to activate the first control module to set the first pull-down circuit in the first half of the on-time and activate the second control module to set the third pull-down circuit in the second half of the on-time.

[0062] It should be noted that the limitations of the steps involved in this solution do not, on the premise of not affecting the implementation of the specific solution, determine the order of execution of the steps. The steps written in the front can be executed first, or can be executed later, or even can be executed simultaneously. As long as this solution can be implemented, it should be regarded as falling within the protection scope of this application.

[0063] It should be noted that the inventive concept of this application can form a very large number of embodiments. However, due to the limited space of the application documents, it is impossible to list them all. Therefore, on the premise of non-conflict, the above-described embodiments or technical features can be arbitrarily combined to form new embodiments. After the combination of the embodiments or technical features, the original technical effect will be enhanced.

[0064] The technical solution of the present application can be widely used in various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, MVA (Multi-Domain Vertical Alignment) display panels. Of course, it can also be other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, and the above solutions are all applicable.

[0065] The above content is a further detailed description of the present application in combination with specific optional implementation manners. It cannot be determined that the specific implementation of the present application is only limited to these descriptions. For those of ordinary skill in the technical field to which the present application belongs, without departing from the concept of the present application, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present application.

Claims

1. A row driving circuit includes a plurality of cascaded row driving units, characterized in that, each of the row driving units corresponding to each gate line after the (n - 1)-th gate line includes: a charging module, whose control end is connected to the output end of the (n - 1)-th stage gate driving signal, the input end is connected to the first level signal output end, and the output end is connected to the first node; a driving module, whose control end is connected to the first node, the input end is connected to the clock signal corresponding to the n-th stage gate driving signal, and the output end outputs the n-th stage gate driving signal; a first control module, whose control end is connected to the first node, the input end is connected to the output end of the first power supply module, and the output end is connected to the second level signal output end through the second node; a first pull-down module, whose first control end is connected to the output end of the (n - 2)-th stage gate driving signal, the second control end is connected to the second node, the input end is connected to the first node, and the output end is connected to the second level signal output end; and a second pull-down module, whose control end is connected to the output end of the (n + 1)-th stage gate driving signal, the input end is connected to the first node, and the output end is connected to the second level signal output end; wherein, n is a natural number greater than or equal to 3; when the output end of the (n - 2)-th stage gate driving signal outputs a first level signal, the first pull-down module pulls down the voltage of the second node; when the output end of the (n + 1)-th stage gate driving signal outputs a first level signal, the first power supply module outputs the first level signal, and the first pull-down module and the second pull-down module pull down the voltage of the first node; the first pull-down module includes a third transistor and a fourth transistor, the control end of the third transistor is connected to the output end of the (n - 2)-th stage gate driving signal, the input end is connected to the control end of the fourth transistor, and the output end is connected to the second level signal output end; the control end of the fourth transistor is connected to the second node, the input end is connected to the first node, and the output end is connected to the second level signal output end.

2. The row driving circuit according to claim 1, characterized in that, the charging module includes a first transistor, the second pull-down module includes a second transistor, the first control module includes a fifth transistor, and the driving module includes a sixth transistor; the control end of the first transistor is connected to the output end of the (n - 1)-th stage gate driving signal, the input end is connected to the first level signal output end, and the output end is connected to the first node; the control end of the second transistor receives the (n + 1)-th stage gate driving signal, the input end is connected to the first node, and the output end is connected to the second level signal output end; the control end of the fifth transistor is connected to the first node, the input end is connected to the first power supply module, and the output end is connected to the second level signal output end; the control end of the sixth transistor is connected to the first node, the input end is connected to the clock signal, and the output end outputs the n-th stage gate driving signal; the first power supply module includes a seventh transistor, and an eighth transistor is further provided between the output end of the (n - 2)-th stage gate driving signal and the third transistor; The control terminal and the input terminal of the seventh transistor receive a control voltage signal, and the output terminal is connected to the input terminal of the fifth transistor; the control terminal and the input terminal of the eighth transistor receive the (n-2)th stage gate driving signal, and the output terminal is connected to the control terminal of the third transistor.

3. The row driving circuit according to any one of claims 1 or 2, characterized in that the row driving circuit further includes: a second control module, the control terminal is connected to the first node, the input terminal is connected to the output terminal of the second power supply module, and the output terminal is connected to the second level signal output terminal; and a third pull-down module, the third control terminal is connected to the output terminal of the (n-2)th stage gate driving signal, the fourth control terminal is connected to the third node, the input terminal is connected to the first node, and the output terminal is connected to the second level signal output terminal; wherein, the third pull-down module includes a ninth transistor and a tenth transistor, and the second control module includes an eleventh transistor; the control terminal of the ninth transistor is connected to the output terminal of the (n-2)th stage gate driving signal, the input terminal is connected to the control terminal of the tenth transistor, and the output terminal is connected to the second level signal output terminal; the control terminal of the tenth transistor is connected to the third node, the input terminal is connected to the first node, and the output terminal is connected to the second level signal output terminal; the control terminal of the eleventh transistor is connected to the first node, the input terminal is connected to the second power supply module, and the output terminal is connected to the second level signal output terminal; the first power supply module connected to the first control module and the second power supply module connected to the second control module respectively input opposite control voltages to the first control module and the second control module; the second power supply module includes a twelfth transistor, the control terminal and the input terminal of the twelfth transistor receive a control voltage signal, and the output terminal is connected to the input terminal of the eleventh transistor.

4. The row driving circuit according to claim 2, characterized in that the threshold voltage of the fifth transistor is less than the threshold voltage of the seventh transistor.

5. The row driving circuit according to claim 1, characterized in that each row driving circuit further includes a thirteenth transistor, the control terminal of the thirteenth transistor is connected to a reset signal, the input terminal of the thirteenth transistor is connected to the output terminal of the first transistor, and the output terminal of the thirteenth transistor is connected to the second level signal output terminal.

6. The row driving circuit according to claim 3, characterized in that a fourteenth transistor is further provided between the output terminal of the (n-3)th stage gate driving signal and the third transistor; the control terminal and the input terminal of the fourteenth transistor receive the (n-3)th stage gate driving signal, and the output terminal is connected to the control terminal of the third transistor in the first pull-down module.

7. A display panel, characterized in that it includes the row driving circuit according to any one of claims 1-6, and the row driving circuit is used for driving and displaying of the display panel.

8. A driving method for driving the row driving circuit according to any one of claims 1-6, characterized in that it includes steps: The output terminal of the (n - 2)-th stage gate driving signal outputs a first level signal to activate the first pull-down module to pull down the voltage of the second node; The output terminal of the (n - 1)-th stage gate driving signal outputs a first level signal to activate the charging module to pre-charge the first node to control the activation of the driving module, generate and output the n-th stage gate driving signal according to the clock signal corresponding to the n-th stage gate driving signal; And The output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal to activate the second pull-down module to pull down the voltage of the first node; The first control module receives the first level signal output by the first power supply module, the second node receives the first level signal for charging, and activates the first pull-down module to pull down the voltage of the first node; wherein, n is a natural number greater than or equal to 3.

9. The driving method according to claim 8, characterized in that the output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal to activate the second pull-down module to pull down the voltage of the first node; The steps that the first control module receives the first level signal output by the first power supply module, the second node receives the first level signal for charging, and activates the first pull-down module to pull down the voltage of the first node include: When the display panel displays the current frame, the output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal to activate the second pull-down module to pull down the voltage of the first node; the first control module receives the first level signal output by the first power supply module, the second node receives the first level signal for charging, and activates the first pull-down module to pull down the voltage of the first node; when the display panel displays the next frame of the current frame, the output terminal of the (n + 1)-th stage gate driving signal outputs a first level signal to activate the second pull-down module to pull down the voltage of the first node; the second control module receives the first level signal output by the second power supply module and activates the third pull-down module to pull down the voltage of the first node; wherein, when the first control module receives the first level signal output by the first power supply module, the second control module receives the second level signal output by the second power supply module; when the first control module receives the second level signal output by the first power supply module, the second control module receives the first level signal output by the second power supply module.

10. The driving method according to claim 8, characterized in that The period of the first level signal of the gate driving signal corresponding to each gate line is T, and the interval time between the rising edges of the first level signals of the gate driving signals corresponding to two adjacent row driving units is any value between 1 / 6 and 1 / 3 of the period T of the first level signal.

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