Ensuring the integrity of data stored in memory by using watermarks

Abstract

Systems and methods involving ensuring the integrity of data stored in memory by using a watermark are described. An example method in a system including a processor and a memory can include receiving data for storage at an address in the memory. The method can also include, after encoding the data with an error correction code to generate intermediate data having a first number of bits, reversibly altering the intermediate data with a watermark to generate watermarked data for storage in the memory, where the watermark is generated by applying a cryptographic function to a user key and the address, and where the watermarked data has a second number of bits, the second number of bits equaling the first number of bits.

Description

Background Technology

[0001] Computing, storage, and networking resources are increasingly accessed via distributed computing systems, including public clouds, private clouds, or a hybrid of both. Public clouds comprise global networks of servers performing various functions, including storing and managing data, running applications, and delivering content or services such as streaming video, email, office productivity software, or social media. Servers and other components may reside in data centers around the world. While public clouds provide services to the public via the internet, businesses can use private or hybrid clouds. Both private and hybrid clouds also include networks of servers located in data centers. Cloud service providers offer access to these resources by providing cloud computing and storage resources to customers. In any such distributed computing system, multiple computing entities can access the same memory. Furthermore, in some memory systems, it may be unclear whether data retrieved from an address is actually the data that should be stored at that address. Therefore, better memory systems are needed where multiple entities can access the same memory. Summary of the Invention

[0002] One aspect of this disclosure relates to a method in a system including a processor and memory. The method may include receiving data for storage at an address in the memory. The method may further include, after encoding the data using error-correcting codes to generate intermediate data having a first number of bits, reversibly modifying the intermediate data using a watermark to generate watermarked data for storage in the memory, wherein the watermark is generated by applying a cryptographic function to a user key and an address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits.

[0003] In another aspect, this disclosure relates to a system including a host server that includes a memory controller coupled to a memory and a processor. The system may also include a management program associated with the host server, the management program being configured to manage a plurality of computing entities. The memory controller may be configured to: (1) receive data from one of the plurality of computing entities for storage at an address in memory, and (2) after encoding the data with error-correcting codes to generate intermediate data having a first number of bits, reversibly modify the intermediate data with a watermark to generate watermarked data for storage in memory, wherein the watermark is generated by applying a cryptographic function to the address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits.

[0004] In another aspect, this disclosure relates to a method performed in a host server including a processor and memory. The method may include receiving plaintext data from one of a plurality of computing entities associated with the host server for storage at an address in memory. The method may further include encrypting the plaintext data using at least a user key associated with the computing entity to generate encrypted data. The method may further include, after encoding the encrypted data with an error-correcting code to generate intermediate data having a first number of bits, reversibly modifying the intermediate data with a message authentication code to generate watermarked data for storage in memory, wherein the message authentication code is generated by applying a cryptographic function to the user key and the address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits.

[0005] This summary portion is provided to present a simplified view of the selected concepts, which will be further described in the detailed description below. This summary portion is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0006] This disclosure is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity and are not necessarily drawn to scale.

[0007] Figure 1 A diagram illustrating a system environment for ensuring data integrity using watermarking, based on an example, is shown.

[0008] Figure 2 A diagram is shown, based on an example, of a host server that includes a system for ensuring data integrity by using watermarking;

[0009] Figure 3 A diagram illustrating a data path used to ensure data integrity through the use of watermarking is shown, based on an example.

[0010] Figure 4 A diagram illustrating another data path for ensuring data integrity by using watermarking, based on an example;

[0011] Figure 5 The system environment for implementing a system that ensures data integrity by using watermarking is shown as an example.

[0012] Figure 6 A flowchart based on an example method is shown; and

[0013] Figure 7 Another flowchart based on an example method is shown. Detailed Implementation

[0014] The examples described in this disclosure relate to ensuring the integrity of data stored in a multi-user computing system by using watermarking. This data may be stored in a memory module included in a host server. Multiple host servers may be included in a server rack or server stack. The host server can be any server in a cloud computing environment configured to serve a tenant or other subscriber to a cloud computing service. Example memory technologies include, but are not limited to, volatile memory technologies, non-volatile memory technologies, and quasi-volatile memory technologies. Example memory types include dynamic random access memory (DRAM), flash memory (e.g., NAND flash), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), phase-change memory (PCM), and resistive random access memory (RRAM). More broadly, the examples in this disclosure relate to a computing environment in which even if one user has access to another user's memory, this cannot be done without detection. Examples of the technologies described in this disclosure can be implemented in systems such as personal computers, laptops, mobile phones, cellular towers (e.g., 5G cellular towers), edge computing sites, game controllers, or other similar devices.

[0015] Cloud computing can refer to a model of on-demand networking that enables access to a shared pool of configurable computing resources. For example, cloud computing can be adopted in the market to provide ubiquitous and convenient on-demand access to a shared pool of configurable computing resources. This shared pool of configurable computing resources can be rapidly provisioned and released via virtualization with low management effort or service provider interaction, and then scaled accordingly. Cloud computing models can be composed of various features, such as on-demand self-service, broad network access, resource pooling, rapid elasticity, metered services, etc. Cloud computing models can be used to expose various service models, such as, for example, Hardware as a Service (“HaaS”), Software as a Service (“SaaS”), Platform as a Service (“PaaS”), and Infrastructure as a Service (“IaaS”). Cloud computing models can also be deployed using different deployment models, such as private clouds, community clouds, public clouds, hybrid clouds, etc.

[0016] Figure 1A diagram is shown illustrating a system environment 100 for ensuring the integrity of stored data through the use of watermarking, according to an example. In this example, system environment 100 may correspond to a cloud computing stack in a data center. System environment 100 may be implemented as a server rack. In this example, system environment 100 may include host servers 110, 120, and 130. Each host server may include one or more processors configured to provide at least some form of computing functionality. As an example, host server 110 may include CPUs 112 and 114, host server 120 may include CPUs 122 and 124, and host server 130 may include CPUs 132 and 134. Host server 110 may also include memory 116 and memory 118. Host server 120 may also include memory 126 and memory 128. Host server 130 may also include memory 136 and memory 138.

[0017] Continue to refer to Figure 1 Host server 110 can be configured to execute instructions corresponding to hypervisor 140. Hypervisor 140 can also be configured to interact with virtual machines (VMs) (e.g., VM 142, VM 144, and VM 146). Instructions corresponding to the VMs can be executed using either CPU 112 or CPU 114 associated with host server 110. Hypervisor 150 can also be configured to interact with virtual machines (VMs) (e.g., VM 152, VM 154, and VM 156). Instructions corresponding to these VMs can be executed using either CPU 122 or CPU 124 associated with host server 120. Hypervisor 160 can also be configured to interact with virtual machines (VMs) (e.g., VM 162, VM 164, and VM 166). Instructions corresponding to these VMs can be executed using either CPU 132 or CPU 134 associated with host server 130.

[0018] Hypervisor 140 can share control information with hypervisor 150 via a control path. This control path can correspond to a path implemented using a bus system (e.g., a server rack bus system or other types of bus systems). Hypervisor 150 can share control information with hypervisor 160 via another control path. This control path can also correspond to a path implemented using a bus system. Each of hypervisors 140, 150, and 160 can be a kernel-based virtual machine (KVM) hypervisor, a Hyper-V hypervisor, or another type of hypervisor. Although Figure 1System 100 is shown as including a specific number of components arranged and coupled in a particular manner, but it may include fewer or additional components arranged and coupled in different manners. As an example, although... Figure 1 Not shown, but each host server may include an operating system for managing specific aspects of the host server. As another example, system 100 may include any number of host servers combined as part of a rack or stack. As another example, each host server may include any number of CPUs, GPUs, memory modules, or other components as needed to provide cloud computing, storage, and / or networking functions. Furthermore, the functions associated with system 100 may be assigned or combined as needed. Moreover, although... Figure 1 This describes access to the host server's memory via a VM; however, other types of computing entities, such as containers, microVMs, microservices, and single-core processors for serverless computing, can access memory in a similar manner. As used herein, the term "computing entity" includes, but is not limited to, implementations of functions, hypervisors, applications, services, microservices, containers, single-core processors for serverless computing, or any executable code (in the form of hardware, firmware, software, or any combination of the foregoing).

[0019] Figure 2A host server 200, including a memory controller 250, is illustrated according to one example. The host server 200 may include a CPU 210, a cache 220, a memory controller 250, and memory 280. The CPU 210 may be coupled to the cache 220 via bus 212 to allow fast access to instructions or data in the cache. In this example, the cache 220 may be an L2 cache and may also be coupled to other caches, such as an L1 cache (not shown). The CPU 210 may be coupled to the memory controller 250 to allow the exchange of data / control signals. The cache 220 may also be coupled to the memory controller 250 to allow the exchange of data and metadata or other information. In one example, the CPU 210, cache 220, and memory controller 250 may be integrated into a single module (e.g., a SoC). The memory controller 250 may be coupled to the memory 280 via bus 264 (e.g., a DDR memory bus or another type of bus). Memory 280 can correspond to any type of storage medium, including random access memory (e.g., DRAM), memory-class memory, or any other type of memory suitable for storing data to be used as part of host server 200. Furthermore, although not shown, a clock source may be used to synchronize signals as needed. The clock source can be implemented as a phase-locked loop (PLL) circuit or another type of clock circuit. In one example, memory 280 can correspond to a DRAM module (e.g., DIMM) coupled to memory controller 250 via bus 264 (e.g., single-channel or multi-channel). Each memory module may include a memory chip.

[0020] Regarding access to memory (e.g., DIMMs) associated with a host server, broadly speaking, a computing entity (e.g., a virtual machine (VM)) can access the host server's memory in two ways. In these cases, when the VM is accessing the physical memory associated with its executing CPU, it is a load or store access, which can be translated into a bus transaction by the hardware associated with the system.

[0021] Still referencing Figure 2The memory controller 250 can receive addresses (ADDR) from the CPU 210 via bus 232. The memory controller 250 may include address decoding logic (not shown) to decode the received address and provide commands to the memory 280. As an example, if the memory 280 is implemented as DRAM, the memory controller 250 can decode the received address into appropriate control signals for accessing the DRAM. In this example, the address may correspond to a host physical address. In one example, an operating system (not shown) associated with the host server 200 can maintain a mapping between virtual addresses (used by computing entities such as virtual machines) and host physical addresses. A memory management unit (MMU) associated with the CPU 210 can translate virtual addresses into host physical addresses. Other suitable address translation mechanisms may also be used. The memory controller 250 may further maintain a mapping between host physical addresses and logical addresses used for the memory 280. As an example, if the memory 280 is DRAM, the logical address may correspond to a DDR logical address.

[0022] Memory controller 250 can receive data (DATA) from cache 220 via bus 236. Memory controller 250 may include key generator 252. Key generator 252 can be coupled to scrambling logic 254 via bus 242. Key generator 252 can also be coupled to encryption / decryption logic 256 via bus 244. Scrambling logic 254 can be coupled to watermarking logic 260 via bus 246. Encryption / decryption logic 256 can be coupled to ECC encoder / decoder 270 via bus 248. ECC encoder / decoder 270 can be coupled to watermarking logic 260 via bus 262. Watermarking logic 260 can be coupled to memory 280 via bus 264. Although... Figure 2 The system host server 200 and memory controller 250 are shown as comprising a specific number of components arranged and coupled in a particular manner, but each component may include fewer or additional components arranged and coupled in a different manner. As an example, although... Figure 2 Not shown, but each host server 200 may include an operating system for managing specific aspects of the host server. As another example, each host server 200 may include any number of CPUs, GPUs, memory modules, or other components as needed to provide cloud computing, storage, and / or networking functions. Furthermore, functions associated with host server 200 may be assigned or combined as needed. Moreover, memory controller 250 may include additional functionality, including the ability to control multiple channels coupled to different memory media. As another example, watermarking logic 260 may be coupled to a channel controller (not shown), which may in turn be coupled to memory 280.

[0023] Continue to refer to Figure 2 In one example, the hypervisor can assign a unique logical number to each user (e.g., a guest VM). This logical number can be referred to as a user ID. CPU 210 can provide the user ID to cache 220, allowing it to be broadcast to all memory channels associated with CPU 210. Therefore, with respect to host server 200, the user ID can be provided to key generator 252, which is included as part of memory controller 250. Channels associated with memory controller 250 can generate numbers that serve as keys for users associated with the user ID. When a write operation is performed against a user, the user ID can be used to generate the user key, or a previously generated user key can be used. Thus, in one example, when memory controller 250 is notified of a new valid user ID, key generator 252 can generate a user key corresponding to the user ID and store it within memory controller 250. In this way, when a pre-existing user ID is associated with a memory operation, memory controller 250 can simply use the stored user key instead of generating a new user key.

[0024] CPU (e.g., Figure 1 CPU 112 can access both memory 116 and memory 118 using the same user ID for the computing entity. Furthermore, memory operations performed by computing entities running on CPU 112, CPU 114, or simultaneously on both CPU 112 and CPU 114 can use the same user ID, regardless of which CPU initiates the memory operation. In another example, the user ID can be localized for each CPU. Thus, in a system with two CPUs, one CPU can register user ID X with its associated memory controller, and the other CPU can register user ID Y with its associated memory controller, and a bus system (e.g., a UPI bus) connecting the two CPUs can translate between the two user IDs such that the correct user ID (X or Y) is presented to the memory controller serving the memory operation in question. A user key (e.g., a user key) can be used to encrypt data to convert data from plaintext to ciphertext. As an example, encryption / decryption logic 256 can be used to convert data from plaintext to ciphertext. When a read operation is performed on behalf of the same user, the same previously generated user key can be used for decryption. As an example, encryption / decryption logic 256 can be used to perform both encryption and decryption.

[0025] Once the user key is generated, it can be stored within memory controller 250 as part of an array (or another type of data structure). Memory controller 250 can be configured such that the user key cannot be accessed externally and will never exit memory controller 250. At some point later, the hypervisor can determine that the compute entity (e.g., a guest VM) needs to be shut down or terminated. This could be the result of the virtual machine being unloaded or otherwise terminated. The hypervisor (e.g., any of hypervisors 140, 150, or 160) can broadcast another command to memory controller 350 indicating that the user ID associated with the compute entity is no longer valid. Memory controller 250 can then clear the user key associated with the compute entity (e.g., the guest VM). Therefore, even if CPU 210 issues an instruction to read data associated with the no longer valid user ID of the compute entity, memory controller 250 will not be able to generate the correct watermark, and an exception will be thrown. Thus, because the user key associated with the invalid user ID has been cleared, even if malicious code impersonates a user with an invalid user ID, it will be unable to obtain the data.

[0026] Still referencing Figure 2 Encrypted data can be encoded using ECC codes. Examples of ECC codes include, but are not limited to, Reed-Solomon codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and Low-Density Parity-Check (LDPC) codes. As an example, the ECC encoder / decoder 270 can generate 576 bits of code, where 512 bits can be data bits and 64 bits can be ECC bits.

[0027] Continue to refer to Figure 2 After encoding the encrypted data using error-correcting codes to generate intermediate data with a first number of bits (e.g., 576 bits, where 512 bits can be data bits and 64 bits can be ECC bits), Figure 2The watermarking logic 260 can be used to apply watermarks (e.g., Message Authentication Code (MAC)) to intermediate data to generate watermarked data for storage in memory. In one example, the MAC can be a cryptographic function with a key and input. For stronger security guarantees, in one example, the function can be a pseudo-random function. The watermark can be combined with the intermediate data using any type of permutation, scrambling, or combination function that causes reversible changes. Appropriate MACs can be constructed using hash functions (e.g., HMAC (key hash for message authentication), KMAC (KECCAK message authentication code) or block ciphers (e.g., Advanced Encryption Standard (AES)-CMAC). Although such MACs have a fixed output length, they can be repeatedly applied to the input along with a counter to create any number of output bits as needed. Besides MACs, other key cryptographic functions with pseudo-random outputs can also be used. As an example, block ciphers (e.g., Advanced Encryption Standard (AES)-Cryptographic Block Chaining (CBC) or AES-CTR (Counter Block Mode)) can be used to encrypt user keys and / or addresses and counters. Furthermore, stream ciphers whose output depends on the user key and address can also be used.

[0028] Exemplary changes include, but are not limited to: performing an XOR operation between the watermark and intermediate data, rotating intermediate data based on the watermark, and other essentially reversible changes. The watermark is chosen to ensure that the position of an error is not altered after the watermark is applied. For example, a Reed-Solomon code can be understood as having symbols that must be aligned at certain points. In one example, suppose the watermark application is a rotation, and therefore some bits of that symbol are rotated to different symbols, while some of those bits remain in the original symbol. In this example, if an actual error exists in the data, it is possible that the error exists only in one symbol, and the underlying memory medium is designed to attempt to confine the fault mechanism to a single symbol. Since these bits have been moved to two separate symbols, the error can no longer be corrected. Accordingly, in this example, the memory system has been weakened by converting a correctable error into an uncorrectable one. If, conversely, no bits are allowed to go to different symbols, then the memory system is not weakened because the error can still be corrected even if the bits are moved to different positions within the same symbol. Therefore, rotations that do not cause data bits to move across symbols may be a usable efficient permutation. For example, because the XOR mechanism does not move any bits, errors remain in their original underlying locations and are therefore correctable just as before the watermark was applied.

[0029] In response to a read request from CPU 210 for data at a read address, a watermark can be applied to the retrieved watermarked data (e.g., data stored in memory 280) to generate intermediate data. As an example, watermarking logic 260 can replace the watermark with the watermarked data retrieved from the address to generate intermediate data. ECC encoder / decoder 270 can decode the intermediate data to generate decoded data; if decoding results in an uncorrectable error, the read operation can be terminated by memory controller 250; otherwise, the decoded data can be decrypted using encryption / decryption logic 256 to generate plaintext data. The plaintext data can be provided to CPU 210 via cache 220.

[0030] In summary, in the examples associated with this disclosure, the example memory controller is configured to generate authentication codes (e.g., Message Authentication Codes (MACs)), but instead of writing them into memory as additional data, it is used to reversibly alter data encoded by error-correcting codes (ECCs). In conventional systems, MACs can be stored as metadata in addition to user data and ECC. Since every bit is a valuable resource, this leads to conflicts, such as trade-offs between MAC size and ECC strength. Furthermore, because corruption of data bits is a potential attack vector, a system with reduced ECC strength is practically impossible to be more secure. One advantage of the permutation scheme is the absence of contention for metadata bits, as well as the absence of ECC weakening. Thus, in other words, the Message Authentication Code (MAC) is used as an implicit MAC rather than an explicit MAC to ensure the integrity of data stored in memory.

[0031] In such a system, matching read and write operations add and subtract entropy to the data bits with a precise balance, such that when the MAC matches (which is necessary), the MAC information is effectively lost, and the ECC system has complete integrity. Some examples of this disclosure further require that the permitted permutations must be permutations that do not move bits outside their corrected symbols, and additionally, MACs can be used in ECC for purposes such as adjusting weights due to physical differences in error rates at different bit positions.

[0032] In some examples, methods for imprinting Message Authentication Codes (MACs) into data storage are described without requiring additional metadata bits. These techniques use the MAC to permute data during write operations and the same MAC is used to reverse the change during read operations. The data is reversibly altered after the error correction code is computed. If the user performing the write operation is different from the user performing the read operation, their keys will be different from each other, therefore their MACs will not match, the reversible change will not be reversed, and ECC will fail. In practice, in such examples, the MAC is stored as a "watermark" that does not require additional bits, and the ECC mechanism is borrowed for MAC integrity checking.

[0033] If the MAC used by the write party differs from that used by the read party, the reversibly modified data will mismatch, and the data will not be restored to its original value. The reversible modification operation is performed across all bits, effectively generating random codewords, so ECC will report the mismatch as an uncorrectable error. In these examples, ECC integrity must be strong enough to support security requirements, as the system would be insecure if other error causes went undetected. Advantageously, using MAC to reversibly modify data eliminates storage overhead. In effect, the MAC entropy is orthogonally imprinted onto all data bits, but if the same MAC is used by the read party, this imprint is completely removed, so the data can be corrected with full strength and integrity unaffected. The reversible modification method is needed so that if an error does occur in the data during storage, the error remains correctable after the reversible modification is reversed. In some examples, this is achieved by using each bit of the MAC to guide a very localized transformation that keeps all bits within the same correction sign.

[0034] In a DRAM-based memory system, assuming 64 bits of metadata per 512 bits of data, the Reed-Solomon error correction code can be configured to correct only one 16-bit symbol. This leaves approximately 42 bits of integrity checking in the ECC algorithm. Alternatively, for the 64 bits of metadata per 512 bits of data, the Reed-Solomon error correction code can be configured to correct two 16-bit symbols. This can slightly improve reliability, but integrity may drop to approximately 24 bits. In different memory systems, assuming 128 bits of metadata per 512 bits of data, the Reed-Solomon error correction code can be configured to correct either one 64-bit symbol or two 32-bit symbols. Assuming each chip provides 64 bits, if the 64 bits of symbols can be corrected, this can provide "chip kill" fault protection. Therefore, even if the chip completely fails, the data can still be recreated. While Reed-Solomon is a good choice for DRAM-based memory systems and offers good false positive rejection, other ECC techniques with strong false positive rejection capabilities may also be compatible. The key requirement is that reversible alterations should not weaken the error correction scheme in the presence of regular physical errors. For example, if the memory system uses flash memory, the application of watermarks may need to be designed so as not to interfere with error repair algorithms across multiple levels of cells.

[0035] Figure 3 A diagram illustrating a data path 300 for ensuring data integrity using watermarking, based on an example, is shown. In this example, operations on data and other information (e.g., user keys and addresses) can be performed using... Figure 2The memory controller 250 is used to execute this. Data path 300 assumes a data size of 512 bits. Furthermore, it is assumed that the user cannot change their identifier or interact with the memory controller as another user. In this example, it is further assumed that the user (e.g., a computing entity) can access the memory through the following functions: (1) Write (address A, data D) (writing data D to address A, where D is a fixed-length data block (512 bits in this example)); (2) Read (address A) (reading the data stored at address A); and (3) Corrupt (address A) (simulating a row-hammer-like attack, where the user can introduce random corruption into the data stored at address A). If the user performs a write (A, D) and then a read (A), there may be read, write, and corruption operations performed by other (potentially malicious) users in the system, affecting address A. Moreover, it is assumed that the user cannot directly access the data written to the medium by the memory controller, but can only access the memory via read, write, and corruption functions. Furthermore, in this example, the user key is never derived from the memory controller 250. Finally, in this example, it is assumed that the intermediate values ​​calculated by the memory controller will not leak (neither through side-channel attacks nor directly). If a corrupted operation occurs between a write and a read, the memory controller 250 ensures that a read error is thrown indicating corruption of the data.

[0036] Table 1 illustrates data movement and other operations as part of a storage sequence that uses memory controller 250 to store data.

[0037]

[0038] Table 1

[0039] Table 2 shows the usage Figure 2 The memory controller 250 from Figure 2 The memory 280 retrieves a portion of the loaded sequence of data for data movement and other operations.

[0040]

[0041] Table 2

[0042] Figure 4A diagram is shown illustrating another data path 400 for ensuring data integrity by using watermarking, according to an example. Data path 400 assumes a data size of 512 bits. Furthermore, it is assumed that a user cannot change their identifier and interact with the memory controller as another user. In this example, it is further assumed that a user (e.g., a computing entity) can access memory via: (1) write (address A, data D) (writing data D to address A, where D is a fixed-length data block (512 bits in this example)); (2) read (address A) (reading the data stored at address A); and (3) corrupt (address A): (simulating a hammer-like attack where a user can introduce random corruption into the data stored at address A). If a user performs a write (A, D) and then a read (A), there could be read, write, and corrupt operations performed by other (potentially malicious) users in the system, affecting address A. Furthermore, it is assumed that the user cannot directly access the data written to the medium by the memory controller, but can only access the memory via read, write, and corrupt functions. Additionally, in this example, the user key is never derived from the memory controller 250. Finally, in this example, it is assumed that the intermediate values ​​calculated by the memory controller will not be leaked (neither through side-channel attacks nor directly). If a corrupted operation occurs between a write and a read, the memory controller 250 ensures that a read error is thrown, signaling data corruption.

[0043] Table 3 shows the usage Figure 2 The memory controller 250 stores a portion of the stored data sequence for data movement and other operations.

[0044]

[0045] Table 3

[0046] Table 4 shows the usage Figure 2 The memory controller 250 from Figure 2 The memory 280 retrieves a portion of the loaded sequence of data for data movement and other operations.

[0047]

[0048]

[0049] Table 4

[0050] Although Tables 1, 2, 3, and 4 illustrate the use of specific cryptographic functions as part of the scrambling operation for generating message authentication codes, other techniques described above can be used alternatively. As examples, hash functions (e.g., HMAC (key hash for message authentication), KMAC (KECCAK message authentication code) or block ciphers (e.g., Advanced Encryption Standard (AES)-CMAC) can be used. Furthermore, as mentioned earlier, other key cryptographic functions with pseudo-random outputs besides MAC can also be used. As examples, block ciphers (e.g., Advanced Encryption Standard (AES)-Cryptographic Block Linking (CBC) or AES-CTR (Counter Block Mode)) can be used to encrypt user keys and / or addresses and counters. Although references... Figure 3 and Figure 4 The described example portrays the XOR operation as part of the data path, but other permutations can also be used. As examples, other permutations include rotating bits or dividing certain bits between groups and using these bits to preserve the bits in the same order as before or to reverse the order of the bits. Generally, any reversible operation such as XOR can be used for permutations.

[0051] Figure 5A system environment 500 for implementing a system and method according to an example is shown. In this example, system environment 500 may correspond to a portion of a data center. As an example, the data center may include multiple rack clusters, including platform hardware such as server nodes, storage nodes, network nodes, or other types of nodes. Server nodes may be connected to switches to form a network. The network enables connectivity between each possible combination of switches. System environment 500 may include server 1 510 and server N 530. System environment 500 may also include data center-related functions 560, including deployment / monitoring 570, directory / identification service 572, load balancing 574, data center controller 576 (e.g., software-defined networking (SDN) controller and other controllers), and router / switch 578. Server 1 510 may include a host processor 511, a host hypervisor 512, memory 513, (multiple) storage interface controllers (SICs) 514, cooling 515 (e.g., cooling fans or other cooling devices), (multiple) network interface controllers (NICs) 516, and storage disks 517 and 518. Server N530 may include a host processor 531, a host hypervisor 532, memory 533, (multiple) storage interface controllers (SICs) 534, cooling 535 (e.g., cooling fans or other cooling devices), (multiple) network interface controllers (NICs) 536, and storage disks 537 and 538. Server 1 510 may be configured to support virtual machines, including VM1 519, VM2 520, and VMN 521. The virtual machines may also be configured to support applications, such as APP1 522, APP2 523, and APPN 524. Server N 530 may be configured to support virtual machines, including VM1 539, VM2 540, and VMN 541. The virtual machines may also be configured to support applications (APPs), such as Application 1 542, Application 2 543, and Application N 544.

[0052] Continue to refer to Figure 5 In one example, system environment 500 can enable multiple tenants using a Virtual Extensible Local Area Network (VXLAN) architecture. Each virtual machine (VM) can be allowed to communicate with VMs within the same VXLAN segment. Each VXLAN segment can be identified by a VXLAN Network Identifier (VNI). Although Figure 5 System environment 500 is shown as including a specific number of components arranged and coupled in a particular manner, but it may include fewer or additional components arranged and coupled in different manners. Furthermore, functions associated with system environment 500 can be assigned or combined as needed. Moreover, although... Figure 5VMs are shown, but other types of computing entities, such as containers, microVMs, microservices, and single kernels for serverless functionality, can also be used in a similar way.

[0053] Figure 6 A flowchart 600 is shown according to an example method. In this example, the method can be executed in a system including a processor and memory. As an example, the method can be used as... Figure 2 Part of the host server 200 is executed. Figure 2 As part of the host server Figure 1 This is part of the system environment 100. Step 610 may include receiving data for storage at an address in memory. As an example, as part of step 610, the memory controller (e.g., Figure 2 The CPU 250 can receive data from the cache 220 for storing addresses (ADDR) provided by the CPU 210. Furthermore, in one example, the data could be about... Figure 3 And the 512 bits of plaintext data described in Table 1.

[0054] Step 620 may include, after encoding the data using error-correcting codes to generate intermediate data having a first number of bits, reversibly altering the intermediate data using a watermark to generate watermarked data for storage in memory, wherein the watermark is generated by applying a cryptographic function to a user key and an address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits. As an example, a memory controller (e.g., Figure 2 The memory controller 250 can perform actions such as regarding Figure 2 and Figure 3 This step is described. In this example, after encoding the data using error-correcting codes to generate intermediate data with a first number of bits (e.g., 576 bits, where 512 bits can be data bits and 64 bits can be ECC bits), Figure 2 The watermarking logic 260 can be used to reversibly modify intermediate data using a watermark (e.g., a MAC) to generate watermarked data for storage in memory. Examples of reversible modifications include, but are not limited to: performing an XOR operation between the watermark and intermediate data, rotating intermediate data based on the watermark, and other inherently reversible modifications. Additional examples of MACs and other watermarks are available in [reference]. Figure 2 As described earlier. Although Figure 6 Flowchart 600 is described as including a specific number of steps executed in a particular order, but the method may include additional or fewer steps executed in a different order. Users may include a hypervisor, virtual machine (VM), microVM, microservice, or a single kernel for serverless functionality.

[0055] Figure 7 Another flowchart 700 is shown, illustrating a method according to an example. In this example, the method can be executed in a host server including memory and a processor. As an example, the method can be used as... Figure 2 Part of the host server 200 is executed. Figure 2 The host server 200 as Figure 1 This is part of the system environment 100. Step 710 may include receiving plaintext data from one of a plurality of computing entities associated with the host server for use at an address in memory. As an example, as part of step 710, the memory controller (e.g., Figure 2 CPU 250 can receive plaintext data from cache 220 for storing addresses (ADDR) provided by CPU 210. Furthermore, in one example, the plaintext data could be about... Figure 3 And the 512 bits of plaintext data described in Table 1. The computing entity may include a hypervisor, virtual machine (VM), microVM, microservice, or a single kernel for serverless functionality.

[0056] Step 720 may include encrypting plaintext data using at least a user key associated with the computing entity to generate encrypted data. As an example, as part of step 720, the memory controller (e.g., Figure 2 250) can be as previously mentioned Figure 2 The plaintext data is encrypted as described. Furthermore, in one example, the encrypted data could be previously mentioned... Figure 3 And the 512 bits of encrypted data described in Table 1.

[0057] Step 730 may include, after encoding the encrypted data using error-correcting codes to generate intermediate data having a first number of bits, reversibly modifying the intermediate data using a message authentication code to generate watermarked data for storage in memory, wherein the message authentication code is generated by applying a cryptographic function to a user key and an address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits. As an example, a memory controller (e.g., Figure 2 The memory controller 250 can perform actions such as regarding Figure 2 and Figure 3 The described step. In this example, after encoding the encrypted data using error-correcting codes to generate intermediate data with a first number of bits (e.g., 576 bits, where 512 bits can be data bits and 64 bits can be ECC bits), Figure 2The watermarking logic 260 can be used to reversibly modify intermediate data by a MAC to generate watermarked data for storage in memory. Examples of reversible modifications include, but are not limited to, performing an XOR operation between the MAC and the intermediate data, rotating the intermediate data based on the MAC, and other inherently reversible modifications. Additional examples of MACs and other watermarks can be found in [reference]. Figure 2 As described above. Despite Figure 7 Flowchart 700 is described as including a specific number of steps performed in a particular order, but the method may include additional steps performed in a different order.

[0058] In summary, this disclosure relates to a method in a system including a processor and a memory. The method may include: receiving data for storage at an address in the memory. The method may further include: after encoding the data using an error-correcting code to generate intermediate data having a first number of bits, reversibly modifying the intermediate data using a watermark to generate watermarked data for storage in the memory, wherein the watermark is generated by applying a cryptographic function to a user key and an address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits.

[0059] The system may also include a memory controller, and the method may further include: the memory controller generating a user key based on a user identifier associated with a user. The system may also include a hypervisor, and the method may further include: the hypervisor assigning a user identifier to a user. A user may include a hypervisor, a virtual machine (VM), a microVM, a microservice, or a single kernel for serverless functionality.

[0060] The intermediate data may also include metadata, and the method may also include: reversibly altering the intermediate data and metadata using a watermark.

[0061] The method may further include: reading watermarked data from memory at an address specified in memory in response to a read operation; recalculating a previously applied watermark on intermediate data by processing the watermarked data using a user key; and removing the previously applied watermark to generate second intermediate data. The method may further include: decoding the second intermediate data using error-correcting codes to generate decoded data; and terminating the read operation if decoding results in an uncorrectable error.

[0062] In another aspect, this disclosure relates to a system including a host server that includes a memory controller coupled to a memory and a processor. The system may also include a management program associated with the host server, configured to manage a plurality of computing entities. The memory controller may be configured to: (1) receive data from one of the plurality of computing entities for storage at an address in memory, and (2) after encoding the data with error-correcting codes to generate intermediate data having a first number of bits, reversibly modify the intermediate data using a watermark to generate watermarked data for storage in memory, wherein the watermark is generated by applying a cryptographic function to the address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits.

[0063] The hypervisor can also be configured to assign user identifiers to compute entities, and the memory controller can also be configured to generate user keys based on the user identifiers associated with the compute entities. Compute entities can include a hypervisor, a virtual machine (VM), a microVM, a microservice, or a single kernel for serverless functionality. Intermediate data can also include metadata, and the memory controller can also be configured to reversibly modify the metadata using watermarks.

[0064] The memory controller can also be configured to: read watermarked data from memory at a specified address in response to a read request from a computing entity; recalculate a previously applied watermark on intermediate data by processing the watermarked data using the address; and remove the previously applied watermark to generate second intermediate data. The memory controller can also be configured to: decode the second intermediate data using error-correcting codes to generate decoded data, and terminate the read request if decoding results in an uncorrectable error.

[0065] In another aspect, this disclosure relates to a method performed in a host server including a processor and memory. The method may include: receiving plaintext data from one of a plurality of computing entities associated with the host server for storage at an address in memory. The method may further include: encrypting the plaintext data using at least a user key associated with the computing entity to generate encrypted data. The method may further include: after encoding the encrypted data using an error-correcting code to generate intermediate data having a first number of bits, reversibly modifying the intermediate data using a message authentication code to generate watermarked data for storage in memory, wherein the message authentication code is generated by applying a cryptographic function to the user key and the address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits.

[0066] The system may also include a memory controller, and the method may further include: the memory controller generating a user key based on a user identifier associated with a computing entity. The method may also include a hypervisor associated with a host server that assigns the user identifier to the computing entity. The computing entity may include a hypervisor, a virtual machine (VM), a microVM, a microservice, or a single kernel for serverless functionality. The intermediate data may also include metadata, and the method may further include reversibly altering the intermediate data and metadata using a watermark.

[0067] The method may further include: in response to a read request from a computing entity at a specified address, reading watermarked data from memory at the address; recalculating a previously applied watermark on intermediate data by processing the watermarked data using a user key; and removing the previously applied watermark to generate second intermediate data. The method may further include: decoding the second intermediate data using error-correcting codes to generate decoded data; and terminating the read request if decoding results in an uncorrectable error, otherwise decrypting the decoded data to generate second plaintext data.

[0068] It should be understood that the methods, modules, and components described herein are merely exemplary. Alternatively or additionally, the functionality described herein may be performed at least in part by one or more hardware logic components. For example, but not limited to, illustrative types of hardware logic components that may be used include Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), Systems-on-Chip (SOCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract but still explicit sense, any arrangement of components that implement the same functionality is effectively “associated” to achieve the desired functionality. Therefore, any two components combined herein to achieve a particular function can be considered “associated” with each other to achieve the desired functionality, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered “operably connected” or “coupled” with each other to achieve the desired functionality.

[0069] The functionality associated with some of the examples described in this disclosure may also include instructions stored in non-transitory media. As used herein, the term "non-transitory media" refers to any medium that stores data and / or instructions that cause the machine to operate in a particular manner. Exemplary non-transitory media include non-volatile media and / or volatile media. Non-volatile media include, for example, hard disks, solid-state drives, magnetic disks or tapes, optical disks or tapes, flash memory, EPROM, NVRAM, PRAM, or other such media, or networking versions of such media. Volatile media include, for example, dynamic memory, such as DRAM, SRAM, cache, or other such media. Non-transitory media are distinct from transmission media but may be used in conjunction with transmission media. Transmission media are used to transmit data and / or instructions to or from the machine. Exemplary transmission media include coaxial cables, fiber optic cables, copper wires, and wireless media, such as radio waves.

[0070] Furthermore, those skilled in the art will recognize that the boundaries between the functions of the above operations are merely illustrative. The functions of multiple operations can be combined into a single operation, and / or the functions of a single operation can be distributed across additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be varied in various other embodiments.

[0071] Although specific examples are provided in this disclosure, various modifications and changes may be made without departing from the scope of this disclosure as set forth in the claims. Therefore, the specification and drawings are to be regarded as illustrative rather than restrictive, and all such modifications are to be included within the scope of this disclosure. Any benefits, advantages, or solutions to problems described herein with respect to certain examples are not intended to be construed as key, essential, or fundamental features or elements of any or all claims.

[0072] Furthermore, the term "a" or "an" as used herein is defined as one or more. Additionally, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that the introduction of another claim element by the indefinite article "a" or "an" limits any particular claim containing that introduced claim element to an invention containing only one such element, even if the introductory phrase "one or more" or "at least one" is included along with the indefinite article, such as "a" or "an," in the same claim. The same applies to the use of definite articles.

[0073] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not intended to indicate the time or other priority of these elements.

Claims

1. A method in a system including a processor and memory, the method comprising: Receive data at the address to be stored in the memory; After encoding the data using error-correcting codes to generate intermediate data having a first number of bits, the intermediate data is reversibly modified using a watermark to generate watermarked data for storage in the memory, wherein the watermark is generated by applying a cryptographic function to a user key and the address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits, and wherein the method further includes supplying the user key by a memory controller based on a user identifier associated with the user; as well as In response to a read operation specifying the address in the memory, Read the watermarked data from the memory. The watermark previously applied to the intermediate data is recalculated by processing the watermarked data using the user key. Remove the previously applied watermark to generate the second intermediate data. The error correction code is used to decode the second intermediate data to generate decoded data, and If the decoding results in an uncorrectable error, the read operation is terminated.

2. The method according to claim 1, wherein the error correction code includes Reed-Solomon error correction code.

3. The method of claim 1, wherein the system further includes a management program, and wherein the method further includes: The management program assigns the user identifier to the user.

4. The method of claim 1, wherein the user includes one of a hypervisor, a virtual machine (VM), a microVM, a microservice, or a single kernel for serverless functionality.

5. The method of claim 1, wherein the intermediate data further includes metadata, and the method further includes: The metadata can be reversibly altered using the watermark.

6. The method of claim 1, wherein the watermark includes a message authentication code (MAC), and wherein the MAC is used as an implicit MAC.

7. The method according to claim 1, further comprising: If the decoding results in a correctable error, the decoded data is corrected to generate corrected data.

8. A system comprising: A host server, including a memory controller coupled to a memory and a processor; as well as A management program, associated with the host server, is configured to manage multiple computing entities, wherein the memory controller is configured to: Data is received from one of the plurality of computing entities for use at an address in the memory. User keys are supplied based on the user identifier associated with the user. After encoding the data using error-correcting codes to generate intermediate data having a first number of bits, the intermediate data is reversibly modified using a watermark to generate watermarked data for storage in the memory, wherein the watermark is generated by applying a cryptographic function to the address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits; and In response to a read operation specifying the address in the memory, Read the watermarked data from the memory. The watermark previously applied to the intermediate data is recalculated by processing the watermarked data using the user key. Remove the previously applied watermark to generate the second intermediate data. The error correction code is used to decode the second intermediate data to generate decoded data, and If the decoding results in an uncorrectable error, the read operation is terminated.

9. The system of claim 8, wherein the memory controller is further configured not to export the user key from the system.

10. The system of claim 8, wherein the computing entity comprises one of the hypervisor, virtual machine (VM), microVM, microservice, or a single kernel for serverless functionality.

11. The system of claim 8, wherein the intermediate data further includes metadata, and wherein the memory controller is further configured to reversibly change the metadata using the watermark.

12. The system of claim 8, wherein the watermark includes a message authentication code (MAC), and wherein the MAC is used as an implicit MAC.

13. The system of claim 8, wherein the memory controller is further configured to: if the decoding results in a correctable error, correct the decoded data to generate corrected data.

14. A method executed in a host server including a processor and memory, the method comprising: Plaintext data is received from one of a plurality of computing entities associated with the host server for use at an address in the memory; The plaintext data is encrypted using at least the user key associated with the computing entity to generate encrypted data; After encoding the encrypted data using error-correcting codes to generate intermediate data having a first number of bits, the intermediate data is reversibly modified using message authentication codes to generate watermarked data for storage in the memory, wherein the message authentication codes are generated by applying a cryptographic function to the user key and the address, and wherein the watermarked data has a second number of bits, the second number of bits being equal to the first number of bits, wherein the host server further includes a memory controller, and the method further includes: the memory controller supplying the user key based on a user identifier associated with the computing entity; as well as In response to a read operation specifying the address in the memory, Read the watermarked data from the memory. The watermark previously applied to the intermediate data is recalculated by processing the watermarked data using the user key. Remove the previously applied watermark to generate the second intermediate data. The error correction code is used to decode the second intermediate data to generate decoded data, and If the decoding results in an uncorrectable error, the read operation is terminated.

15. The method of claim 14, wherein the error correction code comprises a Reed-Solomon error correction code.

16. The method of claim 14, further comprising: The management program associated with the host server assigns the user identifier to the computing entity.

17. The method of claim 14, wherein the computing entity comprises a hypervisor, a virtual machine (VM), a microVM, a microservice, or a single kernel for serverless functionality.

18. The method of claim 14, wherein the intermediate data further includes metadata, and the method further includes: The metadata can be reversibly altered using the watermark.

19. The method of claim 14, wherein the watermark includes a message authentication code (MAC), and wherein the MAC is used as an implicit MAC.

20. The method of claim 14, further comprising: If the decoding results in a correctable error, the decoded data is corrected to generate corrected data.

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