Organic light emitting display device

Abstract

Disclosed is an organic light emitting display device. The device includes: a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes: an organic light emitting element for emitting light based on a driving current; a driving transistor for controlling the driving current, wherein the driving transistor includes a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; a first transistor for diode-connecting the second node and the third node to each other; a second transistor for applying a data voltage to the first node; a third transistor for applying a high potential driving voltage to the first node; a fourth transistor for forming a current path between the driving transistor and the organic light emitting element; a fifth transistor for selectively applying a stress voltage and an initialization voltage to the third node; and a sixth transistor for applying a reset voltage to a fourth node that is an anode electrode of the organic light emitting element.

Description

Technical Field

[0001] This disclosure relates to organic light-emitting display devices, and more specifically, to organic light-emitting display devices in which organic light-emitting elements emit light based on light-emitting signals. Background Technology

[0002] Organic light-emitting elements (OLEDs), which are self-emissive components, include an anode electrode and a cathode electrode, as well as an organic compound layer formed between them. The organic compound layer consists of a hole transport layer (HTL), an emissive layer (EML), and an electron transport layer (ETL). When a driving voltage is applied to the anode and cathode electrodes, holes passing through the HTL and electrons passing through the ETL move to the EML and combine with each other to form excitons. Therefore, the EML emits visible light. Active-matrix organic light-emitting display devices, including self-emissive organic light-emitting elements (OLEDs), are widely used due to their fast response speed, high luminous efficiency, brightness, and wide viewing angle.

[0003] In an organic light-emitting display device, pixels, each including an organic light-emitting element, are arranged in a matrix, and the brightness level of the pixels is adjusted based on the grayscale level of video data. Each pixel includes: an organic light-emitting element, a driving transistor that controls the driving current flowing through the organic light-emitting element based on a gate-source voltage, and at least one switching transistor that programs the gate-source voltage of the driving transistor. The pixel circuit, including the organic light-emitting element, the driving transistor, and at least one switching transistor, operates based on a scan signal and a light-emitting signal.

[0004] Therefore, the pixel circuit provides driving current to the organic light-emitting element based on the scanning signal and the emission signal. At this point, charge sharing occurs at some nodes of the pixel circuit. Consequently, when the organic light-emitting element emits light, black defects may occur, or the brightness level of the display panel may become uneven. Summary of the Invention

[0005] The applicant of this disclosure has invented an organic light-emitting display device in which the pixel circuit has been redesigned to eliminate the aforementioned problems.

[0006] Therefore, the purpose of this disclosure is to provide an organic light-emitting display device that can eliminate blackout phenomena.

[0007] Another objective of this disclosure is to provide an organic light-emitting display device capable of uniformizing the brightness levels of pixels.

[0008] The purpose of this disclosure is not limited to the purposes mentioned above. Other purposes and advantages not mentioned in this disclosure may be understood based on the following description and may be more clearly understood based on embodiments of this disclosure. Furthermore, it will be readily understood that the purposes and advantages of this disclosure can be achieved using the means set forth in the claims and combinations thereof.

[0009] One aspect of this disclosure provides an organic light-emitting display device, comprising: a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes: an organic light-emitting element for emitting light based on a driving current; a driving transistor for controlling the driving current, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; a first transistor for connecting the second node and the third node to each other in a diode manner; a second transistor for applying a data voltage to the first node; a third transistor for applying a high-potential driving voltage VDD to the first node; a fourth transistor for forming a current path between the driving transistor and the organic light-emitting element; a fifth transistor for selectively applying a stress voltage Vobs and an initialization voltage Vini to the third node; and a sixth transistor for applying a reset voltage VAR to the fourth node, which serves as the anode electrode of the organic light-emitting element.

[0010] One aspect of this disclosure provides an organic light-emitting display device, comprising: a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes: an organic light-emitting element; a driving transistor for providing a driving current to the organic light-emitting element, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; and a reset transistor for applying a reset voltage to a fourth node serving as an anode electrode of the organic light-emitting element, wherein each of the plurality of pixels operates during a stress period, an initialization period, a sampling period, a reset period, and a light-emitting period, wherein during the stress period, a bias stress is applied to the driving transistor; wherein during the initialization period, a second node or a third node is initialized based on an initialization voltage; wherein during the sampling period, the second node is charged to a voltage corresponding to the sum of a data voltage and a threshold voltage of the driving transistor; wherein during the reset period, the reset transistor resets the fourth node based on the reset voltage; and wherein during the light-emitting period, a driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light.

[0011] One aspect of this disclosure provides an organic light-emitting display device, comprising: a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes: an organic light-emitting element; a driving transistor for providing a driving current to the organic light-emitting element, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; and a reset transistor for applying a reset voltage to a fourth node serving as an anode electrode of the organic light-emitting element during a reset period in a refresh frame, such that the third node and the fourth node are at the same potential equal to the reset voltage, wherein in the refresh frame, a data voltage is programmed to the pixel, the reset period is a period in the refresh frame during which the voltage level of the anode electrode of the organic light-emitting element is fixed at the reset voltage for the remaining period of the refresh frame excluding the light-emitting period, and during the light-emitting period, a driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light.

[0012] Specific details of other embodiments are included in the detailed description and accompanying drawings.

[0013] According to this disclosure, the anode electrode of the organic light-emitting element can be maintained at a constant voltage level, thereby minimizing brightness variations in the organic light-emitting display device and thus improving its image quality.

[0014] The effects of this disclosure are not limited to those described above, and those skilled in the art will clearly understand other effects not mentioned based on the following description. Attached Figure Description

[0015] Figure 1 This is a block diagram of an organic light-emitting display device according to one embodiment of the present disclosure.

[0016] Figure 2 This is a circuit diagram showing the pixels of an organic light-emitting display device according to one embodiment of the present disclosure.

[0017] Figure 3 This is a waveform diagram showing each of the light emission signal and the scan signal of an organic light-emitting display device according to one embodiment of the present disclosure during a refresh frame.

[0018] Figure 4 This is a waveform diagram showing each of the light emission signal and the scan signal of an organic light-emitting display device according to one embodiment of the present disclosure during a reset frame.

[0019] Figure 5A This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during a bias stress period.

[0020] Figure 5BThis is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during an initial time period.

[0021] Figure 5C This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during a sampling period.

[0022] Figure 5D This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during the anode reset period.

[0023] Figure 5E This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during the light-emitting period.

[0024] Figures 6A to 6C This is a diagram illustrating an improvement of an organic light-emitting display device according to one embodiment of the present disclosure relative to a comparative example. Detailed Implementation

[0025] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will be discussed later in the appendix. Figure 1 The embodiments described in detail below will become apparent. However, this disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Therefore, these embodiments have been described only to complete this disclosure and to fully inform those skilled in the art of the subject of this disclosure of its scope, and this disclosure is limited only by the scope of the claims.

[0026] The shapes, dimensions, scales, angles, numbers, etc., disclosed in the accompanying drawings used to describe embodiments of this disclosure are exemplary, and this disclosure is not limited thereto. The same reference numerals denote the same elements herein. Furthermore, for the sake of simplicity, descriptions and details of well-known steps and elements have been omitted. In addition, numerous specific details are set forth in the following detailed description of this disclosure to provide a thorough understanding of it. However, it should be understood that this disclosure can be practiced without these specific details. In other instances, well-known methods, processes, components, and circuits have not been described in detail to avoid unnecessarily obscuring aspects of this disclosure.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used herein, unless the context otherwise indicates, the singular constructs “a” and “an” are intended to include the plural constructs. It will also be understood that the terms “comprising,” “having,” and “including” as used in the specification specify the presence of the stated features, integers, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and / or portions thereof. As used herein, the term “and / or” includes any and all combinations of one or more associated listed items. Expressions such as “at least one” preceding a list of elements may modify the entire list of elements and may not modify individual elements in that list. Errors or tolerances may occur when interpreting numerical values, even if they are not explicitly described.

[0028] Furthermore, it will be understood that when a first element or layer is referred to as existing “on” a second element or layer, the first element may be directly disposed on the second element or indirectly disposed on the second element, wherein a third element or layer is disposed between the first and second elements or layers. It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, the element or layer may be directly on the other element or layer, directly connected to or directly coupled to the other element or layer, or one or more intermediate elements or layers may exist. Furthermore, it will be understood that when an element or layer is referred to as being “between” two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may exist.

[0029] Furthermore, as used herein, when a layer, membrane, region, plate, etc., is disposed "on" or "on top" of another layer, membrane, region, plate, etc., the former can directly contact the latter, or another layer, membrane, region, plate, etc., can be disposed between the former and the latter. As used herein, when a layer, membrane, region, plate, etc., is directly disposed "on" or "on top" of another layer, membrane, region, plate, etc., the former directly contacts the latter, and another layer, membrane, region, plate, etc., is not disposed between the former and the latter. Additionally, as used herein, when a layer, membrane, region, plate, etc., is disposed "below" or "below" another layer, membrane, region, plate, etc., the former can directly contact the latter, or another layer, membrane, region, plate, etc., can be disposed between the former and the latter. As used herein, when a layer, membrane, region, plate, etc., is directly disposed "below" or "below" another layer, membrane, region, plate, etc., the former directly contacts the latter, and another layer, membrane, region, plate, etc., is not disposed between the former and the latter.

[0030] In descriptions of temporal relationships, such as "after," "following," or "before," another event may occur between the two events unless it is indicated that it is "directly after," "directly following," or "directly before."

[0031] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or part described below may be referred to as a second element, component, region, layer, or part.

[0032] Features of the various embodiments of this disclosure can be combined with each other in part or in whole, and can be technically related to or operable on each other. Embodiments can be implemented independently of each other, or can be implemented together in an associated relationship.

[0033] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms and are intended to describe inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. These terms can be used to prevent unauthorized use by infringers to design around the provided precise or absolute figures, in order to aid in understanding this disclosure.

[0034] Unless otherwise defined, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0035] The contents of this disclosure will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 This is a block diagram of an organic light-emitting display device according to one embodiment of the present disclosure.

[0037] Reference Figure 1 An organic light-emitting display device according to one embodiment of the present disclosure includes a display panel 100, a timing control circuit 200, a data driver 300, and gate drivers 401 and 402.

[0038] The display panel 100 includes a display area A / A for displaying images and a non-display area N / A located outside the display area A / A. Various signal lines and gate drivers 401 and 402 are disposed in the non-display area.

[0039] Multiple pixels P are disposed in a display area A / A to display an image. Additionally, in the display area A / A, n gate lines GL1 to GLn extending along a first direction and m data lines DL1 to DLm extending in a direction different from the first direction are arranged. The multiple pixels P are electrically connected to the n gate lines GL1 to GLn and the m data lines DL1 to DLm. Therefore, a gate voltage is applied to each pixel P through each of the gate lines GL1 to GLn, and a data voltage is applied to each pixel P through each of the data lines DL1 to DLm. Furthermore, each pixel P presents a grayscale level based on the gate voltage and the data voltage. Finally, based on the grayscale level displayed from each pixel P, an image is displayed from the display area A / A.

[0040] In the non-display area N / A, gate drivers 401 and 402 and various signal lines are arranged to transmit signals for controlling the operation of pixels P arranged in the display area A / A.

[0041] The timing control circuit 200 transmits the input image signal RGB received from the host system to the data driver 300.

[0042] The timing control circuit 200 generates control signals GCS and DCS based on timing signals received along with the image data RGB, such as the clock signal DCLK, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the data enable signal DE, to control the operation timing of the gate drivers 401 and 402 and the data driver 300. In this context, the horizontal synchronization signal Hsync indicates the time taken for a horizontal line to be drawn on the display screen, the vertical synchronization signal Vsync indicates the time taken for a frame to be drawn on the display screen, and the data enable signal DE indicates the time period during which data voltage is supplied to the pixel P defined in the display panel 100.

[0043] In other words, the timing control circuit 200 receives the timing signal, outputs the gate control signal GCS to the gate drivers 401 and 402, and outputs the data control signal DCS to the data driver 300.

[0044] The data driver 300 receives the data control signal DCS and outputs the data voltage to the data lines DL1 to DLm.

[0045] Specifically, the data driver 300 generates a sampling signal based on the data control signal DCS, latches the image data RGB based on the sampling signal and converts the image data into a data voltage, and then provides the data voltage to the data lines DL1 to DLm in response to the source output enable (SOE) signal.

[0046] The data driver 300 can be connected to the bonding pads of the display panel 100 using a COG (Chip-on-Glass) solution, or it can be directly mounted on the display panel 100. In some cases, the data driver can be integrated into the display panel 100. Alternatively, the data driver 300 can be mounted using a COF (Chip-on-Film) solution.

[0047] Each of the gate drivers 401 and 402 can sequentially provide a scan signal, a light emission signal, and a reset signal corresponding to the gate voltage to the gate lines GL1 to GLn based on the gate control signal GCS.

[0048] Typically, gate drivers 401 and 402 can be formed independently of the display panel 100 and can be electrically connected to the display panel in various ways. However, according to one embodiment of the present disclosure, the gate drivers 401 and 402 of the organic light-emitting display device can be formed in the form of a thin film pattern when manufacturing the substrate of the display panel 100, and can then be embedded in the non-display area N / A in a GIP (gate in panel) scheme.

[0049] In addition, gate drivers 401 and 402 may include a first gate driver 401 and a second gate driver 402 respectively disposed on two opposite sides of the display panel 100.

[0050] Specifically, the first gate driver 401 provides scan signals and reset signals to a plurality of pixels P. Therefore, the first gate driver 401 may include a plurality of scan driver stages and a plurality of reset driver stages. Furthermore, the plurality of scan driver stages provide scan signals to the plurality of pixels P, while the plurality of reset driver stages provide reset signals to the plurality of pixels P.

[0051] Furthermore, the second gate driver 402 provides scan signals and light emission signals to the plurality of pixels P. Therefore, the second gate driver 402 may include a plurality of scan driving stages and a plurality of light emission driving stages. The plurality of scan driving stages provide scan signals to the plurality of pixels P, while the plurality of light emission driving stages provide light emission signals to the plurality of pixels P.

[0052] The configuration and driving scheme for multiple pixels P will be described in detail below.

[0053] Each switching element constituting each of the plurality of pixels P can be implemented as a transistor having an n-type or p-type MOSFET structure. Although an example of a switching element being implemented as an n-type transistor is shown below, this disclosure is not limited thereto.

[0054] Furthermore, a transistor is a three-electrode device consisting of a gate electrode, a source electrode, and a drain electrode. The source electrode provides charge carriers to the transistor. In a transistor, charge carriers can flow out from the source electrode. The drain electrode is the electrode through which charge carriers leave the transistor. That is, in a MOSFET, charge carriers flow from the source electrode to the drain electrode. In an n-type MOSFET (NMOS), the charge carriers are electrons; therefore, the voltage at the source electrode is lower than the voltage at the drain electrode, allowing electrons to flow from the source electrode to the drain electrode. In an n-type MOSFET, electrons flow from the source electrode to the drain electrode, causing current to flow from the drain electrode to the source electrode. In a p-type MOSFET (PMOS), the charge carriers are holes; therefore, the voltage at the source electrode is higher than the voltage at the drain electrode, allowing holes to flow from the source electrode to the drain electrode. In a p-type MOSFET, current flows from the source electrode to the drain electrode because holes flow from the source electrode to the drain electrode. It should be noted that the source and drain electrodes of a MOSFET are not fixed. For example, the source and drain electrodes of a MOSFET can be interchanged based on the voltage applied to them. This disclosure should not be limited to the source and drain electrodes of the transistors in the following embodiments.

[0055] Figure 2 This is a circuit diagram showing the pixels of an organic light-emitting display device according to one embodiment of the present disclosure.

[0056] Each pixel P includes an organic light-emitting element (OLED), a driving transistor (DT), and first to sixth transistors (T1 to T6). Each pixel P may also include a capacitor (Cst).

[0057] Organic light-emitting elements (OLEDs) emit light using a driving current supplied to them by a driving transistor DT. An organic compound layer consisting of multiple layers is formed between the anode and cathode electrodes of the OLED. This organic compound layer may include at least one hole transfer layer, at least one electron transfer layer, and a light-emitting layer (EML). In this context, the hole transfer layer serves as a layer for injecting or transporting holes into the light-emitting layer and may include, for example, a hole injection layer (HIL), a hole transport layer (HTL), and an electron blocking layer (EBL). Similarly, the electron transfer layer serves as a layer for injecting or transferring electrons into the light-emitting layer and may include, for example, an electron transport layer (ETL), an electron injection layer (EIL), and a hole blocking layer (HBL). The anode electrode of the OLED is connected to a fourth node N4, and the cathode electrode is connected to the input terminal of a low-potential driving voltage VSS.

[0058] The driving transistor DT controls the driving current applied to the organic light-emitting element (OLED) based on its source-gate voltage Vsg. The driving transistor DT can be implemented as a p-type MOSFET (PMOS) or as an LTPS (low-temperature polycrystalline silicon) thin-film transistor. Furthermore, the source electrode of the driving transistor DT is connected to a first node N1, its gate electrode is connected to a second node N2, and its drain electrode is connected to a third node N3.

[0059] The first transistor T1 connects its gate and drain electrodes to each other in a diode manner. The first transistor T1 can be implemented as an n-type MOSFET (NMOS) or an oxide thin-film transistor to minimize leakage current. The first transistor T1 includes a drain electrode connected to the third node N3, a source electrode connected to the second node N2, and a gate electrode connected to the first scan signal line transmitting the first scan signal SC1(n). Therefore, in response to the high level of the first scan signal SC1(n) as an on-state level, the first transistor T1 connects the gate and drain electrodes of the driving transistor DT to each other in a diode manner.

[0060] The second transistor T2 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor DT. The second transistor T2 can be implemented as a p-type MOSFET (PMOS) or an LTPS (low-temperature polysilicon) thin-film transistor. The second transistor T2 includes a source electrode connected to the data line, a drain electrode connected to the first node N1, and a gate electrode connected to the second scan signal line that transmits the second scan signal SC2(n). Therefore, in response to the low-level second scan signal SC2(n), which is the on-state, the second transistor T2 applies the data voltage Vdata provided from the data line to the first node N1, which serves as the source electrode of the driving transistor DT.

[0061] The third transistor T3 applies a high-potential drive voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT. The third transistor T3 can be implemented as a p-type MOSFET (PMOS) or an LTPS (low-temperature polycrystalline silicon) thin-film transistor. The third transistor T3 includes a source electrode connected to a high-potential drive voltage line transmitting the high-potential drive voltage VDD, a drain electrode connected to the first node N1, and a gate electrode connected to a light-emitting signal line transmitting the third light-emitting signal EM(n+2). Therefore, in response to the low-level third light-emitting signal EM(n+2) which is the on-state, the third transistor T3 applies the high-potential drive voltage VDD to the first node N1, which serves as the source electrode of the driving transistor DT.

[0062] The fourth transistor T4 forms the current path between the driving transistor DT and the organic light-emitting element (OLED). The fourth transistor T4 can be implemented as a p-type MOSFET (PMOS) or an LTPS (low-temperature polycrystalline silicon) thin-film transistor. The fourth transistor T4 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to the light-emitting signal line that transmits the first light-emitting signal EM(n). In response to the first light-emitting signal EM(n), the fourth transistor T4 forms the current path between the third node N3 (the source electrode of the fourth transistor T4) and the fourth node N4 (the drain electrode of the fourth transistor T4). Therefore, the fourth transistor T4 forms the current path between the driving transistor DT and the organic light-emitting element (OLED) in response to the low level of the first light-emitting signal EM(n), which is the on-state level.

[0063] The fifth transistor T5 applies the initialization voltage Vini to the third node N3, which serves as the drain electrode of the driving transistor DT. The fifth transistor T5 can be implemented as a p-type MOSFET (PMOS) or an LTPS (low-temperature polycrystalline silicon) thin-film transistor. The fifth transistor T5 includes a source electrode connected to a digital initialization voltage line DVini that selectively transmits the bias stress voltage Vobs (hereinafter referred to as the "stress voltage") and the initialization voltage Vini; a drain electrode N3 connected to the third node; and a gate electrode connected to a third scan signal line that transmits the third scan signal SC3(n). Therefore, in response to a low-level third scan signal SC3(n) as an on-state, the fifth transistor T5 applies the initialization voltage Vini to the third node N3, which serves as the drain electrode of the driving transistor DT. Furthermore, the stress voltage Vobs and the initialization voltage Vini provided through the digital initialization voltage line DVini can have different voltage levels. The level of the stress voltage Vobs can be greater than the level of the initialization voltage Vini.

[0064] The sixth transistor T6 (also called the reset transistor) applies a reset voltage VAR to the fourth node N4, which serves as the anode of the organic light-emitting element. The sixth transistor T6 can be implemented as a p-type MOSFET (PMOS) or an n-type MOSFET (NMOS) to share the light-emitting signal without adding a separate signal, or it can be implemented as an oxide thin-film transistor. The sixth transistor T6 includes a source electrode connected to the reset voltage line transmitting the reset voltage VAR, a drain electrode connected to the fourth node N4, and a gate electrode connected to the light-emitting signal line transmitting the second light-emitting signal EM(n+1). Therefore, in response to the high level of the second light-emitting signal EM(n+1) as a turn-on level, the sixth transistor T6 applies the reset voltage VAR to the fourth node N4, which serves as the anode of the organic light-emitting element.

[0065] The storage capacitor Cst includes a first electrode connected to the second node N2 and a second electrode connected to the high-potential drive voltage line that transmits the high-potential drive voltage VDD. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the drive transistor DT, while the other electrode of the storage capacitor Cst is connected to the source electrode of the third transistor T3.

[0066] Figure 3 This is a waveform diagram showing each of the light emission signal and the scan signal of an organic light-emitting display device according to one embodiment of the present disclosure during a refresh frame.

[0067] Figure 4 This is a waveform diagram showing each of the light emission signal and the scan signal of an organic light-emitting display device according to one embodiment of the present disclosure during a reset frame.

[0068] Figure 5A This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during a bias stress period.

[0069] Figure 5B This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during an initial time period.

[0070] Figure 5C This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during a sampling period.

[0071] Figure 5D This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during the anode reset period.

[0072] Figure 5E This is a circuit diagram of the pixels of an organic light-emitting display device according to one embodiment of the present disclosure during the light-emitting period.

[0073] Reference Figures 2 to 5E The operation of an organic light-emitting display device according to one embodiment of the present disclosure will be described below.

[0074] An organic light-emitting display device according to one embodiment of this disclosure can operate independently in refresh frames and reset frames. In a refresh frame, a data voltage Vdata is programmed in each pixel P, and the organic light-emitting element (OLED) emits light. Furthermore, a reset frame can be a vertical blank frame. In a reset frame, the anode of the OLED is reset.

[0075] In an organic light-emitting display device according to one embodiment of the present disclosure, a refresh frame can be divided into a bias stress period (hereinafter referred to as a "stress period"), an initial period Ti, a sampling period Ts, a light-emitting period Te, and an anode reset period Tar (hereinafter referred to as a "reset period"). The stress period refers to the period during which bias stress is applied to the first node N1, which serves as the source electrode of the driving transistor DT. The stress period may include a first stress period Tobs1 and a second stress period Tobs2. The initial period Ti refers to the period during which the voltage of the third node N3, which serves as the drain electrode of the driving transistor DT, is initialized. The sampling period Ts refers to the period during which the threshold voltage Vth of the driving transistor DT is sampled and the data voltage Vdata is programmed. The light-emitting period Te refers to the period during which the organic light-emitting element OLED emits light based on the driving current caused by the programming of the source-gate voltage of the driving transistor DT. The reset period Tar refers to the period during which the voltage level of the anode electrode of the organic light-emitting element OLED is fixed at the reset voltage VAR for the remaining period excluding the light-emitting period Te.

[0076] Specifically, refer to Figure 3 and Figure 5A During the first stress period Tobs1, the second light-emitting signal EM(n+1) has a high level as the on-state, and the third scan signal SC3(n) has a low level as the on-state. Therefore, the sixth transistor T6 is turned on, causing the reset voltage VAR to be applied to the fourth node N4. That is, the anode electrode of the organic light-emitting element OLED is reset based on the reset voltage VAR. Furthermore, the fifth transistor T5 is turned on, causing the stress voltage Vobs to be applied from the digital initialization voltage line DVini to the third node N3. The stress voltage Vobs can be selected from a voltage range sufficiently higher than the operating voltage of the organic light-emitting element OLED, and can be set to be equal to or lower than the high-potential driving voltage VDD. That is, the voltage Vgs between the gate and source of the driving transistor DT can be reduced by applying bias stress to the third node N3, which is the drain electrode of the driving transistor DT, during the first stress period Tobs1. Therefore, the source-drain current Ids of the driving transistor DT can flow during the first stress period Tobs1, thereby reducing the hysteresis of the driving transistor DT. Furthermore, referring to… Figure 3 and Figure 5BDuring the initial period Ti, the first scan signal SC1(n) is high as the on-level, the third scan signal SC3(n) is low as the on-level, and the second emission signal EM(n+1) is high as the on-level. Therefore, the first transistor T1 and the fifth transistor T5 are turned on, causing the initialization voltage Vini from the digital initialization voltage line DVini to be applied to the second node N2. Thus, the gate electrode of the driving transistor DT is initialized based on the initialization voltage Vini. The initialization voltage Vini can be selected within a voltage range sufficiently lower than the operating voltage of the organic light-emitting element OLED, and the initialization voltage Vini can be set to be equal to or lower than the low-potential driving voltage VSS. Furthermore, during the initial period Ti, the sixth transistor T6 remains on, maintaining the reset voltage VAR at the fourth node N4.

[0077] In addition, refer to Figure 3 and Figure 5C During the sampling period Ts, the first scan signal SC1(n) is high as the on level, the second scan signal SC2(n) is low as the on level, and the second emission signal EM(n+1) is high as the on level. Furthermore, during the sampling period Ts, the second transistor T2 is turned on, causing the data voltage Vdata to be applied to the first node N1. Additionally, when the first transistor T1 is turned on, the driving transistor DT is in a diode-connected state, thus short-circuiting the gate and drain electrodes of the driving transistor DT. Therefore, the driving transistor DT can function as a diode. During the sampling period Ts, the second node N2 is charged to a voltage corresponding to the sum of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT.

[0078] During the sampling period Ts, current Ids flows between the source and drain of the driving transistor DT. The gate and drain electrodes of the driving transistor DT are in a diode connection state. Therefore, due to the current flowing from the source electrode to the drain electrode, the voltage of the second node N2 increases until the gate-source voltage Vgs of the driving transistor DT reaches Vth.

[0079] In addition, refer to Figure 3 and Figure 5ADuring the second stress period Tobs2, the second light-emitting signal EM(n+1) has a high level as the on-state, and the third scan signal SC3(n) has a low level as the on-state. Therefore, the sixth transistor T6 is turned on, causing the reset voltage VAR to be applied to the fourth node N4. That is, the anode electrode of the organic light-emitting element OLED is reset based on the reset voltage VAR. In addition, the fifth transistor T5 is turned on, causing the stress voltage Vobs to be applied to the third node N3. That is, the hysteresis effect of the driving transistor DT can be reduced by applying bias stress to the third node N3, which is the drain electrode of the driving transistor DT, during the second stress period Tobs2.

[0080] In addition, refer to Figure 3 and Figure 5D During the reset period Tar, the first light-emitting signal EM(n) has a low level as the on-state, and the second light-emitting signal EM(n+1) has a high level as the on-state. Therefore, the sixth transistor T6 is turned on, causing the reset voltage VAR to be applied to the fourth node N4. That is, the anode electrode of the OLED is reset based on the reset voltage VAR. Furthermore, the fourth transistor T4 is turned on, causing the third node N3 and the fourth node N4 to have the same potential.

[0081] At this point, the sixth transistor T6 is turned on because the second light-emitting signal EM(n+1) has a conduction level, so that the reset voltage VAR is provided to the fourth node N4. In other words, because the fourth transistor T4 is implemented as a p-type MOSFET (PMOS) and the sixth transistor T6 is implemented as an n-type MOSFET (NMOS), the third node N3 and the fourth node N4 can have the same potential, that is, the reset voltage VAR level during the period when the first light-emitting signal EM(n) is low and the second light-emitting signal EM(n+1) is high.

[0082] When the sixth transistor T6 is implemented as a p-type MOSFET (PMOS), or when another scan signal, such as the third scan signal SC3(n), is applied to the sixth transistor T6 instead of the second light-emitting signal EM(n+1), during the light-emitting period Te, at the moment when the level of the first light-emitting signal EM(n) becomes a low level, which is the on-state level, charge sharing may occur between the third node N3 and the fourth node N4. That is, even if the intention is to present a black image, a black failure may occur due to charge sharing when the OLED emits light. In a black failure, the image is presented at a low gray level of approximately 0.7 to 1 nit instead of a black gray level.

[0083] Therefore, in one embodiment of this disclosure, when the sixth transistor T6 is driven using the second light-emitting signal EM(n+1), and even when the level of the first light-emitting signal EM(n) becomes a low level (which is the on-state) during the light-emitting period Te, a reset voltage VAR with a voltage level lower than the operating voltage of the organic light-emitting element OLED is provided to the fourth node N4. Therefore, the organic light-emitting element OLED does not emit light, and the third node N3 and the fourth node N4 can be at the same potential, i.e., the reset voltage VAR level.

[0084] Furthermore, since the reset voltage VAR is continuously applied to the fourth node N4 during the remaining time period excluding the light-emitting period Te, the fourth node N4 may not be in a floating state, or the potential of the fourth node N4 may not increase due to the floating state. Even when the fourth transistor T4 is turned on based on the first light-emitting signal EM(n), the potential of the fourth node N4 may depend on the reset voltage VAR until the second light-emitting signal EM(n+1) is turned off.

[0085] In addition, refer to Figure 3 and Figure 5E During the emission period Te, each of the first emission signal EM(n) and the third emission signal EM(n+2) has a low level as the on-state. Therefore, the third transistor T3 is turned on, so that a high-potential driving voltage VDD is applied to the first node N1. Furthermore, since the second node N2 is coupled to the high-potential driving voltage VDD through the storage capacitor Cst, the high-potential driving voltage VDD is reflected at the second node N2. Additionally, the fourth transistor T4 is turned on, thus forming a current path between the third node N3 and the fourth node N4. Therefore, a driving current Ioled is applied to the organic light-emitting element OLED through the source and drain electrodes of the driving transistor DT.

[0086] In addition, refer to Figure 4 During the sampling period Ts in the reset frame, the first scan signal SC1(n) is held at a low level as a shutdown level, while the second scan signal SC2(n) is held at a high level as a shutdown level. Therefore, the data voltage Vdata is not programmed in each pixel P during the reset frame.

[0087] However, each of the first light emission signal EM(n), the second light emission signal EM(n+1), the third light emission signal EM(n+2), and the third scan signal SC3(n) oscillates periodically. That is, because the third scan signal SC3(n) oscillates periodically, the reset frame can include multiple stress periods Tobs.

[0088] In other words, during the reset frame, the anode electrode of the organic light-emitting element OLED can be reset based on the reset voltage VAR, and bias stress can be applied to the third node N3, which serves as the drain electrode of the driving transistor DT.

[0089] Finally, in an organic light-emitting display device according to one embodiment of this disclosure, the anode electrode of the organic light-emitting element (OLED) can be periodically reset within refresh frames and reset frames. Therefore, a continuous increase in the voltage of the anode electrode of the OLED due to leakage current can be prevented, allowing the anode electrode of the OLED to maintain a constant voltage level. Thus, brightness variations in the organic light-emitting display device can be minimized, thereby improving its image quality.

[0090] Figures 6A to 6C This is a diagram illustrating an improvement of an organic light-emitting display device according to one embodiment of the present disclosure relative to a comparative example.

[0091] Figure 6A This is a graph showing the variation of the driving current Ioled flowing in the organic light-emitting element (OLED) of a pixel in an organic light-emitting display device according to one embodiment of the present disclosure. It can be seen that, in the comparative example, when the sixth transistor T6 is driven based on the third scan signal SC3(n), the driving current Ioled is not constant, but varies based on the charge sharing phenomenon between the third node N3 and the fourth node N4 at the moment when the first light-emitting signal EM(n) becomes a low level as the on-state.

[0092] Conversely, in this embodiment, the transistor is driven by the second emission signal EM(n+1). Therefore, the fourth node N4 is fixed at the reset voltage VAR until the second emission signal EM(n+1) becomes low, which is the off-level. Thus, the drive current Ioled does not change and can remain at a fixed value.

[0093] In other words, during the reset period Tar, the drive current Ioled is unaffected by changes in the scan signal and remains constant. Therefore, even when the voltage level difference between the reset voltage VAR and the low-level drive voltage VSS reaches 1.7V, a black fault will not occur.

[0094] Figure 6B This is a diagram illustrating the reset voltage VAR and drive current Ioled of the fourth node N4 in a pixel of an organic light-emitting display device according to one embodiment of the present disclosure. a refers to the drive current Ioled in the pixel in the bright portion of the display panel 100, and b refers to the drive current Ioled in the pixel in the dark portion of the display panel 100.

[0095] In the comparative example, the sixth transistor T6, which provides the reset voltage VAR to the fourth node N4, is implemented as a p-type MOSFET (PMOS). Therefore, the reset voltage VAR is applied to the fourth node N4 and gradually increases while the third scan signal SC3(n) is high. At this point, when the first emission signal EM(n) goes high as the on-state, the third node N3 and the fourth node N4 enter a charge-sharing state, resulting in a momentary peak in the reset voltage VAR.

[0096] Conversely, in this embodiment, an n-type MOSFET (NMOS) is used. Therefore, unlike the comparative example, when the first light-emitting signal EM(n) has a high level as the on-state, the reset voltage VAR decreases. Consequently, the drive current Ioled decreases based on the reduction in reset voltage VAR, thus reducing the difference between the drive current Ioled in the bright and dark areas, thereby improving the low grayscale uniformity of the display panel 100.

[0097] Figure 6C This is a graph showing the uniformity of the drive current Ioled in each pixel of an organic light-emitting display device according to one embodiment of the present disclosure, based on the threshold voltage Vth of the drive transistor DT.

[0098] The threshold voltage Vth of the driving transistor DT can vary depending on the uniformity of the manufacturing process. In this respect, the greater the uniformity of the threshold voltage Vth, the greater the variation in the driving current Ioled flowing through the organic light-emitting element OLED. In other words, when the pixel structure of this embodiment is applied, the vibration in the driving current Ioled is less than that in the comparative example, thereby improving the low grayscale uniformity of the display panel 100.

[0099] As described above, in an organic light-emitting display device according to one embodiment of the present disclosure, black defects can be reduced and brightness variations at low gray levels can be minimized, thereby improving image quality.

[0100] An organic light-emitting display device according to one embodiment of the present disclosure can be described as follows.

[0101] One aspect of this disclosure provides an organic light-emitting display device, comprising: a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes: an organic light-emitting element for emitting light based on a driving current; a driving transistor for controlling the driving current, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; a first transistor for connecting the second node and the third node to each other in a diode manner; a second transistor for applying a data voltage to the first node; a third transistor for applying a high-potential driving voltage VDD to the first node; a fourth transistor for forming a current path between the driving transistor and the organic light-emitting element; a fifth transistor for selectively applying a stress voltage Vobs and an initialization voltage Vini to the third node; and a sixth transistor for applying a reset voltage VAR to the fourth node, which serves as the anode electrode of the organic light-emitting element.

[0102] In one embodiment of the organic light-emitting display device, the device operates separately in refresh frames and reset frames. In the refresh frame, a data voltage is programmed to the pixel, and in the reset frame, the anode electrode of the organic light-emitting element is reset. The refresh frame is divided into a stress period, an initial period, a sampling period, a reset period, and a light-emitting period. During the stress period, a bias stress is applied to the driving transistor. During the initial period, a second or third node is initialized based on an initialization voltage. During the sampling period, the second node is charged to a voltage corresponding to the sum of the data voltage and the threshold voltage Vth of the driving transistor. During the reset period, a fourth node is reset based on a reset voltage VAR. During the light-emitting period, a driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light.

[0103] In one embodiment of the organic light-emitting display device, when the fourth transistor is turned on during the reset period, the third node and the fourth node are at the same potential equal to the reset voltage.

[0104] In one embodiment of the organic light-emitting display device, each of the first transistor and the sixth transistor includes an n-type MOSFET.

[0105] In one embodiment of the organic light-emitting display device, each of the driving transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor includes a p-type MOSFET.

[0106] In one embodiment of the organic light-emitting display device, each of the first transistor and the sixth transistor includes an oxide thin-film transistor.

[0107] In one embodiment of the organic light-emitting display device, each of the driving transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises a low-temperature polycrystalline silicon thin-film transistor.

[0108] In one embodiment of an organic light-emitting display device, a first transistor includes: a drain electrode connected to a third node, a source electrode connected to a second node, and a gate electrode connected to a first scan signal line for transmitting a first scan signal. A second transistor includes: a source electrode connected to a data line, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line for transmitting a second scan signal. A third transistor includes: a source electrode connected to a high-potential drive voltage line for transmitting a high-potential drive voltage, a drain electrode connected to the first node, and a gate electrode connected to a third light-emitting signal line for transmitting a third light-emitting signal. A fourth transistor includes: a source electrode connected to the third node, a drain electrode connected to the fourth node, and a gate electrode connected to the first light-emitting signal line for transmitting the first light-emitting signal. A fifth transistor includes: a source electrode connected to a digital initialization voltage line for selectively transmitting a stress voltage or an initialization voltage, a drain electrode connected to the third node, and a gate electrode connected to the third scan signal line for transmitting a third scan signal. A sixth transistor includes: a source electrode connected to a reset voltage line for transmitting a reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to the second light-emitting signal line for transmitting a second light-emitting signal.

[0109] In one embodiment of the organic light-emitting display device, the organic light-emitting display device further includes a storage capacitor having an electrode connected to a second node.

[0110] One aspect of this disclosure provides an organic light-emitting display device, comprising: a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes: an organic light-emitting element; a driving transistor for providing a driving current to the organic light-emitting element, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; and a reset transistor for applying a reset voltage to a fourth node serving as an anode electrode of the organic light-emitting element, wherein each of the plurality of pixels operates during a stress period, an initialization period, a sampling period, a reset period, and a light-emitting period, wherein during the stress period, a bias stress is applied to the driving transistor; wherein during the initialization period, a second node or a third node is initialized based on an initialization voltage; wherein during the sampling period, the second node is charged to a voltage corresponding to the sum of a data voltage and a threshold voltage of the driving transistor; wherein during the reset period, the reset transistor resets the fourth node based on the reset voltage; and wherein during the light-emitting period, a driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light.

[0111] In one embodiment of the organic light-emitting display device, during the reset period, the third node and the fourth node are at the same potential equal to the reset voltage.

[0112] In one embodiment of the organic light-emitting display device, the driving transistor includes a p-type MOSFET.

[0113] In one embodiment of the organic light-emitting display device, the driving transistor includes a low-temperature polycrystalline silicon thin-film transistor.

[0114] In one embodiment of the organic light-emitting display device, the reset transistor includes an n-type MOSFET.

[0115] In one embodiment of the organic light-emitting display device, the reset transistor includes an oxide thin-film transistor.

[0116] One aspect of this disclosure provides an organic light-emitting display device, comprising: a plurality of pixels arranged in a display panel, wherein each of the plurality of pixels includes: an organic light-emitting element; a driving transistor for providing a driving current to the organic light-emitting element, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; and a reset transistor for applying a reset voltage to a fourth node serving as an anode electrode of the organic light-emitting element during a reset period in a refresh frame, such that the third node and the fourth node are at the same potential equal to the reset voltage, wherein in the refresh frame, a data voltage is programmed to the pixel, the reset period is a period in the refresh frame during which the voltage level of the anode electrode of the organic light-emitting element is fixed at the reset voltage for the remaining period of the refresh frame excluding the light-emitting period, and during the light-emitting period, a driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light.

[0117] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not necessarily limited to these embodiments. Various modifications can be made to the present disclosure without departing from the technical spirit of the present disclosure. Therefore, the embodiments disclosed herein are not intended to limit the technical concept of the present disclosure, but rather to describe the present disclosure. The scope of the technical spirit of the present disclosure is not limited by the embodiments. Therefore, it should be understood that the embodiments described above are illustrative and non-limiting in all respects. The scope of protection of the present disclosure should be interpreted by the claims, and all technical concepts within the scope of the present disclosure should be interpreted as including within the scope of the present disclosure.

Claims

1. An organic light-emitting display device, comprising: Multiple pixels arranged in the display panel, Each of the plurality of pixels includes: Organic light-emitting elements used for emitting light based on driving current; A driving transistor for controlling the driving current, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; A first transistor is used to connect the second node and the third node to each other in a diode manner; The second transistor is used to apply the data voltage to the first node; The third transistor is used to apply a high-potential drive voltage to the first node; A fourth transistor is used to form a current path between the driving transistor and the organic light-emitting element; A fifth transistor is used to selectively apply stress voltage and initialization voltage to the third node; and The sixth transistor is used to apply a reset voltage to the fourth node, which serves as the anode electrode of the organic light-emitting element. During the reset period in the refresh frame, the reset voltage is applied to the anode electrode of the organic light-emitting element. The refresh frame includes a reset period and a light emission period set sequentially. The reset period includes a first stress period, an initial period, a sampling period, and a second stress period set sequentially. During the first stress period and the second stress period, bias stress is applied to the driving transistor. During the reset period, when both the fourth and sixth transistors are turned on, the third and fourth nodes remain at the same potential. This period, during which both the fourth and sixth transistors are turned on, falls between the second stress period and the light-emitting period. The fourth transistor is driven by the first light-emitting signal. The sixth transistor is driven by the second light-emitting signal. The third transistor is driven by a third light-emitting signal. The first light-emitting signal, the second light-emitting signal, and the third light-emitting signal are sequentially delayed in time.

2. The organic light-emitting display device according to claim 1, wherein, The organic light-emitting display device operates independently in the refresh frame and the reset frame, wherein, in the refresh frame, the data voltage is programmed to the pixel, and in the reset frame, the anode electrode of the organic light-emitting element is reset. During the initial time period, the second node or the third node is initialized based on the initialization voltage. During the sampling period, the second node is charged to a voltage corresponding to the sum of the data voltage and the threshold voltage of the driving transistor. During the reset period, the fourth node is reset based on the reset voltage. During the light-emitting period, the driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light.

3. The organic light-emitting display device according to claim 1, wherein, Each of the first transistor and the sixth transistor includes an n-type MOSFET.

4. The organic light-emitting display device according to claim 1, wherein, Each of the driving transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor includes a p-type MOSFET.

5. The organic light-emitting display device according to claim 1, wherein, Each of the first transistor and the sixth transistor comprises an oxide thin-film transistor.

6. The organic light-emitting display device according to claim 1, wherein, Each of the driving transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises a low-temperature polycrystalline silicon thin-film transistor.

7. The organic light-emitting display device according to claim 1, wherein, The first transistor includes: a drain electrode connected to the third node, a source electrode connected to the second node, and a gate electrode connected to a first scan signal line for transmitting a first scan signal. The second transistor includes: a source electrode connected to a data line, a drain electrode connected to the first node, and a gate electrode connected to a second scan signal line for transmitting a second scan signal. The third transistor includes: a source electrode connected to a high-potential drive voltage line for transmitting the high-potential drive voltage, a drain electrode connected to the first node, and a gate electrode connected to a third light-emitting signal line for transmitting the third light-emitting signal. The fourth transistor includes: a source electrode connected to the third node, a drain electrode connected to the fourth node, and a gate electrode connected to a first light-emitting signal line for transmitting the first light-emitting signal. The fifth transistor includes: a source electrode connected to a digital initialization voltage line for selectively transmitting the stress voltage or the initialization voltage; a drain electrode connected to the third node; and a gate electrode connected to a third scan signal line for transmitting the third scan signal. The sixth transistor includes: a source electrode connected to a reset voltage line for transmitting the reset voltage, a drain electrode connected to the fourth node, and a gate electrode connected to a second light-emitting signal line for transmitting the second light-emitting signal.

8. The organic light-emitting display device according to any one of claims 1 to 7, wherein, The organic light-emitting display device further includes: A storage capacitor having one electrode connected to the second node.

9. An organic light-emitting display device, comprising: Multiple pixels arranged in the display panel, Each of the plurality of pixels includes: Organic light-emitting elements; A driving transistor for providing driving current to the organic light-emitting element, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; A third transistor used to apply a high-potential drive voltage to the first node; A transistor for forming a current path between the driving transistor and the organic light-emitting element; and A reset transistor is used to apply a reset voltage to the fourth node, which serves as the anode electrode of the organic light-emitting element. Each of the plurality of pixels operates during a sequentially set reset period and an emission period, wherein the reset period includes a sequentially set first stress period, an initial period, a sampling period, and a second stress period. During the first stress period and the second stress period, bias stress is applied to the driving transistor. During the initial time period, the second node or the third node is initialized based on the initialization voltage. During the sampling period, the second node is charged to a voltage corresponding to the sum of the data voltage and the threshold voltage of the driving transistor. During the reset period, the reset transistor resets the fourth node based on the reset voltage. During the light-emitting period, the driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light. During the reset period, the reset voltage is applied to the anode electrode of the organic light-emitting element. During the reset period, when both the transistor forming the current path and the reset transistor are turned on, the third node and the fourth node remain at the same potential. This period, in which both the transistor forming the current path and the reset transistor are turned on, occurs between the second stress period and the light-emitting period. The transistor used to form the current path is driven by a first light-emitting signal. The reset transistor is driven by a second light-emitting signal. The third transistor is driven by a third light-emitting signal. The first light-emitting signal, the second light-emitting signal, and the third light-emitting signal are sequentially delayed in time.

10. The organic light-emitting display device according to claim 9, wherein, The driving transistor includes a p-type MOSFET.

11. The organic light-emitting display device according to claim 9, wherein, The driving transistor includes a low-temperature polycrystalline silicon thin-film transistor.

12. The organic light-emitting display device according to claim 9, wherein, The reset transistor includes an n-type MOSFET.

13. The organic light-emitting display device according to claim 9, wherein, The reset transistor includes an oxide thin-film transistor.

14. An organic light-emitting display device, comprising: Multiple pixels arranged in the display panel, Each of the plurality of pixels includes: Organic light-emitting elements; A driving transistor for providing driving current to the organic light-emitting element, wherein the driving transistor includes: a source electrode serving as a first node, a gate electrode serving as a second node, and a drain electrode serving as a third node; A third transistor used to apply a high-potential drive voltage to the first node; A transistor for forming a current path between the driving transistor and the organic light-emitting element; and A reset transistor is used to apply a reset voltage to the fourth node, which serves as the anode electrode of the organic light-emitting element, during a reset period in the refresh frame. In the refresh frame, the data voltage is programmed into the pixel. The refresh frame includes a reset period and a light emission period set sequentially. The reset period includes a first stress period, an initial period, a sampling period, and a second stress period set sequentially. During the first stress period and the second stress period, bias stress is applied to the driving transistor. The reset period is the time during which the voltage level of the anode electrode of the organic light-emitting element is fixed at the reset voltage for the remaining time period in the refresh frame, excluding the light-emitting period. During the light-emitting period, the driving current is applied to the organic light-emitting element, causing the organic light-emitting element to emit light. During the reset period, the reset voltage is applied to the anode electrode of the organic light-emitting element. During the reset period, when both the transistor forming the current path and the reset transistor are turned on, the third node and the fourth node remain at the same potential. This period, in which both the transistor forming the current path and the reset transistor are turned on, occurs between the second stress period and the light-emitting period. The transistor used to form the current path is driven by a first light-emitting signal. The reset transistor is driven by a second light-emitting signal. The third transistor is driven by a third light-emitting signal. The first light-emitting signal, the second light-emitting signal, and the third light-emitting signal are sequentially delayed in time.

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