Methods for correcting overlay errors

Abstract

This disclosure provides a method for correcting overlay errors. The method includes: obtaining an overlay error based on a lower layer pattern and an upper layer pattern of a wafer, wherein the lower layer pattern is obtained by a first manufacturing apparatus through which the wafer passes, and the upper layer pattern is obtained by an exposure apparatus; generating a corrected overlay error based on the overlay error and a process performed on the wafer after the first manufacturing apparatus and before the exposure apparatus; and adjusting the exposure apparatus based on the corrected overlay error.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Applications Nos. 17 / 568,033 and 17 / 568,151 (i.e., priority date “January 4, 2022”), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a method for correcting overlay errors. Background Technology

[0004] With the development of the semiconductor industry, reducing overlay error between photoresist patterns and underlying patterns in photolithography operations has become increasingly important. Various factors, such as the asymmetrical shape of the measurement structure, make accurate measurement of overlay error more difficult, thus requiring new overlay measurement markers and methods for more precise measurement.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0006] One aspect of this disclosure provides an overlay correction mark. The mark includes a first pattern and a second pattern. The first pattern is disposed on a substrate and located at a first water level. The first pattern includes a plurality of first patterns and a plurality of second patterns. The first patterns extend along a first direction and are arranged along a second direction different from the first direction. The second patterns are arranged along the second direction, wherein the outline of each of the plurality of first patterns is different from the outline of each of the plurality of second patterns. The second pattern is disposed at a second horizontal level different from the first water level.

[0007] Another aspect of this disclosure provides a method for correcting overlay errors. The method includes: obtaining an overlay error based on a lower layer pattern and an upper layer pattern of a wafer, wherein the lower layer pattern is obtained by a first manufacturing apparatus through which the wafer passes, and the upper layer pattern is obtained by an exposure apparatus; generating a corrected overlay error based on the overlay error and a process performed on the wafer after the first manufacturing apparatus and before the exposure apparatus; and adjusting the exposure apparatus based on the corrected overlay error.

[0008] Another aspect of this disclosure provides a method for correcting overlay errors. The method includes: receiving a wafer having a substrate; forming a first pattern on the substrate of the wafer; performing multiple processes on the wafer; forming a second pattern on the first pattern of the wafer using an exposure apparatus; obtaining an overlay error based on the first and second patterns of the wafer; generating a corrected overlay error based on the overlay error and the multiple processes; and adjusting the exposure apparatus based on the corrected overlay error.

[0009] Embodiments of this disclosure disclose an overlay mark for measuring overlay error. The front layer of the overlay mark may include different sub-patterns so that correction data can be generated from each sub-pattern. Selecting correction data from a specific sub-pattern can refine the correction of overlay error, thus making the correction of overlay error more realistic.

[0010] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0011] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0012] Figure 1 This is a top view illustrating a wafer of some embodiments of this disclosure.

[0013] Figure 2 This is an enlarged view illustrating some embodiments of this disclosure. Figure 1 The dotted areas in the middle.

[0014] Figure 3 This is a top view illustrating the superimposed labels of some embodiments of this disclosure.

[0015] Figure 4A This is an example of some embodiments of the present disclosure. Figure 3 A sectional view of line A-A'.

[0016] Figure 4B This is an example of some embodiments of the present disclosure. Figure 3 A cross-sectional view of line B-B'.

[0017] Figure 5This is a top view illustrating the superimposed labels of some embodiments of this disclosure.

[0018] Figure 6 This is a top view illustrating the superimposed labels of some embodiments of this disclosure.

[0019] Figure 7 This is a top view illustrating the superimposed labels of some embodiments of this disclosure.

[0020] Figure 8 This is a block diagram illustrating a semiconductor fabrication system according to some embodiments of the present disclosure.

[0021] Figure 9 This is a flowchart illustrating a method for generating correction data from an overlay correction system according to some embodiments of this disclosure.

[0022] Figure 10 This is a flowchart illustrating methods for correcting overlay errors in various aspects of this disclosure.

[0023] Figure 11 This is a flowchart illustrating methods for correcting overlay errors in various aspects of this disclosure.

[0024] Figure 12 This is a flowchart illustrating methods for correcting overlay errors in various aspects of this disclosure.

[0025] Figure 13 This is a block diagram illustrating the hardware of a semiconductor fabrication system for various aspects of this disclosure.

[0026] Explanation of reference numerals in the attached figures:

[0027] 10: Wafers

[0028] 20: Overlay Marker

[0029] 30: Cutting track

[0030] 40: Chip

[0031] 100: Base

[0032] 110: Overlay Marker

[0033] 120: Pattern

[0034] 130: Pattern

[0035] 140: Intermediate Structure

[0036] 150: Mask

[0037] 210: Overlay mark

[0038] 210': Overlay mark

[0039] 210”: Overlay mark

[0040] 220: Pattern

[0041] 220': Pattern

[0042] 222: Secondary Pattern

[0043] 224: Secondary Pattern

[0044] 226: Secondary Pattern

[0045] 226d: Segmentation

[0046] 230: Pattern

[0047] 232: Secondary Pattern

[0048] 300: Semiconductor Fabrication System

[0049] 301: Wafer

[0050] 310: Manufacturing equipment

[0051] 320-1, ..., 320-N: Manufacturing equipment

[0052] 330: Exposure equipment

[0053] 340: Overlay measuring equipment

[0054] 350: Network

[0055] 350: Network

[0056] 360: Controller

[0057] 370: Overlay (OVL) Correction System

[0058] 400: Method

[0059] 410: Operation

[0060] 420: Operation

[0061] 430: Operation

[0062] 440: Operation

[0063] 500: Calibration Method

[0064] 510: Operation

[0065] 520: Operation

[0066] 522: Operation

[0067] 524: Operation

[0068] 526: Operation

[0069] 530: Operation

[0070] 540: Operation

[0071] 550: Operation

[0072] 560: Operation

[0073] 562: Operation

[0074] 564: Operation

[0075] 5641: Operation

[0076] 5642: Operation

[0077] 5643: Operation

[0078] 566: Operation

[0079] 568: Operation

[0080] 570: Operation

[0081] 600: Semiconductor Fabrication System

[0082] 601: Processor

[0083] 603: Non-transitory computer-readable storage media

[0084] 605: Bus

[0085] 607: Input and Output (I / O) Interface

[0086] 609: Network Interface

[0087] 610: User Interface

[0088] A-A': Line (cutting line)

[0089] B-B': Line (cutting line)

[0090] X: Direction

[0091] Y: direction

[0092] Z: Direction Detailed Implementation

[0093] Embodiments, or examples, of the present disclosure illustrated in the accompanying drawings will now be described in specific language. It should be understood that this is not intended to limit the scope of the disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as commonly done by one of ordinary skill in the art to which this disclosure relates. Reference numerals may be repeated throughout the embodiments, but this is not intended to apply a feature of one embodiment to another, even if they share the same reference numerals.

[0094] It should be understood that although the terms first, second, third, etc., can be used to describe various elements, components, regions, layers, or portions, these elements, components, regions, layers, or portions are not limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer, or portion from another. Therefore, the first element, component, region, layer, or portion discussed below can be referred to as the second element, component, region, layer, or portion without departing from the teachings of the concept of the invention.

[0095] The terminology used herein is for describing particular embodiments only and is not intended to limit one to the concepts of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include multiple forms unless the context clearly indicates otherwise. It should be further understood that the terms "comprising" and "including" as used in this specification indicate the presence of the stated feature, integer, step, operation, element, or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0096] Reference Figure 1 and Figure 2 , Figure 1 This is a top view illustrating various aspects of the present disclosure of wafer 10. Figure 2 yes Figure 1 A magnified view of the midpoint-shaped area.

[0097] like Figure 1 and Figure 2 As shown, wafer 10 is sawn into multiple chips 40 along dicing 30. Each chip 40 may include a semiconductor element, which may include an active element and / or a passive element. The active element may include a memory chip (e.g., a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, etc.), a power management chip (e.g., a power management integrated circuit (PMIC) chip), a logic chip (e.g., a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), a microcontroller, etc.), a radio frequency (RF) chip, a sensor chip, a microelectromechanical system (MEMS) chip, a signal processing chip (e.g., a digital signal processing (DSP) chip), a front-end chip (e.g., an analog front-end (AFE) chip), or other active elements. Passive elements may include a capacitor, a resistor, an inductor, a fuse, or other passive elements.

[0098] In some embodiments, the overlay mark 20 may be located on the dicing track 30. The overlay mark 20 may be disposed at the corner of the edge of each chip 40. In some embodiments, the overlay mark may be located inside the chip 40. The overlay mark 20 may be used to measure whether the opening of the current layer, such as the photoresist layer, is precisely aligned with a pre-layer in the semiconductor process.

[0099] Figure 3 This is a top view illustrating the stacking marks 110 for aligning different layers on a substrate 100, representing various aspects of this disclosure. (See figure) Figure 3 As shown, a semiconductor device structure, such as a wafer, may include stacked markings 110 on a substrate 100.

[0100] Substrate 100 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. Substrate 100 may include an elemental semiconductor, including silicon or germanium in single-crystal, polycrystalline, or amorphous form; a compound semiconductor material, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; an alloy semiconductor material, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable material; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy with a gradient Ge characteristic, wherein the composition of Si and Ge changes from the ratio at one location of the gradient SiGe characteristic to the ratio at another location. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, the SiGe alloy may be mechanically tensioned by another material in contact with the SiGe alloy. In some embodiments, substrate 100 may have a multilayer structure, or substrate 100 may include a multilayer compound semiconductor structure.

[0101] Overlay marker 110 may include patterns 120 and 130 on substrate 100. Pattern 120 may be a pattern of a preceding layer. Pattern 130 may be a pattern of a current layer. The preceding layer (or lower layer) may be located at a different horizontal level than the current layer (or upper layer). Each pattern 120 (or pattern 130) may be located in one of four orthogonal destination regions, two of which are used to measure overlay error in the X direction and two of which are used to measure overlay error in the Y direction.

[0102] When measuring a stacking error using a stacking mark (such as stacking mark 110), the deviation in the X direction is measured along a straight line in the X direction of stacking mark 110. The deviation in the Y direction is further measured along a straight line in the Y direction of stacking mark 110. A single stacking mark, including patterns 120 and 130, can be used to measure a deviation in one X direction and one Y direction between two layers on a substrate. Therefore, the accuracy of alignment between the current layer and the preceding layer can be determined based on the deviations in the X and Y directions. Stacking error may include deviation in the X direction (ΔX), deviation in the Y direction (ΔY), or a combination of both.

[0103] Figure 4A It is along Figure 3 A cross-sectional view taken along the cutting line A-A'.

[0104] like Figure 3 and Figure 4A As shown, pattern 120 may be disposed on substrate 100. Pattern 120 may be disposed in intermediate structure 140. In some embodiments, pattern 120 may include the same material as an isolation structure. In some embodiments, pattern 120 may be disposed at the same elevation as the isolation structure. The isolation structure may include, for example, shallow trench isolation (STI), field oxidation (FOX), localized oxidation of silicon (LOCOS) features, and / or other suitable isolation elements. The isolation structure may include a dielectric material such as silicon oxide, silicon nitride, silicon oxy-nitride, fluorinated silicate (FSG), a low-k dielectric material, combinations thereof, and / or other suitable materials.

[0105] In some embodiments, pattern 120 may include the same material as a gate structure. For example, the gate structure may be sacrificial, such as a dymmy gate structure. In some embodiments, pattern 120 may be disposed at the same elevation as the gate structure. In some embodiments, pattern 120 may include a dielectric layer of the same material as a gate dielectric layer, and a conductive layer of the same material as a gate electrode layer.

[0106] In some embodiments, the gate dielectric layer may include silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), or combinations thereof. In some embodiments, the gate dielectric layer may include a dielectric material, such as a high-k dielectric material. The high-k material may have a dielectric constant (k value) greater than 4. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), or other suitable materials. Other suitable materials are also within the scope of this disclosure.

[0107] In some embodiments, the gate electrode layer may include a polysilicon layer. In some embodiments, the gate electrode layer may be fabricated using a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other suitable materials. In some embodiments, the gate electrode layer may include a work function layer. The work function layer may be fabricated using a metallic material, and the metallic material may include metals with N-work function or metals with P-work function. N-work function metals include tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or combinations thereof. P-work function metals include titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or combinations thereof. Other suitable materials are also within the scope of this disclosure. The gate electrode layer may be formed by low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced CVD (PECVD).

[0108] In some embodiments, pattern 120 may include the same material as a conductive via, which may be disposed on a conductive wire, such as a first metal layer (M1 layer). In this embodiment, pattern 120 may include a barrier layer and a conductive layer surrounded by the barrier layer. The barrier layer may include a metal nitride or other suitable material. The conductive layer may include a metal, such as W, Ta, Ti, Ni, Co, Hf, Ru, Zr, Zn, Fe, Sn, Al, Cu, Ag, Mo, Cr, alloy, or other suitable material. In this embodiment, pattern 120 may be formed by a suitable deposition process, such as sputtering and physical vapor deposition (PVD).

[0109] Intermediate structure 140 may include one or more intermediate layers made of an insulating material, such as silicon oxide or silicon nitride. In some embodiments, intermediate structure 140 may include a conductive layer, such as a metal layer or alloy layer. In some embodiments, one or more intermediate layers may be formed by a suitable film deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). After the intermediate layer is formed, a thermal operation, such as rapid thermal annealing, may be performed. In other embodiments, a planarization operation, such as chemical mechanical polishing (CMP), may be performed. In other embodiments, a removal operation, such as an etching process, may be performed. The etching process may include, for example, a dry etching process or a wet etching process. It is understood that additional operations may be provided before, during, and after the above processes, and some of the above operations may be replaced or omitted for other embodiments of the method. The order of operations / processes may be interchanged.

[0110] Figure 4B It is along Figure 3A cross-sectional view taken along the cutting line B-B'.

[0111] like Figure 3 and Figure 4B As shown, pattern 130 is disposed on intermediate structure 140. In some embodiments, pattern 130 may be a plurality of openings defined by mask 150. Mask 150 may be formed on intermediate structure 140 and will be removed in a subsequent process. Mask 150 may include a positive or negative photoresist (such as a polymer), or a hard mask (such as silicon nitride or silicon oxynitride). The layer including mask 150 and pattern 130 may be patterned using a suitable photolithography process, for example, forming a photoresist layer on intermediate structure 140, exposing the photoresist layer to a pattern through a mask, baking and developing the photoresist to form mask 150 and pattern 130. Mask 150 can then be used to define the pattern into intermediate structure 140, such that the portion of intermediate structure 140 exposed to pattern 130 can be removed.

[0112] Because multiple semiconductor processes are performed after pattern 120 is formed, the outline of pattern 120 may be deformed and have an asymmetrical profile. The deformed pattern 120 may result in a relatively large deviation in the overlay error estimate.

[0113] Figure 5 This is a top view illustrating the stacked reference numeral 210 of some embodiments of the present disclosure.

[0114] Overlay marks 210 may include various features on substrate 100, such as patterns 220 and 230. Pattern 220 may be a pattern of a preceding layer. Pattern 230 may be a pattern of a current layer. The preceding layer (or lower layer) may be located at a different horizontal level than the current layer (or upper layer). Each pattern 220 (or pattern 230) may be located in one of four orthogonal destination regions, two of which are used to measure overlay error in the X direction and two of which are used to measure overlay error in the Y direction.

[0115] In some embodiments, pattern 220 may include the same material as an isolation feature and may be located at the same elevation as the isolation feature. In some embodiments, pattern 220 may include the same material as a gate structure and may be located at the same elevation as the gate structure. In some embodiments, pattern 220 may include the same material as a conductive via and may be located at the same elevation as the conductive via.

[0116] In some embodiments, each pattern 220 may have multiple sub-patterns 222, 224, and 226. In some embodiments, each sub-pattern 222, 224, and 226 may have different outlines in a plan view. In some embodiments, each sub-pattern 222, 224, and 226 may have different dimensions (e.g., surface area in a plan view).

[0117] Each sub-pattern 222 may extend along a first direction, such as the Y direction. Multiple sub-patterns 222 may be arranged along a second direction, such as the X direction. In some embodiments, each sub-pattern 222 may have, for example, a rectangular outline.

[0118] Multiple subpatterns 224 may be arranged along a second direction. Each subpattern 224 may extend along a third direction, which is inclined relative to the X and Y directions. For example, a subpattern 224 may have a first edge and a second edge inclined relative to the first edge. The first edge may extend along the second direction, while the second edge may extend along the third direction. In some embodiments, the subpattern 224 may be inclined relative to the subpattern 222. In some embodiments, the size of the subpattern 224 may be larger than (or exceed) the size of the subpattern 222. In some embodiments, the spacing between the multiple subpatterns 224 may be greater along the second direction than the spacing between the multiple subpatterns 222. In some embodiments, the number of subpatterns 224 may be different from the number of subpatterns 222. In some embodiments, the number of subpatterns 224 may be less than the number of subpatterns 222. In some embodiments, each subpattern 224 may have, for example, a parallelogram outline.

[0119] Multiple subpatterns 226 may be arranged along a second direction. Each subpattern 226 may have multiple segments 226d arranged along a first direction. In some embodiments, the size of each segment 226d may be smaller than the size of each subpattern 222. In some embodiments, the spacing between the multiple subpatterns 226 may be the same as the spacing between the multiple subpatterns 222 along the second direction. In some embodiments, the segments of the subpattern 226 may have, for example, a rectangular outline. Although Figure 5 It is explained that secondary pattern 224 is disposed between secondary patterns 222 and 226, but the relative positions of secondary patterns 222, 224 and 226 can be modified. For example, in other embodiments, secondary pattern 222 may be disposed between secondary patterns 224 and 226.

[0120] Pattern 230 may have multiple sub-patterns 232. Each sub-pattern 232 may extend along a first direction. The multiple sub-patterns 232 may be arranged along a second direction. In some embodiments, the length of the sub-patterns 232 may be greater than the length of the sub-patterns 222 along the first direction. In some embodiments, the spacing between the multiple sub-patterns 232 may be the same as the spacing between the multiple sub-patterns 222 along the second direction. In some embodiments, the spacing between the multiple sub-patterns 232 may be less than the spacing between the multiple sub-patterns 224 along the second direction. In some embodiments, each sub-pattern 232 may have, for example, a rectangular outline. In some embodiments, pattern 220 may consist of sub-patterns having two or more different outlines, while pattern 230 may consist of sub-patterns having a single outline.

[0121] Although Figure 5 It is not shown in the figure, but it should be noted that an intermediate structure can be set to overlay pattern 220, and pattern 230 is set on the intermediate structure.

[0122] When measuring a stacking error using a stacking mark (such as stacking mark 210), the deviation in the X direction is measured along a straight line in the X direction of stacking mark 210. The deviation in the Y direction is further measured along a straight line in the Y direction of stacking mark 210. A single stacking mark, including patterns 220 and 230, can be used to measure a deviation in one X direction and one Y direction between two layers on a substrate. Whether a layer and its predecessor are precisely aligned can be determined from the deviations in the X and Y directions. Stacking error may include deviation in the X direction (ΔX), deviation in the Y direction (ΔY), or a combination of both.

[0123] More specifically, the images of patterns 220 and 230 obtained from the overlay measurement equipment can be used to calculate the overlay error. As mentioned above, multiple semiconductor manufacturing processes are performed after pattern 220 is formed; the outline of pattern 220 may be deformed and have an asymmetrical outline. To obtain a more realistic overlay error, the overlay error obtained from the overlay measurement equipment can be further corrected. An overlay correction system can receive optical image information from the pattern of the previous layer and the pattern of the current layer, and then generate multiple correction data corresponding to each corresponding correction parameter. Thus, the overlay correction system can generate a corrected overlay error. A controller (e.g., a computer) then sends a signal instructing how to adjust the exposure equipment according to the corrected overlay error. Therefore, the exposure equipment used to define pattern 230 will be adjusted according to the corrected overlay error. In some embodiments, the correction data can be configured to generate an offset value in the X direction, an offset value in the Y direction, or a combination of both, to compensate for the overlay error.

[0124] Because one or more semiconductor processes are performed on the wafer after the front layer is formed, the outline of the overlay marks in the front layer may be deformed and have an asymmetrical outline due to different processes, such as a deposition process, an etching process, a chemical mechanical polishing process, or other processes. Therefore, the overlay error based on these deformed patterns of the front layer may deviate from reality. It has been found that each unit of the correction data may have different degrees of error depending on the patterns with different outlines. That is, a set of correction data may have a smaller error (or deviation from reality) based on pattern A, while having a larger error based on pattern B, whose outline differs from that of pattern A. Another set of correction data may have the opposite result: a larger error based on pattern A, and a smaller error based on pattern B.

[0125] For example, the overlay correction system may include multiple sets of correction parameters, such as inter-field spread and inter-field rotation. If an etching process is performed after the previous layer is formed, the correction data generated by subpattern 224 (generated by correction parameters related to inter-field spread) may have a small error relative to the actual situation. If a chemical mechanical polishing is performed after the previous layer is formed, the correction data generated by subpattern 226 (generated by correction parameters related to inter-field rotation) may have a small error relative to the actual situation. The correction data generated by subpattern 222 (generated by correction parameters not related to inter-field spread and inter-field rotation) may also have a small error relative to the actual situation. By selecting correction data with a small deviation from the actual situation, the corrected overlay error with a small deviation can be estimated.

[0126] As described above, correction data from different patterns (or subpatterns) may have varying degrees of error. In embodiments of this disclosure, the front layer may include patterns with different profiles, each pattern used to generate a series of respective correction data. These correction data from different subpatterns can be selected to obtain a corrected overlay error with a smaller deviation from the actual situation. The exposure apparatus will be adjusted according to the corrected overlay error, and the alignment accuracy between the front and current layers will be improved in subsequent semiconductor processes.

[0127] Figure 6 This is a top view illustrating some embodiments of the present disclosure, specifically the stacked reference 210'.

[0128] Figure 6 The stacking mark 210' shown can be used with Figure 5 The overlay mark 210 shown is similar, but the composition of pattern 220' is different. In some embodiments, the CMP process can be omitted after forming the front layer, and pattern 220' can be composed of subpatterns 222 and 224. In this embodiment, correction parameters that are not part of the inter-field spread can be selected from subpattern 222 to generate correction data.

[0129] As mentioned above, correction data from different patterns (or subpatterns) may have varying degrees of error. In this embodiment, the front layer may include patterns with different contours, which can be used to generate a correction overlay error with minimal deviation from the actual situation. The exposure equipment will be adjusted based on this correction overlay error, improving the alignment accuracy between the front and current layers in subsequent semiconductor processes.

[0130] Figure 7 This is a top view of the stacked reference 210, which illustrates some embodiments of this disclosure.

[0131] Figure 7 The overlay mark 210 shown can be used with Figure 5The overlay mark 210 shown is similar, but the composition of pattern 220” is different. In some embodiments, the etching process can be omitted after the formation of the front layer, and pattern 220” can be composed of sub-patterns 222 and 226. In this embodiment, correction parameters that do not belong to inter-field rotation can be selected from sub-pattern 222 to generate correction data.

[0132] As mentioned above, correction data from different patterns (or subpatterns) may have varying degrees of error. In this embodiment, the front layer may include patterns with different contours, which can be used to generate a correction overlay error with minimal deviation from the actual situation. The exposure equipment will be adjusted based on this correction overlay error, improving the alignment accuracy between the front and current layers in subsequent semiconductor processes.

[0133] Figure 8 This is a block diagram illustrating a semiconductor fabrication system 300 according to some embodiments of the present disclosure.

[0134] The semiconductor fabrication system 300 may include multiple fabrication devices 310, 320-1, ..., 320-N, an exposure device 330, and an overlay measurement device 340. The fabrication devices 310, 320-1, ..., 320-N, the exposure device 330, and the overlay measurement device 340 may be coupled to a controller 360 and an overlay (OVL) calibration system 370 via a network 350.

[0135] Manufacturing equipment 310 can be configured to form patterns in the preceding layer, for example Figure 5 The pattern 220 is shown in the figure. In some embodiments, the manufacturing apparatus 310 may be configured to form an isolation structure, a gate structure, a conductive via, or other layers. Manufacturing apparatuses 320-1, ..., and 320-N may be configured to form an intermediate structure, such as... Figure 4A The intermediate structure 140 is shown. Each of the manufacturing equipment 320-1, ..., and 320-N can be configured to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

[0136] Exposure equipment 330 can be configured to form a pattern in the current layer, for example Figure 5 Pattern 230 is shown.

[0137] The overlay measuring device 340 can be configured to obtain optical images of the patterns of the previous layer and the current layer, and generate an overlay error based on the optical images of the patterns of the previous layer and the current layer.

[0138] Network 350 can be the Internet or an internal network using network communication protocols such as Transmission Control Protocol (TCP). Through network 350, each manufacturing device 310, 320-1-320-N, exposure device 330, and stack-up measurement device 340 can download or upload work-in-process (WIP) information about wafers or manufacturing equipment from controller 360 or stack-up calibration system 370.

[0139] The controller 360 may include a processor, such as a central processing unit (CPU), to generate a correction overlay error based on the overlay measurement device 340 and the correction data generated from the overlay correction system 370.

[0140] The overlay correction system 370 may include correction parameters related to information of the optical image, and thus correction data can be generated from the corresponding correction parameters. The overlay correction system 370 may include, for example, a computer or a server. In some embodiments, the correction data may be generated or calculated via program code or a programming language. In some embodiments, the deviation in the X direction (ΔX), the deviation in the Y direction (ΔY), or a combination of both may be generated by a formula including correction parameters. Although Figure 8 The overlay correction system 370 is signal-connected to the overlay measurement device 340 via network 350, but this disclosure is not intended to be limiting. In other embodiments, the overlay correction system 370 may be a program built into the overlay measurement device 340.

[0141] although Figure 8 No other manufacturing equipment is shown preceding manufacturing equipment 310, but this exemplary embodiment is not intended to be limiting. In other exemplary embodiments, various manufacturing equipment may be arranged preceding manufacturing equipment 310 and may be used to perform various processes according to design requirements.

[0142] In an exemplary embodiment, wafer 301 is transferred to manufacturing equipment 310 to initiate a series of different processes. Wafer 301 may form at least one layer of material through various stages of processes. This exemplary embodiment is not intended to limit the processes of wafer 301. In other exemplary embodiments, wafer 301 may include various layers, or any stage between the start and finish of a product, prior to being transferred to manufacturing equipment 310. In an exemplary embodiment, wafer 301 may be processed sequentially by manufacturing equipment 310, 320-1 to 320-N, exposure equipment 330, and stack-up measurement equipment 340.

[0143] Figure 9 The flowchart illustrates a method 400 for generating correction data from an overlay correction system in various aspects of this disclosure.

[0144] Method 400 begins with operation 410, in which an overlay correction system, such as overlay correction system 370, is provided. In some embodiments, overlay correction system 370 may include a plurality of correction parameters P1, P2, ... and PN, which can be used to generate a corresponding correction data or a correction overlay error.

[0145] Method 400 continues with operation 420, in which information about an optical image is provided. For example, the optical image may be generated from patterns (or sub-patterns) A, B, C, and D, and information about the optical image may be uploaded to a network. In some embodiments, patterns or sub-patterns A, B, C, and D may correspond to sub-patterns 222, 224, 226, and 230, respectively.

[0146] Method 400 continues with operation 430, in which correction data is generated. In some embodiments, pattern (or sub-pattern) A can be used to generate correction data a1 from parameter P1, correction data a2 from parameter P2, and so on. Thus, correction data a1, a2, ..., and aN are generated based on pattern or sub-pattern A and correction parameters P1-PN. Similarly, correction data b1, b2, ..., and bN are generated based on pattern (or sub-pattern) B and correction parameters P1-PN, correction data c1, c2, ..., and cN are generated based on pattern (or sub-pattern) C and correction parameters P1-PN, and correction data d1, d2, ..., and dN are generated based on pattern (or sub-pattern) D and correction parameters P1-PN.

[0147] Method 400 continues with operation 440, in which a corrected overlay error is generated. The corrected overlay error can be generated based on the correction data of the corresponding parameters P1-PN. The corrected overlay error can be expressed by a formula that includes the offset value in the X direction, the offset value in the Y direction, or a combination of both, and the overlay error generated from the overlay measurement device.

[0148] In some other embodiments, operation 430 may be omitted. In this embodiment, the correction of overlay errors, including deviations in the X direction (ΔX), deviations in the Y direction (ΔY), or combinations thereof, may be generated by correction parameters. Each deviation in the X direction (ΔX), deviation in the Y direction (ΔY), or combination thereof, may be expressed by a formula that includes the correction parameters as variables. When information of the optical image is received, these variables can be determined, thus generating the deviations in the X direction (ΔX), deviations in the Y direction (ΔY), or combinations thereof.

[0149] Figure 10 , Figure 11 and Figure 12 This is a flowchart illustrating the overlay correction method 500 of various aspects of this disclosure.

[0150] Reference Figure 10 The calibration method 500 begins with operation 510, in which a wafer is received. The wafer may include a semiconductor substrate, such as a silicon substrate. The wafer may include a plurality of chips separated by dicing lines.

[0151] The correction method 500 continues with operation 520, wherein a first pattern (e.g., a front-layer pattern) is formed by a first manufacturing apparatus. Prior to forming the first pattern, multiple processes can be performed on the substrate of the wafer to form a plurality of features beneath the first pattern. In some embodiments, the first pattern may include a dielectric material, a conductive material, or other suitable material. In some embodiments, the first pattern may be formed in operations configured to form, for example, gate structures, isolation features, conductive vias, or other features. In some embodiments, the first pattern may correspond to... Figure 5 Pattern 220 is shown.

[0152] Reference Figure 11 Operation 520 may include operations 522, 524, and 526, wherein a plurality of first, second, and third patterns are formed. In some embodiments, the first, second, and third patterns may be formed simultaneously. In some embodiments, each of the first, second, and third patterns may correspond to... Figure 5 The subpatterns 222, 224 and 226 are shown.

[0153] Back Figure 10 The correction method 500 continues with operation 530, wherein after the first pattern is formed, multiple processes are performed on the substrate of the wafer. These processes can be used to form an intermediate layer covering the first pattern. The intermediate layer can be formed by multiple manufacturing equipment that can be used to perform a deposition process, an etching process, a chemical mechanical polishing process, a photoresist coating process, a baking process, an alignment process, or other processes.

[0154] The correction method 500 continues with operation 540, wherein a second pattern (e.g., a layer) is formed using an exposure apparatus. In some embodiments, the second pattern may be an opening pattern of a mask, such as photoresist. In some embodiments, the second pattern may correspond to... Figure 5 Pattern 230 is shown.

[0155] The correction method 500 continues to operation 550, wherein an overlay error related to movement along the X and Y directions is generated by the overlay measurement device. In some embodiments, a first pattern, including a plurality of optical images of a first, second, third, and second pattern, is generated by the overlay measurement device, and an overlay error can be generated based on these optical images. In some embodiments, the overlay error may include a deviation (ΔX) in the X direction, a deviation (ΔY) in the Y direction, or a combination of both.

[0156] The correction method 500 continues with operation 560, in which a corrected overlay error is generated by correcting the overlay error obtained in operation 550. In some embodiments, an offset value in the X direction, an offset value in the Y direction, or a combination of both may be generated to compensate for the overlay error generated in operation 550. In some embodiments, the corrected overlay error may be determined or calculated based on the operation for forming the aforementioned intermediate layer located below the current layer, such as operation 530.

[0157] Reference Figure 12 Operation 560 may include operations 562, 564, 566, and 568. Operation 562 may include classifying the correction parameters into first, second, and third groups. For example, the correction parameters may be classified into a first group related to inter-field spread, a second group related to inter-field rotation, and a third group that does not belong to the first or second groups.

[0158] Operation 564 may include operations 5641, 5642, and 5643, wherein a first correction data, a second correction data, and a third correction data are generated from the first, second, and third patterns. Each of the first, second, or third patterns can be used to generate the first, second, and third correction data. That is, correction data for nine units can be generated based on the first, second, and third patterns. The first, second, and third correction data may correspond to the first, second, and third sets of correction parameters, respectively.

[0159] Operation 566 may include selecting data for generating correction overlay errors. In some embodiments, first correction data is selected from a first pattern, second correction data is selected from a second pattern, and third correction data is selected from a third pattern.

[0160] For example, correction parameters P1, P2, ..., and P9, as well as parameters P1, P2, and P3, belong to the first group; parameters P4, P5, and P6 belong to the second group; and parameters P7, P8, and P9 belong to the third group. Correction data a1, a2, ..., and a9 are generated from the first group of subpatterns, correction data b1, b2, ..., and b9 are generated from the second group of subpatterns, and correction data c1, c2, ..., and c9 are generated from the third group of subpatterns. In this embodiment, correction data a1, a2, a3, b4, b5, b6, c7, c8, and c9 are selected to generate offset values ​​in the X direction, offset values ​​in the Y direction, or a combination of both. Therefore, a correction overlay error can be generated based on the aforementioned offsets and the overlay error generated in operation 550.

[0161] In other embodiments, the number of groups of correction parameters may be determined by the process performed on the wafer in operation 530. In some embodiments, an etching process or a chemical mechanical polishing process may be omitted, and the correction parameters may be divided into two groups accordingly. In this case, if there are correction parameters P1, P2, ... and P9, correction data a1-a6 can be selected from the first group of subpatterns, and correction data b7-b9 can be selected from the second group of subpatterns to generate a correction for overlay error. In other embodiments, the number of groups of correction parameters may be greater than 3 depending on how the process is classified, thus classifying the correction parameters according to the classified process.

[0162] Operation 568 may include generating a corrected overlay error based on the overlay error and selected correction data. Operation 568 may be executed by a controller, for example... Figure 8 The controller 360 shown.

[0163] Operations 562, 564, 566, and / or 568 can be performed by the overlay correction system, for example... Figure 8 The overlay correction system 370 shown is illustrated.

[0164] In other embodiments, operations 564, 566, and 566 can be omitted. In this embodiment, the correction of overlay errors, including deviations in the X direction (ΔX), deviations in the Y direction (ΔY), or combinations thereof, can be generated by correction parameters. Each deviation in the X direction (ΔX), deviation in the Y direction (ΔY), or combination thereof, can be expressed by a formula that includes correction parameters as variables. For example, correction parameters P1, P2, ..., P9, and parameters P1, P2, and P3 belong to the first group, parameters P4, P5, and P6 belong to the second group, and parameters P7, P8, and P9 belong to the third group. The variables including correction parameters P1-P3, P4-P6, and P7-P9 can be determined from the optical information of the first group of subpatterns, the second group of subpatterns, and the third group of subpatterns, respectively. Therefore, the correction of overlay errors can be determined.

[0165] Reference Figure 10 The correction method 500 then proceeds to operation 570, wherein the exposure apparatus is adjusted according to the correction of the overlay error. In some embodiments, operation 570 may include adjusting the position of a mask of the exposure apparatus so that the next exposure process can be performed with a smaller overlay error.

[0166] The correction method 500 includes classifying correction parameters into different groups. As mentioned above, correction data from different patterns (or subpatterns) may have varying degrees of error. In this embodiment, the front layer may include patterns with different contours, which can be used to generate a correction for overlay error with smaller deviations from the actual situation. The exposure apparatus will be adjusted according to this correction for overlay error, and the alignment accuracy between the front and current layers will be improved in subsequent semiconductor processes.

[0167] The correction method 500 is merely an example and is not intended to limit the scope of this disclosure beyond what is expressly stated in the claims. Additional operations may be provided before, during, or after each operation of method 500, and some of these operations may be replaced, eliminated, or moved for additional embodiments of the method. In some embodiments, the correction method 500 may also include... Figures 10 to 12 Operations not depicted herein. In some embodiments, the correction method 500 may include... Figures 10 to 12 One or more operations described in the document.

[0168] Figures 10 to 12 The process described herein can be implemented in a controller 360, or in a computing system that organizes the fabrication of wafers by controlling each part or portion of the manufacturing equipment in the facility. Figure 13 This is a block diagram illustrating the hardware of a semiconductor fabrication system 600 according to various aspects of this disclosure. System 600 includes a processor 601 with one or more hardware components and a non-transitory computer-readable storage medium 603 encoded with, i.e., storing, program code (i.e., a set of executable instructions). The computer-readable storage medium 603 may also be encoded with instructions for interfacing with manufacturing equipment used to produce semiconductor components. Processor 601 is electrically coupled to computer-readable storage medium 603 via bus 605. Processor 601 is also electrically coupled to input and output (I / O) interface 607 via bus 605. Network interface 609 is also electrically connected to processor 601 via bus 605. The network interface is connected to a network, thus enabling processor 601 and computer-readable storage medium 603 to be connected to external components via network 350. Processor 601 is configured to execute computer program code encoded in computer-readable storage medium 605, thereby enabling system 600 to perform operations such as... Figures 10 to 12 Some or all of the operations described in the method shown.

[0169] In some exemplary embodiments, processor 601 may be, but is not limited to, a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit. Various circuits or units are within the scope of this disclosure.

[0170] In some exemplary embodiments, the computer-readable storage medium 603 may be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 603 includes a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random access memory (RAM), a read-only memory (ROM), a hard disk, and / or an optical disc. In one or more exemplary embodiments using an optical disc, the computer-readable storage medium 603 further includes an optical disc-read-only memory (CD-ROM), an optical disc-read / write (CD-R / W), and / or a digital video optical disc (DVD).

[0171] In some exemplary embodiments, storage medium 603 stores computer program code configured to be executed by system 600. Figures 8 to 12 The method shown. In one or more exemplary embodiments, storage medium 601 also stores the execution of... Figures 8 to 12 The methods shown require information and information generated during the execution of these methods, and / or a set of executable instructions for execution. Figures 8 to 12 The operation of the method shown. In some exemplary embodiments, a user interface 610 may be provided, for example, a graphical user interface (GUI), for a user to operate on system 600.

[0172] In some exemplary embodiments, storage medium 603 stores instructions for interfacing with an external machine. These instructions enable processor 601 to generate instructions readable by the external machine for efficient execution during analysis. Figures 8 to 12 The method shown.

[0173] System 600 includes an input and output (I / O) interface 607. The I / O interface 607 is connected to external circuitry. In some exemplary embodiments, the I / O interface 607 may include, but is not limited to, a keyboard, keypad, mouse, trackball, touchpad, touchscreen, and / or cursor arrow keys, for transmitting information and commands to processor 601.

[0174] In some exemplary embodiments, the I / O interface 607 may include a display, such as a cathode ray tube (CRT), a liquid crystal display (LCD), a speaker, etc. For example, the display shows information.

[0175] System 600 may also include a network interface 609 coupled to processor 601. Network interface 609 allows system 600 to communicate with network 350, where one or more other computer systems are connected. For example, system 600 may connect via network interface 609 to manufacturing equipment 310, 320-1, ..., 320-N, exposure equipment, stack measurement equipment 340, and stack correction system 370.

[0176] One aspect of this disclosure provides an overlay correction mark. The mark includes a first pattern and a second pattern. The first pattern is disposed on a substrate and located at a first water level. The first pattern includes a plurality of first patterns and a plurality of second patterns. The first patterns extend along a first direction and are arranged along a second direction different from the first direction. The second patterns are arranged along the second direction, wherein the outline of each of the plurality of first patterns is different from the outline of each of the plurality of second patterns. The second pattern is disposed at a second horizontal level different from the first water level.

[0177] Another aspect of this disclosure provides a method for correcting overlay errors. The method includes: obtaining an overlay error based on a lower layer pattern and an upper layer pattern of a wafer, wherein the lower layer pattern is obtained by a first manufacturing apparatus through which the wafer passes, and the upper layer pattern is obtained by an exposure apparatus; generating a corrected overlay error based on the overlay error and a process performed on the wafer after the first manufacturing apparatus and before the exposure apparatus; and adjusting the exposure apparatus based on the corrected overlay error.

[0178] Another aspect of this disclosure provides a method for correcting overlay errors. The method includes: receiving a wafer having a substrate; forming a first pattern on the substrate of the wafer; performing multiple processes on the wafer; forming a second pattern on the first pattern of the wafer using an exposure apparatus; obtaining an overlay error based on the first and second patterns of the wafer; generating a corrected overlay error based on the overlay error and the multiple processes; and adjusting the exposure apparatus based on the corrected overlay error.

[0179] Embodiments of this disclosure disclose an overlay mark for measuring overlay error. The front layer of the overlay mark may include different sub-patterns so that correction data can be generated from each sub-pattern. Selecting correction data from a specific sub-pattern can refine the correction of overlay error, thus making the correction of overlay error more realistic.

[0180] While this disclosure and its advantages have been described in detail, it should be understood that other changes, substitutions, and alternatives may be made without departing from the concept and scope of this disclosure as defined by the published claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0181] Furthermore, the scope of this disclosure is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used in accordance with this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims disclosed in this disclosure.

Claims

1. A method for correcting overlay error, comprising: A stacking error is obtained based on a lower layer pattern and an upper layer pattern of a wafer, wherein the lower layer pattern is obtained by a first manufacturing device through which the wafer passes, and the upper layer pattern is obtained by an exposure device. A corrective overlay error is generated based on the overlay error and a process performed on the wafer after the first manufacturing equipment and before the exposure equipment. The lower layer pattern includes multiple first patterns and multiple second patterns, and the outline of each of the multiple first patterns is different from the outline of each of the multiple second patterns; The multiple correction parameters are divided into a first group of correction parameters and a second group of correction parameters; A first corresponding data for the first set of correction parameters is obtained from the plurality of first patterns, and a second corresponding data for the second set of correction parameters is obtained from the plurality of second patterns; and The corrected overlay error is generated based on the overlay error, the first corresponding data, and the second corresponding data; and The exposure equipment is adjusted according to the correction of the overlay error.

2. The correction method as described in claim 1, further comprising: The first corresponding data of the first set of correction parameters is obtained from the plurality of first patterns, and the third corresponding data of the third set of correction parameters is obtained from the plurality of second patterns; and Select the first corresponding data and the third corresponding data to determine the corrected overlay error.

3. The correction method as described in claim 1, wherein the spacing between the plurality of second patterns is different from the spacing between the plurality of first patterns.

4. The correction method of claim 1, wherein in a plan view, each of the plurality of second patterns extends along a third direction different from the first and second directions.

5. The correction method of claim 1, wherein each of the plurality of second patterns comprises a plurality of segments arranged along a first direction.

6. The correction method of claim 1, wherein in a plan view, the size of each of the plurality of second patterns is different from the size of each of the plurality of first patterns.

7. The correction method as claimed in claim 1, wherein the number of the plurality of second patterns is different from the number of the plurality of first patterns.

8. The correction method of claim 1, wherein the process includes at least one of an etching process, a deposition process, and a chemical mechanical polishing process.

9. The correction method of claim 1, wherein adjusting the exposure equipment includes adjusting the position of a mask of the exposure equipment.

10. A method for correcting overlay error, comprising: Receive a wafer with a substrate; A first pattern is formed on the substrate of the wafer; An intermediate structure is formed to cover the first pattern; A second pattern is formed on the intermediate structure using an exposure device; An overlay error is obtained based on the first and second patterns of the wafer; Based on this overlay error, a corrected overlay error is generated; The formation of the first pattern includes: Forming multiple first patterns; and Multiple secondary patterns are formed, wherein the outline of each of the multiple primary patterns is different from the outline of each of the multiple secondary patterns; The factors that cause this correction overlay error include: The multiple correction parameters are divided into a first group of correction parameters and a second group of correction parameters; A first corresponding data for the first set of correction parameters is obtained from the plurality of first patterns, and a second corresponding data for the second set of correction parameters is obtained from the plurality of second patterns; and The corrected overlay error is generated based on the overlay error, the first corresponding data, and the second corresponding data; and The exposure equipment is adjusted according to the correction of the overlay error.

11. The correction method as described in claim 10, further comprising: The first corresponding data of the first set of correction parameters is obtained from the plurality of first patterns, and the third corresponding data of the third set of correction parameters is obtained from the plurality of second patterns; and Select the first corresponding data and the third corresponding data to determine the corrected overlay error.

12. The correction method of claim 10, wherein in a plan view, each of the plurality of secondary patterns extends along a third direction different from the first and second directions, each of the plurality of secondary patterns includes a plurality of segments arranged along the first direction, and the spacing of the plurality of secondary patterns is different from the spacing of the plurality of primary patterns.

13. The correction method of claim 10, wherein in a plan view, the size of each of the plurality of secondary patterns is different from the size of each of the plurality of primary patterns, and the number of the plurality of secondary patterns is different from the number of the plurality of primary patterns.

14. The correction method of claim 10, wherein the intermediate structure is formed by at least one process including an etching process, a deposition process and a chemical mechanical polishing process.

15. The correction method of claim 10, wherein adjusting the exposure apparatus includes adjusting the position of a mask of the exposure apparatus.

Images