System and method for clock generation in asymmetric image separators

Abstract

This document describes systems and methods for providing image streaming applications using asymmetric image splitters. In one embodiment, a system supporting multi-stream image transmission includes an asymmetric image splitter engine that splits a superframe image stream into two or more image streams, and a fractional clock divider circuit. The fractional clock divider may include a digital feedback control loop and a one-bit Σ-Δ modulator. The fractional clock divider circuit can provide a compatible display clock frequency for each of the two or more image streams. When the multi-stream image stream comprises two image streams, the asymmetric image splitter engine adjusts the vertical asymmetry of the first image stream, which has the shortest height, to the same height as the second image stream by adding vertical padding to the first image stream, which has the shortest height. The superframe image stream may include image streams from video, LiDAR, radar, or other sensors.

Description

[0001] This application is a divisional application of the same patent application filed on June 12, 2019, with application number 201910514395.X.

[0002] Cross-reference to related applications

[0003] This patent application relates to co-pending and co-owned U.S. Provisional Patent Application No. 62 / 684,326, filed June 13, 2018, entitled “SYSTEMS AND METHODS FOR ASYMMETRIC DUAL-VIEW CLOCKGENERATION”, and claims priority to it under 35 USC §119(e), the patent document of which is incorporated herein by reference in its entirety and for all purposes.

[0004] A. Technical Field

[0005] This disclosure generally relates to systems and methods for serializer / deserializer (SerDes) communication. More specifically, this disclosure relates to systems and methods for asymmetric image separator applications.

[0006] B. Background Technology

[0007] Gigabit Multimedia Serial Link (GMSL) serializers and deserializers (SerDes) can support the high bandwidth, complex interconnects, and data integrity requirements of a wide range of applications. For example, but not limited to, applications may include low-power requirements for cameras and a wide range of varying bandwidths for sensor data aggregation. Using shielded twisted-pair (STP) or coaxial cable up to 15 meters long, GMSL serializers and deserializers can meet the stringent electromagnetic compatibility (EMC) requirements of the automotive and other industries. In some embodiments, applications may include future automotive infotainment systems and advanced driver assistance systems (ADAS).

[0008] Spread spectrum capabilities can be built into each serializer and deserializer IC to improve the electromagnetic interference (EMI) performance of the link without the need for an external spread spectrum clock. Interoperability between the serializers and deserializers within the series allows for the use of different interfaces at each end of the link. In addition to driving high-resolution center / rear-seat displays and dashboards, the GMSL SerDes system can also be used in megapixel camera systems.

[0009] In some embodiments, an asymmetric image splitter (e.g., an asymmetric side-by-side dual-view splitter engine) can be used to implement a GMSL SerDes system to receive a single super-video stream containing multiple display images. To generate video clocks for the individual displays within the video multistreaming system, a phase-locked loop (PLL) oscillator can be utilized in the asymmetric image splitter block. The PLL may require additional cost, size, and power consumption.

[0010] Therefore, there is a need for a system and method that can implement an asymmetric image separator clock generation block without the need for a PLL. Attached Figure Description

[0011] Reference will be made to embodiments of the invention, examples of which may be illustrated in the accompanying drawings. These drawings are intended to be illustrative and not restrictive. Although the invention has been described in general within the context of these embodiments, it should be understood that it is not intended to limit the scope of the invention to these specific embodiments.

[0012] Figure 1A The functionality of a serializer / deserializer (SerDes) according to various embodiments of this disclosure is demonstrated.

[0013] Figure 1B Two configurations for video multi-stream transmission according to various embodiments of the present disclosure are described.

[0014] Figure 2A , Figure 2B and Figure 2C Multi-stream video transmission and video separation are described according to various embodiments of the present disclosure.

[0015] Figure 3 Fractional clock dividers according to various embodiments of the present disclosure are described.

[0016] Figure 4 A configuration with a fractional clock divider integrated in a serializer for video multistream transmission according to an embodiment of the present invention is described.

[0017] Figure 5 A simplified block diagram of a computing device / information processing system according to embodiments of this document is depicted. Detailed Implementation

[0018] In the following description, specific details are set forth for purposes of explanation in order to provide an understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these details. Furthermore, those skilled in the art will recognize that the embodiments of the invention described below can be implemented in various ways, such as processes, apparatuses, systems, devices, or methods, on tangible computer-readable media.

[0019] The components or modules shown in the figures illustrate exemplary embodiments of the invention and are intended to avoid obscuring the invention. It should also be understood that throughout this discussion, a component can be described as a separate functional unit that may include subunits; however, those skilled in the art will recognize that various components or portions thereof may be divided into separate components or may be integrated together, including within a single system or component. It should be noted that the functions or operations discussed herein can be implemented as components. Components can be implemented as software, hardware, or a combination thereof.

[0020] Furthermore, the connections between components or systems within the diagram are not intended to be limited to direct connections. However, data between these components may be modified, reformatted, or otherwise altered by intermediate components. Moreover, additional or fewer connections may be used. It should also be noted that the terms "coupled," "connected," or "communicatively coupled" should be understood to include direct connections, indirect connections via one or more intermediate devices, and wireless connections.

[0021] In this specification, references to "one embodiment," "preferred embodiment," "an embodiment," or "embodiments" mean that a specific feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment of the invention and may be included in more than one embodiment. Furthermore, the above phrases appearing in different places in this specification do not necessarily refer to the same embodiment or multiple embodiments.

[0022] Certain terms used in different places in this specification are for illustrative purposes and should not be construed as limiting. A service, function, or resource is not limited to a single service, function, or resource; the use of these terms may refer to a group of related services, functions, or resources, whether discrete or aggregated.

[0023] In addition, it should be noted that: (1) certain steps may be performed optionally; (2) the steps may not be limited to the specific order described herein; (3) these steps may be performed in different orders; and (4) certain steps may be performed simultaneously.

[0024] Figure 1AThe functionality of a serializer / deserializer (SerDes) 100 according to various embodiments of this disclosure is illustrated. The serializer / deserializer (SerDes) 100 can utilize multi-gigabit point-to-point connection technology. In practice, the SerDes 100 is a pair of functional blocks that can be used for high-speed communication to compensate for limited inputs and outputs. These blocks can convert data between a serial data interface and a parallel interface in each direction. In some embodiments, the SerDes 100 can provide data transmission on a single-wire / differential line to minimize the number of I / O pins and interconnects. A parallel clock SerDes can be used to serialize the parallel bus inputs, as well as data address and control signals. The serialized stream can be transmitted along with a reference clock. In some embodiments, the clock can be provided via a phase-locked loop (PLL) oscillator. The serialized stream can be referred to as a superframe image stream.

[0025] In some implementations of video applications, a 70MHz video clock may be required to achieve a resolution of 800×600 pixels. In another implementation, a 140MHz video clock frequency may be required to achieve a full HD resolution of 1920×1080 pixels.

[0026] In some embodiments, the multi-gigabit point-to-point connection technology is the Gigabit Multimedia Serial Link (GMSL) SerDes technology. GMSL technology can simultaneously transmit HD video, audio, control information, aggregated sensor data, and Gigabit Ethernet over a single 15-meter coaxial cable or a 10- to 15-meter shielded twisted-pair cable, while meeting automotive electromagnetic compatibility (EMC) specifications. Using coaxial and shielded twisted-pair cables reduces what would otherwise be a complex interconnect backbone, thus supporting multi-stream video transmission at a lower system cost. Compared to Ethernet, GMSL technology can transmit multi-megapixel images without compression. Thus, GMSL can support machine vision technologies where safety features such as object and pedestrian detection are becoming critical. Other embodiments utilizing data compression may result in artifacts and information loss, potentially limiting the ability to support machine vision.

[0027] Each GMSL SerDes IC features built-in spread spectrum capabilities, which reduce electromagnetic interference (EMI) on the link. The IC's coaxial power transmission architecture eliminates the need for additional power supplies or ground wires, addressing vehicle weight challenges. Utilizing an integrated bidirectional control channel, a single microcontroller can program the serializer, deserializer, and all connected peripherals. In one or more embodiments, this architecture eliminates the need for a remote-side microcontroller and its supporting components, simplifying design and reducing cost, size, and power consumption. Furthermore, the ability to daisy-chain multiple camera modules on the GMSL also reduces system cost and shortens design time. Built-in diagnostic capabilities enhance data integrity.

[0028] Figure 1B Two configurations for video multi-stream transmission according to various embodiments of this disclosure are described. For example... Figure 1B As shown, GMSL technology allows for video aggregation and video decoupling. Video system 110 includes SoC 111, serializers (SER 112, SER 113), deserializers (DES 116, DES 117), CID 118, and IC 119. (CID = Central Instrument Display; IC = Dashboard) SoC is a system-on-a-chip. As shown, SER 112 and SER 113 individually receive video signal 131 and video signal 132 from SoC 111, respectively. SER 112 and SER 113 process their respective video signals and generate video 114 and video 115, respectively. Video 114 and video 115 are coupled to DES 116 and DES 117, respectively, and generate CID 118 and IC 119, respectively. For video system 110, video signals from SoC 111 can be processed in parallel, thus requiring separate serializers and additional I / O interfaces. In one or more embodiments, the superframe image stream includes image streams from video, LIDAR (light detection and ranging), radar, or other sensors. The superframe image stream includes image streams that support advanced driver assistance systems (ADAS) or automotive infotainment applications.

[0029] Asymmetric image separator

[0030] In some other embodiments, video system 120 utilizes GMSL technology, which allows for video aggregation and video decoupling. As shown, video system 120 includes SoC 121, serializer SER 122, deserializers DES 125 and DES 126, CID 127, and IC 128. Figure 1BSER 122 receives multiple video signals 131 / 132 from SoC 121. The multiple video signals 131 / 132 include the contents of video signals 131 and 132. In other words, the multiple video signals 131 / 132 comprise two video signals and can be referred to as a superframe image stream. SER 122 includes an asymmetric image splitter and generates GMSL 123 and GSML 124. GSML 123 and GSML 124 are coupled to DES 125 and DES 126, respectively, and generate CID 127 and IC 128. Examples of asymmetric image splitters at the input of SER 122 may include, but are not limited to, an asymmetric side-by-side dual-view splitter. In some embodiments, multiple images in the input superframe can be formed side-by-side. As shown, utilizing GMSL technology can reduce infrastructure costs.

[0031] Many asymmetric image splitter blocks use PLLs to operate in order to generate video clocks for individual displays. Using PLLs to generate video clocks for individual displays can significantly increase power consumption and area consumption.

[0032] The number of displays in vehicles continues to increase. Traditionally, system designers need to associate a separate SOC video output port with each display. As the number of displays increases, this can mean needing more SOCs or having to choose SOCs with more video output ports, thus increasing costs. If the SOC video ports can be used to drive multiple displays using a single virtual channel, a cheaper SOC with fewer output ports can be used in the system, reducing costs.

[0033] In some embodiments, the asymmetric image splitter engine uses algorithms to operate in order to extract individual video images from multiple image inputs. This process may require the transmitter and receiver to be designed in advance through negotiation among multiple vendors.

[0034] Figure 2A , Figure 2B and Figure 2C Multistream video transmission and video separation according to various embodiments of the present disclosure are depicted. These figures include the following terms: HS = Horizontal Sync; VS = Vertical Sync; Tvbp = Vertical Trailing Edge Time; Tvfp = Vertical Leading Edge Time; Tvact = Vertical Active Time; Thbp = Horizontal Trailing Edge Time; Thfp = Horizontal Leading Edge Time; Thact = Horizontal Active Time; HAS = Horizontal Sync Active Time; BL = Blanking Line. Figure 2A , Figure 2B and Figure 2C An asymmetric image splitter is demonstrated, allowing multiple displays with different resolutions to be driven from the same SOC video output port. In some embodiments, Figure 2A and Figure 2B It can be implemented in SoC 121, and Figure 2C It can be implemented in SER 122 and displayed on DES 125 and DES 126.

[0035] Figure 2A Each video frame 200 and the input signal 202, including effective regions with video image 204 (diagonal pattern) and video image 206 (parallel line pattern), are combined side-by-side and top-aligned to form a superframe. As shown, video image 204 has a higher imager than video image 206. Located below and to the right of video image 206 are unused areas designated for padding and optional filling or blanking. The vertical asymmetry of the shorter image (video image 206) increases the memory requirements in the splitter device. To mitigate this problem, virtual video lines are used to vertically distribute the shorter image (i.e., video image 206) to match the height of the taller video stream (i.e., video image 204). Figure 2B Video frame 210 shows video images 206 that are already vertically distributed.

[0036] Line-stuffed superframes are transmitted from the SOC video port at a faster video clock frequency than the individual displays associated with the display of video images 204 and 212. The output of the system-on-chip (i.e., SoC 121) can be displayed via the output 214 of video frame 210.

[0037] according to Figure 2C Output 214 can be coupled to SER 222. When SER 222 receives a superframe from output 214, it separates video frame 210 into two displays with compatible display timing parameters and an associated display video clock frequency different from the superframe. In some embodiments, the clock frequency of the superframe is 200 MHz and the clock frequency of video image 228 (diagonal pattern) can be 148 MHz, and the clock frequency of video image 232 (square line pattern) can be 67 MHz. The term "clock frequency of video image" can also be referred to as "display clock".

[0038] A display (e.g., DES 125) receives signal GMSL 224 from SER 222 and generates video frame 220. Video frame 220 may include video image 228, which is generated from... Figure 2B The video image 204 is generated. Another display (e.g., DES 126) receives the signal GMSL 226 from SER 222 and generates video frame 230. Video frame 230 may include video image 232, which is generated from... Figure 2BThe video image 212 is generated. Therefore, the video in the superframe is separated into separate video streams. After separation, the individual video streams can be transmitted to a remote location using the same serial link or separate serial links.

[0039] Generation of each display clock

[0040] In some embodiments, display panels and timing controllers exhibit varying levels of flexibility when it comes to how data input streams are transmitted to the display panel. More expensive and sophisticated displays can accept burst and sporadic video input streams, while cheaper displays and timing controllers may be less flexible in their requirements for pixel clock frequency (PCLK) and display blanking timing parameters. Therefore, cheaper panels may require fully smooth video stream input. To enable consumers to use cheaper system components, it may be necessary to leverage the native PCLK frequency and blanking time parameters of each display to re-timing the video image from the superframe. Therefore, it may be necessary to generate any fraction of the superframe PCLK frequency to drive each display.

[0041] In some embodiments, the number of pixels in each frame, including the blanking time, can be determined by the pixel clock frequency ratio between all three images, including video image 228 (diagonal pattern), video image 232 (square pattern), and the superframe image. In basic video interfaces such as DSI, parallel, or LVDS between a SOC and a SerDes receiver, it is assumed that the number of pixels in each superframe is the same between frames. Additionally, it can be assumed that the display video interface clock frequency and the superframe video pixel clock frequency have an integer ratio relationship. This integer ratio is equal to M / N. For example, in a DSI interface, the video interface clock frequency differs from the video pixel clock frequency, which in some cases could be M / N = 67MHz / 200MHz. When the above assumptions are true, the input and output data stream ratios in the system are determined, and the system can generate separate display pixel clock signals in an open-loop manner without feedback using two large integer ratios.

[0042] On the other hand, in more complex standard video interfaces such as Camera Serial Interface (CSI) and Embedded Display Port (EDP), the video interface clock frequency and the superframe pixel clock frequency may not have an integer ratio. Therefore, fractional clock generation methods may be needed to support the generation of fractional video clocks, which cannot be expressed as a ratio of two integers related to the superframe pixel clock. Fractional clock generation methods have been designed to cover... Figure 3 The two scenarios shown are as follows. (DSI, CSI, EDP, and LVDS are video interface standards similar to HDMI: Display Serial Interface = DSI; Camera Serial Interface = CSI; Embedded Display Port = EDP; Low Voltage Differential Signaling = LVDS.)

[0043] Figure 3 A fractional clock divider 300 according to various embodiments of the present disclosure is depicted. N is the number of pixels in a superframe, and M is the number of pixels in a split frame.

[0044] To cover the fundamental case where a slow pixel clock can be represented as a ratio of two large integers, a first-order, one-bit dedicated Σ-Δ modulator was developed, as shown in box 303. In conventional Σ-Δ modulators, the base of the Δ component is always a multiple of two. In this application, Σ equals the number of pixels in the separated display frame (M 301), while Δ equals the number of pixels in the superframe (e.g., N 302). Since the number of pixels in the superframe is not a power of two, the requirement that Δ be a power of two is unacceptable for conventional Σ-Δ modulators. Therefore, the dedicated Σ-Δ modulator compromises on area consumption and uses a digital adder / subtractor (accumulator 306) instead of a digital comparator so that the Σ-Δ modulation can generate a clock as a ratio of two large integers (i.e., M and N). In open-loop operation mode, the scaling error is zero, and in each cycle of the superframe clock 304, accumulator 306 adds M to the accumulated result via block 332. If comparator block 312 encounters an accumulator output greater than N302, multiplier 314 subtracts N from the accumulated result. The output of 312 is either 1 or 0, and this output is used as an enable for clock gate 308. Clock gate 308 dynamically gates the superframe clock 304 and generates a separate display clock 310.

[0045] The dedicated Σ-Δ modulator design only covers the case where the video interface is one of the previously mentioned basic interfaces. To extend the solution to cover the previously mentioned complex video interfaces and fractional-ratio division, a first-in-first-out (FIFO) control loop mode can be added. The FIFO control loop mode may include a FIFO counter 316, a comparison with a programmable threshold 318, a multiplier 320, and a multiplier 322. This control loop is used to jitter the modulator's Σ value and fine-tune the frequency of the split display in real time by adding a non-zero proportional error from M to compensate for the non-integer division relationship between the split display in overframe and steady-state conditions.

[0046] A digital proportional feedback FIFO control loop is implemented. The throughput from the superframe input 317 is used to increment the FIFO counter 316, and the throughput from the output 315 to the split display is used to decrement the counter. When the value of the FIFO counter 316 increases by a certain user-defined threshold, the system is identified as having an overflow tendency and generates an error indication indicating that the split display pixel clock frequency needs to be increased. The absolute value of the error signal is the difference between the programmable threshold 318 and the actual counter value 319. This error signal, generated by multiplier 320, is multiplied by the programmable feedback gain 324 via multiplier 322 and added to the ∑ value of a dedicated ∑-Δ modulator to produce proportional feedback, i.e., proportional error. Since the control loop is designed only for increasing the frequency, when using this mode, the base ∑ value of the ∑-Δ modulator needs to be programmed to be slightly lower than the expected frequency generation value. In some embodiments, the digital feedback control loop can be implemented as a digital feedback control loop. In some embodiments, the digital feedback control loop can be implemented by using the FIFO fill level as a correction signal for fine-tuning the frequency.

[0047] Figure 4 A system 400 for video multistream transmission with memory integrated in a serializer is depicted according to an embodiment of the present invention. In some embodiments, the memory may implement a lookup table. As shown, SoC 421 outputs a video multistream transmission signal 431 to SER 422. SER 422 includes a fractional clock divider 430, which can generate individual video display clocks from a single super video stream containing multiple display images without utilizing a PLL. The output of SER 422 may be GMSL 423 and GMSL 424, which are the inputs to DES 425 and DES 426, respectively. DES 425 and DES 426 are coupled to CID 427 and IC 428, respectively.

[0048] In summary, in one or more embodiments, a system supporting multi-stream image transmission may include: 1) an asymmetric image splitter engine that splits a superframe image stream into two or more image streams; and 2) a fractional clock divider circuit that further includes a one-bit Σ-Δ modulator and a digital proportional error feedback control loop. The fractional clock divider circuit provides a compatible display clock frequency for each of the two or more image streams. The system can be implemented without incorporating one or more phase-locked loop (PLL) oscillators. When the multi-stream image stream comprises two image streams, the asymmetric image splitter block adjusts the vertical asymmetry of the first image stream, which has the shortest height, to the same height as the second image stream by adding horizontal padding to the first image stream.

[0049] In one or more embodiments, a method for multi-streaming images may include: 1) receiving multiple image streams including superframe image streams, wherein each superframe image stream includes a first image stream and a second image stream, and wherein the height of the first image stream is higher than that of the second image stream; 2) adjusting the vertical asymmetry of the second image stream to the same height as the first image stream by adding horizontal padding to the second image stream; 3) splitting the superframe image stream into two separate image streams using an asymmetric image splitter engine; 4) generating a compatible display clock frequency for each of the two separate video display images; and 5) generating the compatible display clock frequency using a fractional clock divider circuit.

[0050] System Implementation Examples

[0051] In embodiments, aspects of this patent document may relate to or be implemented thereon an information processing system / computing system. For the purposes of this disclosure, a computing system may include any tool or set of tools operable for calculating, computed, determined, classified, processed, transmitted, received, retrieved, generated, routed, switched, stored, displayed, transmitted, highlighted, detected, recorded, reproduced, disposed of, or utilized information, intelligence, or data of any form for business, scientific, control, or other purposes. For example, a computing system may be an element of a communication system, such as a GMSL serializer and deserializer capable of simultaneously transmitting streaming image data. A computing system may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and / or other types of memory. Additional components of a computing system may include one or more network or wireless ports for communicating with external devices, and various input and output (I / O) devices such as a keyboard, mouse, touchscreen, and / or video display. A computing system may also include one or more buses operable for transmitting communication between various hardware components.

[0052] Figure 5 A simplified block diagram of a computing device / information processing system (or computing system) according to embodiments of the present disclosure is depicted. It will be understood that the illustrated functions of system 500 can operate to support various embodiments of the information processing system; however, it should be understood that the information processing system can be configured differently and include different components.

[0053] like Figure 5As shown, system 500 includes one or more central processing units (CPUs) 501 that provide computing resources and control the computer. CPU 501 may be implemented using a microprocessor or the like and may also include one or more graphics processing units (GPUs) 517 and / or a floating-point processor for mathematical calculations. System 500 may also include system memory 502, which may take the form of random access memory (RAM), read-only memory (ROM), or both.

[0054] Multiple controllers and peripherals can also be provided, such as Figure 5 As shown. Input controller 503 represents an interface to various input devices 504, such as a keyboard, mouse, or stylus. A SoC controller 505 communicating with a SoC device 506 may also be present. System 500 may further include a storage controller 507 for interface connection to one or more storage devices 508, each of which includes a storage medium such as flash memory, or an optical medium that can be used to record instructions for operating embodiments of systems, utilities, and applications that may include programs implementing various aspects of the present invention. The storage devices 508 may also be used to store processed data or data to be processed according to the present invention. System 500 may further include a display controller 509 for providing an interface to a display device 511. Computing system 500 may further include a serializer controller 512 for communicating with a serializer device 513. The communication controller 510 can interface with one or more communication devices 515, enabling the system 500 to connect to remote devices via any of a variety of networks or via any suitable electromagnetic carrier signal, including infrared signals. These networks include automotive networks, the Internet, cloud resources (e.g., Ethernet cloud, Ethernet Fibre Channel (FCoE) / Data Center Bridge (DCB) cloud, etc.), local area networks (LAN), wide area networks (WAN), and storage area networks (SAN).

[0055] In the illustrated system, all major system components can be linked to bus 516, which may represent more than one physical bus. However, the various system components may or may not be physically close to each other. For example, input data and / or output data can be remotely transmitted from one physical location to another. Furthermore, programs implementing various aspects of the invention can be accessed from a remote location (e.g., a server) via a network. Such data and / or programs can be delivered via any machine-readable medium of a variety of machine-readable media, including but not limited to: magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as CD-ROMs and holographic devices; magneto-optical media; and hardware devices specifically configured to store or for storing and executing program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs), flash memory devices, and ROM and RAM devices.

[0056] Embodiments of the present invention can be encoded on one or more non-transitory computer-readable media using instructions that cause one or more processors or processing units to execute steps. It should be noted that the one or more non-transitory computer-readable media should include both volatile and non-volatile memory. It should be noted that alternative implementations are possible, including hardware implementations or software / hardware implementations. The functionality of a hardware implementation can be implemented using ASIC(s), programmable arrays, digital signal processing circuit systems, etc. Therefore, the term "apparatus" in this disclosure is intended to cover both software and hardware implementations. Similarly, the term "one or more computer-readable media" as used herein includes software and / or hardware, or a combination thereof, having a program of instructions embodied thereon. In consideration of these alternative implementations, it will be understood that the accompanying drawings and description provide functional information that those skilled in the art would need to write program code (i.e., software) and / or manufacture circuitry (i.e., hardware) to perform the desired processing.

[0057] It should be noted that embodiments of the present invention may further relate to computer products having a non-transitory tangible computer-readable medium having computer code thereon for performing various computer-implemented operations. The medium and computer code may be media and computer code specifically designed and constructed for the purposes of the present invention, or they may belong to a class well known or available to those skilled in the art. Examples of tangible computer-readable media include, but are not limited to: magnetic media, such as hard disks, floppy disks, and magnetic tapes; optical media, such as CD-ROMs and holographic devices; magneto-optical media; and hardware devices specifically configured for storing or for storing and executing program code, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs), flash memory devices, and ROM and RAM devices. Examples of computer code include machine code generated by a compiler and files containing high-level code executed by a computer using an interpreter. Embodiments of the present invention may be implemented, in whole or in part, as machine-executable instructions that can reside in program modules executed by a processing device. Examples of program modules include libraries, programs, routines, objects, components, and data structures. In a distributed computing environment, program modules may be physically located in a local, remote, or both environment.

[0058] Those skilled in the art will recognize that the absence of a computing system or programming language is essential for the practice of this invention. They will also recognize that the various elements described above can be physically and / or functionally divided into sub-modules or combined together.

[0059] It will be understood by those skilled in the art that the foregoing examples and embodiments are exemplary and not limited to the scope of this disclosure. It is intended that all arrangements, enhancements, equivalents, combinations, and modifications thereof that will be apparent to those skilled in the art upon reading this specification and studying the accompanying drawings are included within the true spirit and scope of this disclosure. It should also be noted that the elements described in this disclosure may be arranged differently, thus including various relatedness, configurations, and combinations.

Claims

1. An apparatus to support multi-stream image transmission, comprising: a first interface to receive a superframe image signal comprising a first image stream and a second image stream; an asymmetric image separator engine coupled to receive the superframe image signal, the asymmetric image separator engine to separate the superframe image signal into the first image stream and the second image stream; and a fractional clock divider to receive a superframe clock, the fractional clock divider to generate a first clock to drive the first image stream by dividing a frequency of the superframe clock by a first number and to generate a second clock to drive the second image stream by dividing the frequency of the superframe clock by a second number, the superframe clock, the first clock, and the second clock having different frequencies, wherein the fractional clock divider comprises a sigma-delta modulator using an accumulator to allow sigma-delta modulation, and wherein the fractional clock divider further comprises: a comparator block to compare an output from the accumulator to a number of pixels in a superframe and to generate a comparator output; and a clock gate to receive the comparator output to gate the superframe clock and to output the first clock to drive the first image stream and the second clock to drive the second image stream. The fractional clock divider further comprises a feedback control loop, the feedback control loop comprising:

2. The apparatus of claim 1, wherein, a counter to output a counter value, the counter value to increase for each superframe clock active pixel and to decrease for each split display pixel; a first multiplier to generate an error signal, the error signal being a difference between the counter value and a threshold value; and a second multiplier to multiply the error signal by a feedback gain to obtain a proportional error to adjust a number of pixels in a frame of split display.

3. A method for asymmetric image separator clock generation, comprising: receiving a superframe image signal comprising a first image stream and a second image stream; separating, using an asymmetric image separator engine, the superframe image signal into the first image stream and the second image stream; and generating, using a fractional clock divider, a first clock to drive the first image stream and a second clock to drive the second image stream from a superframe clock of the superframe image signal, the superframe clock, the first clock, and the second clock having different frequencies, the first clock being obtained by dividing a frequency of the superframe clock by a first number and the second clock being obtained by dividing the frequency of the superframe clock by a second number, wherein the fractional clock divider comprises a sigma-delta modulator using an accumulator to allow sigma-delta modulation, and wherein generating the first clock and the second clock comprises: comparing, using a comparator block in the fractional clock divider, an output from the accumulator to a number of pixels in a superframe to generate a comparator output; and gating, using a clock gate, the superframe clock to output the first clock to drive the first image stream and the second clock to drive the second image stream. A clock gate in the fractional clock divider is used to gate the superframe clock based on the comparator output to output the first clock for driving the first image stream and the second clock for driving the second image stream.

4. The method of claim 3, wherein, The fractional clock divider includes a feedback control loop that includes: a counter that outputs a counter value that is increased for each superframe clock active pixel and decreased for each split display pixel; a first multiplier that generates an error signal that is a difference between the counter value and a threshold value; and a second multiplier that multiplies the error signal by a feedback gain to obtain a proportional error for adjusting a number of pixels in a frame of split display.

5. The method of claim 3, wherein, In the superframe image signal, the first image stream has a higher height than the second image stream.

6. A system for image multi-streaming, comprising: a first circuit that outputs a superframe image signal that includes a first image stream and a second image stream; an asymmetric image splitter engine that splits the superframe image signal into the first image stream and the second image stream; a fractional clock divider that generates a first clock for driving the first image stream and a second clock for driving the second image stream from a superframe clock of the superframe image signal, the superframe clock, the first clock, and the second clock having different frequencies; a first deserializer that receives the first image stream for display using the first clock; and a second deserializer that receives the second image stream for display using the second clock.

7. The system of claim 6, wherein, The fractional clock divider includes a sigma-delta modulator using an accumulator to allow sigma-delta modulation.

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