splicing display devices

Abstract

A splicing display device includes: multiple display modules interconnected via a first interface circuit and a second interface circuit; and a setting board that receives, during a first time period, a defect occurrence and location signal generated in a faulty module among the multiple display modules via the first interface circuit, generates a defect identification completion signal during a second time period after the first time period, and transmits the defect identification completion signal to the faulty module via the second interface circuit during the second time period.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0194684, filed on December 31, 2021, and Korean Patent Application No. 10-2022-0067758, filed on June 2, 2022, which are incorporated herein by reference as fully set forth herein. Technical Field

[0003] This disclosure relates to expandable splicing display devices. Background Technology

[0004] Large-size displays can be used in various fields, such as indoor and outdoor digital advertising. To meet the demand for large-size displays, scalable video wall display devices have been proposed. In video wall display devices, a single screen is configured by connecting multiple display modules, and the desired screen size can be achieved by adjusting the number of display modules connected to each other. Summary of the Invention

[0005] Because of the nature of commercial products, such video wall displays are primarily installed outdoors, making it difficult for users to visually identify the occurrence or absence of errors. Furthermore, since video wall displays comprise multiple components for configuring large screens, it can take considerable time to determine the cause of an error when it does occur.

[0006] In order to overcome the above-mentioned problems in the related technologies, this disclosure can provide a splicing display device that can automatically check the defect location of the faulty display module and can additionally automatically check the defect history of the faulty display module.

[0007] To achieve these and other advantages, in accordance with the purposes of this disclosure, as embodied and broadly described herein, the splicing display device includes: a plurality of display modules interconnected via a first interface circuit and a second interface circuit; and a setting board that receives, during a first time period, a defect occurrence and location signal generated in a faulty module among the plurality of display modules via the first interface circuit, generates a defect identification completion signal during a second time period following the first time period, and transmits the defect identification completion signal to the faulty module via the second interface circuit during the second time period.

[0008] Additionally, the splicing display device may include: a setting board; and multiple display modules interconnected via a first interface circuit and a second interface circuit. Each of the multiple display modules may include a timing controller configured to: generate a defect occurrence and location signal in the event of a malfunction in the display module, transmit the defect occurrence and location signal to the setting board via the first interface circuit during a first time period, and receive a defect identification completion signal generated by the setting board via the second interface circuit during a second time period following the first time period. Attached Figure Description

[0009] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the specification, serve to illustrate the principles of the disclosure. In the drawings:

[0010] Figure 1 This is a schematic diagram illustrating a splicing display device according to an embodiment of the present disclosure;

[0011] Figure 2 This is a diagram showing the connection configuration of the display module;

[0012] Figure 3 and Figure 4 This is a diagram showing a display panel based on miniature light-emitting diodes (LEDs);

[0013] Figure 5 It is a schematic equivalent circuit diagram of the pixels included in the display panel;

[0014] Figure 6 This is a diagram illustrating the fault diagnosis structure of the splicing display device according to this embodiment;

[0015] Figure 7 This is a diagram schematically illustrating a fault diagnosis sequence of a splicing display device according to this embodiment;

[0016] Figure 8 and Figure 9 This is a diagram illustrating in detail the fault diagnosis sequence of the splicing display device according to this embodiment;

[0017] Figure 10 It is shown that... Figure 8 and Figure 9 A diagram showing an example of a fault diagnosis list corresponding to a history of defect signals;

[0018] Figure 11 This is a diagram illustrating the principle of identifying defects in faulty modules within the setup board;

[0019] Figure 12 This is a diagram illustrating the principle of identifying the location of defects in faulty modules within the setup board;

[0020] Figure 13 This is a diagram illustrating an example of detecting the location of a defect in a faulty module within a setup board and transmitting a defect identification completion signal to the faulty module.

[0021] Figure 14 This is a diagram illustrating an example of receiving a defect identification completion signal from the setup board and transmitting a defect history signal to the setup board;

[0022] Figure 15 It is shown that... Figure 14 A diagram showing an example of a fault diagnosis list corresponding to historical defect signals; and

[0023] Figure 16 This is a diagram illustrating the overall configuration of each display module for implementing a fault diagnosis sequence in a splicing display device according to an embodiment of the present disclosure. Detailed Implementation

[0024] In the following description, the present disclosure will be described more fully with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the disclosure will be detailed and complete and will fully convey the concepts of the disclosure to those skilled in the art.

[0025] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be detailed and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0026] The shapes, sizes, ratios, angles, numbers, etc., disclosed in the accompanying drawings used to describe various embodiments of this disclosure are merely exemplary, and this disclosure is not limited thereto. Similar reference numerals refer to similar elements throughout the document. The same elements are represented by the same reference numerals throughout the specification. As used herein, unless the term "only" is used, the terms "comprising," "having," "including," etc., imply that additional parts may be added. As used herein, unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" are also intended to include the plural forms.

[0027] Even without explicit statement, elements in the various embodiments of this disclosure will be interpreted as including tolerance ranges.

[0028] When describing positional relationships, for example, when describing the positional relationship between two parts as "on", "above", "below", and "next to", one or more other parts may be positioned between the two parts unless "exactly" or "directly" is used.

[0029] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0030] In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such detailed descriptions unnecessarily obscure the essential points of this disclosure. Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic diagram illustrating a splicing display device 100 according to an embodiment of the present disclosure. Figure 2 This is a diagram showing the connection configuration of the display module.

[0032] Reference Figure 1 and Figure 2 According to embodiments of the present disclosure, the splicing display device 100 may include a setup board SET and a plurality of display modules CB. Each of the display modules CB may be referred to as a cabinet.

[0033] Display modules (CBs) can be interconnected via a serial interface circuit to configure a large screen. The total resolution of the large screen can be determined as the sum of the unit resolutions of each display module (CB). For example, in the case of a screen configured with eight display modules (CBs) each having a unit resolution of 960*1080, the total resolution of the screen can be 3840*2160.

[0034] Each display module CB can be implemented as an electroluminescent display type or a liquid crystal display type, and in the following embodiments, an embodiment in which the display module CB is implemented as an electroluminescent display type based on micro light-emitting diodes (LEDs) is used as an example. However, the inventive concept is not limited to the implementation type of the display module CB.

[0035] The SET board can automatically check the location of defects in the fault display module (hereinafter referred to as the fault module) and can also automatically check the defect history of the fault module. For this purpose, the SET board and the display module CB can be interconnected through an interface circuit, which can be implemented as, for example, a serial peripheral interface (SPI), but is not limited thereto.

[0036] The interface circuit can be implemented as a feedback loop type bidirectional multi-link port. This interface circuit enables separate bidirectional serial communication between display modules (CB) and between the setting board (SET) and the display module (CB), thereby ensuring short communication lines and improving the speed and reliability of high-capacity data communication over short communication lines.

[0037] Each display module CB may include multiple display panels PNL, multiple panel driving circuits for driving the display panels PNL, and a timing controller TCON for controlling the operating timing of each panel driving circuit.

[0038] The timing controller TCON can be mounted on the control printed circuit board (PCB) CPCB and can be connected in parallel to the panel drive circuit via a branch cable CBL. The timing controller TCON can also be connected to the adjacent display module CB or setting board SET via interface circuitry.

[0039] The panel driving circuit can be independently connected to each of the multiple display panels PNLs. The panel driving circuit may include a source PCB SPCB connected to the timing controller TCON via a branch cable CBL, a memory circuit MEM mounted on the source PCB SPCB, a conductive film COF electrically connecting the source PCB SPCB to the display panel PNL, a data driver SIC bonded to the conductive film COF, and a gate driver and power circuit electrically connected to the source PCB SPCB.

[0040] The memory circuit MEM can be a non-volatile memory storing panel characteristics and can include correction values ​​for gamma settings, a first compensation value for compensating for drive characteristic deviations / color deviations between pixels, a second compensation value for compensating for boundary deviations between adjacent display panel PNLs, and various image quality and drive control data. The memory circuit MEM can be flash memory and / or electrically erasable programmable read-only memory (EEPROM). A large amount of data may be stored in flash memory, while a small amount of data may be stored in EEPROM.

[0041] Figure 3 and Figure 4 This is a diagram showing a display panel based on micro-LEDs. Figure 5 It is a schematic equivalent circuit diagram of the pixels included in the display panel.

[0042] Reference Figure 3 and Figure 4 A pixel array for reproducing the input image can be set in each display panel PNL. Multiple pixels can be arranged in the pixel array, and signal lines for driving the pixels can also be arranged in the pixel array. The signal lines may include multiple data lines DL for supplying data voltage Vdata to the pixels (see [link to relevant documentation]). Figure 5 ), and multiple gate lines GL used to supply the gate signal GSIG to the pixel (see Figure 5 ), and multiple power lines used to supply source voltage to the pixels.

[0043] Each pixel may include a micro-LED chip (μLED chip) as a light-emitting device (EL). Multiple micro-LED chips (μLED chips) may include a red chip (μLED chip_R), a green chip (μLED chip_G), and a blue chip (μLED chip_B) disposed on a thin-film transistor (TFT) backplane. A red (R) pixel may include a red chip (μLED chip_R) as a light-emitting device (EL), a green (G) pixel may include a green chip (μLED chip_G) as a light-emitting device (EL), and a blue (B) pixel may include a blue chip (μLED chip_B) as a light-emitting device (EL).

[0044] Micro-LED chips (μLED chips) can be transferred from R / G / B donors and thus can be mounted on a TFT backplane. Red chips (μLED chip_R) can be transferred from the R donor, green chips (μLED chip_G) from the G donor, and blue chips (μLED chip_B) from the B donor. Transfer techniques can utilize electrostatic forces, lasers, velocity-dependent viscous forces, and load-dependent viscous forces. Transfer techniques are not limited to these and electrostatic force-based self-assembly can also be used.

[0045] The TFT backplane can be implemented in an active matrix structure for efficient driving. In the TFT backplane, pixels can be defined by data lines (DL), gate lines (GL), and power lines.

[0046] Multiple pixels can constitute a single pixel. For example, R, G, and B pixels arranged adjacent to each other can constitute a single pixel in the direction of extension of the gate line GL or the data line DL.

[0047] As in Figure 5 In this process, the pixel PXL may include a light-emitting device EL, a driving TFT DT, and a node circuit NCON.

[0048] The node circuit NCON can be connected to the gate line GL and the data line DL. A data voltage Vdata can be supplied to the node circuit NCON via the data line DL, and a gate signal GSIG can be supplied to the node circuit NCON via the gate line GL. The node circuit NCON can apply the data voltage Vdata to the gate electrode of the driving TFT DT synchronously with the gate signal GSIG, and therefore, the gate-source voltage of the driving TFT DT can be set based on the conditions used to generate the drive current. The node circuit NCON may include internal compensation circuitry that senses and compensates for the threshold voltage and / or electron mobility of the driving TFT DT.

[0049] A driving TFT DT can be a driving element that generates a driving current based on its gate-source voltage. The gate electrode of the driving TFT DT can be connected to the node circuit NCON, the first electrode (drain electrode) of the driving TFT DT can be connected to the high-level pixel power supply VDD, and the second electrode (source electrode) of the driving TFT DT can be connected to the light-emitting device EL.

[0050] The light-emitting device EL can be a device that emits light with an intensity corresponding to the driving current input to the driving TFT DT. The light-emitting device EL can be implemented using a micro-LED including an inorganic light-emitting layer. The first electrode of the light-emitting device EL can be connected to the driving TFT DT, and the second electrode of the light-emitting device EL can be connected to the low-level pixel power supply VSS.

[0051] The connection configuration and operation of a pixel PXL may be merely an embodiment, and the spirit of this disclosure is not limited thereto. For example, each of the driving TFT DT and the node circuit NCON may be implemented based on a PMOS transistor, an NMOS transistor, or a CMOS transistor. Furthermore, multiple gate lines GL connected to the node circuit NCON may be provided. Additionally, the light-emitting device EL according to this disclosure may be implemented using a common cathode circuit, but it is not limited thereto and may also be implemented using a common anode circuit.

[0052] Figure 6 This is a diagram illustrating the fault diagnosis structure of the splicing display device according to this embodiment. Figure 7 This is a diagram schematically illustrating a fault diagnosis sequence of a splicing display device according to this embodiment.

[0053] Reference Figure 6According to this embodiment, the splicing display device can use a first interface circuit and a second interface circuit based on an SPI scheme for automatic fault diagnosis. The first interface circuit can transmit the defect occurrence and location signals and defect history signals of the faulty module (e.g., the faulty module where the control PCB CPCB#2 is located, which can also be referred to as faulty module CPCB#2 below) from the faulty module to the setting board SET. The second interface circuit can transmit the defect identification completion signal of the setting board SET from the setting board SET to the faulty module. The signal transmission direction of the first interface circuit can be opposite to the signal transmission direction of the second interface circuit.

[0054] The fault diagnosis sequence can be executed together with the "Automatic nID Setup Process" during the power-on sequence period. The power-on sequence period can be the time from when the operating power is turned on in the video wall display device until the displayed screen. The "Automatic nID Setup Process" can represent the following operation: This operation generates module identification numbers corresponding to the connection sequence based on the control of the setup board (SET), and feeds back a control response signal including the generation result to the setup board (SET) through a third interface circuit. Each display module can check its connection sequence through the "Automatic nID Setup Process".

[0055] The setup board (SET) may include a system-on-chip (SOC) for fault diagnosis. The SOC may include a first terminal (input terminal) LI connected to a first interface circuit and a second terminal (output terminal) LCK-O connected to a second interface circuit.

[0056] Each display module may include one of the control PCBs CPCB#1 to CPCB#8 with different connection orders and one of the corresponding timing controllers TCON#1 to TCON#8. The timing controller may include a diagnostic control circuit LCON for generating or transmitting defect occurrence and location signals and optional defect history signals, a first input terminal LI and a first output terminal LO connected to the first interface circuit, and a second input terminal LCK-I and a second output terminal LCK-O connected to the second interface circuit.

[0057] Reference Figure 7 The SET board can receive defect occurrence and location signals from the faulty module (e.g., faulty module CPCB#2) via a first interface circuit during a first time period. Furthermore, the SET board can generate a defect identification completion signal during a second time period following the first time period, and can transmit the defect identification completion signal to the faulty module via a second interface circuit. Optionally, the SET board can also receive defect history signals from the faulty module via the first interface circuit during a third time period following the second time period.

[0058] Each of the defect occurrence and location signal, the defect identification completion signal, and the defect history signal can be a pulse signal that oscillates between high and low logic voltages.

[0059] Figure 8 and Figure 9 This is a diagram illustrating in detail the fault diagnosis sequence of the splicing display device according to this embodiment. Figure 10 It is shown that... Figure 8 and Figure 9 A diagram showing an example of a fault diagnosis list corresponding to historical defect signals. Figures 8 to 10 The image shows an example where the faulty module includes a control PCB CPCB#2 with a connection order of "2".

[0060] Reference Figures 8 to 10 The fault module can periodically sense monitoring signals input through the internal bus line to check for the presence or absence of defects. When a defect occurs, the fault module can update the defect history in the predetermined fault diagnosis list and generate defect occurrence and location signals.

[0061] The fault module can generate defect occurrence and location signals as pulse signals. The fault module can switch the defect occurrence and location signals from a high logic voltage to a low logic voltage, and can also switch the voltage of the defect occurrence and location signals according to their connection order "2", that is, switch the voltage of the defect occurrence and location signals twice accordingly. Therefore, the defect occurrence and location signals may include a first falling edge and two first rising edges arranged following the first falling edge.

[0062] The defect occurrence and location signal of the faulty module can be transmitted to the first terminal LI of the setting board SET through the first interface circuit. During the first time period, the setting board SET can identify the occurrence of the defect of the faulty module based on the first falling edge of the defect occurrence and location signal, count the first rising edges of the defect occurrence and location signal, and identify the location of the faulty module based on the number of first rising edges.

[0063] In the second time period following the first, the SET board can generate a defect identification completion signal to notify the location of the identified faulty module. The defect identification completion signal can be a pulse signal and may include a second rising edge.

[0064] The defect identification completion signal of the SET board can be transmitted to the second input terminal LCK-I of the fault module through the second interface circuit. During the second time period, the fault module can check the defect identification completion status of the SET board based on the second rising edge of the defect identification completion signal.

[0065] In the third time period following the second time period, the fault module can generate a defect history signal as a pulse signal. The fault module can switch the voltage of the defect history signal according to the number corresponding to the defect history setting order in the fault diagnosis list. For example, when the defect history is "short circuit / open circuit", Figure 10 The defect history setting order in the fault diagnosis list can be "2", and the fault module can switch the voltage of the defect history signal twice accordingly. In this case, the defect history signal can include two third rising edges.

[0066] The defect history signal of the faulty module can be transmitted to the first terminal LI of the setting board SET through the first interface circuit. During the third time period, the setting board SET can count the third rising edge of the defect history signal and identify the defect history of the faulty module based on the number of third rising edges. Because the number of third rising edges is two, the setting board SET can identify "short circuit / open circuit" corresponding to the defect history setting sequence "2" in the fault diagnosis list (this setting sequence corresponds to the number of third rising edges, for example, equal to the number of third rising edges) as the defect history of the faulty module.

[0067] Figure 11 This diagram illustrates the principle of identifying defects in faulty modules within the setup board.

[0068] Reference Figure 11 In the fault module CPCB#2, the defect occurrence and location signal can transition from a high logic voltage H to a low logic voltage L. This signal can be transmitted to the first terminal L1 of the setting board SET via a first interface circuit that passes through the display module CPCB#1 between the setting board SET and the fault module CPCB#2. The setting board SET can identify the occurrence of a defect in the fault module CPCB#2 based on the first falling edge FE of the defect occurrence and location signal.

[0069] Figure 12 This is a diagram illustrating the principle of identifying the location of defects in faulty modules within the setup board.

[0070] Reference Figure 12In fault module CPCB#2, the defect occurrence and location signal can switch from a high logic voltage H to a low logic voltage L, and the voltage of the defect occurrence and location signal can also be switched according to the connection sequence "2" of fault module CPCB#2. The defect occurrence and location signal can be transmitted to the first terminal LI of the setting board SET through the first interface circuit, which passes through the display module CPCB#1 between the setting board SET and fault module CPCB#2. The setting board SET can identify the occurrence of a defect in the fault module based on the first falling edge of the defect occurrence and location signal, and can then count the first rising edges RE of the defect occurrence and location signal to identify the display module with connection sequence "2" (which corresponds to the number of first rising edges, for example, equal to the number of first rising edges) as fault module CPCB#2.

[0071] If a defect identification completion signal is not received from the setting board SET within the predetermined time, the fault module CPCB#2 can retransmit the defect occurrence and location signal to the first terminal LI of the setting board SET through the first interface circuit.

[0072] Figure 13 This is a diagram illustrating an example of transmitting a defect identification completion signal from the setup board to the fault module.

[0073] Reference Figure 13 The SET board can check the location of defects in the fault module CPCB#2 and generate a defect identification completion signal. The SET board can transmit the defect identification completion signal to the second input terminal LCK-I of the fault module CPCB#2 via the second interface circuit. The fault module CPCB#2 can check the defect identification completion status of the SET board based on the second rising edge RE' of the defect identification completion signal.

[0074] Figure 14 This is a diagram illustrating an example of receiving a defect identification completion signal from the setup board and transmitting a defect history signal to the setup board. Figure 15 It is shown that... Figure 14 A diagram showing an example of a fault diagnosis list corresponding to a history of defect signals.

[0075] Reference Figure 14 The fault module CPCB#2 can receive the defect identification completion signal from the setting board SET and can generate a defect history signal as a pulse signal. The fault module CPCB#2 can switch the voltage of the defect history signal according to the number corresponding to the defect history setting order in the fault diagnosis list. For example, when the defect history is "GIA monitoring", Figure 15The defect history setting order in the fault diagnosis list can be "1", and the fault module CPCB#2 can switch the voltage of the defect history signal once accordingly. In this case, the defect history signal may include a third rising edge RE.

[0076] The defect history signal of fault module CPCB#2 can be transmitted to the first terminal LI of the setting board SET through the first interface circuit. The setting board SET can count the third rising edge of the defect history signal and identify the defect history of fault module CPCB#2 based on the number of third rising edges. The setting board SET can know the fault diagnosis list in advance. Because the number of third rising edges is one, the setting board SET can identify "GIA monitoring" corresponding to the defect history setting sequence "1" in the fault diagnosis list as the defect history of fault module CPCB#2.

[0077] Figure 16 This is a diagram illustrating the overall configuration of each display module used to implement a fault diagnosis sequence in a splicing display device according to an embodiment of the present disclosure. (Refer to...) Figure 16 The overall configuration of the described display modules can be used for each display module in the splicing display device according to this embodiment, which includes a setting board and multiple display modules interconnected through a first interface circuit and a second interface circuit.

[0078] Reference Figure 16 Each display module may include a timing controller TCON mounted on a control PCB CPCB. The timing controller TCON may include a diagnostic control circuit LCON for generating or transmitting defect occurrence and location signals and defect history signals, a first input terminal LI and a first output terminal LO connected to a first interface circuit, and a second input terminal LCK-I and a second output terminal LCK-O connected to a second interface circuit.

[0079] The diagnostic control circuit LCON may include a defect identifier, a first signal transmitter, a first signal generator, and a second signal transmitter.

[0080] The defect identifier can check the actual defect information (defect location / defect history) input through the internal bus circuitry during a specific time period, and can enable the control signal when defect information is detected.

[0081] The first signal transmitter can check the defect occurrence and location signals received from the adjacent display module, and can transmit the corresponding signals to the first signal generator.

[0082] When an enable control signal is input from the defect identifier, the first signal generator can generate defect occurrence and location signals, and output them via the first interface circuit, for example, and transmit them to the setting board SET. When no enable control signal is input from the defect identifier and defect occurrence and location signals of an adjacent display module are input from the first signal transmitter, the first signal generator can output the input defect occurrence and location signals completely via the first interface circuit, for example, and transmit them to the setting board SET. Furthermore, when the timing of the enable control signal input from the defect identifier overlaps with the timing of the defect occurrence and location signals of an adjacent display module input from the first signal transmitter, the first signal generator can prioritize the generation of defect occurrence and location signals based on the enable control signal, thereby improving operational reliability.

[0083] The second signal transmitter can transmit the defect identification completion signal received from an adjacent display module or setting board SET to another display module. In a fault module, the function of the second signal transmitter may be disabled. Furthermore, in a fault module where an enable control signal has been input from the defect identifier, if a defect identification completion signal is input from the second interface circuit, the first signal generator can generate a defect history signal, which can be output through the first interface circuit and, for example, transmitted to the setting board SET.

[0084] According to embodiments of this disclosure, the location of defects in a faulty display module can be automatically detected by a setting board, and additionally, the defect history of the faulty display module can be automatically checked. Therefore, the splicing display device according to embodiments of this disclosure can significantly reduce the time spent detecting the location and cause of defects.

[0085] Furthermore, according to embodiments of this disclosure, since the setup board analyzes data transmitted via SPI communication based on a predetermined protocol to detect the location and cause of defects, the overall structure required for diagnosing faults can be simplified, and manufacturing costs can be reduced.

[0086] The effects of this disclosure are not limited to the examples above, and various other effects may be included in the specification.

[0087] Although this disclosure has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A tiled display apparatus comprising: a plurality of display modules connected to each other through a first interface circuit and a second interface circuit; and a setting board receiving a defect occurrence and position signal generated in a failure module among the plurality of display modules from the failure module through the first interface circuit and not through the second interface circuit in a first period, generating a defect identification completion signal in a second period after the first period, and transmitting the defect identification completion signal to the failure module through the second interface circuit and not through the first interface circuit in the second period. Each of the defect occurrence and position signal and the defect identification completion signal is a pulse signal that swings between a high logic voltage and a low logic voltage, 2. The tiled display apparatus of claim 1, wherein, the defect occurrence and position signal includes a first falling edge and one or more first rising edges arranged after the first falling edge, and the defect identification completion signal includes a second rising edge. In the first period, the setting board identifies an occurrence of a defect of the failure module based on the first falling edge of the defect occurrence and position signal, counts the first rising edges of the defect occurrence and position signal, and identifies a position of the failure module based on a number of the first rising edges, and 3. The tiled display apparatus of claim 2, wherein, In the second period, the failure module identifies a defect identification completion state of the setting board based on the second rising edge of the defect identification completion signal. The number of the first rising edges varies based on a connection position of the failure module among the plurality of display modules.

4. The tiled display apparatus of claim 2, wherein, The number of the first rising edges corresponds to a connection order of the failure module among the plurality of display modules based on the second interface circuit.

5. The tiled display apparatus of claim 2, wherein, The setting board further receives a defect history signal of the failure module from the failure module through the first interface circuit in a third period after the second period.

6. The tiled display apparatus of claim 1, wherein, The defect history signal is a pulse signal that swings between a high logic voltage and a low logic voltage, and 7. The tiled display apparatus of claim 6, wherein, the defect history signal includes one or more third rising edges. The setting board counts the third rising edges of the defect history signal, and identifies one of defect candidate information in a failure diagnosis list as a defect history of the failure module based on a number of the third rising edges.

8. The tiled display apparatus of claim 7, wherein, The failure diagnosis list of the failure module includes defect candidate information having different setting orders, and 9. The tiled display apparatus of claim 8, wherein, the number of the third rising edges corresponds to a setting order of defect candidate information corresponding to a defect history of the failure module among the defect candidate information. Each of the first interface circuit and the second interface circuit is implemented with a serial peripheral interface.

10. The tiled display apparatus of claim 1, wherein, 11.A tiled display apparatus comprising: a setting board; and a plurality of display modules connected to each other through a first interface circuit and a second interface circuit, wherein each of the plurality of display modules includes: ​ ​ a timing controller configured to generate a defect occurrence and location signal in the event of a failure of the display module and to transmit the defect occurrence and location signal to the set board through the first interface circuit and not through the second interface circuit for a first time period and to receive a defect identification complete signal generated by the set board through the second interface circuit and not through the first interface circuit for a second time period after the first time period.

12. The tiled display apparatus of claim 11, wherein, the timing controller is further configured to generate a defect history signal for the display module and to transmit the defect history signal to the set board through the first interface circuit for a third time period after the second time period.

Images