Light emitting display device

Abstract

A light emitting display apparatus includes a display panel including a plurality of pixels, a plurality of gate lines configured to provide a gate signal to the pixels, and a plurality of stages connected to the plurality of gate lines and configured to output a gate pulse to a group of pixels connected to at least two gate lines among the plurality of gate lines for sensing a characteristic of each pixel among the group of pixels during a sensing period.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2021-0192166, filed in Korea on December 30, 2021, the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates to light-emitting display devices. Background Technology

[0004] Emitting light display devices display images by using light-emitting devices. When an emitting light display device is used continuously, the driving transistors used to drive the light-emitting devices degrade, causing changes in the threshold voltage of the driving transistors, which in turn leads to a degradation in image quality.

[0005] Various compensation methods are used during the display period of the displayed image to compensate for changes in the threshold voltage of the transistor.

[0006] Furthermore, before the start of the display period, after the light-emitting display device is turned on, or before the light-emitting display device is turned off, after the end of the display period, the light-emitting display device senses and stores the threshold voltages of the driving transistors included in all pixels.

[0007] A light-emitting display device can compensate for multiple input image data during a display period by using a threshold voltage stored therein. Therefore, the light-emitting display device can display a normal image even when the threshold voltage of the driving transistor changes.

[0008] However, in related technologies, the time spent sensing connections to each gate line after the sensing period begins can be quite long. Therefore, especially in light-emitting display devices with large screens, sensing all pixels within the light-emitting display device requires a long time period.

[0009] For example, when a user turns off a light-emitting display device and then tries to quickly turn it back on, the user may experience a long time lag because the pixels connected to a grid line are sensed at a time during the sensing period when the power is off (e.g., when the display is blanking or black). This may lead to disappointment (e.g., it may give the user the impression that the device is slow or paused, when in fact the device is just taking a long time to sense all the pixels).

[0010] Furthermore, the power consumption of the device may increase because the device may take a long time to sense all pixels. Summary of the Invention

[0011] Therefore, this disclosure aims to provide a light-emitting display device that substantially eliminates one or more problems caused by the limitations and disadvantages of related technologies.

[0012] One aspect of this disclosure is intended to provide a light-emitting display device capable of sensing pixels connected to at least two gate lines during a sensing period.

[0013] One aspect of this disclosure provides a light-emitting display device, comprising: a light-emitting display panel including a plurality of pixels; a plurality of gate lines configured to provide gate signals to the pixels; and a plurality of stages connected to the plurality of gate lines and configured to output gate pulses to a group of pixels connected to at least two of the plurality of gate lines, for sensing features of each of the group of pixels during a sensing period.

[0014] According to one aspect of this disclosure, a sensing period is initiated after receiving a power-off command to power off the light-emitting display device.

[0015] According to another aspect of this disclosure, a first stage of the plurality of stages is configured to output the gate pulse to a first pixel block connected to four or more gate lines of a first group for sensing features of each pixel in the first pixel block during a first period of the sensing period, and a second stage of the plurality of stages is configured to output the gate pulse to a second pixel block connected to four or more gate lines of a second group for sensing features of each pixel in the second pixel block during a second period of the sensing period after the first period.

[0016] According to one aspect of this disclosure, the plurality of stages include: a first stage connected to a first gate line and a second gate line for providing gate signals to a first group of pixels connected to the first gate line and the second gate line; and a second stage connected to a third gate line and a fourth gate line for providing gate signals to a second group of pixels connected to the third gate line and the fourth gate line, wherein the first stage is configured to output gate pulses to the first gate line and the second gate line for sensing features of each pixel in the first group of pixels during the sensing period, and wherein the second stage is configured to output gate pulses to the third gate line and the fourth gate line for sensing features of each pixel in the second group of pixels during the sensing period.

[0017] According to another aspect of this disclosure, the plurality of stages includes: a third stage connected to the fifth gate line and the sixth gate line for providing gate signals to a third group of pixels connected to the fifth gate line and the sixth gate line, wherein the third stage is configured to output gate pulses to the fifth gate line and the sixth gate line for sensing features of each pixel in the third group of pixels during the sensing period.

[0018] According to one aspect of this disclosure, the at least two gate lines are connected to the same stage among the plurality of stages.

[0019] According to another aspect of this disclosure, the at least two gate lines are connected to at least two different stages among the plurality of stages.

[0020] According to another aspect of this disclosure, each of the plurality of stages includes: a signal output unit configured to sequentially output the gate pulse to the at least two gate lines; and a sensing selector configured to store a selection signal during a sensing selection period of the sensing period, and to control the signal output unit to output the gate pulse based on the selection signal during a sensing execution period of the sensing period, the sensing execution period being after the sensing selection period.

[0021] According to one aspect of this disclosure, the sensing selector includes a capacitor for storing the selection signal.

[0022] According to one aspect of this disclosure, during the sensing selection period of the sensing period, the selection signal is stored in the sensing selector included in at least two of the plurality of levels.

[0023] According to another aspect of this disclosure, the sensing selector is configured to: in response to receiving a first sensing control pulse during the sensing selection period of the first frame period when the selection signal is stored in the sensing selector, control the signal output unit to sequentially output the gate pulse to the at least two gate lines during the sensing execution period of the sensing period when a reset signal is received by the sensing selector.

[0024] According to one aspect of this disclosure, the width of the reset signal is greater than the width of the first sensing control pulse, and the width of the first sensing control pulse is greater than the width of the selection signal.

[0025] According to another aspect of this disclosure, the sensing selector of the nth stage of the plurality of stages is configured to receive a carry signal provided from another stage of the plurality of stages as a selection signal for the nth stage, where n is a positive integer greater than zero.

[0026] According to another aspect of this disclosure, the (n+1)th stage of the plurality of stages is configured to receive different carry signals provided from different stages among the plurality of stages as selection signals for the (n+1)th stage, the different stages being different from the other stage.

[0027] According to one aspect of this disclosure, the sensing selector in each of the plurality of stages further includes: a selection signal transmitter including a fourth transistor configured to transmit a carry signal from the carry output, the carry signal being received by the selection signal controller based on a carry control clock signal applied to the gate of the fourth transistor; and a reset unit including: a fifth transistor having a gate connected to the gate of the third transistor of the selection signal controller, and a sixth transistor having a first terminal connected to the fifth transistor, a gate configured to provide a reset signal, and a second terminal connected to the Q node of the corresponding stage.

[0028] According to one aspect of this disclosure, the sensing selector in each of the plurality of stages further includes: a selection signal storage unit connected between the selection signal controller and the reset unit, the selection signal storage unit including a capacitor.

[0029] According to another aspect of this disclosure, the sense selector in each of the plurality of stages further includes: an initialization unit comprising: a seventh transistor including a first terminal connected to a sixth transistor and a second terminal connected to a Qb node of the corresponding stage; and an eighth transistor including a first terminal connected to the second terminal of the seventh transistor, wherein the gate of the seventh transistor is connected to the gate of the sixth transistor and configured to provide an initialization voltage.

[0030] According to another aspect of this disclosure, the initialization unit is configured to prevent the signal output unit from outputting the gate pulse to the at least two gate lines in response to receiving the initialization voltage.

[0031] According to one aspect of this disclosure, a sensing selector in each of the plurality of stages includes: a selection signal controller, comprising: a first transistor including a first terminal connected to a carry output of another stage among the plurality of stages; a second transistor including a first terminal connected to a second terminal of the first transistor; and a third transistor connected between the second terminal of the first transistor and the first terminal of the second transistor, wherein a first gate of the first transistor is connected to a second gate of the second transistor, and the first gate and the second gate are connected to a sensing control signal line configured to provide the first sensing control pulse.

[0032] According to one aspect of this disclosure, the first gate and the second gate in the selection signal controller of the nth stage of the plurality of stages, and the first gate and the second gate in the selection signal controller of the (n+1)th stage of the plurality of stages, are all connected to the sensing control signal line, where n is a positive integer greater than zero.

[0033] According to another aspect of this disclosure, the first terminal of the first transistor in the nth stage selection signal controller and the first terminal of the first transistor in the (n+1)th stage signal controller are connected to carry outputs from two different stages among the plurality of stages.

[0034] Other advantages and features of this disclosure will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art upon examination of the following, or may be learned by practice of this disclosure. The purposes and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0035] To achieve these and other advantages and in accordance with the purposes of this disclosure, as embodied and broadly described herein, a light-emitting display device is provided, comprising: a light-emitting display panel including gate lines; a gate driver providing gate signals to the gate lines; and a controller controlling the gate driver, wherein the gate driver includes a plurality of stages, each of the plurality of stages including: a signal output unit sequentially outputting gate pulses to at least two gate lines; a signal controller controlling the signal output unit; and a sensing selector storing a selection signal during a sensing period and controlling the signal output unit by using the selection signal during a sensing execution period, wherein the selection signal is stored in the sensing selector included in at least two stages during the sensing period.

[0036] It should be understood that the foregoing general description and the following detailed description of this disclosure are illustrative and are intended to provide further examples and explanations of the claimed disclosure. Attached Figure Description

[0037] The accompanying drawings are included in and form part of this application to provide a further understanding of this disclosure. These drawings illustrate embodiments of the disclosure and, together with the specification, serve to explain the principles of the disclosure. In the drawings:

[0038] Figure 1 This is an example diagram illustrating the structure of a light-emitting display device according to an embodiment of the present disclosure;

[0039] Figure 2 This is an example diagram illustrating the structure of a pixel applied to a light-emitting display device according to an embodiment of the present disclosure;

[0040] Figure 3This is an example diagram illustrating the configuration of a controller applied to a light-emitting display device according to an embodiment of the present disclosure;

[0041] Figure 4 This is an example diagram illustrating the configuration of a gate driver applied to a light-emitting display device according to an embodiment of the present disclosure;

[0042] Figure 5 This is an example diagram schematically illustrating the configuration of a stage in a gate driver of a light-emitting display device according to an embodiment of the present disclosure;

[0043] Figure 6 This is an example diagram illustrating in detail the configuration of a stage in a gate driver of a light-emitting display device according to an embodiment of the present disclosure;

[0044] Figure 7 This is an example diagram illustrating two stages applied in a gate driver of a light-emitting display device according to an embodiment of the present disclosure; and

[0045] Figure 8 This is an example diagram illustrating the waveform of a signal applied to a light-emitting display device according to an embodiment of the present disclosure. Detailed Implementation

[0046] Reference will now be made in detail to embodiments of this disclosure, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0047] The advantages and features of this disclosure, and its implementation methods, will become clearer from the following description of embodiments in conjunction with the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0048] The shapes, dimensions, ratios, angles, and quantities disclosed in the drawings used to describe embodiments of this disclosure are merely examples, and therefore, this disclosure is not limited to the illustrated details. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that such descriptions would unnecessarily obscure the focus of this disclosure. When the terms "comprising," "having," and "including" are used in this specification, additional parts may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0049] When interpreting an element, it is interpreted as including a range of errors, although this is not explicitly described.

[0050] When describing positional relationships, for example, when the positional relationship between two parts is described as "on," "above," "below," and "next to," one or more parts may be arranged between the two parts, unless "exactly" or "directly" is used.

[0051] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases can be included unless “exactly,” “immediately,” or “directly” are used.

[0052] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

[0053] In describing the elements of this disclosure, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used. These terms are intended to identify the corresponding element from other elements, and the basis, order, or number of the corresponding elements shall not be limited by these terms. The expression “connected,” “coupled,” or “adhered” to one element or layer means that the element or layer may be directly connected or adhered to the other element or layer, or indirectly connected or adhered to the other element or layer by means of one or more intermediary elements or layers “arranged” or “inserted” between the elements or layers, unless otherwise stated.

[0054] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of two or more of the first, second, and third items, as well as all items derived from the first, second, or third item.

[0055] Features of the various embodiments of this disclosure may be coupled or combined with each other in part or in whole, and may interoperate with each other in various ways as well as as can be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other or in a mutually dependent relationship.

[0056] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0057] Figure 1 This is an example diagram illustrating the configuration of a light-emitting display device according to an embodiment of the present disclosure. Figure 2 This is an example diagram illustrating the structure of a pixel applied to a light-emitting display device according to an embodiment of the present disclosure. Figure 3 This is an example diagram illustrating the configuration of a controller applied to a light-emitting display device according to an embodiment of the present disclosure. Figure 4 This is an example diagram illustrating the configuration of a gate driver applied to a light-emitting display device according to an embodiment of the present disclosure.

[0058] The light-emitting display device according to this disclosure can be configured with various electronic devices. These electronic devices may include, for example, smartphones or other smart devices, tablet PCs, televisions (TVs), navigation devices, wearable smart devices, and monitors.

[0059] According to the light-emitting display device of this disclosure, such as Figure 1 As shown, the display panel 100 may include a display area 120 for displaying images and a non-display area 130 disposed outside the display area 120; a gate driver 200 that provides gate signals to multiple gate lines GL1 to GLG disposed in the display area 120 of the display panel 100; a data driver 300 that provides data voltages to multiple data lines DL1 to DLd disposed in the display panel 100; a controller 400 that controls the driving of the gate driver 200 and the data driver 300; and a power supply 500 that supplies power to the controller, the gate driver, the data driver, and the display panel. Here, g, d, and n can be positive integers greater than zero.

[0060] First, the light-emitting display panel 100 may include a display area 120 and a non-display area 130. Gate lines GL1 to GLg, data lines DL1 to DLd, and a plurality of pixels 110 may be disposed in the display area 120. Accordingly, the display area 120 may display an image. Here, g and d may each be a natural number. The non-display area 130 may surround the outside of the display area 120.

[0061] Included in each pixel 110 in the luminescent display panel 100, such as Figure 2 As shown, it may include a light-emitting area, which includes a pixel driving circuit PDC and a light-emitting device ED. The pixel driving circuit PDC includes a switching transistor Tsw1, a storage capacitor Cst, a driving transistor Tdr, and a sensing transistor Tsw2.

[0062] The first terminal of the driving transistor Tdr can be connected to the high-voltage power line PLA, through which the high-voltage EVDD is provided, and the second terminal of the driving transistor Tdr can be connected to the light-emitting device ED.

[0063] The first terminal of the switching transistor Tswl can be connected to the data line DL, the second terminal of the switching transistor Tswl can be connected to the gate of the driving transistor Tdr, and the gate of the switching transistor Tswl can be connected to the gate line GL.

[0064] The data voltage Vdata can be provided to the data line DL, and the gate signal GS can be provided to the gate line GL.

[0065] A sensing transistor Tsw2 can be provided to measure the threshold voltage or mobility of the driving transistor Tdr. The first terminal of the sensing transistor Tsw2 can be connected to the second terminal of the driving transistor Tdr and the light-emitting device ED. The second terminal of the sensing transistor Tsw2 can be connected to the sensing line SL, through which a reference voltage Vref is provided. The gate of the sensing transistor Tsw2 can be connected to the sensing control line SCL, through which a sensing control signal SS is provided.

[0066] The sensing line SL can be connected to the data driver 300, or it can be connected to the power supply 500 through the data driver 300. That is, the reference voltage Vref provided from the power supply 500 can be provided to the pixel through the sensing line SL, and the sensing signal transmitted from the pixel through the sensing line SL can be processed by the data driver 300.

[0067] The structure of pixel 110 applied in this disclosure is not limited to Figure 2 The structure shown is such that the structure of pixel 110 can be changed to various configurations.

[0068] However, for the sake of convenience, the following text will include... Figure 2 The light-emitting display device for the pixels shown is described as an example of this disclosure.

[0069] Reference Figure 3 The controller 400 can realign the input video data Ri, Gi, and Bi transmitted from the external system by using the timing synchronization signal TSS transmitted from the external system, and can generate a data control signal DCS to be provided to the data driver 300 and a gate control signal GCS to be provided to the gate driver 200.

[0070] Therefore, such as Figure 3As shown, the controller 400 may include: a data aligner 430, which realigns input video data Ri, Gi, and Bi to generate image data and provides the image data to the data driver 300; a control signal generator 420, which generates a gate control signal GCS and a data control signal DCS using a timing synchronization signal TSS; an input unit 410, which receives the timing synchronization signal and the input video data Ri, Gi, and Bi transmitted from an external system, and transmits the timing synchronization signal and the input video data to the data aligner and the control signal generator, respectively; and an output unit 440, which provides the image data generated by the data aligner and the data control signal DCS generated by the control signal generator to the data driver 300, and provides the gate control signal GCS generated by the control signal generator to the gate driver 200. The controller 400 may include a storage unit 450 for storing various information.

[0071] An external system can perform the functions of the drive controller 400 and the electronic device. For example, when the electronic device is a television set, the external system can receive various audio, video, and text information through a communication network and can transmit the received video information to the controller 400. In this case, the image information may include input video information.

[0072] The power supply 500 can generate various powers and can provide the generated power to the controller 400, the gate driver 200, the data driver 300 and the light-emitting display panel 100.

[0073] The data driver 300 can be disposed on a chip-on-film (COF) attached to the light-emitting display panel 100, or it can be directly disposed in the light-emitting display panel 100.

[0074] The data driver 300 can supply the data voltage Vdata to the data lines DL1 to DLd during the display period of the displayed image.

[0075] The data driver 300 can convert the sensing signal received through the sensing line SL into digital sensing data, and can transmit the sensing data to the controller 400 during the sensing period. The sensing signal can be a signal associated with the characteristics of the driving transistor Tdr, or a signal associated with the characteristics of the light-emitting device ED.

[0076] In other words, during the sensing period, the threshold voltage of the driving transistor Tdr, the mobility of the driving transistor Tdr, or the current flowing through the light-emitting device ED can be sensed.

[0077] Here, the sensing period can be the period from when the light-emitting display device is turned on until the start of the display period, or it can be the period from when the display period ends until the light-emitting display device is turned off.

[0078] Turning on the light-emitting display device indicates that power is supplied to the controller 400, gate driver 200, data driver 300, and power supply 500 that configure the light-emitting display device. Therefore, the controller 400, gate driver 200, data driver 300, and power supply 500 are driven. When the controller 400, gate driver 200, data driver 300, and power supply 500 are normally driven with the light-emitting display device turned on, a display period can begin, and an image can be displayed through the light-emitting display panel 100.

[0079] Turning off the light-emitting display device can mean supplying only the minimum power to the light-emitting display device. For example, when the light-emitting display device is off, the controller 400 can be powered only by the power supply 500, so only the minimum function of the light-emitting display device can be performed.

[0080] As described above, the sensing period can be the period from when the light-emitting display device is turned on until the start of the display period, or it can be the period from when the display period ends until the light-emitting display device is turned off.

[0081] In the following description, for ease of description, the light-emitting display device that is the period from the end of the display period until the light-emitting display device is turned off will be described as an example of this disclosure.

[0082] In other words, during the image display period, when the user turns off the power to the electronic device (e.g., by pressing the power button on the electronic device or remote control), the light-emitting display device can stop displaying the image and perform a sensing operation. When the sensing operation is complete, the light-emitting display device can be completely turned off. Here, the period during which the sensing operation is performed can be a sensing period.

[0083] Finally, the gate driver 200 can be configured as an integrated circuit (IC) and can be mounted in the non-display area 130. Alternatively, the gate driver 200 can be directly embedded in the non-display area 130 using a gate-in-panel (GIP) type. When using the GIP type, the transistors constituting the gate driver 200 can be implemented in the non-display area using the same process as the transistors included in each pixel 110.

[0084] The gate driver 200 can provide gate pulses GP1 to GPg to gate lines GL1 to GLg.

[0085] When a gate pulse generated by the gate driver 200 is supplied to the gate of the switching transistor Tswl included in the pixel 110, the switching transistor Tswl can be turned on. When the switching transistor Tswl is turned on, the data voltage supplied through the data line can be provided to the pixel 110.

[0086] When a gate cutoff signal generated by the gate driver 200 is provided to the switching transistor Tsw1, the switching transistor Tsw1 can be turned off. When the switching transistor Tsw1 is turned off, the data voltage is not provided to the pixel 109.

[0087] The gate signal GS provided to the gate line GL may include a gate pulse and a gate cutoff signal.

[0088] Therefore, such as Figure 4 As shown, the gate driver 200 may include multiple stages 201 (e.g., stage 1-g, where g is a positive integer greater than zero).

[0089] Each of stage 201 can be connected to at least one gate line GL. Each stage 201 can be driven based on a start signal transmitted from controller 400, or it can be driven based on a carry signal transmitted from the previous or next stage.

[0090] Here, the preceding stage can refer to the stage that is driven before the currently driven stage and outputs a gate pulse. In this case, the preceding stage can be adjacent to the currently driven stage, or at least one other stage can be set between the preceding stage and the currently driven stage.

[0091] Furthermore, the next stage can represent a stage that is driven later than the currently driven stage and outputs a gate pulse. In this case, the next stage can be adjacent to the currently driven stage, or at least one other stage can be set between the next stage and the currently driven stage.

[0092] Each of stage 201 may include at least two transistors and can be configured in various types.

[0093] In the following text, reference will be made to Figures 5 to 8 Describe the configuration and functionality of each level 201.

[0094] Figure 5 This is an example diagram illustrating, schematically, the configuration of a stage applied to a light-emitting display device according to an embodiment of the present disclosure.

[0095] As described above, the gate driver 200 may include multiple stages 201, and each stage 201 may be connected to at least one gate line GL.

[0096] In the following description, stage 201 connected to at least two gate lines will be described as an example embodiment of the present disclosure, and more specifically, stage 201 connected to four gate lines will be described as an example of the present disclosure.

[0097] In this case, such as Figure 5As shown, each stage may include: a signal output unit 220 that sequentially outputs gate pulses to at least two gate lines; a signal controller 210 that controls the signal output unit 220; and a sensing selector 230 that stores a selection signal during the sensing period and controls the signal output unit 220 by using the selection signal during the sensing execution period.

[0098] First, the signal output unit 220 can sequentially output gate pulses to at least two gate lines.

[0099] For example, such as Figure 5 As shown, the signal output unit 220 can output gate pulses GPk, GPk+1, GPk+2 and GPk+3 (where k is a natural number less than g) to four gate lines.

[0100] For this purpose, four gate clocks SCCLK1 to SCCLK4 with different phases can be provided to the signal output unit 220. Four gate pulses GPk, GPk+1, GPk+2 and GPk+3 can be output based on the four gate clocks SCCLK1 to SCCLK4.

[0101] Four gate pulses, GPk, GPk+1, GPk+2 and GPk+3, can be sequentially supplied to the four gate lines.

[0102] The signal output unit 220 can output the gate cutoff signal to the gate line that does not output the gate pulse.

[0103] Therefore, the signal output unit 220 may include a transistor.

[0104] Secondly, the signal controller 210 can perform the function of controlling the signal output unit 220.

[0105] In other words, the signal controller 210 can control the signals supplied to the Q node and the signals supplied to the Qb node; therefore, the signal output unit 220 can output a gate pulse or a gate cutoff signal (see, for example, [reference needed]). Figure 5 and Figure 6 ).

[0106] The signal controller 210 can be driven based on the start signal transmitted from the controller 400 or the carry signal transmitted from the previous state or the next level, and the Q node control signal can be transmitted to the Q node Q.

[0107] The signal output unit 220 can sequentially output at least two gate pulses based on the Q-node control signal.

[0108] The signal controller 210 can be driven based on the carry signal transmitted to the previous or next stage, and the Qb node control signal can be transmitted to the Qb node Qb.

[0109] The signal output unit 220 can output a gate cutoff signal to the gate line based on the Qb node control signal. According to an embodiment of the present invention, the Qb node can be effectively precharged or can be prepared more quickly, and can perform sensing of pixels connected to each gate line more quickly during power-off sensing, thus improving the user experience and reducing power consumption.

[0110] The structure of the signal controller 210 is currently used to configure the gate driver, or one of the various structures known to those skilled in the art may be applied.

[0111] In other words, the signal controller 210 can be configured differently to have various structures and functions known to those skilled in the art.

[0112] Third, the sensing selector 230 can store the selection signal during the sensing selection period and can control the signal output unit 220 by using the selection signal during the sensing execution period.

[0113] Specifically, in this disclosure, during the sensing selection period, the selection signal can be stored in a sensing selector 230 included in at least two stages.

[0114] Therefore, during the sensing period, pixels connected to gate lines that are connected to at least two stages can be sensed (e.g., pixels connected to more than one gate line can be sensed during the same sensing period).

[0115] The sensor selector 230 can store the carry signal CS provided from the previous or next stage as a selection signal. Specifically, when a sensing control pulse configuring the sensing control signal LSP is transmitted to the sensor selector 230, the carry signal CS can be stored in the sensor selector 230.

[0116] The sensor selector 230 can be initialized based on the select carry signal CS provided from the previous or next stage. When the sensor selector 230 is initialized, the select signal stored in the sensor selector 230 can be deleted.

[0117] When a reset pulse configuring the reset signal RESET is transmitted to the sense selector 230, the sense selector 230 can provide a selection signal to the signal output unit 220 through the Q node Q. Therefore, gate pulses can be sequentially output from the signal output unit 220.

[0118] When an initialization voltage VST is input after a reset pulse is provided, a gate pulse may not be output from signal output unit 220.

[0119] Figure 6These are example diagrams illustrating in detail the configuration of a stage applied to a light-emitting display device according to embodiments of the present disclosure. That is, Figure 6 The above reference is an example. Figure 5 Detailed examples of stages are described, and specifically, stage n (stage n) is illustrated. In the following description, stage 201 connected to four gate lines is described as an example of this disclosure. Therefore, the following description can be applied to stage 201 connected to two gate lines, stage connected to three gate lines, and stage connected to five or more gate lines. For example, each of the sense selector 230, signal controller 210, and signal output unit 220 may correspond to Figure 6 The circuit shown consists of different circuit sections.

[0120] First, the signal output unit 220 can output the gate pulse and the gate cutoff signal to the four gate lines. That is, the signal output unit 220 can output the gate signals GS(4n-3), GS(4n-2), GS(4n-1), and GS(4n) to the four gate lines.

[0121] In this case, such as Figure 1 As shown, the four gate lines may include gate lines GL4n-3 to GL4n, where n is a positive integer greater than zero.

[0122] In order to output four gate pulses, the signal output unit 220 may include four pull-up transistors Tu1 to Tu4.

[0123] The gates of the four pull-up transistors Tu1 to Tu4 can be connected to the signal controller 210 via the Q node Q.

[0124] The first terminals of the four pull-up transistors Tu1 to Tu4 can be connected to the lines that provide the first gate clock SCCLK1 to the fourth gate clock SCCLK4, respectively.

[0125] The first gate clock SCCLK1 to the fourth gate clock SCCLK4 can have different phases. Four gate pulses can be output sequentially based on the first gate clock SCCLK1 to the fourth gate clock SCCLK4.

[0126] The second terminals of the four pull-up transistors Tu1 to Tu4 can be connected to the gate lines GL4n-3 to GL4n, respectively.

[0127] The signal output unit 220 may include a first carry output transistor Tc1 for outputting a carry signal C. The carry signal C output from stage n may be provided to the previous stage and the next stage. The signal controllers 210 of the previous and next stages may be driven by the carry signal C, or the sense selector 230 may be driven.

[0128] As mentioned above, the preceding level can be the (n-1)th level adjacent to the nth level, or it can be one of the levels separate from the nth level. Furthermore, the next level can be the (n+1)th level adjacent to the nth level, or it can be one of the levels different from the nth level.

[0129] The gate of the first carry-out transistor Tc1 can be connected to the Q node Q. The first terminal of the first carry-out transistor Tc1 can be connected to the line through which the 4n-3 carry clock SRCLK(4n-3) is input. The second terminal of the first carry-out transistor Tc1 can be connected to the carry-out line. As described above, the carry-out line can be connected to the previous stage and the next stage.

[0130] In order to output the gate cutoff signal to the four gate lines, the signal output unit 220 may include four pull-down transistors Tdn1 to Tdn4.

[0131] The gates of the four pull-down transistors Tdn1 to Tdn4 can be connected to the signal controller 210 via the Qb node Qb.

[0132] The first terminals of the four pull-down transistors Tdn1 to Tdn4 can be connected to the gate lines GL4n-3 to GL4n, respectively.

[0133] The second terminals of the four pull-down transistors Tdn1 to Tdn4 can be connected to the line that provides the gate cutoff voltage GVSS2, which is to be used as the gate cutoff signal.

[0134] The gate of the second carry-out transistor Tc2 can be connected to node Qb, the first terminal of the second carry-out transistor Tc2 can be connected to the first terminal of the second carry-out transistor Tc2, and the second terminal of the second carry-out transistor Tc2 can be connected to the line that provides the carry voltage GVSS1. The carry cutoff voltage GVSS1 can be equal to or different from the gate cutoff voltage GVSS2.

[0135] A carry signal C with a high or low level can be output through the first carry output transistor Tc1 and the second carry output transistor Tc2. The carry signal C output from stage n is as follows: Figure 6As shown, it can be the carry signal C(4n-3) of the 4n-3rd bit.

[0136] For example, a carry signal C with a high level can be output through the first carry output transistor Tc1, and a carry signal C with a low level can be output through the second carry output transistor Tc2.

[0137] Secondly, the signal controller 210 can perform the function of controlling the signal output unit 220.

[0138] In other words, the signal controller 210 can be driven by the carry signal C provided from the previous stage or the next stage. Therefore, a Q-node control signal that enables the output gate pulse can be provided to the Q-node Q, and a Q-node control signal that enables the output gate cutoff signal can be provided to the Q-node Qb.

[0139] As described above, the signal controller 210 can be configured as one of the various configurations currently in use or used to configure the gate driver 200 that are known to those skilled in the art.

[0140] Furthermore, the features of this disclosure do not correspond to the signal controller 210. Therefore, Figure 6 A detailed description of the signal controller 210 shown is omitted.

[0141] The configuration and functions of the signal controller 210 will be briefly described below.

[0142] For example, when a start signal Vs is provided from controller 400 or the previous stage, signal controller 210 can provide a first drive voltage GVDD1 to Q node Q. The start signal Vs provided from the previous stage can be a carry signal C.

[0143] The pull-up transistors Tu1 to Tu4 of the signal output unit 220 can be turned on by the first driving voltage GVDD1, and the first gate clock SCCLK1 to the fourth gate clock SCCLK4 can be input to the turned-on pull-up transistors Tu1 to Tu4.

[0144] Four gate pulses can be output as four gate lines GL4n-3 to GL4n using the first gate clock SCCLK1 to the fourth gate clock SCCLK4.

[0145] When a cutoff signal Vr is received from the previous or next stage after four gate pulses have been output, pull-up transistors Tu1 to Tu4 can be turned off, thus eliminating the need to output gate pulses. The cutoff signal Vr transmitted from the previous or next stage can be a carry signal C.

[0146] In this configuration, pull-down transistors Tdn1 to Tdn4 can be turned on, and the gate cutoff voltage GVSS2 can be output to the four gate lines GL4n-3 to GL4n through pull-down transistors Tdn1 to Tdn4. The gate cutoff voltage GVSS2 can be the gate cutoff signal.

[0147] Another stage that has received the carry signal C from the nth stage can sequentially output gate pulses to other gate lines, and after outputting the gate pulses, it can output a gate cutoff signal from another stage.

[0148] When the above process is repeated through all stages, the gate pulse GP can be sequentially provided to the first to the g gate lines GL1 to GLg.

[0149] Third, the sensing selector 230 can store the selection signal during the sensing selection period, and can control the signal output unit 220 by using the selection signal during the sensing period.

[0150] Therefore, such as Figure 6 As shown, the sensing selector 230 may include a selection signal storage unit 233 (e.g., capacitor C1), a selection signal controller 231 (e.g., transistors T1, T2 and T3), a selection signal transmitter 232 (e.g., transistor T4), and a reset unit 234 (e.g., transistors T5 and T6).

[0151] First, the basic characteristics of the elements constituting the sensing selector 230 will be described below.

[0152] The selection signal controller 231 can transmit the selection carry signal CS from the previous stage to the selection signal transmitter 232 based on the first sensing control pulse input during the sensing selection period.

[0153] The selection signal transmitter 232 can transmit the selection carry signal CS received by the selection signal controller 231 to the selection signal storage unit 233.

[0154] The selection signal storage unit 233 can store the selection carry signal CS. Specifically, the selection signal storage unit 233 can store the selection carry signal CS as a selection signal. The selection signal storage unit 233 can be a capacitor. The capacitor constituting the selection signal storage unit 233 can be called the selection signal capacitor C1.

[0155] The reset unit 234 can transmit the selection signal to the signal output unit 220 during the selected execution period.

[0156] The structure and function of the selection signal controller 231 will be described below.

[0157] The selection signal controller 231 may include a first transistor T1. A first terminal of the first transistor T1 may receive a selection carry signal CS, a second terminal of the first transistor T1 may be connected to the selection signal transmitter 232, and a sensing control signal LSP may be input to the gate of the first transistor T1.

[0158] The signal controller 231 may also include a second transistor T2 and a third transistor T3.

[0159] The first terminal of the second transistor T2 can be connected to the second terminal of the first transistor T1, the second terminal of the second transistor T2 can be connected to the selection signal transmitter 232, and the gate of the second transistor T2 can be connected to the gate of the first transistor T1.

[0160] The first terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1, the second terminal of the third transistor T3 can be connected to the first terminal of the selection signal capacitor C1, and the gate of the third transistor T3 can be connected to the second terminal of the selection signal capacitor C1.

[0161] In this case, the first terminal of the selection signal capacitor C1 can be connected to the line that provides the first drive voltage GVDD1 through the line, and the second terminal of the selection signal capacitor C1 can be connected to the selection signal transmitter 232.

[0162] In other words, the selection signal controller 231 may consist of only the first transistor T1. In this case, the selection carry signal CS provided by the first transistor T1 can be stored in the selection signal storage unit 233 via the selection signal transmitter 232. The selection carry signal CS stored in the selection signal storage unit 233 may be referred to as the selection signal.

[0163] However, in order to enhance the storage capacity of the selection signal storage unit 233, the selection signal controller 231 may also include a second transistor T2 and a third transistor T3.

[0164] The structure and function of the selection signal transmitter 232 will be described below.

[0165] Selecting the signal transmitter 232 may include a fourth transistor T4.

[0166] The first terminal of the fourth transistor T4 can be connected to the second terminal of the first transistor T1, the second terminal of the fourth transistor T4 can be connected to the second terminal of the selection signal capacitor C1, and the gate of the fourth transistor T4 can be connected to the line that provides the first carry control clock CC. When the selection signal controller 231 also includes a second transistor T2 and a third transistor T3, the first terminal of the fourth transistor T4 can be connected to the second terminal of the second transistor T2, and the second terminal of the fourth transistor T4 can be connected to the gate of the third transistor T3.

[0167] When the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, the carry signal CS can be transmitted and stored in the selection signal storage unit 233.

[0168] However, when the first transistor T1, the second transistor T2, and the fourth transistor T4 are turned on, the selection signal stored in the selection signal storage unit 233 can be discharged through the selection carry signal CS. Therefore, the selection signal can be deleted from the selection signal storage unit 233.

[0169] The structure and function of the reset unit 234 will be described below.

[0170] The reset unit 234 may include a fifth transistor T5 and a sixth transistor T6.

[0171] The first terminal of the fifth transistor T5 can be connected to the line that provides the first drive voltage GVDD1, the second terminal of the fifth transistor T5 can be connected to the first terminal of the sixth transistor T6, and the gate of the fifth transistor T5 can be connected to the selection signal storage unit 233 and the selection signal transmitter 232. Specifically, the gate of the fifth transistor T5 can be connected to the second terminal of the selection signal capacitor C1.

[0172] The first terminal of the sixth transistor T6 can be connected to the second terminal of the fifth transistor T5, the second terminal of the sixth transistor T6 can be connected to the signal output unit 220, and the gate of the sixth transistor T6 can be connected to the line input reset signal RESET. Specifically, the second terminal of the sixth transistor T6 can be connected to the signal output unit 220 through the Q node Q.

[0173] The sixth transistor T6 can be turned on by the reset pulse constituting the reset signal RESET during the sensing period. Therefore, the selection signal can be provided to the signal output unit 220 and the signal output unit 220 can output at least two gate pulses based on the selection signal.

[0174] Finally, the sense selector 230 may include an initialization unit 235. When the initialization voltage VST is input to the initialization unit 235 after the reset pulse is provided to the reset unit 234, the gate pulse may not be output from the signal output unit 220.

[0175] In other words, when the input initialization voltage VST is applied, the initialization unit 235 can transmit the carry-off voltage GVSS1 to the Q node Q. The pull-up transistors Tu1 to Tu4 can be turned off by the carry-off voltage GVSS1, therefore, gate pulses will not be output through the pull-up transistors Tu1 to Tu4.

[0176] Initialize unit 235, such as Figure 6 As shown, it may include a seventh transistor T7 and an eighth transistor T8.

[0177] The first terminal of the seventh transistor T7 can be connected to the Q node Q, the second terminal of the seventh transistor T7 can be connected to the first terminal of the eighth transistor T8, and the gate of the seventh transistor T7 can be connected to the line that provides the initialization voltage VST.

[0178] The first terminal of the eighth transistor T8 can be connected to the second terminal of the seventh transistor T7, the second terminal of the eighth transistor T8 can be connected to the line that provides the carry cutoff voltage GVSS1, and the gate of the eighth transistor T8 can be connected to the gate of the seventh transistor T7.

[0179] In the following text, reference will be made to Figures 1 to 8 The operation method of the light-emitting display device according to this disclosure is described.

[0180] Specifically, Figure 7 This is an example diagram illustrating two stages applied to a light-emitting display device according to an embodiment of the present disclosure, and Figure 8 This is an example diagram illustrating the waveform of a signal applied to a light-emitting display device according to an embodiment of the present disclosure. In the following description, references to the above are... Figures 1 to 6 Descriptions that are identical or similar to those given will be omitted or will be given only briefly.

[0181] As described above, one of the objectives of this disclosure is to provide a light-emitting display device capable of sensing pixels connected to at least two gate lines during one frame period of a sensing time.

[0182] Specifically, at least two gate lines can be connected to at least two stages. That is, in this disclosure, pixels connected to at least two gate lines that are connected to at least two stages can be sensed during the sensing period.

[0183] The following describes a method for sensing pixels connected to eight gate lines connected to two stages during a sensing period. Therefore, the following description can be applied to a method for sensing pixels connected to all gate lines connected to two or more stages, where at least two gate lines can be connected to one stage.

[0184] In the following description, such as Figure 7 As shown, the two levels can include the nth level (Stage n) and the (n+1)th level (Stage n+1).

[0185] Each of Stage n and Stage n+1 can include the above references Figure 6 The components described are the same as those in Stage n. In this case, as described above, the structure of the signal controller 210 can be modified to various types. Therefore, in Figure 7 The detailed structure of the signal controller 210 constituting Stage n and Stage n+1 is not illustrated herein. However, a detailed example of the signal controller 210 is provided in [the document / document / etc.]. Figure 6 As shown in the figure. Therefore, a detailed description of the signal controller 210 is omitted below.

[0186] The internal configurations of Stage n and Stage (n+1) can be identical. Furthermore, the first drive voltage GVDD1, gate cutoff voltage GVSS2, carry cutoff voltage GVSS1, and sense control signal LSP input to Stage n can be the same as those input to Stage (n+1). In this case, the sense control signal LSP can be transmitted from the controller 400. That is, the sense control signal LSP can be included in the gate control signal GCS.

[0187] However, the carry signal CS input to stage n can be a different signal than the carry signal CS input to stage (n+1). Furthermore, the phase of the first carry signal CS1 input to stage n can be opposite to the phase of the second carry signal CS2 input to stage (n+1).

[0188] In the following description, the select carry signal CS input to the nth stage is the 4n-5th gate signal output to the 4n-5th gate line, and the select carry signal CS input to the n+1th stage is the 4n-4th gate signal output to the 4n-4th gate line. Such a light-emitting display device will be described as an example of this disclosure.

[0189] In other words, the carry signal CS can be one of the carry signals C output by the first carry transistor Tc1 and the second carry transistor Tc2 included in the previous stage or the next stage, or it can be one of the gate signals GS output to the gate line connected to the previous stage or the next stage.

[0190] For additional description, the select carry signal CS input to the nth stage and the (n+1)th stage can be selected from various signals generated by the previous or next stage (e.g., gate signal GS and carry signal C).

[0191] In the following text, the (4n-5)th gate signal output to the (4n-5)th gate line can be called the (4n-5)th select carry signal CS(4n-5), and the (4n-4)th gate signal output to the (4n-4)th gate line can be called the (4n-4)th select carry signal CS(4n-4). Therefore, as Figure 8 As shown, the 4n-5th gate pulse GP4n-5 can be included in the 4n-5th select carry signal CS(4n-5), and the 4n-4th gate pulse GP4n-4 can be included in the 4n-4th select carry signal CS(4n-4).

[0192] The gate pulse GP4n-3, output to the gate line 4n-3 connected to stage n, can also be used as the carry signal CS for another stage. Therefore, in Figure 8 In this context, the gate signal GS, which includes the gate pulse GP4n-3 output to the gate line 4n-3, is exemplified as the carry signal CS(4n-3) selected by the gate pulse GP4n-3.

[0193] In other words, the carry signal CS(4n-5), the carry signal CS(4n-4), and the carry signal CS(4n-3) can be as follows: Figure 8 The signals generated in the sequence shown.

[0194] Furthermore, the first gate clock SCCLK1 to the fourth gate clock SCCLK4 input to stage n can be signals different from the fifth gate clock SCCLK5 to the eighth gate clock SCCLK8 input to stage n+1. That is, as... Figure 8 As shown, the first gate clock SCCLK1 to the fourth gate clock SCCLK4 and the fifth gate clock SCCLK5 to the eighth gate clock SCCLK8 can be different signals with different phases.

[0195] In this case, the first gate clock SCCLK1 to the fourth gate clock SCCLK4 can be provided to the nth stage (nth stage), and then the fifth gate clock SCCLK5 to the eighth gate clock SCCLK8 can be input to the (n+1)th stage (Stagen+1).

[0196] By using the first gate clock SCCLK1 to the fourth gate clock SCCLK4 and the fifth gate clock SCCLK5 to the eighth gate clock SCCLK8, the gate pulses can be sequentially output to the 4n-3 gate line GL4n-3 to the 4n+4 gate line GL4n+4.

[0197] First, when the display period DP begins after the light-emitting display device is turned on, the controller 400, gate driver 200 and data driver 300 can be driven, so that the light-emitting display panel 100 can display an image.

[0198] Subsequently, when the user turns off the power to the light-emitting display device or electronic device during the display period DP, the display period DP can end, and the sensing period SP can begin.

[0199] In other words, during the display period DP when the user turns off the power to the electronic device (e.g., by pressing the power button on the electronic device or remote control), the light-emitting display device can stop displaying the image and perform a sensing operation. Here, the period during which the sensing operation is performed can be the sensing period SP.

[0200] Subsequently, when the display period ends, the sensing period SP can begin. Alternatively, the sensing period can be executed at startup (during the power-on sequence) before the first display frame is displayed or between active drivers or display frames during the blanking period.

[0201] In the following description, the sensing period may include sensing selection period A and pixel sensing period B.

[0202] Furthermore, in the following description, the sensing period can be executed as a sequence of periods (e.g., a series of selected period A and pixel sensing period B).

[0203] In other words, the first sensing period executed after the start of the sensing period SP can be called the first sensing period, and the second sensing period executed can be called the second sensing period.

[0204] After the first sensing period, the second to the (m-1)th sensing periods can be repeated, and when the (m-1)th sensing period ends, the mth period can begin (where m is a natural number less than g).

[0205] The same type of operation can be performed in each of the first to m-th time periods. Therefore, the m-th time period will be described below as an example of this disclosure. That is, sensing operations can be performed on pixels connected to the n-th and (n+1)-th stages in the m-th time period. Figure 8 In this context, the first to the (m-1)th time interval is represented by C.

[0206] Subsequently, when the m-th time period begins, the sensing selection time period A can begin.

[0207] When the sensing selection period A begins, the signal controller 210 of Stage 1 can be driven and can sequentially output gate pulses to the first gate line GL1 through the fourth gate line GL4. In this case, the data driver 300 can output the data voltage Vdata representing black to the data lines DL1 through DLd. Therefore, the light-emitting display device can display a black image or a black screen. Thus, although sensing operation is being performed, the user can still recognize that the light-emitting display device is turned off.

[0208] Subsequently, the second stage (Stage 2) can be driven and can sequentially output gate pulses to the fifth through eighth gate lines.

[0209] This operation can be repeated up to level n-1.

[0210] The (n-1)th stage can output gate pulses from the 4n-7th to the 4n-4th stage, and then the nth stage can be driven.

[0211] In this case, as described above, the 4n-5th gate pulse GP4n-5 output to the 4n-5th gate line can be input as the carry signal CS of the nth stage. That is, the 4n-5th carry signal CS(4n-5) can be input to the selection signal controller 231 of the nth stage.

[0212] When the carry signal CS(4n-5) is input to the selection signal controller 231 of stage n, the controller 400 can provide a first carry control clock CC1 and a first sensing control pulse SP1 with a high level to stage n. The first sensing control pulse SP1 and the first carry control clock CC1 can be included in the gate control signal GCS.

[0213] In other words, information about sensing performed on pixels connected to stage n and stage n+1 during time period m can be stored in controller 400, or information related to sensing control signal LSP including a first sensing control pulse SP1 based on timing settings can be stored in controller 400.

[0214] When the carry signal CS(4n-5) is input to the selection signal controller 231 of stage n, the first transistor T1 and the second transistor T2 of the selection signal controller 231 can be turned on by the first sensing control pulse SP1 with a high level when the sensing control pulse SP1 is provided to stage n.

[0215] In this case, the fourth transistor T4 of the select signal transmitter 232 can also be turned on by the first carry control clock CC1 with a high level.

[0216] When the first transistor T1, the second transistor T2, and the fourth transistor T4 of stage n are turned on, the 4n-5 select carry signal CS(4n-5) can be stored in the selection signal storage unit 233 (e.g., capacitor C1) of stage n through the first transistor T1, the second transistor T2, and the fourth transistor T4.

[0217] In this case, the 4n-5th select carry signal CS(4n-5) with a high level can be the select signal.

[0218] Subsequently, the 4n-4th gate pulse GP4n-5, output to the 4n-4th gate line, can be input as the carry signal CS for the (n+1)th stage. That is, the 4n-4th carry signal CS (4n-4) can be input to the selection signal controller 231 for the (n+1)th stage.

[0219] When the carry signal CS(4n-4) is input to the selection signal controller 231 of stage n+1, the controller 400 can provide stage n+1 with a second carry control clock CC2 and a first sensing control pulse SP1 with a high level. That is, the first sensing control pulse SP1 provided to stage n can be provided to stage n+1.

[0220] Therefore, the pulse width of the first sensing control pulse SP1 can be set to be equal to or greater than the pulse width of each of the (4n-5)th carry selection signal CS(4n-5) and the (4n-4)th carry selection signal CS(4n-4). Furthermore, the first carry control clock CC1 and the second carry control clock CC2 can be clocks that alternately have a high level, and the width of each of the first carry control clock CC1 and the second carry control clock CC2 can be set to be equal to the pulse width of each of the (4n-5)th carry selection signal CS(4n-5) and the (4n-4)th carry selection signal CS(4n-4).

[0221] When the 4n-4th select carry signal CS(4n-4) is input to the selection signal controller 231 of the (n+1)th stage, the first transistor T1 and the second transistor T2 of the selection signal controller 231 can be turned on by the first sensing control pulse SP1 with a high level when the sensing control pulse SP1 is provided to the (n+1)th stage.

[0222] In this case, the fourth transistor T4 of the selection signal transmitter 232 of stage n+1 can also be turned on by the second carry control clock CC2 with a high level.

[0223] When the first transistor T1, the second transistor T2, and the fourth transistor T4 of the (n+1)th stage are turned on, the 4n-4th carry signal CS(4n-4) can be stored in the selection signal storage unit 233 of the (n+1)th stage through the first transistor T1, the second transistor T2, and the fourth transistor T4 of the (n+1)th stage.

[0224] In this case, the 4n-4th select carry signal CS(4n-4) with a high level can be the select signal.

[0225] Through the above processing, during the sensing selection period A, the 4n-5th selection carry signal CS(4n-5) with a high level can be stored in the selection signal storage unit 233 of the nth stage, and the 4n-4th selection carry signal CS(4n-4) with a high level can be stored in the selection signal storage unit 233 of the n+1th stage.

[0226] Subsequently, other stages can be driven sequentially, so gate pulses can be output sequentially to other gate lines.

[0227] In this case, the high-level sensing control signal LSP may not be provided to the stage.

[0228] In other words, a sensing control signal LSP (i.e., the first sensing control pulse SP1) with a high level can be provided to the stage only at the moment when the storage selection signal of the sensing selection period A is being provided. At the moment when the first sensing control pulse SP1 is provided, a selection carry signal with a high level (e.g., only the 4n-5th selection carry signal CS(4n-5) and the 4n-4th selection carry signal CS(4n-4)) can be stored as a selection signal in the respective selection signal storage unit 233 of the nth stage and the (n+1)th stage.

[0229] Subsequently, when the sensing selection period A for sensing pixels connected to one set of gate lines ends, the sensing period B for sensing pixels connected to another set of gate lines can begin.

[0230] When sensing period B begins, controller 400 may provide a high-level reset signal RESET (e.g., reset pulse RP) to the stage.

[0231] like Figure 8 As shown, the reset pulse RP can have a pulse width of 8H. Here, 1H can be the pulse width of the carry-select signal CS. That is, the pulse width of the reset pulse RP can be at least eight times the pulse width of the carry-select signal CS. In this case, the pulse width of the first sensing control pulse SP1 can be 2H. For example, the pulse width of the reset pulse RP can be greater than the pulse width of the sensing control pulse SP, and the pulse width of the sensing control pulse SP can be greater than the pulse width of the carry-select signal CS (e.g., the pulse width of RP > the pulse width of SP > the pulse width of CS).

[0232] When the reset pulse RP is provided to stage n and stage n+1, the sixth transistor T6 in the reset unit 234 in each of stage n and stage n+1 can be turned on, so that the first drive voltage GVDD1 with a high level can be applied to the Q node.

[0233] In other words, because the fifth transistor T5 is turned on by the selection signal and the sixth transistor T6 is turned on by the reset pulse RP, the first drive voltage GVDD1 can be applied to the Q node through the fifth transistor T5 and the sixth transistor T6.

[0234] Therefore, the first pull-up transistor Tu1 to the fourth pull-up transistor Tu4 in each of the nth stage and the (n+1)th stage can be turned on.

[0235] Subsequently, when the first pull-up transistor Tu1 to the fourth pull-up transistor Tu4 in each of the nth and n+1th stages are turned on during 8H when the first drive voltage GVDD1 is applied to the Q node, the 4n-3 to 4n+4 gate pulses can be sequentially provided to the 4n-3 gate line GL4n-3 to the 4n+4 gate line GL4n+4 during 8H based on the first gate clock SCCLK1 to the eighth gate clock SCCLK8.

[0236] Subsequently, when the gate pulses from the 4n-3rd to the 4n+4th are supplied to the gate lines from the 4n-3rd to the 4n+4th, the corresponding switching transistor Tswl connected to each of the gate lines from the 4n-3rd to the 4n+4th, the data voltage can be supplied to the corresponding driving transistor Tdr.

[0237] In this case, when the sensing transistor Tsw2 is turned on by the sensing control signal SS, information fragments associated with the characteristics of the driving transistor Tdr or the characteristics of the light-emitting device ED can be transmitted to the data driver 300 through the sensing transistor Tsw2 and the sensing line SL.

[0238] The data driver 300 can convert the sensing signal received through the sensing line SL into digital sensing data and can transmit the sensing data to the controller 400.

[0239] The controller can calculate the change in the threshold voltage of the driving transistor Tdr, the change in the mobility of the driving transistor Tdr, the change in the current flowing in the light-emitting device ED, or the change in the voltage applied to the light-emitting device ED using sensing data.

[0240] In other words, during sensing period B, as described above, sensing operations can be performed on pixels connected to gate lines GL4n-3 to GL4n+4 connected to the nth and n+1th stages (e.g., during sensing period B, pixels connected to 8 different gate lines can be sensed).

[0241] Subsequently, when sensing period B ends, sensing selection period A' of the (m+1)th sensing period can begin, and then pixels connected to eight different gate lines in different groups can be sensed, and this process can be repeated until all pixels have been sensed during the power-off sensing sequence. Alternatively, sensing during the power-on sensing sequence or between display frames can be implemented as real-time sensing.

[0242] In this case, as described in conjunction with the sensing selection period A of the m-th time period, the n-th to n-1-th stages can be driven sequentially, and thus, the gate pulses can be sequentially output to the gate line.

[0243] When the high-level selection carry signals CS(4n-5) and CS(4n-4) are input to the nth stage and the (n+1)th stage, the high-level selection control signal LSP may not be provided.

[0244] Therefore, the selection signal may not be provided to stage n and stage (n+1). However, the selection signal stored in stage m can still be stored in stage n and stage (n+1).

[0245] Subsequently, as Figure 8 As shown, during the sensing selection period A' of the (m+1)th time period, a high-level selection control signal LSP (i.e., the second sensing control pulse SP2) can be provided to all levels.

[0246] In this case, a high-level select carry signal CS can be provided to the two stages to be sensed in the sensing period of the (m+1)th time period, so the select signal can be stored in the two stages.

[0247] However, as Figure 8As shown, when the second sensing control pulse SP2 is provided to the nth stage and the (n+1)th stage, the 4n-5th carry selection signal CS(4n-5) and the 4n-4th carry selection signal CS(4n-4) with low level can be provided to the nth stage and the (n+1)th stage, and the first carry control clock CC1 with high level and the second carry control clock CC2 with high level can be provided to the nth stage and the (n+1)th stage in sequence.

[0248] Therefore, the first transistor T1 and the second transistor T2 of stage n can be turned on by the second sensing control pulse SP2, and the fourth transistor T4 can be turned on by the first carry control clock CC1 with a high level. Thus, a low level can be provided to the first terminal of the first transistor T1 of stage n.

[0249] Furthermore, the first transistor T1 and the second transistor T2 of the (n+1)th stage can be turned on by the second sensing control pulse SP2, and the fourth transistor T4 can be turned on by the second carry control clock CC2 with a high level. Therefore, a low level can be provided to the first terminal of the first transistor T1 of the (n+1)th stage.

[0250] Therefore, the high-level selection signal in the selection signal capacitor C1 of the selection signal storage unit 233 stored in each of the nth stage and the (n+1)th stage can be discharged to the first terminal of the first transistor T1 through the fourth transistor T4, the second transistor T2 and the first transistor T1.

[0251] Therefore, the selection signal no longer needs to be stored in stage n and stage (n+1), and the selection signal can be cleared from these two stages.

[0252] In other words, through the above processing, during the sensing selection period A' of the (m+1)th time period, the selection signal can be stored in two stages, which will be sensed during the sensing period of the (m+1)th time period, and the selection signal stored in the nth stage (Stage n) and the (n+1)th stage (Stage n+1) can be discharged (e.g., deleted or cleared).

[0253] Subsequently, operations such as those performed during the sensing execution period in the m+1th time period can be performed. Specifically, during the sensing execution period in the m+1th time period, sensing of the pixels connected to the level storing the selection signal can be performed during the sensing selection period A' in the m+1th time period.

[0254] Then, the above process can be repeated until the final level.

[0255] Therefore, pixels connected to all levels can be sensed, and the entire display panel can be sensed when a power failure signal is received from the user.

[0256] Finally, once all stages of sensing are complete, the light-emitting display device can be completely turned off. In this case, the sensing data of all driving transistors sensed through these processes can be stored in the controller 400.

[0257] When the light-emitting display device is turned on again, the controller 400 can use the sensing data stored in the storage unit 450 to correct the change in the threshold voltage of the driving transistor Tdr during the display period DP.

[0258] According to one or more embodiments of the present disclosure described above, pixels connected to at least two levels can be sensed in a sub-segment of a sensing time period.

[0259] Therefore, according to one or more embodiments of this disclosure, the time period for sensing all pixels can be reduced compared to light-emitting display devices of the related art.

[0260] For additional description, when all stages n and n+1 are driven during the sensing selection period A, the controller may provide the first sensing control pulse SP1 to stages n and n+1.

[0261] In this case, the selection signal can be stored in the nth sensing selector included in the nth stage that has received the first sensing control pulse SP1 and the n+1th sensing selector included in the (n+1)th stage that has received the first sensing control pulse SP1.

[0262] The two stages (stage n and stage n+1) that store the selection signal can sequentially provide gate pulses to the gate lines connected to the two stages.

[0263] In other words, when the reset pulse RP is received by stage n and stage n+1 during the sensing period B, stage n and stage n+1 can sequentially output gate pulses to the gate lines connected to stage n and stage n+1.

[0264] Therefore, sensing can be performed on pixels connected to both levels.

[0265] When another sensing selection period A' begins after sensing period B and the second sensing control pulse SP2 is provided to the stage, the selection signals stored in the nth and n+1th sensing selectors can be discharged and deleted.

[0266] The sensing operation of the threshold voltage of the sensing drive transistor can be performed before the start of the display period after the light-emitting display device is turned on, or it can be performed after the end of the display period and before the light-emitting display device is turned off.

[0267] According to one or more embodiments of this disclosure, the threshold voltage of a driving transistor corresponding to at least two gate lines can be sensed in one cycle. Therefore, the threshold voltage of all driving transistors included in a light-emitting display device can be sensed rapidly. For example, pixels connected to two or more gate lines can be sensed during the same time period, rather than sensing only pixels connected to one gate line during a single time period.

[0268] Therefore, the time period from when the light-emitting display device is turned on until the start of the display period can be shortened, allowing the user to check the image earlier than in related technologies. For example, according to embodiments of this disclosure, the light-emitting display device can be repeatedly turned off and on much faster than in related technologies. For instance, when a user turns off a light-emitting display device in related technologies and then attempts to quickly turn it back on, the user may experience a long time lag (e.g., where it may appear as if nothing has happened while the screen is black), because a pixel on a gate line is sensed at the moment of power failure, which could lead to too much disappointment.

[0269] Furthermore, the time between the end of the display period and the shutdown of the light-emitting display device can be shortened, thus reducing the power consumption of the light-emitting display device. Therefore, the light-emitting display device can improve the user experience while saving energy.

[0270] The features, structures, and effects described above in this disclosure are included in at least one embodiment, but are not limited to only one embodiment. Furthermore, those skilled in the art can achieve the features, structures, and effects described in at least one embodiment of this disclosure through combinations or modifications of other embodiments. Therefore, anything relating to combinations and modifications should be understood as being within the scope of this disclosure.

[0271] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from its spirit or scope. Therefore, this disclosure is intended to cover such modifications and variations, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: A light-emitting display panel comprising multiple pixels; Multiple gate lines are configured to provide gate signals to the pixel; as well as Multiple stages are connected to the multiple gate lines and configured to output gate pulses to a group of pixels connected to at least two of the multiple gate lines, for sensing features of each pixel in the group of pixels during a sensing period. Each of the plurality of levels includes: A sensing selector is configured to store a selection signal during a sensing selection period of the sensing period, and to control a signal output unit to output the gate pulse based on the selection signal during a sensing execution period of the sensing period, the sensing execution period being after the sensing selection period. The sensing selector in each of the plurality of levels includes: A selection signal transmitter, including a fourth transistor, is configured to transmit a carry signal from a carry output, which is received by a selection signal controller based on a carry control clock signal applied to the gate of the fourth transistor.

2. The light-emitting display device according to claim 1, wherein the sensing period is initiated after receiving a power-off command for powering off the light-emitting display device.

3. The light-emitting display device of claim 1, wherein the first stage of the plurality of stages is configured to output the gate pulse to a first pixel block connected to four or more gate lines of a first group, for sensing features of each pixel in the first pixel block during a first time period of the sensing time period, and The second of the plurality of stages is configured to output the gate pulse to a second pixel block connected to four or more gate lines of the second group for sensing features of each pixel in the second pixel block during a second period following the first period of the sensing time.

4. The light-emitting display device according to claim 1, wherein the plurality of stages comprises: The first stage is connected to the first gate line and the second gate line, and is used to provide gate signals to a first group of pixels connected to the first gate line and the second gate line. as well as The second stage, connected to the third and fourth gate lines, is used to provide gate signals to a second group of pixels connected to the third and fourth gate lines. The first stage is configured to output gate pulses to the first gate line and the second gate line, for sensing features of each pixel in the first group of pixels during the sensing period. The second stage is configured to output gate pulses to the third gate line and the fourth gate line for sensing features of each pixel in the second group of pixels during the sensing period.

5. The light-emitting display device according to claim 4, wherein the plurality of stages comprises: The third stage, connected to the fifth and sixth gate lines, is used to provide gate signals to a third group of pixels connected to the fifth and sixth gate lines. The third stage is configured to output gate pulses to the fifth and sixth gate lines for sensing features of each pixel in the third group of pixels during the sensing period.

6. The light-emitting display device according to claim 1, wherein the at least two gate lines are connected to the same stage among the plurality of stages.

7. The light-emitting display device according to claim 1, wherein the at least two gate lines are connected to at least two different stages among the plurality of stages.

8. The light-emitting display device according to claim 1, wherein each of the plurality of stages further comprises: The signal output unit is configured to output the gate pulses sequentially to the at least two gate lines.

9. The light-emitting display device according to claim 8, wherein the sensing selector includes a capacitor for storing the selection signal.

10. The light-emitting display device of claim 8, wherein during the sensing selection period of the sensing period, the selection signal is stored in the sensing selector included in at least two of the plurality of levels.

11. The light-emitting display device according to claim 8, wherein, The sensor selector is configured as follows: In response to receiving a first sensing control pulse during the sensing selection period of the first frame period when the selection signal is stored in the sensing selector, the signal output unit is controlled to sequentially output the gate pulse to the at least two gate lines during the sensing execution period of the sensing period when a reset signal is received by the sensing selector.

12. The light-emitting display device according to claim 11, wherein the width of the reset signal is greater than the width of the first sensing control pulse, and the width of the first sensing control pulse is greater than the width of the selection signal.

13. The light-emitting display device according to claim 8, wherein the sensing selector of the nth stage of the plurality of stages is configured to receive a carry signal provided from another stage of the plurality of stages as a selection signal for the nth stage, where n is a positive integer greater than zero.

14. The light-emitting display device of claim 13, wherein the (n+1)th stage of the plurality of stages is configured to receive different carry signals provided from different stages of the plurality of stages as selection signals for the (n+1)th stage, the different stages being different from the other stage.

15. The light-emitting display device of claim 13, wherein the sensing selector in each of the plurality of stages further comprises: The reset unit includes: The fifth transistor has a gate that is connected to the gate of the third transistor in the selection signal controller, and The sixth transistor has a first terminal connected to the fifth transistor, a gate configured to provide a reset signal, and a second terminal connected to the Q node of the corresponding stage.

16. The light-emitting display device of claim 15, wherein the sensing selector in each of the plurality of stages further comprises: A selection signal storage unit is connected between the selection signal controller and the reset unit. The selection signal storage unit includes a capacitor.

17. The light-emitting display device of claim 15, wherein the sensing selector in each of the plurality of stages further comprises: Initialization unit, including: The seventh transistor includes a first terminal connected to the sixth transistor and a second terminal connected to the Qb node of the corresponding stage; and The eighth transistor includes a first terminal connected to the second terminal of the seventh transistor. The gate of the seventh transistor is connected to the gate of the sixth transistor and is configured to provide an initialization voltage.

18. The light-emitting display device according to claim 17, wherein the initialization unit is configured as follows: In response to receiving the initialization voltage, the signal output unit is prevented from outputting the gate pulse to the at least two gate lines.

19. The light-emitting display device of claim 8, wherein the sensing selector in each of the plurality of stages comprises: Select the signal controller, including: The first transistor includes a first terminal connected to the carry output of another stage among the plurality of stages; The second transistor includes a first terminal connected to a second terminal of the first transistor; and A third transistor is connected between the second terminal of the first transistor and the first terminal of the second transistor. The first gate of the first transistor is connected to the second gate of the second transistor, and the first gate and the second gate are connected to a sensing control signal line, configured to provide a first sensing control pulse.

20. The light-emitting display device according to claim 19, wherein the first gate and the second gate in the selection signal controller of the nth stage of the plurality of stages, and the first gate and the second gate in the selection signal controller of the (n+1)th stage of the plurality of stages, are all connected to the sensing control signal line, where n is a positive integer greater than zero.

21. The light-emitting display device according to claim 20, wherein the first terminal of the first transistor in the selection signal controller of the nth stage and the first terminal of the first transistor in the signal controller of the (n+1)th stage are connected to carry outputs from two different stages among the plurality of stages.

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