Display device

Abstract

A display device includes a substrate including a display area and a non-display area surrounding the display area; a plurality of pixels disposed in the display area; a gate driver disposed in the non-display area at least one side of the display area, the gate driver including a plurality of stages including a first stage and a second stage; and a plurality of gate lines extending from the gate driver to the display area, wherein the plurality of gate lines includes a first gate line and a second gate line, the first gate line including a linear portion and being connected to the first stage, the second gate line including a linear portion and a curved portion and being connected to the second stage, wherein a size of the second stage can be greater than a size of the first stage.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2021-0191553, filed on December 29, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more specifically, to a display device capable of reducing or minimizing the RC (resistance-capacitance) delay of the gate signal. Background Technology

[0004] Currently, with the advent of the comprehensive information age, the field of display devices that visually present electrical information signals has developed rapidly, and research continues to be conducted to improve the performance of various display devices, such as thinness, light weight, and low power consumption.

[0005] Representative display devices may include liquid crystal displays (LCDs), field emission displays (FEDs), electrowetting displays (EWDs), and organic light-emitting diode displays (OLEDs).

[0006] Among these display devices, electroluminescent displays, including organic light-emitting displays, are self-emissive, eliminating the need for a separate light source, unlike liquid crystal displays. Therefore, electroluminescent displays can be manufactured with light weight and small thickness. Furthermore, electroluminescent displays are expected to be used in various fields because they offer advantages not only in power consumption due to low-voltage operation, but also in color reproduction, response speed, viewing angle, and contrast ratio (CR). However, there is still room for improvement in display devices such as electroluminescent displays, for example, in minimizing the RC delay of the gate signal. Summary of the Invention

[0007] One object of this disclosure is to provide a display device that can minimize RC delay variations due to differences in gate line lengths.

[0008] Another objective of this disclosure is to provide a display device that can mitigate the RC delay of scan signals in gate lines with curved portions, thereby improving the appearance of spots (blemishes) in an image.

[0009] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] A display device according to one aspect of this disclosure includes: a substrate including a display area and a non-display area surrounding the display area; a plurality of pixels disposed in the display area; a gate driver disposed in the non-display area on one or both sides of the display area, the gate driver including a plurality of stages, the plurality of stages including a first stage and a second stage; and a plurality of gate lines extending from the gate driver to the display area, wherein the plurality of gate lines include a first gate line and a second gate line, the first gate line including a linear portion and connected to the first stage, the second gate line including a linear portion and a curved portion and connected to the second stage, wherein the size of the second stage may be larger than the size of the first stage.

[0011] Further details of the exemplary embodiments are included in the following detailed description and accompanying drawings.

[0012] According to this disclosure, the RC delay variation between gate lines having only a linear portion and gate lines having both a linear portion and a curved portion can be reduced.

[0013] According to this disclosure, the sampling time of the scanning signal is adequately ensured to improve the problem of light spots in the image.

[0014] The effects of this disclosure are not limited to those illustrated above, and many more different effects are included in this specification. Attached Figure Description

[0015] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 This is a schematic plan view of a display device according to exemplary embodiments of the present disclosure;

[0017] Figure 2 It is along Figure 1 A schematic enlarged cross-sectional view taken from line II-II';

[0018] Figure 3A This is a schematic diagram of a gate driver for a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 3B This is a schematic diagram of multiple scan stages of a scan driver for a gate driver of a display device according to exemplary embodiments of the present disclosure;

[0020] Figure 4 This is a schematic enlarged view of the non-display area to the right of the display area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 5 yes Figure 1 Enlarged view of area A;

[0022] Figure 6 This is a schematic enlarged view of the corner (corner) area of ​​the display area and non-display area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 7A and Figure 7B It is a waveform of the scanning signal of the display device according to the comparative embodiments and exemplary embodiments of the present disclosure;

[0024] Figure 8 This is a schematic plan view of a display device according to another exemplary embodiment of the present disclosure;

[0025] Figure 9 yes Figure 8 Enlarged view of area B; and

[0026] Figure 10 This is a schematic enlarged view of a display device according to yet another exemplary embodiment of the present disclosure. Detailed Implementation

[0027] The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0028] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “including” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0029] Even if not explicitly stated, components are interpreted as including (including) the normal tolerance range.

[0030] When terms such as “above,” “over,” “below,” and “near (next)” are used to describe the positional relationship between two parts, one or more parts may be positioned between the two parts, unless these terms are used in conjunction with the terms “immediately following” or “directly.”

[0031] When one element or layer is placed "on" another element or layer, yet another element or layer can be directly inserted onto or between the other element or layer.

[0032] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component referred to below may be the second component in the technical concept of this disclosure.

[0033] Throughout the specification, similar reference numerals generally denote similar elements.

[0034] The dimensions and thicknesses of the components shown in the accompanying drawings are illustrated for ease of description, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0035] Features of the various embodiments of this disclosure may be partially or wholly attached to or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently or in association with each other.

[0036] In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic plan view of a display device according to exemplary embodiments of the present disclosure. Figure 1 For ease of description, only the substrate 110, the pad portion PAD, and the data driver DD are shown among the various components of the display device 100.

[0038] Reference Figure 1 The substrate 110 includes a display area AA and a non-display area NA.

[0039] The substrate 110 is a base (base) component for supporting various components of the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass or a plastic material such as polyimide.

[0040] In the display area AA, an image is displayed and multiple pixels are set. The display area AA can contain display elements for displaying the image and a driving section for driving the display elements. For example, when the display device 100 is an organic light-emitting display device, the display element can be an organic light-emitting device including an anode, an organic layer, and a cathode. The driving section can be composed of various components for driving the organic light-emitting device, such as power lines, gate lines, data lines, transistors, and storage capacitors. In the following description, for ease of description, it is assumed that the display device 100 is an organic light-emitting display device, but the display device 100 is not limited to organic light-emitting display devices.

[0041] Reference Figure 1 The substrate 110 may have corner regions of any kind, and the display area AA may have a shape corresponding to the corner regions of the substrate 110 of any kind. The corner regions of the display area AA and the substrate 110 may have circular shapes. However, this disclosure is not limited thereto, and the substrate 110 and the display area AA may have various shapes suitable for the design of an electronic device (device) in which the display device 100 is mounted.

[0042] Display area AA includes a first display area AA1, a second display area AA2, and a third display area AA3. The first display area AA1 is related to... Figure 1 The first display area AA is located in the upper and central portions of the display area AA. The second display area AA2 and the third display area AA3 are areas that extend from one side of the first display area AA and are spaced apart from each other. Therefore, a portion of the non-display area NA, in particular a portion of the second non-display area NA2 (which will be described later), can be disposed between the second display area AA2 and the third display area AA3. The second display area AA2 and the third display area AA3 can be configured to correspond to some of the corner areas among a plurality of corner areas. A structure having the shape of the display area AA as described above can be called a notch structure.

[0043] In the non-display area NA, no image is displayed, and various wiring and circuits for driving the display elements of the display area AA are provided. For example, in the non-display area NA, data drivers DD, gate drivers GD, link (connection) lines, pads PAD, etc. can be provided.

[0044] The non-display area NA can be an area extending from the display area AA, but is not limited to this, and can be an area surrounding or enclosing the display area AA.

[0045] The non-display area NA may include a first non-display area NA1, a curved area BA, and a second non-display area NA2. The second non-display area NA2 may extend from the display area AA. The curved area BA may extend from the second non-display area NA2 and may be curved. The first non-display area NA1 may extend from the curved area BA.

[0046] In the first non-display area NA1, data drivers (DD), pads (PAD), etc., can be configured. Various signal lines or pads connected to the PCB are configured within the pads. Power pads, data pads, gate pads, etc., can be configured within the pads.

[0047] The data driver DD is mounted in a separate PCB or connected to a separate PCB, which is connected to the display panel via pad portions (PADs). Alternatively, the data driver DD is mounted or connected as a chip-on-panel (COP) between the pad portions (PADs) and the display area (AA). The data driver DD includes at least one source driver IC (integrated circuit). The at least one source driver IC is supplied with digital video data and source timing control signals from a timing controller. In response to the source timing control signals, the at least one source driver IC converts the digital video data into a gamma voltage to generate a data voltage, which is supplied through the data lines of the display area (AA).

[0048] Multiple bending patterns can be provided in the bending zone BA. The bending zone BA is a zone that is bent in the final product such that cracks may occur when the bending zone BA is bent due to stress concentrated on the bending patterns provided in the bending zone BA. Therefore, in order to minimize the cracks, the bending patterns can be formed by patterns with a specific shape. For example, the bending pattern can be a pattern that repeatedly provides conductive patterns having at least one of square (rhomboid), rhomboid, zigzag (sawtooth) and circular shapes. In addition to the shapes described above, the bending pattern can also have any other shape that can minimize stress concentrated on the bending pattern or cracks, but is not limited to this.

[0049] The second non-display area NA2 is a region that surrounds the display area AA and includes a region between the curved area BA and the display area AA, wherein connection lines such as power connection lines and data connection lines can be provided. That is, the second non-display area NA2 is used to transmit signal output from the driver to the display area AA. When the substrate 110 includes corner areas with different shapes, the second non-display area NA2 can have a shape corresponding to the shape of the substrate 110 and the display area AA.

[0050] like Figure 1 As shown, the gate driver GD can be disposed on both sides of the display area AA in the second non-display area NA2 of the non-display area NA, but this disclosure is not limited thereto. In particular, as another example or as an alternative, the gate driver can be disposed only on one side of the display area as needed or configured. The gate driver GD can be implemented using a gate in panel (GIP), but is not limited thereto. Reference will be made below. Figures 3A to 6 A more detailed description of the gate driver GD.

[0051] First, refer to Figure 2 The multiple pixels of the display device 100 are described in more detail.

[0052] Figure 2 It is along Figure 1 A schematic enlarged cross-sectional view taken from line II-II'.

[0053] Reference Figure 2 The display device 100 according to an exemplary embodiment of the present disclosure is a top-emitting display device. The display device 100 may include a substrate 110, a buffer layer 111, a transistor 120, a gate insulating layer 112, an interlayer insulating layer 113, a passivation layer 114, a first planarization layer 115, a connecting electrode 190, a second planarization layer 116, a dam 117, a light-emitting device 130, and a package portion 140.

[0054] The substrate 110 can support various components of the display device 100. The substrate 110 can be formed of glass or a flexible plastic material. For example, when the substrate 110 is formed of a plastic material, the substrate can be formed of polyimide (PI).

[0055] A buffer layer (or insulating layer) 111 may be disposed on the substrate 110. The buffer layer 111 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or as a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). The buffer layer 111 may be used to improve the adhesion between the layers formed on the buffer layer 111 and the substrate 110 and to block alkaline components from leaking from the substrate 110.

[0056] Transistor 120 can be disposed on buffer layer 111. Transistor 120 may include active layer 121, gate electrode 124, source electrode 122, and drain electrode 123. Here, depending on the pixel circuit design, source electrode 122 can be used as drain electrode, and drain electrode 123 can be used as source electrode. Active layer 121 of transistor 120 can be disposed on buffer layer 111.

[0057] The active layer 121 can be formed of various materials such as polycrystalline silicon, amorphous silicon, or oxide semiconductor. The active layer 121 may include a channel region in which a channel is formed when the transistor 120 is driven, and source and drain regions located on either side of the channel region. The source region refers to the portion of the active layer 121 connected to the source electrode 122, and the drain region refers to the portion of the active layer 121 connected to the drain electrode 123.

[0058] A gate insulating layer 112 can be disposed on the active layer 121 of the transistor 120. The gate insulating layer 112 can be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes can be formed in the gate insulating layer 112, through which the source electrode 122 and drain electrode 123 of the transistor 120 are connected to the source and drain regions of the active layer 121 of the transistor 120.

[0059] The gate electrode 124 of transistor 120 can be disposed on the gate insulating layer 112. The gate electrode 124 can be formed of a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof. The gate electrode 124 can be formed on the gate insulating layer 112 to overlap (stack) with the channel region of the active layer 121 of transistor 120.

[0060] An interlayer insulating layer (or insulating layer) 113 may be disposed on the gate insulating layer 112 and the gate electrode 124. The interlayer insulating layer 113 may be formed as a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). Contact holes may be formed in the interlayer insulating layer 113, through which the source and drain regions of the active layer 121 of the transistor 120 are exposed.

[0061] The source electrode 122 and drain electrode 123 of transistor 120 can be disposed on interlayer insulating layer 113.

[0062] The source electrode 122 and drain electrode 123 of transistor 120 can be connected to the active layer 121 of transistor 120 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113. Therefore, the source electrode 122 of transistor 120 can be connected to the source region of active layer 121 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113. Furthermore, the drain electrode 123 of transistor 120 can be connected to the drain region of active layer 121 through contact holes formed in the gate insulating layer 112 and the interlayer insulating layer 113.

[0063] The source electrode 122 and drain electrode 123 of transistor 120 can be formed using the same process. Furthermore, the source electrode 122 and drain electrode 123 of transistor 120 can be formed from the same material. The source electrode 122 and drain electrode 123 of transistor 120 can be formed from a single layer or multiple layers of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0064] A passivation layer (or insulating layer) 114 may be disposed on the source electrode 122 and the drain electrode 123 to protect the source electrode 122 and the drain electrode 123. The passivation layer 114 is an insulating layer for protecting components located beneath it. For example, the passivation layer 114 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. Furthermore, according to this exemplary embodiment, the passivation layer 114 may be omitted.

[0065] A first planarization layer (or insulating layer) 115 can be disposed on the transistor 120 and the passivation layer 114. For example... Figure 2 As shown, contact holes can be formed in the first planarization layer 115 to expose the drain electrode 123. The first planarization layer 115 can be an organic material layer that planarizes the upper portion of the transistor 120. For example, the first planarization layer 115 can be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. However, it is not limited to this; the first planarization layer 115 can be an inorganic material layer for protecting the transistor 120. For example, the first planarization layer 115 can be formed of an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx). The first planarization layer 115 can be composed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx).

[0066] A connection electrode 190 can be disposed on the first planarization layer 115. Furthermore, the connection electrode 190 can be connected to the drain electrode 123 of the transistor 120 through contact holes formed in the first planarization layer 115. The connection electrode 190 can be used to electrically connect the transistor 120 and the light-emitting device 130. For example, the connection electrode 190 can be used to electrically connect the drain electrode 123 of the transistor 120 and the first electrode 131 of the light-emitting device 130. The connection electrode 190 can be formed of a single layer or multiple layers of any of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof. The connection electrode 190 can be formed of the same material as the source electrode 122 and drain electrode 123 of the transistor 120.

[0067] A second planarization layer (or insulating layer) 116 can be disposed on the connection electrode 190 and the first planarization layer 115. Furthermore, as... Figure 2 As shown, contact holes can be formed in the second planarization layer 116 to expose the connection electrode 190. The second planarization layer 116 can be an organic material layer that planarizes the upper portion of the transistor 120. For example, the second planarization layer 116 can be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0068] In each of the plurality of pixels, a light-emitting device 130 may be disposed on the second planarization layer 116. The light-emitting device 130 may include a first electrode 131 as an anode, an emitting structure (or light-emitting structure) 132, and a second electrode 133 as a cathode. The first electrode 131 of the light-emitting device 130 may be disposed on the second planarization layer 116. The first electrode 131 may be electrically connected to a connection electrode 190 through a contact hole formed in the second planarization layer 116. Therefore, the first electrode 131 of the light-emitting device 130 is electrically connected to the connection electrode 190 through a contact hole formed in the second planarization layer 116, thereby being electrically connected to the transistor 120.

[0069] The first electrode 131, serving as the anode, can be formed with a multilayer structure, including a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer can be formed from a material with a high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive layer can be formed as a single layer or multiple layers of materials including aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), and titanium (Ti), or alloys thereof. For example, the first electrode 131 can be formed with a structure in which a transparent conductive layer, an opaque conductive layer, and another transparent conductive layer are sequentially stacked. However, the first electrode 131 is not limited to this, and can also be formed with a structure in which a transparent conductive layer and an opaque conductive layer are sequentially stacked.

[0070] A dam 117 may be disposed on the first electrode 131 and the second planarization layer 116. An opening may be formed in the dam 117 to expose the first electrode 131. Since the dam 117 defines the light-emitting area of ​​the display device 100, the dam 117 may also be referred to as a pixel defining layer.

[0071] The emission structure 132, including the emission layer, can be disposed on the first electrode 131.

[0072] The emitting structure 132 of the light-emitting device 130 can be formed such that a hole layer, an emitting layer (or a light-emitting layer), and an electron layer are stacked on the first electrode 131 in this order or in reverse order. Furthermore, the emitting structure 132 may include a first emitting structure and a second emitting structure opposite to each other and having a charge-generating layer therebetween. In this case, either the emitting layer of the first emitting structure and the second emitting structure can generate blue light, and the other emitting layer of the first emitting structure and the second emitting structure can generate yellow-green light, allowing white light to be generated through the first emitting structure and the second emitting structure. The white light generated in the emitting structure 132 is incident on a color filter disposed above the emitting structure 132 to achieve a color image. Furthermore, each emitting structure 132 can generate colored light corresponding to each sub-pixel without the need for a separate color filter to achieve a color image. For example, the emitting structure 132 of the red sub-pixel can generate red light, the emitting structure 132 of the green sub-pixel can generate green light, and the emitting structure 132 of the blue sub-pixel can generate blue light.

[0073] The second electrode 133, serving as the cathode, can be further disposed on the emitting structure 132. Since the display device 100 is a top-emitting display device, the second electrode 133 can be formed of a very thin metal material or a transparent conductive material. The second electrode 133 of the light-emitting device 130 can be disposed on the emitting structure 132 opposite to the first electrode 131, wherein the emitting structure 132 is located between the first electrode 131 and the second electrode 133. In the display device 100 according to an exemplary embodiment of the present disclosure, the second electrode 133 can be a cathode electrode. The encapsulation portion 140 can be further disposed on the second electrode 133 to suppress moisture (water) penetration.

[0074] The encapsulation portion 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143. The first inorganic encapsulation layer 141 of the encapsulation portion 140 may be disposed on the second electrode 133. Furthermore, the organic encapsulation layer 142 may be disposed on the first inorganic encapsulation layer 141. Furthermore, the second inorganic encapsulation layer 143 may be disposed on the organic encapsulation layer 142. The first inorganic encapsulation layer 141 and the second inorganic encapsulation layer 143 of the encapsulation portion 140 may be formed of inorganic materials such as silicon nitride (SiNx) or silicon oxide (SiOx). The organic encapsulation layer 142 of the encapsulation portion 140 may be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0075] Figure 3A This is a schematic diagram of a gate driver for a display device according to an exemplary embodiment of the present disclosure.

[0076] refer to Figure 3AThe gate driver (GD) may include multiple stages, including a first stage, a second stage, and a third stage. The first and second stages may be stages that normally output signals, while the third stage may be a dummy stage (pseudo-stage) that does not output signals. In particular, as... Figure 3A As shown, the gate driver GD may include a scan driver SD and multiple scan clock lines SCLK. In this case, the scan driver SD may include multiple scan levels SST.

[0077] The scan driver SD can output scan signals to multiple scan lines belonging to one type of gate line. The scan driver SD receives various clock signals, gate high voltage, and gate low voltage from the multiple scan clock lines SCLK to output scan signals. The scan driver SD may include multiple scan stages SST, and the multiple scan stages SST can output scan signals.

[0078] Despite Figure 3A Only the scan clock line SCLK is shown in the diagram, but this disclosure is not limited thereto. The start pulse line, gate high voltage line, and gate low voltage line that drive the scan driver SD can also be set.

[0079] Despite Figure 3A The text describes a gate driver (GD) that includes only a scan driver (SD) and a scan clock line (SCLK), but the gate driver may also include an additional emitter driver and emitter clock line for outputting light-emitting signals.

[0080] In the following text, we will also refer to Figure 3B A more detailed description is provided of the multiple scan levels SST included in the scan drive SD.

[0081] Figure 3B This is a schematic diagram of multiple scan levels of a scan driver for a gate driver of a display device according to an embodiment of the present disclosure.

[0082] First, each of the plurality of scan levels SST (e.g., first scan level SST1, second scan level SST2, and third scan level SST3) includes a scan circuit to output a scan signal. The scan circuit can be constructed from various transistors or from various transistors and capacitors. In this case, the scan circuit may include a scan buffer transistor SBT and additional scan circuits ASC excluding the scan buffer transistor SBT (e.g., first scan buffer transistor SBT1, second scan buffer transistor SBT2, and third scan buffer transistor SBT3). That is, the remaining components of the scan circuit excluding the scan buffer transistor SBT can be defined as additional scan circuits ASC (e.g., first additional scan circuit ASC1, second additional scan circuit ASC2, and third additional scan circuit ASC3). In this case, the scan buffer transistor SBT may be the transistor with the largest area size in the plan view among all the transistors included in the scan circuit, and the scan signal can be output from the output terminal of the scan buffer transistor SBT. That is, the footprint area of ​​the SBT transistor is larger than the footprint area of ​​some locations in the circuit and, in some embodiments, the footprint area of ​​the ASC transistor. In this configuration, the scan buffer transistor SBT includes a first scan buffer transistor SBT1 and a second scan buffer transistor SBT2, which function as normal output scan buffer transistors, and a third scan buffer transistor SBT3, which functions as a dummy scan buffer transistor. The first scan buffer transistor SBT1 and the second scan buffer transistor SBT2 are respectively located in the first scan stage SST1 and the second scan stage SST2, which are normal output scan stages and output signals normally. The third scan buffer transistor SBT3 is located in the third scan stage SST3, which is a dummy output scan stage and does not output signals normally. Furthermore, the additional scan circuit ASC includes a first additional scan circuit ASC1 and a second additional scan circuit ASC2, respectively located in the first scan stage SST1 and the second scan stage SST2, and a third additional scan circuit ASC3, located in the third scan stage SST3.

[0083] In some embodiments, the first scan stage SST1 includes a first additional scan circuit ASC1 adjacent to and coupled to the first scan buffer transistor SBT1, the second scan stage SST2 includes a second additional scan circuit ASC2 adjacent to and coupled to the second scan buffer transistor SBT2, and the third scan stage SST3 includes a third additional scan circuit ASC3 adjacent to and coupled to the third scan buffer transistor SBT3. Viewed from a plan view, the first additional scan circuit ASC1, the second additional scan circuit ASC2, and the third additional scan circuit ASC3 have the same area.

[0084] The plurality of scan levels SST includes a plurality of first scan levels SST1, a plurality of second scan levels SST2, and a plurality of third scan levels SST3. Figure 3B The illustration shows only one of the plurality of first scan levels SST1, one of the plurality of second scan levels SST2, and two third scan levels SST3 of different shapes.

[0085] The plurality of first scan levels SST1 and the plurality of second scan levels SST2 can be normal output scan levels that normally output scan signals. The plurality of third scan levels SST3 can be dummy scan levels that do not normally output scan signals. First scan level SST1 may include a first scan buffer transistor SBT1 and a first additional scan circuit ASC1. Second scan level SST2 may include a second scan buffer transistor SBT2 and a second additional scan circuit ASC2. Third scan level SST3 may include a third scan buffer transistor SBT3 and a third additional scan circuit ASC3. In this case, the first additional scan circuit ASC1, the second additional scan circuit ASC2, and the third additional scan circuit ASC3 can be identical. Furthermore, the first scan buffer transistor SBT1, the second scan buffer transistor SBT2, and the third scan buffer transistor SBT3 can be functionally identical. However, the third scan buffer transistor SBT3, which is a dummy scan level, may not output a scan signal.

[0086] Meanwhile, the plurality of first scan stages SST1 and the plurality of second scan stages SST2, which are normal output scan stages, can have different sizes. The first scan stage SST1 can be connected to a first gate line GL1 having only a linear (straight) portion (see...). Figure 5 (which will be described below), and the second scan stage SST2 can be connected to the second gate line GL2, which has a linear portion and a bent portion (see...). Figure 5 Therefore, the size of the second scan buffer transistor SBT2 of the second scan stage SST2 can be larger than the size of the first scan buffer transistor SBT1 of the first scan stage SST1. Correspondingly, the size of the second scan stage SST2 can be larger than the size of the first scan stage SST1. Here, the size can refer to the area as viewed from a plan view. The following will refer to... Figures 5 to 7B The dimensions of the second scan buffer transistor SBT2 of the second scan stage SST2 and the dimensions of the first scan buffer transistor SBT1 of the first scan stage SST1 are described in more detail.

[0087] Furthermore, some of the third scan levels SST3 and other third scan levels SST3 may have different sizes. For example, in Figure 3B Of the multiple third scan levels SST3 shown, the third scan level SST3 with a relatively large size can have the same size and configuration as the first scan level SST1, but unlike the first scan level SST1, it does not output a signal normally. Furthermore, in Figure 3B Of the multiple third scan levels SST3 shown, the third scan level SST3 with a relatively small size can have the same configuration as the first scan level SST1 and the second scan level SST2. However, unlike the first scan level SST1 and the second scan level SST2, the third scan level SST3 with a relatively small size may not output a signal normally and may have a size smaller than the first scan level SST1 and the second scan level SST2. In this case, the size of the third scan buffer transistor SBT3 of the third scan level SST3 can be smaller than the size of the first scan buffer transistor SBT1 of the first scan level SST1 and the size of the second scan buffer transistor SBT2 of the second scan level SST2. The following will refer to... Figures 5 to 7B The dimensions of the third scan buffer transistor SBT3 of the third scan stage SST3 are described in more detail.

[0088] Figure 4 This is a schematic enlarged view of the non-display area to the right of the display area of ​​a display device according to an embodiment of the present disclosure. Figure 5 yes Figure 1 An enlarged view of area A. Figure 6 This is a schematic enlarged view of the corner area of ​​the display area and the non-display area of ​​a display device according to an embodiment of the present disclosure. For example, Figure 4 This is a schematic diagram of a non-display area NA located to the right of the first display area AA1 of the display area AA of the display device 100, and only the component for the gate driver GD among the various components of the display device 100 is shown. Meanwhile, although in Figure 4 The non-display area NA, located to the right of the first display area AA1, and the non-display area NA, located in the second display area AA2 (as shown in the image), have already been described. Figure 1 The non-display area NA on the left (as shown) is also set symmetrically, so the same description can be applied. Furthermore, although in Figure 6 In the previous description, a local region has been depicted in which only the second gate line GL2 is disposed in the lower right corner region among multiple corner regions of the display area AA. The same description can be applied to other corner regions. For ease of description, in Figure 5 In the display device 100, only one of the multiple gate lines GL, namely a first gate line GL1 and a second gate line GL2, is shown among the various components.

[0089] First, refer to Figure 5 The plurality of gate lines GL can be configured to extend from the gate driver GD to the display area AA. The plurality of gate lines GL may include a first gate line GL1 and a second gate line GL2. The first gate line GL1 is a gate line comprising only a linear portion, and the second gate line GL2 is a gate line comprising both a linear portion and a curved portion. For example, the first gate line GL1 is located in the display area (especially...). Figure 5 The first gate line GL1 extends straight within a first display area (AA1) in a first direction. On the other hand, the second gate line GL2 includes a curved portion extending in the display area in a second direction transverse to the first direction. Similar to the first gate line GL1, one or more linear portions of the second gate line GL2 extend in the first direction. As shown, the second gate line GL2 may change its direction of extension at least once. The second gate line GL2 may include one or more curved portions within the display area. For example, Figure 5 The diagram shows two curved sections within region A. A linear section also exists between the two curved sections shown in region A. The linear section between the two curved sections extends upwards in a third direction perpendicular to the first direction.

[0090] A first gate line GL1 is disposed in the first display area AA1 of the display area AA, a portion of the second gate line GL2 is disposed in the first display area AA1, and another portion of the second gate line GL2 is disposed in the second display area AA2 and the third display area AA3 of the display area AA. For example, refer to Figure 5 The second gate line GL2 extends linearly to the left from the third display area AA3, and then has a curved portion extending near the boundary between the second non-display area NA2 and the third display area AA3, with a curved shape. Subsequently, a portion of the second gate line GL2 is set as a straight line in the first display area AA1, and then the second gate line GL2 has a curved portion extending near the boundary between the second non-display area NA2 and the second display area AA2, also with a curved shape (e.g., one or more curved portions of the second gate line are curved according to the shape of the second non-display area NA2). In this case, the first scan level SST1 is connected to the first gate line GL1, and the second scan level SST2 is connected to the second gate line GL2. Therefore, the second scan level SST2 can be set in the non-display area NA corresponding to the corner area of ​​the display area AA, that is, in the non-display area NA corresponding to the second display area AA2 and the third display area AA3.

[0091] Despite Figure 5For ease of description, one first gate line GL1 and one second gate line GL2 are shown, but multiple first gate lines GL1 and multiple second gate lines GL2 can be provided.

[0092] Reference Figure 4 In the non-display area NA located to the right of the first display area AA1, multiple first scan levels SST1 and multiple scan clock lines SCLK can be configured. Specifically, in the first display area AA1, a first gate line GL1 with only a linear portion is primarily configured. Therefore, in the non-display area NA located to the right of the first display area AA1, multiple first scan levels SST1 serving as normal output scan signals and multiple first emitter levels serving as normal output emitters serving as normal output light emission signals are configured, but second scan levels SST2 and third scan levels SST3 are not configured. Firstly, this is primarily because the first gate line GL1 is located in the first display area AA1, thus the second scan level SST2 is not configured. Furthermore, the third scan level SST3, which is a dummy level, is not configured to achieve optimal layout design by outputting the necessary scan signals in the smallest possible space.

[0093] Reference Figure 1 , Figure 5 and Figure 6 The boundaries between the non-display area NA in the corner area corresponding to display area AA and display area AA, as well as the boundaries between the third display area AA3 and the second non-display area NA2, can have curved shapes. Therefore, for areas (domains) with the same vertical width, the length of the boundary between the non-display area NA in the corner area corresponding to display area AA and display area AA can be longer than the length of the boundary between the non-display area NA on the right side of display area AA and display area AA. Therefore, for areas with the same vertical width, the number of scan levels SST provided in the non-display area NA in the corner area corresponding to display area AA can be greater than the number of scan levels SST provided in the non-display area NA on the right side of display area AA.

[0094] In this case, for areas with the same vertical width, the number of scan signals output from the gate driver GD corresponding to the corner area of ​​display area AA can be equal to the number of scan signals output from the gate driver GD disposed in the non-display area NA to the right of display area AA. Here, Figure 6The illustrated area shows a region where only the second gate line GL2 is provided, such that only the second scan level SST2 connected to the second gate line GL2 is provided, while the first scan level SST1 connected to the first gate line GL1 is not provided. Therefore, for regions with the same vertical width, the number of second scan levels SST2, which are normal output scan levels, corresponding to the corner region of the display region AA, can be equal to the number of first scan levels SST1 provided in the non-display region NA to the right of the display region AA. However, for regions with the same vertical width, the number of scan levels SST and emitter levels provided in the non-display region NA to the corner region of the display region AA can be greater than the number of scan levels SST and emitter levels provided in the non-display region NA to the right of the display region AA. Therefore, in the non-display region NA to the corner region of the display region AA, a third scan level SST3, which is a dummy scan level, can be further provided.

[0095] Reference Figure 6 In the non-display area NA, which corresponds to the corner area of ​​the display area AA, multiple second scan levels SST2, multiple third scan levels SST3, and multiple scan clock lines SCLK can be set. That is, in the non-display area NA, which corresponds to the corner area of ​​the display area AA, not only can multiple second scan levels SST2 be set as normal output scan levels that output scan signals normally, but also multiple third scan levels SST3 can be set as dummy scan levels that do not output scan signals normally. In this way, multiple third scan levels SST3 with the same circuit structure can be set in the remaining space after setting multiple second scan levels SST2 in the non-display area NA, which corresponds to the corner area of ​​the display area AA. Therefore, signals can be transmitted in the scan driver SD, and the manufacturing process can be executed more smoothly.

[0096] The arrangement order of multiple second scan levels SST2 and multiple third scan levels SST3 set in the non-display area NA corresponding to the corner area of ​​display area AA can be irregular (non-constant). That is, the number and position of multiple third scan levels SST3 set in addition to multiple second scan levels SST2 can be determined based on the curvature of the boundary between display area AA and the non-display area NA corresponding to the corner area of ​​display area AA. Therefore, as... Figure 6 As shown, the order in which the multiple second scan levels SST2 and the multiple third scan levels SST3 are set can be irregular. However, this disclosure is not limited thereto, and therefore the order in which the multiple second scan levels SST2 and the multiple third scan levels SST3 are set can be regular.

[0097] Reference Figure 6The third scan level SST3 can be either the preceding (previous) or following (after) the second scan level SST2. That is, in this figure, the third scan level SST3 can be set adjacent to the second scan level SST2.

[0098] In the adjacent second scan stages SST2 and third scan stages SST3, the relatively smaller third scan stage SST3 can have different dimensions. Specifically, the size of the second scan buffer transistor SBT2 of the second scan stage SST2 can be larger than the size of the third scan buffer transistor SBT3 of the relatively smaller third scan stage SST3. Therefore, the second scan stage SST2 can be larger than the relatively smaller third scan stage SST3. However, the size of the second additional scan circuit ASC2 of the second scan stage SST2 can be equal to the size of the third additional scan circuit ASC3 of the relatively smaller third scan stage SST3. Therefore, the portion protruding from the second scan stage SST2 can be disposed within the recessed portion of the relatively smaller third scan stage SST3.

[0099] In the following text, we will refer to... Figure 7A and Figure 7B Describe the effects of the display device 100 according to an exemplary embodiment of the present disclosure.

[0100] Figure 7A and Figure 7B This refers to the waveform of the scan signal of the display device according to the comparative embodiments and exemplary embodiments of the present disclosure. In particular, Figure 7B It is the waveform of the scan signal transmitted via the second gate line GL2 in the display device 100 according to an exemplary embodiment of the present disclosure. Figure 7A This is the waveform of the scan signal transmitted via the second gate line GL2 in the comparative embodiment. According to the comparative embodiment, unlike the display device 100 according to the exemplary embodiments of this disclosure, the scan stage SST connected to the first gate line GL1 and the second gate line GL2 respectively has scan buffer transistors SBT of the same size.

[0101] In the case of the display device with a notch structure as described above, the lengths of the first gate line and the second gate line change. That is, the first gate line has only a linear portion, while the second gate line has both a curved portion and a linear portion. Specifically, the curved portion of the second gate line is arranged along the curved shape of the notch structure, so that the second gate line has a more meandering shape than the first gate line. Therefore, the length of the second gate line can be longer than the length of the first gate line. As described above, when the length of the second gate line increases, the resistance of the second gate line increases, which increases the RC delay of the scan signal transmitted through the second gate line. Therefore, it may cause a change in the RC delay between the scan signal transmitted through the second gate line and the scan signal transmitted through the first gate line.

[0102] However, as in the comparative embodiment, when the scan buffer transistors of the scan stages connected to the first and second gate lines have the same size, the fall time Tf and rise time Tr of the scan signal transmitted through the second gate line are prolonged, making it difficult to ensure sampling time. Furthermore, the longer fall and rise times of the scan signal transmitted through the second gate line compared to the first gate line can lead to the problem of light spots appearing in the region where the second gate line is located.

[0103] Therefore, in the display device 100 according to an embodiment of the present disclosure, the size of the second scan stage SST2 connected to the second gate line GL2 is increased to be larger than the size of the first scan stage SST1 connected to the first gate line GL1. In this way, the RC delay variation between the scan signal transmitted through the first gate line GL1 and the scan signal transmitted through the second gate line GL2 can be reduced. That is, the size of the second scan buffer transistor SBT2 connected to the second scan stage SST2, which has a larger resistance, is increased to reduce the load on the second scan stage SST2. Therefore, the RC delay of the scan signal transmitted through the second gate line GL2, which increases with the increase in resistance of the second gate line GL2, can be reduced. In this case, although the size of the third scan buffer transistor SBT3 of the third scan stage SST3 is reduced, the third scan stage SST3 is a dummy stage, so that the reduction in the size of the third scan buffer transistor SBT3 does not affect the performance of the gate driver GD. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the size of the second scan buffer transistor SBT2 of the second scan stage SST2 is increased to be larger than the size of the first scan buffer transistor SBT1 of the first scan stage SST1. In this way, the RC delay of the scan signal transmitted through the second gate line GL2 can be reduced. As a result, the RC delay variation between the scan signal transmitted through the first gate line GL1 and the scan signal transmitted through the second gate line GL2 is reduced, and the spot problem is also improved.

[0104] In one embodiment, the area of ​​the third scan level SST3 is equal to or smaller than the area of ​​one of the first scan level SST1 and the second scan level SST2 for normal output signals. As previously mentioned, the third scan level SST3 is a dummy level. Therefore, decreasing or increasing the area of ​​the third scan level SST3 as viewed from a plan view does not necessarily affect the performance of the third scan level SST3. The third scan level SST3 and other scan levels can be employed to achieve an optimal layout design.

[0105] Figure 8 This is a schematic plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 9 yes Figure 8 An enlarged view of area B. Besides the display device 200, which also includes a camera area CMA disposed within display area AA, the display area AA is not divided into a first display area AA1, a second display area AA2, and a third display area AA3. Figure 8 and Figure 9 The display device 200 and Figures 1 to 6 The display device 100 is basically the same as the display device 100, so redundant descriptions will be omitted.

[0106] Reference Figure 8 and Figure 9 The camera area CMA is set within the display area AA. The camera area CMA where the camera is located is set within the display area AA. Therefore, no image is actually displayed within the camera area CMA. The camera area CMA can be set to correspond to some of the multiple corner areas (i.e., the lower corner areas) of the display area AA. The outline of the camera area CMA can include, for example... Figure 8 and Figure 9 The curved shape shown is not limited to this.

[0107] Multiple gate lines GL can be configured to extend from the gate driver GD to the display area AA. The multiple gate lines GL may include a first gate line GL1 and a second gate line GL2. The first gate line GL1 is a gate line consisting only of a linear portion, and the second gate line GL2 is a gate line including both a linear portion and a curved portion. The first gate line GL1 is disposed in an area of ​​the display area AA where the camera area CMA is not located. The linear portion of the second gate line GL2 is disposed in the display area AA and located on one or more sides of the camera area CMA. The curved portion of the second gate line GL2 is a line disposed along the boundary between the camera area CMA and the display area AA (i.e., the outline of the camera area CMA). For example, refer to... Figure 9 The second gate line GL2 extends linearly from the right end of the display area AA towards the left and has a curved portion that meanders along the contour of the camera area CMA, which has a curved shape. In this case, the first scan level SST1 is connected to the first gate line GL1, and the second scan level SST2 is connected to the second gate line GL2. Therefore, the second scan level SST2 can be set in the non-display area NA corresponding to the corner area of ​​the display area AA (i.e., corresponding to the camera area CMA).

[0108] Despite Figure 9 For ease of description, one first gate line GL1 and one second gate line GL2 are shown, but multiple first gate lines GL1 and multiple second gate lines GL2 can be provided.

[0109] Therefore, in a display device 200 according to another exemplary embodiment of the present disclosure, the size of the second scan stage SST2 connected to the second gate line GL2 that bypasses the camera region CMA (bypasses the camera region CMA) is increased to be larger than the size of the first scan stage SST1 connected to the first gate line GL1. In this way, the RC delay variation between the scan signal transmitted through the first gate line GL1 and the scan signal transmitted through the second gate line GL2 can be reduced. That is, the size of the second scan buffer transistor SBT2 connected to the second scan stage SST2, which has a large resistance due to its longer length, is increased to reduce the load on the second scan stage SST2. Therefore, the RC delay of the scan signal transmitted through the second gate line GL2, which increases with the increase in resistance of the second gate line GL2, can be reduced. Therefore, in a display device 200 according to another embodiment of the present disclosure, the size of the second scan buffer transistor SBT2 of the second scan stage SST2 is increased to be larger than the size of the first scan buffer transistor SBT1 of the first scan stage SST1 to reduce the RC delay of the scan signal transmitted through the second gate line GL2. Therefore, the RC delay variation between the scan signal transmitted through the first gate line GL1 and the scan signal transmitted through the second gate line GL2 can be reduced, and the spot problem can be improved.

[0110] Figure 10 This is a schematic enlarged view of a display device according to another embodiment of the present disclosure. Figure 10 The display device 300 and Figures 1 to 6 The only difference between the display devices 100 is the configuration of multiple scan levels SST, but the other configurations are basically the same, so redundant descriptions will be omitted.

[0111] refer to Figure 10 The spacing between the second scan level SST2 and its preceding stage (especially the third scan level SST3) can be different from the spacing between the second scan level SST2 and its following stage (especially the third scan level SST3). For example, the spacing between the second scan level SST2, which includes a second scan buffer transistor SBT2 with a larger size, and its preceding stage disposed in the protruding direction of the second scan level SST2, can be greater than the spacing between the second scan level SST2 and its following stage disposed in the non-protruding direction of the second scan level SST2 (in other words, the opposite direction to the protruding direction). That is, the third scan level SST3, which is a dummy stage disposed in the protruding direction of the second scan level SST2, and the third scan level SST3, which is a dummy stage disposed in the non-protruding direction of the second scan level SST2, are disposed in different ways (especially with different spacing) to make it easier to design the second scan buffer transistor SBT2 of the second scan level SST2.

[0112] In a display device 300 according to another embodiment of the present disclosure, the size of the second scan stage SST2 connected to the second gate line GL2 that bypasses the notch structure is increased to be larger than the size of the first scan stage SST1 connected to the first gate line GL1. In this way, the RC delay variation between the scan signal transmitted through the first gate line GL1 and the scan signal transmitted through the second gate line GL2 can be reduced. Therefore, the RC delay variation between the scan signal transmitted through the first gate line GL1 and the scan signal transmitted through the second gate line GL2 can be reduced, and the spotting problem can be improved.

[0113] Furthermore, in a display device 300 according to another embodiment of the present disclosure, the interval between the second scan level SST2 and the preceding level disposed in the protruding direction of the second scan level SST2 can be greater than the interval between the second scan level SST2 and the following level disposed in the non-protruding direction of the second scan level SST2. That is, in a display device 300 according to another embodiment of the present disclosure, a third scan level SST3 disposed as a dummy level in the protruding direction of the second scan level SST2 and a third scan level SST3 disposed as a dummy level in the non-protruding direction of the second scan level SST2 are disposed in different ways (in particular, at different intervals) to facilitate the design of the second scan buffer transistor SBT2 of the second scan level SST2. Therefore, the RC delay of the scan signal transmitted by the second gate line GL2 can be reduced more effectively (efficiently).

[0114] Embodiments of this disclosure can also be described below.

[0115] A display device according to one aspect of this disclosure may include: a substrate including a display area and a non-display area surrounding the display area; a plurality of pixels disposed in the display area; a gate driver disposed in the non-display area on one or both sides of the display area, the gate driver including a plurality of stages, the plurality of stages including a first stage and a second stage; and a plurality of gate lines extending from the gate driver to the display area, wherein the plurality of gate lines include: a first gate line including a linear portion and connected to the first stage and a second gate line including a linear portion and a curved portion and connected to the second stage, and wherein the size of the second stage may be larger than the size of the first stage.

[0116] According to some embodiments of this disclosure, the dimensions of the second level and the first level may refer to the area as observed from a plan view.

[0117] According to some embodiments of this disclosure, the display area may include multiple corner areas, and the second level may be disposed in a non-display area corresponding to the multiple corner areas.

[0118] According to some embodiments of this disclosure, each of the plurality of corner regions may have a circular shape.

[0119] According to some embodiments of this disclosure, the display area may include a first display area and a second and a third display area extending from a portion of the first display area, a portion of the non-display area may be disposed between the second and the third display areas, and a portion of the second gate line may be disposed in the second and the third display areas.

[0120] According to some embodiments of this disclosure, the second display area and the third display area may correspond to some of the plurality of corner areas, and the second level may be set in the non-display area corresponding to the second display area and the third display area.

[0121] According to some embodiments of this disclosure, each of the boundary between the second display area and the non-display area and the boundary between the third display area and the non-display area may have a curved shape, and the curved portion of the second gate line may be disposed along the boundary between the second display area and the non-display area and the boundary between the third display area and the non-display area.

[0122] According to some embodiments of this disclosure, the display device may further include a camera area located in the display area, wherein the second gate line may be disposed in the display area and located on one or more sides of the camera area.

[0123] According to some embodiments of this disclosure, the camera area may correspond to some of the plurality of corner areas, and the second level may be set in the non-display area corresponding to the camera area.

[0124] According to some embodiments of this disclosure, the outline of the camera area may include a curved shape, and the curved portion of the second gate line may be disposed along the boundary between the camera area and the display area.

[0125] According to some embodiments of this disclosure, each of the plurality of stages may include a buffer transistor, and the size of the buffer transistor of the second stage may be larger than the size of the buffer transistor of the first stage.

[0126] According to some embodiments of this disclosure, the plurality of stages may further include a third stage, wherein the first stage and the second stage are stages that normally output signals, the third stage may be a dummy stage that does not output signals, and the third stage may be a stage before or after the second stage.

[0127] According to some embodiments of this disclosure, the size of the third level may be smaller than the size of the first level and the size of the second level.

[0128] According to some embodiments of this disclosure, the size of the third-stage buffer transistor may be smaller than the size of the first-stage buffer transistor and the size of the second-stage buffer transistor.

[0129] According to some embodiments of this disclosure, the interval between the second stage and the preceding stage of the second stage may be different from the interval between the second stage and the following stage of the second stage.

[0130] According to some embodiments of this disclosure, the gate driver may include a scan driver, which may include a first scan stage, a second scan stage, and a third scan stage corresponding to the first stage, the second stage, and the third stage, respectively, and the size of the second scan stage may be larger than the size of the first scan stage.

[0131] According to some embodiments of this disclosure, the first scan stage, the second scan stage, and the third scan stage may each have a first scan buffer transistor, a second scan buffer transistor, and a third scan buffer transistor, and the size of the second scan buffer transistor may be larger than the size of the first scan buffer transistor.

[0132] According to some embodiments of this disclosure, a plurality of third scan levels with different sizes can be used. The third scan level with a relatively large size can have the same size and the same configuration as the first scan level, and the third scan level with a relatively small size can have the same configuration as the first scan level and the second scan level, but can have a smaller size than the first scan level and the second scan level.

[0133] According to some embodiments of this disclosure, a plurality of second scan levels and a plurality of third scan levels may be disposed in a non-display area corresponding to a corner area of ​​the display area, and the arrangement order of the plurality of second scan levels and the plurality of third scan levels may be regular or irregular.

[0134] According to some embodiments of this disclosure, a portion protruding from the second scan level may be disposed in a recessed portion of a third scan level having a relatively small size among the plurality of third scan levels.

[0135] According to some embodiments of this disclosure, the third scan stage can be a pre-stage or a post-stage of the second scan stage, including a second scan stage with a larger second scan buffer transistor and a pre-stage disposed in the protruding direction of the second scan stage, the interval between them can be greater than the interval between the second scan stage and a post-stage disposed in the non-protruding direction of the second scan stage.

[0136] It will be apparent to those skilled in the art that various modifications and variations can be made to this disclosure without departing from the technical concept or scope thereof. Therefore, it can be presumed that embodiments of this disclosure cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area; Multiple pixels are set in the display area; A gate driver disposed on at least one side of the display area in the non-display area, the gate driver comprising multiple stages, the multiple stages including a first stage and a second stage; and Multiple gate lines extending from the gate driver to the display area The plurality of gate lines include a first gate line and a second gate line. The first gate line includes a linear portion and is connected to the first stage. The second gate line includes a linear portion and a curved portion and is connected to the second stage. The first stage includes a first scan buffer transistor and a first additional scan circuit adjacent to and connected to the first scan buffer transistor, and the second stage includes a second scan buffer transistor and a second additional scan circuit adjacent to and connected to the second scan buffer transistor. Wherein, the size of the second level is larger than the size of the first level, and As can be seen from the plan view, the first additional scanning circuit and the second additional scanning circuit have the same area.

2. The display device as claimed in claim 1, wherein, The dimensions of the second level and the dimensions of the first level refer to the area as viewed from the plan view.

3. The display device as claimed in claim 1, wherein, The display area includes multiple corner areas, and the second level is disposed in the non-display area corresponding to the multiple corner areas.

4. The display device as claimed in claim 3, wherein, The display area includes a first display area and a second and a third display area extending from a portion of the first display area. A portion of the non-display area is disposed between the second and the third display areas, and a portion of the second gate line is disposed in the second and the third display areas.

5. The display device as claimed in claim 4, wherein, The second display area and the third display area correspond to some of the corner areas among the plurality of corner areas, and the second level is disposed in the non-display area corresponding to the second display area and the third display area.

6. The display device as claimed in claim 4, wherein, Each of the boundary between the second display area and the non-display area and the boundary between the third display area and the non-display area includes a curved shape, and the curved portion of the second gate line is disposed along the boundary between the second display area and the non-display area and the boundary between the third display area and the non-display area.

7. The display device as claimed in claim 3, wherein, The display device further includes: The camera area is located in the display area. The second gate line is disposed in the display area and located on one or more sides of the camera area.

8. The display device as claimed in claim 7, wherein, The camera area corresponds to some of the multiple corner areas, and the second level is set in the non-display area corresponding to the camera area.

9. The display device as claimed in claim 1, wherein, The size of the second scan buffer transistor is larger than the size of the first scan buffer transistor.

10. The display device as claimed in claim 9, wherein, The multiple levels also include a third level. Wherein, the first stage and the second stage output signals, and The third stage includes a dummy stage that does not output a signal, and the third stage is either the stage before or after the second stage.

11. The display device as claimed in claim 10, wherein, The size of the third level is smaller than the size of the first level and the size of the second level.

12. The display device as claimed in claim 11, wherein, The size of the third scan buffer transistor in the third stage is smaller than the size of the first scan buffer transistor and the size of the second scan buffer transistor.

13. The display device as claimed in claim 10, wherein, The interval between the second stage and the preceding stage of the second stage is different from the interval between the second stage and the following stage of the second stage.

14. The display device as claimed in claim 10, wherein, The gate driver includes a scan driver, which includes a first scan stage, a second scan stage, and a third scan stage corresponding to the first stage, the second stage, and the third stage, respectively, and the size of the second scan stage is larger than the size of the first scan stage.

15. The display device as claimed in claim 14, wherein, The first scan stage, the second scan stage, and the third scan stage each have a first scan buffer transistor, a second scan buffer transistor, and a third scan buffer transistor, and the size of the second scan buffer transistor is larger than the size of the first scan buffer transistor.

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