Gate driver and display device using the same

Abstract

A display device includes: a pixel connected to a power line, to which a pixel driving voltage is supplied; a data line extending along a first direction and connected to the pixel, the data line applying a data voltage of an image to the pixel; a gate line connected to the pixel and extending along a second direction, the gate line applying a gate signal to the pixel; a data driver configured to supply a data voltage to the data line during a display mode and to supply sensed data to the data line during a sensing mode; a gate driver configured to supply a gate signal to the gate line; and a sensing circuit configured to sense current flowing through a power line connected to a subset of pixels from the pixel during a sensing mode, the subset of pixels being arranged along the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2021-0191991, filed on December 30, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a gate driver and a display device using the gate driver. Background Technology

[0004] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDP), etc.

[0005] Based on the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices and organic light-emitting display devices. Active-matrix organic light-emitting display devices use self-emissive elements, such as organic light-emitting diodes (hereinafter referred to as "OLEDs"), to reproduce input images. Organic light-emitting display devices have advantages such as fast response speed, high luminous efficiency, high brightness, and wide viewing angle.

[0006] Some display devices (such as liquid crystal displays or organic light-emitting diode displays) include: a display panel comprising a plurality of sub-pixels; a driver that outputs drive signals for driving the display panel; a power supply that generates power to supply the display panel or the driver; etc. Drivers include gate drivers that provide scan signals or gate signals to the display panel and data drivers that provide data signals to the display panel.

[0007] In this display device, when drive signals such as scan signals, EM signals and data signals are provided to multiple sub-pixels formed in the display panel, the selected sub-pixels transmit light or emit light directly to display an image. Summary of the Invention

[0008] In this configuration, each sub-pixel includes a driving thin-film transistor (TFT) that controls the current flowing through the light-emitting element and one or more switching TFTs that switch the current. Degradation may occur due to prolonged driving of the driving TFTs, and a current-sensing-based compensation method is applied to compensate for this degradation. However, since the current-sensing-based compensation method repeatedly senses the current after writing data to one pixel block and then senses the current after writing data to the next pixel block, the sensing time required to sense the entire block becomes longer.

[0009] This disclosure aims to address all the aforementioned needs and problems.

[0010] This disclosure aims to provide a gate driver that can reduce sensing time and a display device including the gate driver.

[0011] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0012] In one embodiment, a display device includes: a plurality of pixels connected to a power line, a pixel driving voltage supplied to the power line, the plurality of pixels being divided into a plurality of pixel blocks extending along a first direction, and each pixel block including a different subset of pixels from the plurality of pixels; a plurality of data lines extending along the first direction and connected to the plurality of pixels, the plurality of data lines applying a plurality of data voltages of pixel data of an image to the plurality of pixels; and a plurality of gate lines connected to the plurality of pixels and extending along a second direction intersecting the first direction, the plurality of gate lines applying gate signals to the plurality of pixels. A pixel; a data driver configured to supply the plurality of data voltages of the image to the plurality of data lines during a display mode and to supply sensing data to the plurality of data lines during a sensing mode; a gate driver configured to supply the gate signal to the plurality of gate lines; and a sensing circuit configured to sense current flowing through a power line connected to a subset of pixels included in each pixel block in a column of the plurality of pixel blocks during the sensing mode, each of the subsets of pixels included in each pixel block supplying the sensing data during the sensing mode.

[0013] In one embodiment, a display device includes: a plurality of pixels connected to a power line, a pixel driving voltage supplied to the power line; a plurality of data lines extending along a first direction and connected to the plurality of pixels, the plurality of data lines applying a plurality of data voltages of pixel data of an image to the plurality of pixels; a plurality of gate lines connected to the plurality of pixels and extending along a second direction intersecting the first direction, the plurality of gate lines applying gate signals to the plurality of pixels; a data driver configured to supply the plurality of data voltages of the image to the plurality of data lines during a display mode and to supply sensed data to the plurality of data lines during a sensing mode; a gate driver configured to supply the gate signals to the plurality of gate lines; and a sensing circuit configured to sense current flowing through a power line connected to a subset of pixels arranged along the first direction during the sensing mode.

[0014] In one embodiment, a sensing circuit includes: a resistor; and a switch configured to connect the resistor in series with a power line during a sensing period and to disconnect the resistor from the power line during a display period in which an image is displayed via a display panel, the power line supplying pixel driving voltages to a plurality of pixels of the display panel divided into multiple columns of pixel blocks, wherein the sensing circuit is configured to, during the sensing period, in response to sensing data applied to a subset of pixels during a sensing mode, sequentially sense each pixel block included in a column of pixel blocks by measuring the current flowing through a power line connected to a subset of pixels included in a target pixel block of the column.

[0015] In this disclosure, when driven in sensing mode, since a sensing area is selected in the column direction along the data line, and then light emission control signals are sequentially applied in blocks within the sensing area to sense the current, the sensing time or sensing cycle time can be greatly shortened and the consistency can be improved.

[0016] In this disclosure, since the current flowing through the power line to which the pixel driving voltage is applied forms a path that bypasses the light-emitting element as a current path, the light emission of the light-emitting element is suppressed, thus solving the visibility problem.

[0017] The effects of this disclosure are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art through the following description and the appended claims. Attached Figure Description

[0018] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0019] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figure 2 It is shown Figure 1 A diagram showing the cross-sectional structure of the display panel;

[0021] Figure 3 This is a circuit diagram showing the pixel circuit connected to the external compensation circuit of this disclosure;

[0022] Figures 4 to 8 This is a diagram illustrating the working principle of the sensing circuit according to an embodiment;

[0023] Figure 9A and Figure 9B This is a graph used to compare and illustrate the total sensing time;

[0024] Figures 10A to 10D It is a diagram showing various changes in the shape of the block;

[0025] Figures 11A to 11D This diagram illustrates the principle of selecting the sensing area;

[0026] Figure 12 This is a diagram illustrating a shift register of a gate driver according to an embodiment of the present disclosure;

[0027] Figure 13 This is a diagram illustrating the signal processing unit of the sensor driver according to an embodiment;

[0028] Figure 14 This is a diagram illustrating the signal processing unit of the EM driver according to an embodiment; and

[0029] Figure 15 It is shown Figure 14 The waveform of the output signal of the signal processing unit shown is shown. Detailed Implementation

[0030] The advantages and features of this disclosure, and its implementation methods, will be more clearly understood through the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will complete the disclosure and enable those skilled in the art to fully understand its scope. This disclosure is limited only to the scope of the appended claims.

[0031] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, the same reference numerals generally denote the same elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0032] Terms such as “including,” “comprising,” “having,” and “consisting of” used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0033] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0034] When using terms such as “above,” “over,” “below,” and “adjacent” to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used in conjunction with the terms “immediately” or “directly.”

[0035] Terms such as "first" and "second" can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or name preceding the component.

[0036] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0037] The following embodiments may be combined or integrated with each other in whole or in part, and may be technically connected and operated in various ways. These embodiments may be implemented independently of each other or in relation to each other.

[0038] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 The diagram shows the cross-sectional structure of the display panel.

[0040] Reference Figure 1 and Figure 2 The display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0041] Display panel 100 may be a rectangular structure having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. Display panel 100 includes a pixel array AA for displaying input images. Pixel array AA includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. Display panel 100 may also include power lines commonly connected to the pixels. Power lines may include power lines to which a pixel drive voltage EVDD is applied, power lines to which an initialization voltage Vinit is applied, power lines to which a reference voltage Vref is applied, and power lines to which a low-potential power supply voltage EVSS is applied. These power lines are commonly connected to the pixels.

[0042] The pixel array AA includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln comprises a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. Pixels arranged in a pixel row share a gate line 103. Sub-pixels arranged along the data line direction Y share the same data line 102. A horizontal time period 1H is obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0043] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device that displays images on a screen and allows the actual background to be seen.

[0044] The display panel 100 can be a flexible display panel. The flexible display panel can be made of a plastic OLED panel. An organic thin film can be disposed on the back of the plastic OLED panel, and the pixel array AA and the light-emitting elements can be formed on the organic thin film.

[0045] To achieve color, each pixel 101 can be divided into red sub-pixels (hereinafter referred to as "R sub-pixels"), green sub-pixels (hereinafter referred to as "G sub-pixels"), and blue sub-pixels (hereinafter referred to as "B sub-pixels"). Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry. The pixel circuitry is connected to data lines, gate lines, and power lines.

[0046] Pixels can be arranged as real-color pixels and pentile pixels. By using a preset pixel rendering algorithm to drive two sub-pixels with different colors as a single pixel 101, pentile pixels can achieve a higher resolution than real-color pixels. The pixel rendering algorithm can compensate for insufficient color representation in each pixel using the colors of light emitted from neighboring pixels.

[0047] A touch sensor can be mounted on the display panel 100. Touch input can be sensed using a separate touch sensor or by using pixels. The touch sensor can be mounted on the screen of the display panel, externally mounted, or implemented as an in-cell touch sensor embedded in the pixel array AA.

[0048] like Figure 2 As shown, when viewed from a cross-sectional perspective, the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10.

[0049] Circuit layer 12 may include pixel circuitry connected to wiring such as data lines, gate lines, and power lines, gate drivers (GIPs) connected to gate lines, etc. The wiring and circuit elements of circuit layer 12 may include multiple insulating layers, two or more metal layers (separated by insulating layers), and active layers comprising semiconductor materials.

[0050] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a protective layer comprising an organic film and a passivation film.

[0051] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulating structure with alternating layers of organic and inorganic films. The inorganic film blocks the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When organic and inorganic films are stacked in multiple layers, the movement path of moisture or oxygen becomes longer compared to a single layer, thereby effectively blocking the penetration of moisture and oxygen that affect light-emitting element layer 14.

[0052] A touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include a metal wiring pattern forming the capacitor of the touch sensor and an insulating layer. The capacitor of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate can improve visibility and contrast by converting the polarized light reflected by the metal of the touch sensor layer and circuit layer 12. The polarizing plate may be implemented as a polarizing plate combining a linear polarizing plate and a phase retardation film, or a circular polarizing plate. A cover glass may be adhered to the polarizing plate.

[0053] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include a red color filter, a green color filter, a blue color filter, and a black matrix pattern. The color filter layer can replace a polarizing plate and improve color purity by absorbing a portion of the wavelengths of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a color filter layer 20 with higher light transmittance than a polarizing plate to the display panel, the light transmittance of the display panel PNL can be improved, as can the thickness and flexibility of the display panel PNL. A cover glass may be adhered to the color filter layer.

[0054] Power supply 140 generates the DC power required to drive the pixel array AA and display panel driver of display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 140 can adjust the DC input voltage from a host system (not shown) to generate DC voltages such as gamma reference voltage VGMA, gate on-state voltages VGH and VEH, gate off-state voltages VGL and VEL, pixel drive voltage EVDD, pixel low-level power supply voltage EVSS, reference voltage Vref, initialization voltage Vinit, anode voltage Vano, etc. Gamma reference voltage VGMA is provided to data driver 110. Gate on-state voltages VGH and VEH, and gate off-state voltages VGL and VEL are provided to gate driver 120. Pixel drive voltage EVDD, pixel low-level power supply voltage EVSS, reference voltage Vref, initialization voltage Vinit, anode voltage Vano, etc., are collectively provided to the pixels.

[0055] Under the control of the timing controller (TCON) 130, the display panel driver writes the pixel data (digital data) of the input image into the pixels of the display panel 100.

[0056] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may also include a demultiplexer array 112 disposed between the data driver 110 and the data line 102.

[0057] The demultiplexer array 112 uses multiple demultiplexers (DEMUX) to sequentially provide data voltages output from the channels of the data driver 110 to the data lines 102. The demultiplexers may include multiple switching elements disposed on the display panel 100. When the demultiplexers are disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 can be omitted.

[0058] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. The touch sensor driver can be integrated into a single driver integrated circuit (IC). In mobile or wearable devices, the timing controller 130, power supply 140, data driver 110, touch sensor driver, etc., can be integrated into a single driver integrated circuit (IC).

[0059] The display panel driver can operate in a low-speed drive mode under the control of the timing controller (TCON) 130. When the input image for a preset number of frames does not change during input image analysis, the low-speed drive mode can be set to reduce the power consumption of the display device. In low-speed drive mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver circuit and the display panel 100 can be reduced by decreasing the pixel refresh rate. The low-speed drive mode is not limited to the case of inputting a still image. For example, when the display device is operating in standby mode, or when a user command or input image has not been input to the display panel driver for a predetermined time or longer, the display panel driver can operate in low-speed drive mode.

[0060] Data driver 110 generates a data voltage Vdata by converting pixel data of the input image received from timing controller 130 using a digital-to-analog converter (DAC) at each frame interval with a gamma-compensated voltage. The gamma reference voltage VGMA is divided for each grayscale level by a voltage divider circuit. The gamma-compensated voltage divided from the gamma reference voltage VGMA is provided to the DAC of data driver 110. The data voltage Vdata is output through the output buffer AMP in each channel of data driver 110.

[0061] Gate driver 120 may include scan driver 121 and EM driver 122. Gate driver 120 may be implemented together with the TFT array of pixel array AA as an in-panel gate (GIP) circuit directly formed on the circuit layer 12 of display panel 100. The in-panel gate (GIP) circuit may be disposed on the bezel area BZ, which is a non-display area of ​​display panel 100, or distributed in the pixel array that reproduces the input image. Under the control of timing controller 130, gate driver 120 sequentially outputs gate signals to gate line 103. Gate driver 120 may provide gate signals to gate line 103 sequentially by shifting the gate signals using a shift register. Gate signals may include scan pulses, transmit control pulses (hereinafter referred to as "EM pulses"), initial pulses, and sensing pulses.

[0062] The shift register of the gate driver 120 responds to the start pulse and the pulse of the shift clock output gate signal from the timing controller 130, and shifts the pulse according to the shift clock timing.

[0063] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized with it from the host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal time period (1H).

[0064] The host system can be any of a television (TV) system, tablet computer, laptop computer, navigation system, personal computer (PC), home theater system, mobile device, and in-vehicle system. The host system can scale the image signal from the video source according to the resolution of the display panel 100 and transmit the image signal along with the timing signal to the timing controller 130.

[0065] The timing controller 130 multiplies the input frame rate by i and controls the operating timing of the display panel driver circuit with a frame rate of input frame rate × i (where i is a positive integer greater than 0) Hz. The input frame rate is 60Hz in the NTSC (National Television Standards Committee) scheme and 50Hz in the PAL (Phase Alternating Line) scheme. The timing controller 130 can reduce the drive frequency of the display panel driver by lowering the frame rate to a frequency between 1Hz and 30Hz, thereby reducing the pixel refresh rate in low-speed drive mode.

[0066] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operating timing of the data driver 110, a control signal for controlling the operating timing of the demultiplexer array 112, and a gate timing control signal for controlling the operating timing of the gate driver 120. The timing controller 130 controls the operating timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0067] The voltage level of the gate timing control signal output from the timing controller 130 can be converted into gate on-voltages VGH and VEH and gate off-voltages VGL and VEL by a level shifter (not shown), and then provided to the gate driver 120. That is, the level shifter converts the low-level voltage of the gate timing control signal into the gate off-voltages VGL and VEL, and the high-level voltage of the gate timing control signal into the gate on-voltages VGH and VEH. The gate timing signal includes a start pulse and a shift clock.

[0068] Due to process variations and device characteristic variations caused in the manufacturing process of the display panel 100, differences may exist in the electrical characteristics of the driving elements between pixels, and these differences increase as the driving time of the pixels increases. Internal or external compensation techniques can be applied to organic light-emitting diode displays to compensate for these variations in the electrical characteristics of the driving elements between pixels. Internal compensation techniques use an internal compensation circuit implemented in each pixel circuit to sample the threshold voltage of the driving element for each sub-pixel to compensate the gate-source voltage Vgs of the driving element by an amount equal to the threshold voltage. External compensation techniques use an external compensation circuit to sense the current or voltage of the driving element in real time, which varies according to the electrical characteristics of the driving element. External compensation techniques compensate for the variations (or changes) in the electrical characteristics of the driving elements in each pixel in real time by modulating the pixel data (digital data) of the input image to be as much as the sensed changes (or alterations) in the electrical characteristics of the driving element for each pixel. The display panel driver can use external and / or internal compensation techniques to drive the pixels.

[0069] Figure 3 This is a circuit diagram showing the pixel circuit of the present disclosure connected to an external compensation circuit.

[0070] Reference Figure 3 The pixel circuit includes a light-emitting element EL, a driving element DT that provides current to the light-emitting element EL, a first switching element M01 that connects to the pixel driving voltage line 41 in response to the light-emitting control signal EM, a second switching element M02 that connects the data line 40 to the node n2 in response to the scan signal SCAN, a capacitor Cst connected to the gate of the driving element DT, a third switching element M03 that connects the reference voltage line 43 to the node n3 in response to the sensing signal SENSE, and a fourth switching element M04 that connects the initialization voltage line 44 to the node n2 in response to the initialization signal INIT.

[0071] The pixel driving voltage EVDD is applied to the first electrode of the driving element DT through the first power supply line 41. The driving element DT drives the light-emitting element OLED by providing current to the light-emitting element OLED according to the gate-source voltage Vgs. When the forward voltage between the anode and cathode is greater than or equal to the threshold voltage, the light-emitting element OLED turns on and emits light. A low potential voltage EVSS is applied to the cathode of the light-emitting element EL. A capacitor Cst is connected between the gate and the second electrode of the driving element DT to maintain the gate-source voltage Vgs of the driving element DT.

[0072] The first switching element M01 is turned on according to the gate turn-on voltage of the light emission control signal EM applied from the gate line, so as to connect the pixel driving voltage line 41 to the first node n1.

[0073] The second switching element M02 is turned on according to the gate turn-on voltage of the scan signal SCAN applied from the gate line, so as to connect the data line 40 to the gate of the drive element DT and the capacitor Cst.

[0074] The third switching element M03 applies a reference voltage VpreR in response to the sensing signal SENSE. The reference voltage VpreR is applied to the pixel circuit through the reference voltage line 43.

[0075] The fourth switching element M04 is turned on according to the gate turn-on voltage of the initialization signal INIT, so as to connect the initialization voltage line 44 to the gate of the driving element DT and the capacitor Cst.

[0076] The light-emitting element (EL) can be implemented as an OLED. An OLED includes an organic compound layer formed between the anode and cathode. This organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The switching elements M01 and M02 can be implemented as n-channel oxide thin-film transistors (TFTs).

[0077] Organic light-emitting diodes (OLEDs) used as light-emitting elements can have a series structure with multiple light-emitting layers stacked on top of each other. OLEDs with a series structure can improve pixel brightness and lifespan.

[0078] In this scenario, in sensing mode, the current flowing through the channel of the driving element DT or the voltage between the driving element DT and the light-emitting element EL is sensed via reference voltage line 43. The current flowing through reference voltage line 43 is converted into voltage by an integrator and then into digital data by an analog-to-digital converter (ADC). This digital data is sensing data that includes threshold voltage or mobility information of the driving element DT. The sensing data is transmitted to a data operation unit. The data operation unit can receive the sensing data from the ADC to compensate for pixel drive deviations and degradation by adding or multiplying a compensation value selected based on the sensing data to the pixel data.

[0079] Figures 4 to 8 This is a diagram illustrating the working principle of the sensing circuit according to an embodiment.

[0080] Reference Figure 4 This allows the chip-on-film (COF) to be attached to the display panel PNL. The COF includes a driver IC (SiC) and connects the source PCB (SiC) to the display panel PNL. The driver IC (SiC) includes a data driver.

[0081] The timing controller 130 and the power supply unit 150 can be mounted on the control PCB CPCB. The control PCB CPCB can be connected to the source PCB SPCB via a flexible circuit film (e.g., flexible printed circuit (FPC)).

[0082] By including the aforementioned reference voltage controller, the timing controller 130 can adjust the reference voltage Vref output from the power supply unit 150 based on the result of comparing the reference voltage Vref_sensed sensed from the display panel PNL with the reference voltage Vref output from the power supply unit 150.

[0083] The reference voltage Vref output from the power supply unit 150 can be supplied to the display panel PNL via the FPC, source PCB SPCB, and COF. Therefore, in the display panel PNL, the reference voltage Vref input unit IN is close to the driver IC SIC.

[0084] The reference voltage line REFL on the display panel PNL can be connected to the power supply unit 150 via COF, source PCB SPCB, and FPC. The reference voltage line REFL can be grouped using shorting bars SB. The shorting bars can be formed on one side of the display panel PNL and can be formed as glass line (LOG) lines on the display panel instead of glass line (LOG) lines in the driver IC SIC. The reference voltage line REFL connected to all pixels on the display panel PNL can be connected to the shorting bars.

[0085] The sensing unit 160 senses the current flowing through the pixel power line when driven in sensing mode after power is turned off, provided that a high potential voltage EVDD is applied. The sensing unit 160 provides the sensed current to the timing controller 130.

[0086] Reference Figure 5 The sensing unit 160 may include a resistor R connected to the pixel power line and an ADC connected to the resistor R. The sensing unit 160 may also include a switch SW connected between the pixel power line and the resistor R. The switch SW is off in display mode and on in sensing mode.

[0087] When switch SW is off in display mode, a high-potential voltage EVDD is applied to pixel PXL through the pixel power line. When switch SW is on in sensing mode, the high-potential voltage EVDD is applied to pixel PXL through the pixel power line and resistor R, and the current flowing through resistor R is sensed by an ADC. The ADC is configured to convert the voltage difference across the resistor into a digital value during sensing mode. In one embodiment, this voltage difference represents the current flowing through the pixel power line during sensing mode. TCON 130 receives this digital value and generates a compensation value for the corresponding pixel block to compensate for variations in the electrical characteristics of pixels 101 included in the corresponding block by adding or multiplying the compensation value to the pixel data of the input image.

[0088] Reference Figure 6A In this embodiment, when driven in sensing mode, the gate on-state voltage of the light emission control signal EM is applied to the first switching element M01, the gate on-state voltage of the scan pulse SCAN is applied to the second switching element M02, and the gate on-state voltage of the sensing signal SENSE is applied to the third switching element M03. The gate on-state voltages are applied to the first switching element M01, the second switching element M02, and the third switching element M03, and these elements are turned on to form a current path. The current flowing through the pixel driving voltage line 41 flows through this current path to the reference voltage line 43 and not to the light emission element EL.

[0089] Therefore, in the embodiments, when driven in sensing mode, current sensing can be performed without emitting light from the light-emitting element, and the visibility problem can be solved because the light emission of the light-emitting element is suppressed.

[0090] Reference Figure 6B In an embodiment, when driven in sensing mode, since the gate cutoff voltage of the light emission control signal EM is applied to the first switching element M01, current can be prevented from flowing through the pixel driving voltage line 41 even when the gate turn-on voltage is applied to the second switching element M02 and the third switching element M03 and the second switching element M02 and the third switching element M03 are turned on.

[0091] As described above, when driven in sensing mode, the pixel circuit can be selected via the emission control signal EM. That is, the amount of current flowing can be measured by allowing current to flow only through the selected pixel circuit.

[0092] Reference Figure 7 The sensing unit senses current in units of blocks comprising a predetermined number of pixels. Here, the block can be a square with the same number of pixels in the row direction X and the same number of pixels in the column direction Y, for example, a 30-pixel × 30-pixel square. The block is not limited to a square and can be implemented in various shapes.

[0093] The sensing unit 160 senses current on a block-by-block basis, and senses the current flowing through each block in a predetermined order. Different currents are sensed based on the characteristics and degradation level of the pixels included in each block.

[0094] The method of sensing current in blocks can shorten the overall sensing time and can be implemented with a simpler structure compared to the method of sensing current in pixels.

[0095] In this embodiment, clock speed and consistency are improved by sensing the current flowing through each block in the column direction Y rather than sensing the current flowing through each block in the row direction X.

[0096] Reference Figure 8 In this embodiment, a pixel structure for sensing current on a block-by-block basis is shown. A reference voltage line and a high-potential voltage line are shared by all pixels on the display panel, and a data voltage line is connected to each pixel in the column direction Y.

[0097] Therefore, even when both the reference voltage and the high-potential voltage are applied to all pixels on the display panel, it is possible to select which blocks to perform sensing based on whether data is applied. For example, white data can be applied to all pixels in the first block ONBLK where sensing is performed, and black data can be applied to all pixels in the second block OFFBLK where sensing is not performed.

[0098] Here, when white data is applied to one block on the display panel, black data is applied to the remaining blocks.

[0099] When white data is applied to all pixels in the first block of the sensing operation, the sensing unit 160 senses the current flowing through the pixel drive voltage lines. In this case, since the current flowing through the pixel drive voltage lines has a large value on a block-by-block basis, an integrator is not required in the sensing unit.

[0100] Figure 9A and Figure 9B This is a graph used to compare and illustrate the total sensing time.

[0101] Reference Figure 9A In an embodiment, when driven in sensing mode, sensing data (i.e., white data) can be applied to each block in the column direction Y, and the current flowing through each block can be sensed.

[0102] In this case, the total sensing time T 总 It can be defined by the following equation 1.

[0103] [Equation 1]

[0104] T 总 =[T寻址 +(T 感测 ×N_Vblock)×N_subpxl×N_Hblock

[0105] Here, T 寻址 T is the time when the sensing data is applied. 感测 It is the time to sense the current flowing through each block. N_Vblock is the number of blocks in the column direction Y, N_subpxl is the number of subpixels in the block in the column direction Y, and N_Hblock is the number of blocks in the row direction X.

[0106] For example, when the total number of blocks is 36×64 and the number of pixels in each block is 30×30, for FHD 120hz RGB, the total sensing time T 总 The time is [8.33 milliseconds + (2 milliseconds × 36)] × 3 × 64, which is 15.42 seconds.

[0107] Reference Figure 9B In the comparative example, when driven in sensing mode, sensing data (i.e., white data) can be applied to each block in the row direction X, and the current flowing through each block can be sensed.

[0108] In this case, the total sensing time T 总 It can be defined by the following equation 2.

[0109] [Equation 2]

[0110] T 总 =(T 寻址 +T 感测 )×N_subpxl×N_Hblock×N_Vblock

[0111] For example, when the total number of blocks is 36×64 and the number of pixels in each block is 30×30, for FHD 120hz RGB, the total sensing time T 总 The time is (8.33 milliseconds + 2 milliseconds) × 3 × 64 × 36, which is 71.4 seconds.

[0112] [Table 1]

[0113]

[0114]

[0115] As shown in Table 1, since the addressing time difference between the embodiments and the comparative examples is large, it can be seen that the total sensing time in the embodiments is significantly reduced compared with the comparative examples.

[0116] Figures 10A to 10D This is a diagram showing various changes in the shape of the block.

[0117] Reference Figure 10A and Figure 10B The table below shows the case where the size of the block to be sensed changes. In this case, as shown in Table 2, the cycle time can be shortened according to the size of the block.

[0118] [Table 2]

[0119]

[0120] Reference Figure 10C and Figure 10D The number of blocks of applied data can be varied. For example, a data voltage can be applied to each block in the column direction Y, or the blocks in the column direction Y can be divided into multiple groups, and the data voltage can be applied to each group. As described above, since the cycle time can be shortened for the same block size compared to the comparative example, and the block size can be made smaller for the same cycle time, consistency can be improved. Therefore, various configurations for current sensing are possible in the embodiments, and the design can be modified to an optimal configuration taking into account cycle time, block size, consistency, etc.

[0121] Figures 11A to 11D This diagram illustrates the principle of selecting the sensing area.

[0122] Reference Figure 11A In an embodiment, sensing data (i.e., white data) can be applied to pixels in sensing area M1 that are sensed along the data line in the vertical or column direction Y, and black data can be applied to pixels in non-sensing areas M2 to M8 that are not sensed.

[0123] In this embodiment, the sensing area can be selected by applying white data. Current can then be sensed for each block included within the selected sensing area.

[0124] Reference Figure 11B The current should be sensed in units of one block within the sensing area. In this case, a light control signal can be used to select the block.

[0125] In an embodiment, a light emission control signal can be sequentially applied to select blocks N1 to N6 included in a sensing area M1 set along the data line in the column direction Y.

[0126] Reference Figure 11C When the first block N1 included in the sensing area M1 is selected, a high voltage level of the light emission control signal is applied to the first block N1, so the pixel driving voltage EVDD flows through the driving element, and a low voltage level of the light emission control signal can be applied sequentially to the second block N2 to the sixth block N6 included in the sensing area M1.

[0127] In this case, since each sub-pixel in the first block N1 sensed in the block group uses Figure 3 The circuit shown allows the first switching element M01 to be turned on by the high voltage level of the light emission control signal, thus applying the pixel driving voltage EVDD to form a current path.

[0128] However, because each sub-pixel of the remaining block in the sensed area is used Figure 3 The circuit shown is used to implement this, so the first switching element M01 is turned off by the low voltage level of the light emission control signal, and no pixel driving voltage EVDD is applied, so no current path is formed.

[0129] Reference Figure 11D During the period when white data following the addressing interval is applied to the sensing interval of blocks N1 to N6 in the sensing area, blocks N1, N2, N3, N4, N5 and N6 in the sensing area can be driven sequentially to sense current.

[0130] Figure 12 This is a diagram illustrating a shift register of a gate driver according to an embodiment of the present disclosure. Figure 13 This is a diagram illustrating the signal processing unit of the sensor driver according to an embodiment. Figure 14 This is a diagram illustrating the signal processing unit of the EM driver according to an embodiment, and Figure 15 It is shown Figure 14 The waveform of the output signal of the signal processing unit shown is shown.

[0131] Reference Figure 12 According to an embodiment, the gate driver 120 includes a plurality of signal processing units STG1, STG2, STG3, STG4, STG5, STG6 and STG7 cascaded via a carry line through which a carry signal is transmitted.

[0132] The timing controller 130 can use the start pulse Vst input to the gate driver 120 to adjust the width of the gate driver's output signal GOUT and the multiple outputs.

[0133] Each of the signal processing units STG1, STG2, STG3, STG4, STG5, STG6, and STG7 receives a start pulse or carry signal and clock signals CLK1, CLK2, CLK3, and CLK4 output from the previous odd or even signal processing unit. The first signal processing unit STG1 is driven starting from the start pulse Vst, and the other signal processing units STG2, STG3, STG4, STG5, STG6, and STG7 receive the carry signal from the previous odd or even signal processing unit and are then driven.

[0134] Reference Figure 13 Each signal processing unit of the sensing driver according to the embodiment includes a first circuit unit 210 and a second circuit unit 220. The first circuit unit 210 charges or discharges a first control node (hereinafter referred to as "Q node") and a second control node (hereinafter referred to as "Qb node").

[0135] In this configuration, the first circuit unit 210 includes a control circuit for controlling the charging and discharging of Q node Q and Qb node Qb, and an inverter circuit for inverting the voltage of Q node Q and applying the voltage to Qb node Qb. The inverter circuit includes a Qb node charging unit and a Qb node discharging unit.

[0136] The second circuit unit 220 responds to the potential of Q node Q and Qb node Qb by outputting a sensing signal SEOUT(n).

[0137] The second circuit unit 220 includes first buffer transistors T1 and T2 that output a sensing signal SEOUT(n). The first buffer transistors T1 and T2 are respectively a first pull-up transistor T1 that is turned on based on the potential of node Q, and a first pull-down transistor T2 that is turned on based on the potential of node Qb. In the first pull-up transistor T1, the gate is connected to node Q, the first electrode is connected to the clock signal line SECLK(n), and the second electrode is connected to the first output terminal SEOUT(n). In the first pull-down transistor T2, the gate is connected to node Qb, the first electrode is connected to the first output terminal SEOUT(n), and the second electrode is connected to the low-potential voltage line SEGVSS0. The first buffer transistors T1 and T2 output the sensing signal SEOUT(n) based on a clock signal applied through the clock signal line SECLK(n) and a low-potential voltage applied through the low-potential voltage line SEGVSS0.

[0138] In this case, such as Figure 6A As shown, in an embodiment, when driven in sensing mode, the voltage of the sensing signal is set to remain at a high voltage level, thereby forming a current path that bypasses the light-emitting element. For example, in an embodiment, when driven in sensing mode, the voltage applied to the clock signal line SECLK(n) and the low-potential voltage line SEGVSS0 can be set to a high voltage level.

[0139] Reference Figure 14 Each signal processing unit of the EM driver according to the embodiment includes a first circuit unit 211 and a second circuit unit 221. The first circuit unit 211 charges or discharges a first control node (hereinafter referred to as "Q node") and a second control node (hereinafter referred to as "Qb node").

[0140] In this configuration, the first circuit unit 211 includes a control circuit for controlling the charging and discharging of Q node Q and Qb node Qb, and an inverter circuit for inverting the voltage of Q node Q and applying the voltage to Qb node Qb. The inverter circuit includes a Qb node charging unit and a Qb node discharging unit.

[0141] The second circuit unit 221 responds to the potential of Q node Q and Qb node Qb by outputting the light emission control signal EMOUT(n).

[0142] The second circuit unit 221 includes first buffer transistors T1 and T2 that output a light-emitting control signal EMOUT(n). The first buffer transistors T1 and T2 are respectively a first pull-up transistor T1 that is turned on based on the potential of node Q, and a first pull-down transistor T2 that is turned on based on the potential of node Qb. In the first pull-up transistor T1, the gate is connected to node Q, the first electrode is connected to the clock signal line EMCLK(n), and the second electrode is connected to the first output terminal EMOUT(n). In the first pull-down transistor T2, the gate is connected to node Qb, the first electrode is connected to the first output terminal EMOUT(n), and the second electrode is connected to the low-potential voltage line EMGVSS0. The first buffer transistors T1 and T2 output the light-emitting control signal EMOUT(n) based on the clock signal applied through the clock signal line EMCLK(n) and the low-potential voltage applied through the low-potential voltage line EMGVSS0.

[0143] Reference Figure 15 Each of the signal processing units STG1, STG2, STG3, STG4, STG5, STG6, and STG7 outputs a light-emitting control signal sequentially by shifting the start pulse or carry signal output from the previous signal processing unit according to the timing of the clock signal. In this embodiment, the signal processing units may output the light-emitting control signals sequentially in blocks.

[0144] Here, as an example, a case is shown where a block includes five pixel rows.

[0145] For example, in the first sensing range (①), a light emission control signal with a high voltage level can be applied according to the clock signal EMCLK(ON) from the signal processing unit connected to the first block, and in the second sensing range (②), a light emission control signal with a high voltage level can be applied according to the clock signal EMCLK(ON) from the signal processing unit connected to the second block.

[0146] The light emission control signal applied to the first block can be applied at a high voltage level during the first sensing interval based on the rising edge of the clock signal EMCLK(ON), and can be applied at a low voltage level during the second sensing interval based on the rising edge of the clock signal EMCLK(OFF). That is, the light emission control signal from the signal processing unit can be applied at a high voltage level only during the interval in which the current amount of the corresponding block is sensed.

[0147] Therefore, as Figure 6A and Figure 6B As shown, in an embodiment, when driven in sensing mode, since the voltage of the light emission control signal is applied at a high voltage level to the pixel circuit in the selected block located in the sensing area and at a low voltage level to the pixel circuit in the unselected block located in the sensing area, the block can be selected by the light emission control signal.

[0148] In one embodiment, a display device includes: a plurality of pixels connected to a power line, a pixel driving voltage supplied to the power line, the plurality of pixels being divided into a plurality of pixel blocks extending along a first direction, and each pixel block including a different subset of pixels from the plurality of pixels; a plurality of data lines extending along the first direction and connected to the plurality of pixels, the plurality of data lines applying a plurality of data voltages of pixel data of an image to the plurality of pixels; and a plurality of gate lines connected to the plurality of pixels and extending along a second direction intersecting the first direction, the plurality of gate lines applying gate signals to the plurality of pixels. A pixel; a data driver configured to supply the plurality of data voltages of the image to the plurality of data lines during a display mode and to supply sensing data to the plurality of data lines during a sensing mode; a gate driver configured to supply the gate signal to the plurality of gate lines; and a sensing circuit configured to sense current flowing through a power line connected to a subset of pixels included in each pixel block in a column of the plurality of pixel blocks during the sensing mode, each of the subsets of pixels included in each pixel block supplying the sensing data during the sensing mode.

[0149] In one embodiment, during the sensing mode, the sensing circuit sequentially senses each pixel block included in the column of pixel blocks, wherein each subset of pixels included in each pixel block is supplied with the sensing data and sensed based on the sensing data based on the current flowing through the power line.

[0150] In one embodiment, the sensing data includes white data and the display panel driver is configured to supply the white data to each pixel block from the currently sensing column of pixel blocks, and to supply black data to the remaining pixel blocks included in other columns of pixel blocks that are not currently being sensed.

[0151] In one embodiment, each of the plurality of pixels includes: a driving element comprising a first electrode, a gate, and a second electrode, the first electrode being connected to a first node, the gate being connected to a second node, and the second electrode being connected to a third node; a first switching element comprising a first electrode, a gate, and a second electrode, the first electrode being connected to a power line, a pixel driving voltage being applied to the power line, a light emission control signal being applied to the gate, and the second electrode being connected to the first node; and a light-emitting element comprising an anode and a cathode, the anode being connected to the third node, and a low-level power supply voltage being applied to the cathode. A capacitor located between the second node and the third node; a second switching element comprising a first electrode, a gate, and a second electrode, the first electrode of the second switching element being connected to a data line, a data voltage from the plurality of data voltages being applied to the data line, a scan signal being applied to the gate of the second switching element, and the second electrode of the second switching element being connected to the second node; and a third switching element comprising a first electrode, a gate, and a second electrode, the first electrode of the third switching element being connected to the third node, a sensing signal being applied to the gate of the third switching element, and the second electrode of the third switching element being connected to a reference line, and a reference voltage being applied to the reference line.

[0152] In one embodiment, during the sensing mode, in response to an on level, the light emission control signal is applied to the gate of each first switching element, turning on each first switching element included in each pixel of the target pixel block of the currently being sensed column of pixels, and in response to an off level, the light emission control signal is applied to the gate of each first switching element, turning off each first switching element included in each pixel of the remaining pixel block of the currently being sensed column of pixels.

[0153] In one embodiment, during the sensing mode, a light emission control signal in response to an on-level is applied to the gate of each of the first switching elements, and each of the first switching elements included in each pixel of the remaining pixel block included in the other column of pixel blocks supplying the black data is turned on because it is not currently being sensed.

[0154] In one embodiment, during the display mode, current flows through the light-emitting elements included in the plurality of pixels, while during the sensing mode, the current does not flow through the light-emitting elements included in the pixel blocks from the currently being sensed column of pixels.

[0155] In one embodiment, the sensing circuit includes: a resistor; a switch configured to connect the resistor in series with the power line during the sensing mode and to disconnect the resistor from the power line during the display mode; and an analog-to-digital converter (ADC) connected in parallel with the resistor, the ADC being configured to convert a voltage difference across the resistor into a digital value representing the current flowing through the power line during the sensing mode.

[0156] In one embodiment, the pixel data of the image is adjusted by a compensation value based on the digital value.

[0157] In one embodiment, the gate driver includes a shift register configured to output the sensing signal. The shift register includes a plurality of signal processing units, each signal processing unit including: a first transistor including a gate, a first electrode, and a second electrode of the first transistor, the gate of the first transistor being connected to a first control node of the signal processing unit, the first electrode of the first transistor being connected to a clock node, and the second electrode of the first transistor being connected to an output node for outputting the sensing signal; and a second transistor including a gate, a first electrode, and a second electrode of the second transistor, the gate of the second transistor being coupled to a second control node of the signal processing unit, the first electrode of the second transistor being connected to the output node, and the second electrode of the second transistor being connected to a voltage node, wherein during the display mode, a clock switching between an on-state voltage and an off-state voltage is input to the clock node, a low-potential reference voltage is applied to the voltage node, and during the sensing mode, the on-state voltage is applied to each of the clock node and the voltage node.

[0158] In one embodiment, a display device includes: a plurality of pixels connected to a power line, a pixel driving voltage supplied to the power line; a plurality of data lines extending along a first direction and connected to the plurality of pixels, the plurality of data lines applying a plurality of data voltages of pixel data of an image to the plurality of pixels; a plurality of gate lines connected to the plurality of pixels and extending along a second direction intersecting the first direction, the plurality of gate lines applying gate signals to the plurality of pixels; a data driver configured to supply the plurality of data voltages of the image to the plurality of data lines during a display mode and to supply sensed data to the plurality of data lines during a sensing mode; a gate driver configured to supply the gate signals to the plurality of gate lines; and a sensing circuit configured to sense current flowing through a power line connected to a subset of pixels arranged along the first direction during the sensing mode.

[0159] In one embodiment, the plurality of pixels are divided into multiple columns of pixel blocks extending along the first direction, and each pixel block includes a different subset of pixels from the plurality of pixels.

[0160] In one embodiment, the subset of pixels is included in a pixel block from a currently being sensed column of pixels, and the sensed data including white data is provided to the pixels included in the column of pixels, and black data is provided to the pixels included in the remaining columns of pixels from the multiple columns of pixels that are not currently being sensed during the sensing mode.

[0161] In one embodiment, during the sensing mode, the sensing circuit sequentially senses each pixel block included in the column of pixel blocks currently being sensed, such that each subset of pixels included in each pixel block is supplied with the white data and sensed based on the sensing current flowing through the power line according to the white data.

[0162] In one embodiment, each of the plurality of pixels includes: a driving element comprising a first electrode, a gate, and a second electrode, the first electrode being connected to a first node, the gate being connected to a second node, and the second electrode being connected to a third node; a first switching element comprising a first electrode, a gate, and a second electrode, the first electrode being connected to a power line, a pixel driving voltage being applied to the power line, a light emission control signal being applied to the gate, and the second electrode being connected to the first node; a light-emitting element comprising an anode and a cathode, the anode being connected to the third node, and a low-level power supply voltage being applied to the cathode; and a capacitor. The capacitor is located between the second node and the third node; and a second switching element, the second switching element including a first electrode, a gate, and a second electrode, the first electrode of the second switching element being connected to a data line, a data voltage from the plurality of data voltages being applied to the data line, a scan signal being applied to the gate of the second switching element, the second electrode of the second switching element being connected to the second node; and a third switching element, the third switching element including a first electrode, a gate, and a second electrode, the first electrode of the third switching element being connected to the third node, a sensing signal being applied to the gate of the third switching element, the second electrode of the third switching element being connected to a second power line of the plurality of power lines, a reference voltage being applied to the second power line.

[0163] In one embodiment, during the sensing mode, in response to an on level, the light emission control signal is applied to the gate of each first switching element, turning on each first switching element included in each pixel of the target pixel block of the currently being sensed column of pixels, and in response to an off level, the light emission control signal is applied to the gate of each first switching element, turning off each first switching element included in the remaining pixel blocks of the currently being sensed column of pixels.

[0164] In one embodiment, during the sensing mode, a light emission control signal in response to an on-level is applied to the gate of each of the first switching elements, and each of the first switching elements included in each pixel of the remaining pixel block included in the remaining column of pixel blocks supplied with the black data is turned on because it is not currently being sensed. In one embodiment, a sensing circuit includes: a resistor; and a switch configured to connect the resistor in series with a power line during a sensing period and configured to disconnect the resistor from the power line during a display period in which an image is displayed through a display panel, the power line supplying a pixel driving voltage to a plurality of pixels of the display panel divided into multiple columns of pixel blocks, wherein the sensing circuit is configured to, during the sensing period, in response to sensing data applied to a subset of pixels during the sensing mode, sequentially sense each pixel block included in a column of pixel blocks by measuring the current flowing through a power line connected to a subset of pixels included in a target pixel block of the column.

[0165] In one embodiment, the sensing circuit further includes an analog-to-digital converter connected in parallel with the resistor, the analog-to-digital converter being configured to convert the voltage difference across the resistor into a digital value during the sensing mode in response to current flowing through the power line.

[0166] In one embodiment, the pixel data of the image is adjusted by a compensation value based on the digital value.

[0167] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be understood to fall within the scope of the present disclosure.

Claims

1. A display device, comprising: Multiple pixels are connected to a power line, a pixel driving voltage is supplied to the power line, the multiple pixels are divided into multiple columns of pixel blocks extending along a first direction, and each pixel block includes a different subset of pixels from the multiple pixels, wherein the different subsets of pixels in the pixel block are arranged as multiple columns of pixels within the pixel block; Multiple data lines extend along the first direction and are connected to the multiple pixels, and the multiple data lines apply multiple data voltages of the pixel data of the image to the multiple pixels; Multiple gate lines are connected to the plurality of pixels and extend along a second direction intersecting the first direction, the multiple gate lines applying gate signals to the plurality of pixels; A data driver configured to supply the plurality of data voltages of the image to the plurality of data lines during a display mode, and to supply sensing data to the plurality of data lines during a sensing mode; A gate driver configured to supply the gate signal to the plurality of gate lines; and A sensing circuit is configured to sense, during the sensing mode, current flowing through a power line connected to a subset of pixels included in each pixel block of a column of pixels from the multi-column pixel block, each of the subsets of pixels included in each pixel block supplying the sensing data during the sensing mode, and at least one light-emitting element included in the pixels of the subsets of pixels arranged in the multi-column pixel block is configured to receive the sensing data without emitting light during the sensing mode.

2. The display device according to claim 1, wherein, During the sensing mode, the sensing circuit sequentially senses each pixel block included in the column of pixel blocks, such that each subset of pixels included in each pixel block is supplied with the sensing data and sensed based on the sensing data based on the current flowing through the power line.

3. The display device according to claim 2, wherein, The sensing data includes white data and the display panel driver is configured to supply the white data to each pixel block from the currently sensing column of pixel blocks, and to supply black data to the remaining pixel blocks included in other columns of pixel blocks that are not currently being sensed.

4. The display device according to claim 3, wherein, Each of the plurality of pixels includes: A driving element includes a first electrode, a gate, and a second electrode, wherein the first electrode is connected to a first node, the gate is connected to a second node, and the second electrode is connected to a third node. A first switching element, comprising a first electrode, a gate, and a second electrode, wherein the first electrode is connected to the power line, the pixel driving voltage is applied to the power line, the light emission control signal is applied to the gate, and the second electrode is connected to the first node. A light-emitting element, comprising an anode and a cathode, wherein the anode is connected to the third node and a low-level power supply voltage is applied to the cathode; A capacitor, the capacitor being located between the second node and the third node; and A second switching element, comprising a first electrode, a gate, and a second electrode, wherein the first electrode is connected to a data line, a data voltage from the plurality of data voltages is applied to the data line, a scan signal is applied to the gate, and the second electrode is connected to the second node; and A third switching element includes a first electrode, a gate, and a second electrode. The first electrode is connected to the third node, a sensing signal is applied to the gate, and the second electrode is connected to a reference line, with a reference voltage applied to the reference line.

5. The display device according to claim 4, wherein, During the sensing mode, in response to an on level, the light emission control signal is applied to the gate of each first switching element, turning on each first switching element included in each pixel of the target pixel block of the currently being sensed column of pixels, and in response to an off level, the light emission control signal is applied to the gate of each first switching element, turning off each first switching element included in each pixel of the remaining pixel block of the currently being sensed column of pixels.

6. The display device according to claim 5, wherein, During the sensing mode, the light emission control signal in response to the turn-on level is applied to the gate of each of the first switching elements, and each of the first switching elements included in each pixel of the remaining pixel block included in the other column pixel block that supplies the black data is turned on because it is not currently being sensed.

7. The display device according to claim 6, wherein, During the display mode, current flows through the light-emitting elements included in the plurality of pixels, while during the sensing mode, the current does not flow through the light-emitting elements included in the pixel blocks from the currently being sensed column of pixels.

8. The display device according to claim 1, wherein, The sensing circuit includes: Resistor; A switch configured to connect the resistor in series with the power line during the sensing mode and configured to disconnect the resistor from the power line during the display mode; and An analog-to-digital converter (ADC) is connected in parallel with the resistor and is configured to convert the voltage difference across the resistor into a digital value representing the current flowing through the power line during the sensing mode.

9. The display device according to claim 8, wherein, The pixel data of the image is adjusted by a compensation value based on the digital value.

10. The display device according to claim 4, wherein, The gate driver includes a shift register configured to output the sensed signal. The shift register includes a plurality of signal processing units, each of which includes: A first transistor includes a gate, a first electrode, and a second electrode. The gate of the first transistor is connected to a first control node of the signal processing unit, the first electrode is connected to a clock node, and the second electrode is connected to an output node that outputs the sensing signal. The second transistor includes a gate, a first electrode, and a second electrode. The gate of the second transistor is connected to a second control node of the signal processing unit. The first electrode of the second transistor is connected to the output node, and the second electrode is connected to a voltage node. During the display mode, a clock that switches between on-state and off-state voltages is input to the clock node, a low-potential reference voltage is applied to the voltage node, and during the sensing mode, the on-state voltage is applied to each of the clock node and the voltage node.

11. A display device, comprising: Multiple pixels, which are connected to a power line, to which a pixel driving voltage is supplied. Multiple data lines extend along a first direction and are connected to the multiple pixels, the multiple data lines applying multiple data voltages of pixel data of the image to the multiple pixels; Multiple gate lines are connected to the plurality of pixels and extend along a second direction intersecting the first direction, the multiple gate lines applying gate signals to the plurality of pixels; A data driver configured to supply the plurality of data voltages of the image to the plurality of data lines during a display mode, and to supply sensing data to the plurality of data lines during a sensing mode; A gate driver configured to supply the gate signal to the plurality of gate lines; as well as A sensing circuit configured to sense current flowing through a power line connected to a subset of pixels from the plurality of pixels during the sensing mode, the subset of pixels being arranged in multiple columns along the first direction, and at least one light-emitting element included in the pixels of each subset of pixels being configured to receive the sensing data without emitting light during the sensing mode.

12. The display device according to claim 11, wherein, The plurality of pixels are divided into multiple columns of pixel blocks extending along the first direction, and each pixel block includes a different subset of pixels from the plurality of pixels.

13. The display device according to claim 12, wherein, The subset of pixels is included in a pixel block from a currently being sensed column of pixels, and the sensed data including white data is provided to the pixels included in the column of pixels, and black data is provided to the pixels included in the remaining columns of pixels from the multiple columns of pixels that are not currently being sensed during the sense mode.

14. The display device according to claim 13, wherein, During the sensing mode, the sensing circuit sequentially senses each pixel block included in the column of pixel blocks currently being sensed, such that each subset of pixels included in each pixel block is supplied with the white data and sensed based on the sensing current flowing through the power line according to the white data.

15. The display device according to claim 14, wherein, Each of the plurality of pixels includes: A driving element includes a first electrode, a gate, and a second electrode, wherein the first electrode is connected to a first node, the gate is connected to a second node, and the second electrode is connected to a third node. A first switching element, comprising a first electrode, a gate, and a second electrode, wherein the first electrode is connected to the power line, the pixel driving voltage is applied to the power line, the light emission control signal is applied to the gate, and the second electrode is connected to the first node. A light-emitting element, comprising an anode and a cathode, wherein the anode is connected to the third node and a low-level power supply voltage is applied to the cathode; A capacitor, the capacitor being located between the second node and the third node; and A second switching element, comprising a first electrode, a gate, and a second electrode, wherein the first electrode is connected to a data line, a data voltage from the plurality of data voltages is applied to the data line, a scan signal is applied to the gate, and the second electrode is connected to the second node; and The third switching element includes a first electrode, a gate, and a second electrode. The first electrode is connected to the third node, a sensing signal is applied to the gate, and the second electrode is connected to a second power line of the plurality of power lines. A reference voltage is applied to the second power line.

16. The display device according to claim 15, wherein, During the sensing mode, in response to an on level, the light emission control signal is applied to the gate of each first switching element, turning on each first switching element included in each pixel of the target pixel block of the currently being sensed column of pixels, and in response to an off level, the light emission control signal is applied to the gate of each first switching element, turning off each first switching element included in the remaining pixel blocks of the currently being sensed column of pixels.

17. The display device according to claim 16, wherein, During the sensing mode, in response to the turn-on level, the light emission control signal is applied to the gate of each of the first switching elements, and each of the first switching elements included in each pixel of the remaining pixel block, which is supplied with the black data, is turned on because it is not currently being sensed.

18. A sensing circuit, comprising: Resistor; as well as A switch is configured to connect the resistor in series with a power line during a sensing period and to disconnect the resistor from the power line during a display period in which an image is displayed via the display panel, the power line supplying pixel driving voltage to a plurality of pixels of the display panel divided into multiple columns of pixel blocks. The sensing circuit is configured to, during the sensing period, in response to sensing data applied to a subset of pixels during the sensing mode, sequentially sense each pixel block included in a column of pixels by measuring the current flowing through a power line connected to a subset of pixels included in the target pixel block of the column.

19. The sensing circuit according to claim 18, further comprising: An analog-to-digital converter (ADC) connected in parallel with the resistor is configured to convert the voltage difference across the resistor into a digital value during the sensing mode in response to current flowing through the power line.

20. The sensing circuit according to claim 19, wherein, The pixel data of the image is adjusted by a compensation value based on the digital value.

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