Display device

Abstract

A display device according to an exemplary embodiment of the present disclosure includes: a display panel having a plurality of pixels, each of the plurality of pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel with different colors; a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines; and a gate driver configured to supply a gate signal to the plurality of pixels via a plurality of gate lines; wherein the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are sequentially arranged in the same column, thereby enabling an increase in the charging rate of the data voltage.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit and priority of Korean Patent Application No. 10-2021-0194484, filed with the Korean Intellectual Property Office on December 31, 2021. Technical Field

[0003] This disclosure relates to a display device, and more particularly to a display device capable of being driven at a high driving frequency. Background Technology

[0004] Display devices used in computer monitors, televisions, and mobile phones include organic light-emitting displays (OLEDs) that emit their own light, and liquid crystal displays (LCDs) that require a separate light source.

[0005] Among these various display devices, organic light-emitting display devices include a display panel and a driver for driving the display panel, the display panel comprising a plurality of sub-pixels. The driver includes a gate driver supplying gate signals to the display panel and a data driver supplying data voltages. When signals such as gate signals and data voltages are supplied to the sub-pixels of the organic light-emitting display device, selected sub-pixels emit light to display an image.

[0006] Recently, as display panels have become larger, Double Rate Driving (DRD) has been adopted. In DRD, the driving frequency is increased to drive the display panel smoothly. When the driving frequency is increased in this way, the time available for charging the data voltage of the sub-pixels is rapidly reduced. Therefore, there is a defect where data cannot be fully charged into the sub-pixels. Summary of the Invention

[0007] One object of this disclosure is to provide a display device including a sensing transistor for sensing characteristic values ​​of sub-pixels.

[0008] Another object of this disclosure is to provide a display device that allows for improved sensing speed.

[0009] The purpose of this disclosure is not limited to the above-mentioned purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0010] A display device according to an exemplary embodiment of the present disclosure includes: a display panel having a plurality of pixels, each of the plurality of pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel with different colors; a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines; and a gate driver configured to supply a gate signal to the plurality of pixels via a plurality of gate lines; wherein the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are sequentially arranged in the same column, thereby enabling an increase in the charging rate of the data voltage.

[0011] Further detailed topics of exemplary embodiments are included in the detailed description and accompanying drawings.

[0012] According to this disclosure, the light-emitting area can be designed to be enlarged, thereby increasing the aperture ratio of the display device.

[0013] According to this disclosure, the charging rate of the data signal can be improved by reducing the RC delay of the data signal.

[0014] According to this disclosure, even in a specific mode, the charging rate control of the data signal can be kept constant.

[0015] The effects of this disclosure are not limited to those illustrated above, and this specification includes many more effects. Attached Figure Description

[0016] The above and other objects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 This is a schematic diagram of a display device according to an example of the present disclosure.

[0018] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an example of this disclosure.

[0019] Figure 3 This is a block diagram illustrating the disposition relationship of subpixels in a display device according to an example of this disclosure.

[0020] Figure 4 This is a waveform diagram showing the data voltage of a display device according to an example of this disclosure.

[0021] Figure 5A This is a view used to explain the driving order in odd-numbered frames of a display device according to an example of this disclosure.

[0022] Figure 5B This is a view used to explain the driving order in even-numbered frames of a display device according to an example of this disclosure.

[0023] Figure 6 This is a view used to explain the charging rate of the data voltage of a display device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0024] Through reference and appendix Figure 1 The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but may be implemented in various different forms. The exemplary embodiments are provided merely as examples to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be defined by the appended claims.

[0025] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Similar reference numerals generally refer to similar elements throughout the specification. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0026] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0027] When using terms such as “on top of,” “above,” “below,” and “next” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “adjacent” or “direct.”

[0028] When an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer, or there can be an intervening element or layer.

[0029] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from others. Therefore, in the technical concept of this disclosure, the first component mentioned below can be the second component.

[0030] Throughout the specification, the same reference numerals denote the same elements.

[0031] Since the dimensions and thicknesses of each component shown in the accompanying drawings are for ease of interpretation, this disclosure is not necessarily limited to the dimensions and thicknesses of each component shown.

[0032] The features of the various embodiments of this disclosure may be partially or completely coupled or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently or in association with each other.

[0033] The transistor used in the display device of this disclosure can be implemented using at least one of an n-channel transistor (NMOS) and a p-channel transistor (PMOS). The transistor can be implemented using an oxide semiconductor transistor with an oxide semiconductor as the active layer or an LTPS transistor with a low-temperature polycrystalline silicon (LTPS) active layer. The transistor can include at least a gate electrode, a source electrode, and a drain electrode. The transistor can be implemented as a thin-film transistor on a display panel. In the transistor, charge carriers flow from the source electrode to the drain electrode. In the case of an n-channel transistor (NMOS), since the charge carriers are electrons, the source voltage can be lower than the drain voltage, allowing electrons to flow from the source electrode to the drain electrode. In an n-channel transistor (NMOS), current can flow from the drain electrode to the source electrode, and the source electrode can be an output terminal. In the case of a p-channel transistor (PMOS), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source electrode to the drain electrode. In a p-channel transistor (PMOS), current flows from the source electrode to the drain electrode because holes flow from the source electrode to the drain electrode, and the drain electrode can be the output terminal. Therefore, since the source and drain electrodes can be changed according to the applied voltage, it should be noted that the source and drain electrodes of the transistor are not fixed. In this specification, it is assumed that the transistor is an n-channel transistor (NMOS), but this disclosure is not limited thereto; p-channel transistors can also be used, and therefore the circuit configuration can be changed.

[0034] The gate signal of a transistor used as a switching element switches between a gate on-state voltage and a gate off-state voltage. The gate on-state voltage is set above the transistor's threshold voltage Vth, and the gate off-state voltage is set below the transistor's threshold voltage Vth. The transistor turns on in response to the gate on-state voltage and turns off in response to the gate off-state voltage. In the case of NMOS, the gate on-state voltage can be a high gate voltage VGH, and the gate off-state voltage can be a low gate voltage VGL. In the case of PMOS, the gate on-state voltage can be a low gate voltage VGL, and the gate off-state voltage can be a high gate voltage VGH.

[0035] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings.

[0036] Figure 1This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Reference Figure 1 The display device 100 includes a display panel 110, a gate driver 120, a data driver 130, and a timing controller 140.

[0037] Display panel 110 is a panel for displaying images. Display panel 110 may include various circuits, lines, and light-emitting elements disposed on a substrate. Display panel 110 is divided by multiple intersecting data lines DL and multiple gate lines GL, and may include multiple pixels PX connected to the multiple data lines DL and multiple gate lines GL. Display panel 110 may include an active region defined by the multiple pixels PX and a passive region in which various signal lines, pads, etc., are formed. Display panel 110 can be implemented as a display panel 110 used in various display devices such as liquid crystal display devices, organic light-emitting display devices, or electrophoretic display devices. Hereinafter, display panel 110 will be described as a panel for use in an organic light-emitting display device, but this disclosure is not limited thereto.

[0038] The timing controller 140 receives timing signals such as vertical synchronization signals, horizontal synchronization signals, data enable signals, and dot clock signals through a receiver circuit connected to the host system, such as an LVDS or TMDS interface. The timing controller 140 generates timing control signals for controlling the data driver 130 and the gate driver 120 based on the input timing signals.

[0039] Data driver 130 supplies data voltage DATA to multiple sub-pixels SP. Data driver 130 may include multiple source driver integrated circuits (ICs). The multiple source driver ICs can receive digital video data and source timing control signals from timing controller 140. The multiple source driver ICs can generate data voltage VDATA by converting digital video data into gamma voltage in response to the source timing control signals, and supply data voltage VDATA through data lines DL of display panel 110. The multiple source driver ICs can be connected to data lines DL of display panel 110 through chip-on-glass (COG) process or tape-on-bonding (TAB) process. In addition, the source driver ICs can be formed on display panel 110, or formed on a separate PCB substrate and connected to display panel 110.

[0040] Gate driver 120 supplies gate signals to a plurality of sub-pixels SP. Gate driver 120 may include a level shifter and a shift register. The level shifter may shift the level of a clock signal input from timing controller 140 as a transistor-transistor-logic unit (TTL) level input and subsequently supply it to the shift register. The shift register may be formed in a passive region of display panel 110 in a GIP manner, but this disclosure is not limited thereto. The shift register may be constructed of multiple levels that shift and output the gate signal in response to clock and drive signals. The multiple levels included in the shift register may sequentially output gate signals through multiple output terminals.

[0041] The display panel 110 may include a plurality of subpixels SP. The plurality of subpixels SP may be subpixels SP used to emit light of different colors. For example, each of the plurality of subpixels SP may be a red subpixel, a green subpixel, a blue subpixel, and a white subpixel, but this disclosure is not limited thereto. The plurality of subpixels SP may constitute a pixel PX. That is, a red subpixel, a green subpixel, a blue subpixel, and a white subpixel may constitute a pixel PX, and the display panel 110 may include a plurality of pixel PXs.

[0042] Let's refer to the following: Figure 2 In order to describe in more detail the driving circuitry used to drive a sub-pixel SP.

[0043] Figure 2 This is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 2 This is a circuit diagram of one of the multiple sub-pixels SP in the display device 100.

[0044] refer to Figure 2 The sub-pixel SP may include a switching transistor SWT, a sensing transistor SET, a driving transistor DT, a storage capacitor SC, and a light-emitting element 150.

[0045] The light-emitting element 150 may include an anode, an organic layer, and a cathode. The organic layer may include various organic layers, such as a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer. The anode of the light-emitting element 150 can be connected to the output terminal of the driving transistor DT, and a low-potential voltage VSS can be applied to the cathode. Although in Figure 2 The light-emitting element 150 is described as an organic light-emitting element 150, but this disclosure is not limited thereto, and inorganic light-emitting diodes, i.e., LEDs, can also be used as light-emitting elements 150.

[0046] refer to Figure 2The switching transistor SWT is a transistor used to transfer the data voltage DATA to the first node N1 corresponding to the gate electrode of the driving transistor DT. The switching transistor SWT may include a drain electrode connected to the data line DL, a gate electrode connected to the gate line GL, and a source electrode connected to the gate electrode of the driving transistor DT. The switching transistor SWT is turned on by a scan signal SCAN applied from the gate line GL and can transfer the data voltage DATA supplied from the data line DL to the first node N1 corresponding to the gate electrode of the driving transistor DT.

[0047] refer to Figure 2 The driving transistor DT is a transistor used to drive the light-emitting element 150 by configuring it to supply driving current to the light-emitting element 150. The driving transistor DT may include a gate electrode corresponding to a first node N1, a source electrode corresponding to a second node N2 and an output terminal, and a drain electrode corresponding to a third node N3 and an input terminal. The gate electrode of the driving transistor DT may be connected to the switching transistor SWT, the drain electrode of the driving transistor DT may receive a high-potential voltage VDD through a high-potential voltage line VDDL, and the source electrode of the driving transistor DT may be connected to the anode of the light-emitting element 150.

[0048] refer to Figure 2 The storage capacitor SC is a capacitor used to maintain a voltage corresponding to the data voltage DATA within a frame. One electrode of the storage capacitor SC can be connected to the first node N1, and the other electrode of the storage capacitor SC can be connected to the second node N2.

[0049] Meanwhile, in the case of display device 100, as the driving time of each sub-pixel SP increases, circuit elements such as driving transistor DT degrade. Therefore, the unique characteristic values ​​of circuit elements such as driving transistor DT can be changed. Here, the unique characteristic values ​​of circuit elements may include the threshold voltage Vth of driving transistor DT, the mobility α of driving transistor DT, etc. Changes in the characteristic values ​​of circuit elements cause changes in the brightness of the corresponding sub-pixel SP. Therefore, changes in the characteristic values ​​of circuit elements can be used as the same concept as changes in the brightness of sub-pixel SP.

[0050] Furthermore, the degree of variation in the characteristic values ​​of the circuit elements within each sub-pixel SP can differ due to variations in the degree of degradation of the corresponding circuit elements. These differences in the degree of variation in characteristic values ​​between circuit elements lead to brightness deviations between sub-pixel SPs. Therefore, the characteristic value deviation between circuit elements can be used as the same concept as the brightness deviation between sub-pixel SPs. Variations in the characteristic values ​​of circuit elements (i.e., brightness variations in sub-pixel SPs) and characteristic value deviations between circuit elements (i.e., brightness deviations between sub-pixel SPs) reduce the accuracy of the brightness representation of sub-pixel SPs or cause defects such as screen anomalies.

[0051] Therefore, in the sub-pixel SP of the display device 100 according to an exemplary embodiment of the present disclosure, a sensing function for sensing the characteristic value of the sub-pixel SP and a compensation function for compensating the characteristic value of the sub-pixel SP using the sensing result can be provided.

[0052] Therefore, as Figure 2 As shown, in addition to the switching transistor SWT, driving transistor DT, storage capacitor SC, and light-emitting element 150, the sub-pixel SP may further include a sensing transistor SET for effectively controlling the voltage state of the source electrode of the driving transistor DT.

[0053] refer to Figure 2 The sensing transistor SET is connected between the source electrode of the driving transistor DT and the reference voltage line RVL, which is configured to supply a reference voltage Vref, and the gate electrode of the sensing transistor SET is connected to the gate line GL. Therefore, the sensing transistor SET is turned on by the sensing signal SENSE applied through the gate line GL, and the reference voltage Vref supplied through the reference voltage line RVL can be applied to the source electrode of the driving transistor DT. Furthermore, the sensing transistor SET can be used as one of the voltage sensing paths for the source electrode of the driving transistor DT.

[0054] refer to Figure 2 The switching transistor SWT and sensing transistor SET of a sub-pixel SP can share a single gate line GL. That is, the switching transistor SWT and the sensing transistor SET can be applied to the same gate line GL to receive the same gate signal. However, for ease of explanation, the voltage applied to the gate electrode of the switching transistor SWT is called the scan signal SCAN, and the voltage applied to the gate electrode of the sensing transistor SET is called the sensing signal SENSE. However, the scan signal SCAN and the sensing signal SENSE applied to a sub-pixel SP are the same signal transmitted from the same gate line GL. Therefore, in Figure 3 In this context, the scan signal SCAN and the sensing signal SENSE will be defined and described as gate signals GATE1, GATE2, GATE3, and GATE4.

[0055] However, this disclosure is not limited thereto, and only the switching transistor SWT can be connected to the gate line GL, while the sensing transistor SET can be connected to a separate sensing line. Accordingly, the scan signal SCAN can be applied to the switching transistor SWT through the gate line GL, and the sensing signal SENSE can be applied to the sensing transistor SET through the sensing line.

[0056] Therefore, the reference voltage Vref is applied to the source electrode of the driving transistor DT through the sensing transistor SET. The threshold voltage Vth or the mobility α of the driving transistor DT is detected through the reference voltage line RVL. Furthermore, the data driver 130 can compensate for the data voltage DATA based on the detected change in the threshold voltage Vth or the mobility α of the driving transistor DT.

[0057] Let's refer to the following: Figure 3 In order to describe the configuration relationship of multiple sub-pixels in more detail.

[0058] Figure 3 This is a block diagram illustrating the configuration (positioning) of sub-pixels of a display device according to an exemplary embodiment of the present disclosure.

[0059] For ease of explanation, Figure 3 Only four pixels are shown in a 2x2 matrix, and the configuration of these four pixels in a 2x2 matrix is ​​repeated in the active region.

[0060] refer to Figure 3 A pixel PX consists of four sub-pixels: R, G, B, and W. For example, as... Figure 3 As shown, pixel PX may include a first sub-pixel G, a second sub-pixel R, a third sub-pixel W, and a fourth sub-pixel B. Furthermore, the first sub-pixel G may be a green sub-pixel, the second sub-pixel R may be a red sub-pixel, the third sub-pixel W may be a white sub-pixel, and the fourth sub-pixel B may be a blue sub-pixel. However, this disclosure is not limited to this, and the multiple sub-pixels can be varied to have various colors (magenta, yellow, and cyan).

[0061] In addition, the first sub-pixel G, the second sub-pixel R, the third sub-pixel W, and the fourth sub-pixel B can be set in the same column in sequence.

[0062] Specifically, the first pixel PX1, located in the odd-numbered columns, has a first sub-pixel G, a second sub-pixel R, a third sub-pixel W, and a fourth sub-pixel B in that order. Conversely, the second pixel PX2, located in the even-numbered columns, has a fourth sub-pixel B, a third sub-pixel W, a second sub-pixel R, and a first sub-pixel G in that order. In other words, the sub-pixels R, G, B, and W of the first pixel PX1 and the second pixel PX2 have a vertically inverted symmetry about the high-potential voltage line VDDL. However, the arrangement order of the sub-pixels R, G, B, and W in each of the first pixel PX1 and the second pixel PX2 is not limited to this.

[0063] More specifically, such as Figure 3 As shown, in odd-numbered columns, the first sub-pixel G is located in rows 8k-7 and 8k-3, while in even-numbered columns, it is located in rows 8k-4 and 8k. Similarly, in odd-numbered columns, the second sub-pixel R is located in rows 8k-6 and 8k-2, while in even-numbered columns, it is located in rows 8k-5 and 8k-1. Likewise, in odd-numbered columns, the third sub-pixel W is located in rows 8k-5 and 8k-1, while in even-numbered columns, it is located in rows 8k-6 and 8k-2. Finally, in odd-numbered columns, the fourth sub-pixel B is located in rows 8k-4 and 8k, while in even-numbered columns, it is located in rows 8k-7 and 8k-3. However, k represents a natural number greater than or equal to 1.

[0064] In addition, the first sub-pixel G may include a first light-emitting element GE and a first circuit element GC, the second sub-pixel R may include a second light-emitting element RE and a second circuit element RC, the third sub-pixel W may include a third light-emitting element WE and a third circuit element WC, and the fourth sub-pixel B may include a fourth light-emitting element BE and a fourth circuit element BC.

[0065] Furthermore, the first circuit element GC, the second circuit element RC, the third circuit element WC, and the fourth circuit element BC are arranged diagonally relative to data lines DL1, DL2, DL3, and DL4. In other words, the first to fourth circuit elements are arranged diagonally between DL1 and DL4 or between DL3 and DL2. Additionally, the first to fourth circuit elements can be arranged diagonally (zigzag-shaped) within the same pixel. Furthermore, the first light-emitting element GE, the second light-emitting element RE, the third light-emitting element WE, and the fourth light-emitting element BE are also arranged diagonally relative to data lines DL1, DL2, DL3, and DL4. In other words, the first to fourth light-emitting elements are arranged diagonally between DL4 and DL1 or between DL2 and DL3. Additionally, the first to fourth light-emitting elements can be arranged diagonally (zigzag-shaped) within the same pixel. The first to fourth light-emitting elements and the first to fourth circuit elements can be arranged in a reverse zigzag pattern relative to each other with respect to the reference voltage line RVL. The arrangement of the first to fourth circuit elements and the first to fourth light-emitting elements in the odd-numbered columns can be positioned by rotating them 180 degrees relative to the arrangement of the first to fourth circuit elements and the first to fourth light-emitting elements in the even-numbered columns, and vice versa.

[0066] In other words, the first circuit element GC, the second circuit element RC, the third circuit element WC, and the fourth circuit element BC are arranged only based on each of the first light-emitting element GE, the second light-emitting element RE, the third light-emitting element WE, and the fourth light-emitting element BE in both the vertical and horizontal directions, but the first light-emitting element GE, the second light-emitting element RE, the third light-emitting element WE, and the fourth light-emitting element BE are not arranged adjacent to each other in either the vertical or horizontal direction.

[0067] Furthermore, each of the multiple data lines DL1, DL2, DL3, and DL4 includes a first data line DL1 connected to multiple first sub-pixels G, a second data line DL2 connected to multiple second sub-pixels R, a third data line DL3 connected to multiple third sub-pixels W, and a fourth data line DL4 connected to a fourth sub-pixel B. Additionally, the first data lines DL1 and DL3 can be positioned on one side of the multiple pixels, while the second data lines DL2 and DL4 can be positioned on the other side of the multiple pixels.

[0068] For multiple first pixels PX1, the first data line DL1 and the third data line DL3 can be set to the right of multiple sub-pixels R, G, B and W, and can be connected to each of the multiple first sub-pixels G and the multiple third sub-pixels W respectively.

[0069] Furthermore, for multiple first pixels PX1, the second data line DL2 and the fourth data line DL4 can be positioned to the left of multiple sub-pixels R, G, B and W, and can be connected to each of the multiple second sub-pixels R and the multiple fourth sub-pixels B, respectively.

[0070] Conversely, for multiple second pixels PX2, the second data line DL2 and the fourth data line DL4 can be positioned to the right of multiple sub-pixels R, G, B and W, and can be connected to each of the multiple second sub-pixels R and the multiple fourth sub-pixels B, respectively.

[0071] Furthermore, for multiple second pixels PX2, the first data line DL1 and the third data line DL3 can be set to the left of multiple sub-pixels R, G, B and W, and can be connected to each of the multiple first sub-pixels G and the multiple third sub-pixels W respectively.

[0072] Meanwhile, multiple data lines DL1, DL2, DL3 and DL4 extending to multiple circuit elements GC, RC, WC and BC can be set up adjacent to multiple circuit elements GC, RC, WC and BC to connect to multiple circuit elements GC, RC, WC and BC.

[0073] In other words, the first circuit element GC and the third circuit element WC can be set near the first data line DL1 and the third data line DL3, instead of near the second data line DL2 and the fourth data line DL4, and the second circuit element RC and the fourth circuit element BC can be set near the second data line DL2 and the fourth data line DL4, instead of near the first data line DL1 and the third data line DL3.

[0074] Furthermore, a first data voltage DATA1, which is a green data voltage, can be applied to the first data line DL1, and a second data voltage DATA2, which is a red data voltage, can be applied to the second data line DL2. A third data voltage DATA3, which is a white data voltage, can be applied to the third data line DL3, and a fourth data voltage DATA4, which is a blue data voltage, can be applied to the fourth data line DL4.

[0075] In addition, each of the multiple high-potential voltage lines VDDL can be positioned between adjacent data lines in data lines DL1, DL2, DL3, and DL4.

[0076] In other words, the high-potential voltage line VDDL can be set between the first data line DL1 and the third data line DL3, and the high-potential voltage line VDDL can be set between the second data line DL2 and the fourth data line DL4.

[0077] In other words, a high-potential voltage line VDDL is positioned between multiple first pixels PX1 and multiple second pixels PX2. Therefore, one of the first data lines DL1 to the fourth data line DL4 can cross the high-potential voltage line VDDL. For example, in... Figure 3 In the middle, the third data line DL3 crosses the high-potential voltage line VDDL to connect to the third sub-pixel W.

[0078] Each of the multiple gate lines GL1 to GL4 can be disposed within multiple pixels PX1 and PX2. That is, the multiple gate lines GL1 to GL4 can be disposed between the first sub-pixel G and the second sub-pixel R or between the third sub-pixel W and the fourth sub-pixel B.

[0079] Specifically, odd-numbered gate lines GL1 and GL3 are positioned between the first sub-pixel G and the second sub-pixel R in the odd-numbered column, and can be positioned between the third sub-pixel W and the fourth sub-pixel B in the even-numbered column.

[0080] In other words, for a pixel PX1 or PX2, an odd-numbered gate line GL1 or GL3 can be disposed between multiple sub-pixels R, W, G, and B. For example, the first gate line GL1 is disposed between the first sub-pixel G of the first pixel PX1 and the fourth sub-pixel B of the second pixel PX2 in row 8k-7, and between the second sub-pixel R of the first pixel PX1 and the third sub-pixel W of the second pixel PX2 in row 8k-6, and is connected to the first sub-pixel G and the second sub-pixel R of the first pixel PX1 and the third sub-pixel W and the fourth sub-pixel B of the second pixel PX2.

[0081] Even-numbered gate lines GL2 and GL4 can be positioned between the third sub-pixel W and the fourth sub-pixel B in the odd-numbered column, and can be positioned between the first sub-pixel G and the second sub-pixel R in the even-numbered column.

[0082] In other words, for a pixel PX1 or PX2, an even-numbered gate line GL2 or GL4 can be disposed between multiple sub-pixels R, W, G, and B. For example, the second gate line GL2 can be disposed between the second sub-pixel R of the second pixel PX2 disposed in row 8k-5 and the third sub-pixel W of the first pixel PX1, and between the first sub-pixel G of the second pixel PX2 disposed in row 8k-4 and the fourth sub-pixel B of the first pixel PX1, and is connected to the third sub-pixel W and the fourth sub-pixel B of the first pixel PX1 and the first sub-pixel G and the second sub-pixel R of the second pixel PX2.

[0083] Furthermore, each of the multiple reference voltage lines RVL can be set within each of the multiple sub-pixels R, G, B, and W.

[0084] Specifically, each of the multiple reference voltage lines RVL is positioned between the first light-emitting element GE and the first circuit element GC, between the second light-emitting element RE and the second circuit element RC, between the third light-emitting element WE and the third circuit element WC, and between the fourth light-emitting element BE and the fourth circuit element BC.

[0085] One of the multiple reference voltage lines RVL is connected to multiple sub-pixels R, G, B and W arranged in odd-numbered columns, and another of the multiple reference voltage lines RVL is connected to multiple sub-pixels R, G, B and W arranged in even-numbered columns.

[0086] Furthermore, the first circuit element GC and the third circuit element WC can be configured in reverse order with respect to each of the multiple reference voltage lines RVL, as opposed to the second circuit element RC and the fourth circuit element BC.

[0087] As described above, in the display device according to an exemplary embodiment of the present disclosure, multiple data lines DL1 and DL3 disposed between multiple first pixels PX1 and multiple second pixels PX2 can be connected to multiple sub-pixels G and W disposed on both sides thereof, and data voltages DATA1 and DATA3 are applied to the multiple sub-pixels G and W.

[0088] In traditional display devices, multiple data lines are connected to multiple sub-pixels located on one side of the device, thus requiring as many data lines as there are columns of sub-pixels.

[0089] However, in the display device according to an exemplary embodiment of the present disclosure, multiple data lines DL1, DL2, DL3 and DL4 are connected to multiple sub-pixels R, G, B and W disposed on both sides thereon, so only half the number of columns of sub-pixels R, G, B and W of data lines DL1, DL2, DL3 and DL4 are required.

[0090] Therefore, as the area occupied by the data lines in the display panel decreases, the light-emitting area can be designed to be larger, thereby increasing the aperture ratio of the display device. For example, the area occupied by the light-emitting area in the first sub-pixel G can be 29.4%, the area occupied by the light-emitting area in the second sub-pixel R can be 48.2%, the area occupied by the light-emitting area in the third sub-pixel W can be 54.8%, and the area occupied by the light-emitting area in the fourth sub-pixel B can be 32.8%. Thus, the average aperture ratio can be extended to 41.3%.

[0091] Figure 4 This is a waveform diagram showing the data voltage of a display device according to an exemplary embodiment of the present disclosure.

[0092] In the display device according to an exemplary embodiment of the present disclosure, since the number of data lines is reduced as described above, the total resistance of the data lines is reduced, thereby reducing the RC delay of the data signal. Therefore, the charging rate of the data signal can be increased.

[0093] Specifically, refer to Figure 4 In a conventional display device, the data voltage is charged from 0.65V at time t0. Subsequently, at time t1, the data voltage is charged to 7.4241V, and then at time t2, the data voltage is charged to 8.2031V.

[0094] On the other hand, in the display device according to an exemplary embodiment of the present disclosure, at time t0, the data voltage is charged from 0.65V. Subsequently, at time t1, the data voltage is charged to 8.2102V, and thereafter, at time t2, the data voltage is charged to 8.83V.

[0095] In other words, at time t1, compared to the data charging rate of a conventional display device, the data charging rate of the display device according to the exemplary embodiment of the present disclosure can be increased by 9.57%. Furthermore, at time t2, compared to the data charging rate of a conventional display device, the data charging rate of the display device according to the exemplary embodiment of the present disclosure can be increased by 7.09%. That is, the data charging rate of the display device according to the exemplary embodiment of the present disclosure can be improved.

[0096] Below, we will refer to Figure 5A , Figure 5B and Figure 6 A driving method for a display device according to an exemplary embodiment of the present disclosure is described.

[0097] Figure 5A This is a view used to explain the driving order in odd-numbered frames of a display device according to exemplary embodiments of the present disclosure.

[0098] Figure 5B This is a view used to explain the driving order in even-numbered frames of a display device according to exemplary embodiments of the present disclosure.

[0099] Figure 6 This is a view used to explain the charging rate of the data voltage of a display device according to an exemplary embodiment of the present disclosure.

[0100] Although for the sake of explanation, Figure 5A and Figure 5B The data lines, reference voltage lines, and high-potential voltage lines arranged vertically are not shown, but their configuration is similar to... Figure 3 The configuration relationships described in the text are the same.

[0101] And, as Figure 5A and Figure 5B The image illustrates a horizontal stripe pattern, where multiple sub-pixels R, G, B, and W located in rows 8k-7 to 8k-4 emit light, while multiple sub-pixels R, G, B, and W located in rows 8k-3 to 8k do not emit light (indicated by black shading).

[0102] The data charging rates of multiple third sub-pixels W will be described in detail below, but the data charging rates of multiple first sub-pixels G, multiple second sub-pixels R, and multiple fourth sub-pixels B can also be described in the same way as the data charging rates of multiple third sub-pixels W.

[0103] like Figure 6 As shown, when displaying a horizontal stripe pattern, the charging rate of the third data voltage DATA3 can increase during the first horizontal period ① and the second horizontal period ②, and the charging rate of the third data voltage DATA3 can decrease during the third horizontal period ③ and the fourth horizontal period ④. The above-described charging rate waveform of the third data voltage DATA3 can be repeated.

[0104] exist Figure 5A and Figure 5B In this context, the turn-on sequence of multiple gate lines GL1, GL2, GL3, and GL4 in odd-numbered frames can differ from the turn-on sequence of multiple gate lines GL1, GL2, GL3, and GL4 in even-numbered frames. The turn-on sequence of multiple gate lines can be predefined.

[0105] Specifically, in odd-numbered frames, the first gate line GL1, the second gate line GL2, the fourth gate line GL4, and the third gate line GL3 are turned on sequentially, while in even-numbered frames, the second gate line GL2, the first gate line GL1, the third gate line GL3, and the fourth gate line GL4 are turned on sequentially.

[0106] However, the turn-on sequence of multiple gate lines GL1, GL2, GL3, and GL4 in odd-numbered frames and the turn-on sequence of multiple gate lines GL1, GL2, GL3, and GL4 in even-numbered frames can be changed.

[0107] For example, refer to Figure 5A During odd-numbered frames, in the first horizontal period ①, the first gate voltage GATE1, which is at the on level, is applied to the first gate line GL1, so that the third sub-pixel W located in the 8k-6th row is charged using the data voltage.

[0108] Subsequently, during odd-numbered frames, in the second horizontal period ②, the second gate voltage GATE2, which is at the on level, is applied to the second gate line GL2, so that the third sub-pixel W located in the 8k-5 row is charged using the data voltage.

[0109] Subsequently, during odd-numbered frames, in the third horizontal period ③, the fourth gate voltage GATE4, which is at the on level, is applied to the fourth gate line GL4, causing the data voltage charged into the third sub-pixel W located in the 8k-1 row to be discharged (released).

[0110] Subsequently, during odd-numbered frames, in the fourth horizontal period ④, the third gate voltage GATE3, which is at the on level, is applied to the third gate line GL3, causing the data voltage charged into the third sub-pixel W located in the 8k-2 row to be discharged.

[0111] Furthermore, refer to Figure 5B During even-numbered frames, in the first horizontal period ①, the second gate voltage GATE2, which is at the on level, is applied to the second gate line GL2, so that the third sub-pixel W located in the 8k-5 row is charged using the data voltage.

[0112] Subsequently, during even-numbered frames, in the second horizontal period ②, the first gate voltage GATE1, which is at the on level, is applied to the first gate line GL1, so that the third sub-pixel W located in the 8k-6th row is charged using the data voltage.

[0113] Subsequently, during even-numbered frames, in the third horizontal period ③, the third gate voltage GATE3, which is at the on level, is applied to the third gate line GL3, causing the data voltage charged into the third sub-pixel W located in the 8k-2 row to be discharged.

[0114] Subsequently, during even-numbered frames, in the fourth horizontal period ④, the fourth gate voltage GATE4, which is at the on level, is applied to the fourth gate line GL4, causing the data voltage charged into the third sub-pixel W located in the 8k-1 row to be discharged.

[0115] When the horizontal stripe pattern is implemented as described above, the data charging rate of the multiple third sub-pixels W will be referenced. Figure 6 The description is as follows.

[0116] During odd-numbered frames, in the first horizontal period ① when charging of the data voltage begins, the data charging rate of the third sub-pixel W in row 8k-6 can be 70% (weak charging).

[0117] Furthermore, during odd-numbered frames, in the second horizontal cycle ② of completing the charging of the data voltage, the charging rate of the third sub-pixel W set in row 8k-5 can be 100% (strong charging).

[0118] Furthermore, during odd-numbered frames, in the third level period ③ and the fourth level period ④ during which the data voltage is discharged, the charging rate of the third sub-pixel W set in row 8k-2 and the third sub-pixel W set in row 8k-1 can be 0%.

[0119] During even-numbered frames, in the first horizontal period ① when charging of the data voltage begins, the data charging rate of the third sub-pixel W in row 8k-5 can be 70% (weak charging).

[0120] Furthermore, during even-numbered frames, in the second horizontal cycle ② after the data voltage is fully charged, the charging rate of the third sub-pixel W in row 8k-6 can be 100% (strong charging).

[0121] Furthermore, during even-numbered frames, in the third level period ③ and the fourth level period ④ where the data voltage is discharged, the charging rate of the third sub-pixel W set in row 8k-1 and the third sub-pixel W set in row 8k-2 can be 0%.

[0122] In summary, during odd-numbered frames, the data charge rate of the third sub-pixel W in row 8k-5 is 100% (strong charge), while during even-numbered frames it is 70% (weak charge). Therefore, the average data charge rate of the third sub-pixel W in row 8k-5 can be 85%.

[0123] Furthermore, the data charge rate of the third sub-pixel W in row 8k-6 is 100% (strong charge) during even-numbered frames and 70% (weak charge) during odd-numbered frames. Therefore, the average data charge rate of the third sub-pixel W in row 8k-6 can also be 85%. In the above case, depending on the data line RC delay of the display panel and / or the panel size (inches) and refresh rate (Hz), the charge rate during weak / strong charging can have different values. Depending on the panel, the weak charge rate can be 40%-70%, while the strong charge rate can be 95%-100%.

[0124] Therefore, in a display device according to an exemplary embodiment of the present disclosure, by setting a different gate turn-on sequence for each frame, the average value of the data charge rate of the sub-pixel emitted light in the vertical stripe pattern can be set to be the same.

[0125] Therefore, in the display device according to an exemplary embodiment of the present disclosure, no line defects will occur even in a specific pattern, wherein the specific pattern may be Figures 5A to 5B The horizontal or vertical stripe pattern can be used. Therefore, the image quality of the display device according to the exemplary embodiments of this disclosure can be improved.

[0126] Exemplary embodiments of this disclosure can also be described as follows:

[0127] A display device according to an exemplary embodiment of the present disclosure includes: a display panel having a plurality of pixels, each of the plurality of pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel with different colors; a data driver configured to supply a data voltage to the plurality of pixels via a plurality of data lines; and a gate driver configured to supply a gate signal to the plurality of pixels via a plurality of gate lines; wherein the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are sequentially arranged in the same column, thereby enabling an increase in the charging rate of the data voltage.

[0128] The arrangement of the first, second, third, and fourth sub-pixels in odd-numbered columns can be symmetrical to that in even-numbered columns. The positional relationship of the first, second, third, and fourth sub-pixels in odd-numbered columns can be positioned by rotating them 180 degrees relative to their positions in even-numbered columns, and vice versa.

[0129] The first sub-pixel may include a first light-emitting element and a first circuit element, the second sub-pixel may include a second light-emitting element and a second circuit element, the third sub-pixel may include a third light-emitting element and a third circuit element, and the fourth sub-pixel may include a fourth light-emitting element and a fourth circuit element.

[0130] The display device may further include multiple reference voltage lines configured to sense multiple pixels.

[0131] Each of the multiple reference voltage lines can be positioned between the first light-emitting element and the first circuit element, between the second light-emitting element and the second circuit element, between the third light-emitting element and the third circuit element, and between the fourth light-emitting element and the fourth circuit element.

[0132] For each of the multiple sub-pixels, the first and third circuit elements can be configured in reverse order with respect to each of the multiple reference voltage lines as opposed to the second and fourth circuit elements.

[0133] Each of the multiple data lines may include a first data line connected to multiple first sub-pixels, a second data line connected to multiple second sub-pixels, a third data line connected to multiple third sub-pixels, and a fourth data line connected to a fourth sub-pixel.

[0134] The first and third data lines can be positioned on one side of multiple pixels sequentially arranged in the same column, while the second and fourth data lines can be positioned on the other side of multiple pixels sequentially arranged in the same column.

[0135] The first and third circuit elements may be arranged adjacent to the first and third data lines, rather than adjacent to the second and fourth data lines, and the second and fourth circuit elements may be arranged adjacent to the second and fourth data lines, rather than adjacent to the first and third data lines.

[0136] A high-potential voltage line can be provided between the first data line and the third data line, and a high-potential voltage line can be provided between the second data line and the fourth data line.

[0137] Each of the multiple gate lines can be positioned between the first sub-pixel and the second sub-pixel; or it can be positioned between the third sub-pixel and the fourth sub-pixel.

[0138] Odd-numbered gate lines in a plurality of gate lines can be positioned between the first and second sub-pixels in an odd-numbered column, and can be positioned between the third and fourth sub-pixels in an even-numbered column.

[0139] The even-numbered gate line in the multiple gate lines can be positioned between the third and fourth sub-pixels in the odd-numbered columns, and can be positioned between the first and second sub-pixels in the even-numbered columns.

[0140] The turn-on sequence of multiple gate lines in even-numbered frames may differ from the turn-on sequence of multiple gate lines in odd-numbered frames.

[0141] Multiple gate lines may include a first gate line, a second gate line, a third gate line, and a fourth gate line that can be arranged sequentially.

[0142] In even-numbered frames, the first gate line, the second gate line, the fourth gate line, and the third gate line can be turned on sequentially.

[0143] In odd-numbered frames, the second gate line, the first gate line, the third gate line, and the fourth gate line can be turned on sequentially.

[0144] Each of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel may include a switching transistor, a driving transistor, a storage capacitor, a sensing transistor, and a light-emitting element.

[0145] The sensing transistor outputs the threshold voltage and mobility voltage used to sense the driving transistor to the reference voltage line.

[0146] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the following claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device (100), comprising: The display panel (110) is provided with a plurality of pixels, each of the plurality of pixels including a first sub-pixel (G), a second sub-pixel (R), a third sub-pixel (W) and a fourth sub-pixel (B) with different colors. A data driver (130) configured to supply data voltage to the plurality of pixels via multiple data lines (DL); as well as A gate driver (120) is configured to supply gate signals to the plurality of pixels via a plurality of gate lines (GL); In this configuration, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are sequentially arranged in the same column. The positions of the first sub-pixel (G), second sub-pixel (R), third sub-pixel (W), and fourth sub-pixel (B) in the (n+1)th column are arranged to be rotated 180 degrees relative to the positions of the first sub-pixel (G), second sub-pixel (R), third sub-pixel (W), and fourth sub-pixel (B) in the (n)th column, and are also arranged to be rotated 180 degrees relative to the positions of the first sub-pixel (G), second sub-pixel (R), third sub-pixel (W), and fourth sub-pixel (B) in the (n+2)th column, where n is a positive integer.

2. The display device according to claim 1, characterized in that: The first sub-pixel (G) includes a first light-emitting element (GE) and a first circuit element (GC). The second sub-pixel (R) includes a second light-emitting element (RE) and a second circuit element (RC). The third sub-pixel (W) includes a third light-emitting element (WE) and a third circuit element (WC), and The fourth sub-pixel (B) includes a fourth light-emitting element (BE) and a fourth circuit element (BC).

3. The display device according to claim 2, characterized in that, The display device further includes: Multiple reference voltage lines (RVL) Each of the plurality of reference voltage lines is disposed between the first light-emitting element (GE) and the first circuit element (GC), between the second light-emitting element (RE) and the second circuit element (RC), between the third light-emitting element (WE) and the third circuit element (WC), and between the fourth light-emitting element (BE) and the fourth circuit element (BC).

4. The display device according to claim 2, characterized in that: For each of the plurality of pixels, the first circuit element, the second circuit element, the third circuit element, and the fourth circuit element are arranged in a zigzag pattern within the same pixel, and / or For each of the plurality of pixels, the first light-emitting element, the second light-emitting element, the third light-emitting element, and the fourth light-emitting element are arranged in a zigzag pattern within the same pixel.

5. The display device according to any one of claims 2 to 4, characterized in that: Each of the plurality of data lines includes a first data line (DL1) connected to a plurality of first sub-pixels, a second data line (DL2) connected to a plurality of second sub-pixels, a third data line (DL3) connected to a plurality of third sub-pixels, and a fourth data line (DL4) connected to a plurality of fourth sub-pixels. The first data line and the third data line are positioned on one side of a plurality of pixels sequentially arranged in the same column, and The second data line and the fourth data line are positioned on the other side of multiple pixels that are sequentially arranged in the same column.

6. The display device according to claim 5, characterized in that: The first circuit element (GC) and the third circuit element (WC) are positioned adjacent to the first data line (DL1) and the third data line (DL3), rather than adjacent to the second data line (DL2) and the fourth data line (DL4). The second circuit element (RC) and the fourth circuit element (BC) are positioned adjacent to the second data line (DL2) and the fourth data line (DL4), rather than adjacent to the first data line (DL1) and the third data line (DL3).

7. The display device according to claim 5, characterized in that: A high-potential voltage line (VDDL) is provided between the first data line (DL1) and the third data line (DL3), and A high-potential voltage line (VDDL) is provided between the second data line (DL2) and the fourth data line (DL4).

8. The display device according to claim 1, characterized in that: Each of the plurality of gate lines (GL) is disposed between the first sub-pixel (G) and the second sub-pixel (R), and / or between the third sub-pixel (W) and the fourth sub-pixel (B).

9. The display device according to claim 1, characterized in that: The odd-numbered gate lines of the plurality of gate lines (GL) are disposed between the first sub-pixel (G) and the second sub-pixel (R) which are disposed in the odd-numbered column, and are disposed between the third sub-pixel (W) and the fourth sub-pixel (B) which are disposed in the even-numbered column.

10. The display device according to claim 1 or 9, characterized in that: The even-numbered gate lines among the plurality of gate lines are disposed between the third sub-pixel (W) and the fourth sub-pixel (B) which are disposed in the odd-numbered columns, and are disposed between the first sub-pixel (G) and the second sub-pixel (R) which are disposed in the even-numbered columns.

11. The display device according to claim 1, characterized in that: Each of the first sub-pixel (G), the second sub-pixel (R), the third sub-pixel (W), and the fourth sub-pixel (B) includes a switching transistor (SWT), a driving transistor (DT), a storage capacitor (SC), a sensing transistor (SET), and a light-emitting element (150). The sensing transistor outputs a voltage to the reference voltage line, which is used to sense the threshold voltage and mobility of the driving transistor.

12. A method for driving a display device according to any one of the preceding claims, the method comprising: The multiple gate lines are turned on in even frames in a different order than the order in which they are turned on in odd frames (GL).

13. The method according to claim 12, characterized in that, The turn-on sequence in odd-numbered frames is first gate line (GL1), second gate line (GL2), fourth gate line (GL4), and third gate line (GL3), while the turn-on sequence in even-numbered frames is second gate line (GL2), first gate line (GL1), third gate line (GL3), and fourth gate line (GL4).

14. The method according to claim 13, characterized in that, During odd frames: During the first horizontal cycle, a first gate voltage (GATE1) at the on level is applied to the first gate line (GL1), causing the sub-pixel to be charged using the data voltage; During the second horizontal cycle, a second gate voltage (GATE2) at the on level is applied to the second gate line (GL2), causing the sub-pixel to be charged using the data voltage; In the third level cycle, a fourth gate voltage (GATE4) at the on level is applied to the fourth gate line (GL4), causing the sub-pixel to be discharged; In the fourth level cycle, a third gate voltage (GATE3) at the on level is applied to the third gate line (GL3), causing the sub-pixel to be discharged.

15. The method according to claim 14, characterized in that... ； During the first horizontal cycle of charging the starting data voltage, the data charging rate of the sub-pixel is 40%-70%; During the second horizontal cycle of charging the data voltage, the charging rate of the sub-pixel is 95%-100%; as well as During the third and fourth level cycles when the data voltage is discharged, the charging rate of the corresponding sub-pixel is 0%.

16. The method according to claim 14 or 15, characterized in that, During even-numbered frames: During the first horizontal cycle, a second gate voltage (GATE2) at the on level is applied to the second gate line (GL2), causing the sub-pixel to be charged using the data voltage; During the second horizontal cycle, a first gate voltage (GATE1) at the on level is applied to the first gate line (GL1), causing the sub-pixel to be charged using the data voltage; In the third level cycle, a third gate voltage (GATE3) at the on level is applied to the third gate line (GL3), causing the sub-pixel to be discharged; In the fourth level cycle, a fourth gate voltage (GATE4) at the on level is applied to the fourth gate line (GL4), causing the sub-pixel to be discharged.

17. The method according to claim 16, characterized in that... ； During the first horizontal cycle of charging the starting data voltage, the data charging rate of the sub-pixel is 40%-70%; During the second horizontal cycle of charging the data voltage, the charging rate of the sub-pixel is 95%-100%; as well as During the third and fourth level cycles when the data voltage is discharged, the charging rate of the corresponding sub-pixel is 0%.

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