Quantum devices, methods of making quantum devices, and quantum computers

Abstract

The application discloses a quantum device, a quantum device preparation method and a quantum computer, and belongs to the field of quantum information. It comprises: a first substrate formed with a first quantum circuit and a first interconnection element connected with the first quantum circuit, a second substrate formed with a second quantum circuit and a second interconnection element connected with the second quantum circuit, and the second interconnection element and the first interconnection element are jointed, and a supporting element between the first substrate and the second substrate. In the application, the supporting element provides relative rigid support for the first substrate and the second substrate, thereby limiting the relative parallelism of the plane where the first substrate and the second substrate are located, and thus when the first interconnection element and the second interconnection element are jointed, the sum of the thicknesses of the first interconnection element and the second interconnection element is ensured to be the same as the thickness of the supporting element, thereby ensuring that the thickness of the interconnection structure has high consistency, and the problem of uneven distance between the substrates is avoided.

Description

Technical Field

[0001] This application belongs to the field of quantum information, especially the field of quantum computing technology. In particular, this application relates to a quantum device, a method for preparing a quantum device, and a quantum computer. Background Technology

[0002] Quantum computing is a novel computing method that combines quantum mechanics and computer science, performing calculations by manipulating quantum information units in accordance with the laws of quantum mechanics. It uses qubits, composed of microscopic particles, as its basic units, exhibiting the properties of quantum superposition and entanglement. Through the controlled evolution of quantum states, quantum computing can achieve information encoding and computational storage, possessing an unparalleled capacity for information carrying and superior parallel computing capabilities compared to classical computing techniques.

[0003] Quantum chips are the core devices for performing quantum computing. With the increasing demands for computing power, the integration of more and more qubits onto quantum chips has become an inevitable trend. In related technologies, multi-layer substrate interconnects are used to expand the number of integrated qubits. However, multi-layer interconnected quantum chips often suffer from uneven spacing between substrates due to inconsistent thicknesses of the interconnect structures relative to the substrate surface. This can easily lead to undesirable changes in the performance parameters of the quantum chip, such as undesirable changes in the coupling strength between components. Invention Content

[0004] The purpose of this application is to provide a quantum device, a method for fabricating a quantum device, and a quantum computer to overcome the shortcomings of the prior art. It can ensure that the thickness of the interconnect structure is highly consistent and avoid the problem of uneven spacing between substrates.

[0005] One embodiment of this application provides a quantum device comprising:

[0006] A first substrate, on which a first quantum circuit and a first interconnecting element connected to the first quantum circuit are formed;

[0007] A second substrate, on which a second quantum circuit and a second interconnecting element connected to the second quantum circuit are formed, and the second interconnecting element and the first interconnecting element are coupled; and

[0008] A support element is located between the first substrate and the second substrate, and the support element defines the first substrate and the second substrate as being relatively parallel.

[0009] To address the problem of uneven inter-substrate distances often caused by inconsistent thicknesses of interconnect structures relative to the substrate surface in multi-layer interconnected quantum chips, this application provides a quantum device comprising a first substrate with a first interconnect element, a second substrate with a second interconnect element, and a support element located between the first and second substrates. The support element provides relative rigid support to the first and second substrates, thereby defining that the planes on which the first and second substrates are located are relatively parallel. Thus, while achieving the bonding of the first and second interconnect elements, it ensures that the sum of the thicknesses of the first and second interconnect elements is the same as the thickness of the support element, thereby ensuring a high degree of consistency in the thickness of the interconnect structure formed by the first and second interconnect elements and avoiding the problem of uneven inter-substrate distances.

[0010] In some implementations of the quantum device described above, the first interconnect element includes a first barrier layer formed on the first quantum circuit and a first solder layer formed on the first barrier layer, the second interconnect element includes a second barrier layer formed on the second quantum circuit and a second solder layer formed on the second barrier layer, and the first solder layer and the second solder layer are bonded together.

[0011] In some implementations of the quantum device described above, the first barrier layer, the first solder layer, the second barrier layer, and the second solder layer are all patterned superconducting material layers.

[0012] In some implementations of the quantum device described above, both the first barrier layer and the second barrier layer are patterned titanium nitride layers.

[0013] In some implementations of the quantum device described above, the first solder layer and the second solder layer are patterned indium layers.

[0014] In some implementations of the quantum device described above, the supporting element is a non-superconducting pillar.

[0015] In some implementations of the quantum device described above, the pillar is formed on the surface of the first substrate or the surface of the second substrate; or, at least one pillar is formed on the surface of the first substrate and at least one pillar is formed on the surface of the second substrate.

[0016] In some implementations of the quantum device described above, the pillar includes at least one of a silicon pillar and a silicon dioxide pillar.

[0017] In some implementations of the quantum device described above, the silicon pillar is an integral structure with the first substrate or the second substrate.

[0018] In some implementations of the quantum device described above, the first quantum circuit includes a qubit circuit, and the second quantum circuit includes a coplanar waveguide transmission line.

[0019] In some implementations of the quantum device described above, the first substrate and the second substrate are either a single-crystal silicon substrate or a sapphire substrate.

[0020] Another embodiment of this application provides a method for fabricating a quantum device, which includes the following steps:

[0021] A first substrate is provided, and a first quantum circuit and a first interconnect element connected to the first quantum circuit are formed on the first substrate;

[0022] A second substrate is provided, on which a second quantum circuit and a second interconnecting element connected to the second quantum circuit are formed;

[0023] A support element is provided between the first substrate and the second substrate; and

[0024] When a force is applied to the first substrate and / or the second substrate such that the first interconnect element and the second interconnect element engage when the first substrate and the second substrate are defined as being relatively parallel by the support element.

[0025] To address the problem of uneven inter-substrate distances in quantum chips with multilayer substrate interconnects due to inconsistent thicknesses of the interconnect structures relative to the substrate surface, the quantum device fabrication method provided in this application provides a first substrate with a first interconnect element, a second substrate with a second interconnect element, and a support element located between the first and second substrates. Then, relative forces are applied to the first and / or second substrates, which join the first and second interconnect elements and press the first and second substrates against a relatively parallel plane defined by the support element. This compresses the sum of the thicknesses of the first and second interconnect elements to the same thickness as the support element, ensuring a high degree of consistency in the thickness of the interconnect structure formed by the first and second interconnect elements and avoiding the problem of uneven inter-substrate distances.

[0026] In some implementations of the quantum device described above, forming a first quantum circuit and a first interconnect element connected to the first quantum circuit on the first substrate includes: planarizing the first substrate to obtain a first surface; and forming the first circuit and the first interconnect element connected to the first quantum circuit on the first surface.

[0027] In some implementations of the quantum device fabrication method described above, forming the first quantum circuit and the first interconnecting element connected to the first quantum circuit on the first surface includes: forming a first superconducting material layer on the first surface; forming a first barrier material layer on the first superconducting material layer; patterning the first barrier material layer and the first superconducting material layer to obtain the first barrier layer and the first quantum circuit, wherein the first barrier layer is located on the first quantum circuit; and forming a first solder layer on the first barrier layer.

[0028] In some implementations of the quantum device fabrication method described above, prior to the step of forming the first barrier material layer on the first superconducting material layer, the method further includes: removing the natural oxide film located on the surface of the first superconducting material layer.

[0029] In some implementations of the quantum device fabrication method described above, the step of removing the natural oxide film on the surface of the first superconducting material layer includes: ion beam etching of the surface of the first superconducting material layer.

[0030] In some implementations of the quantum device fabrication method described above, prior to the step of forming the first solder layer on the first barrier layer, the method further includes: removing the natural oxide film located on the surface of the first barrier layer.

[0031] In some implementations of the quantum device fabrication method described above, the step of removing the native oxide film on the surface of the first barrier layer includes: ion beam etching of the surface of the first barrier layer.

[0032] In some implementations of the quantum device fabrication method described above, the step of forming a second quantum circuit and a second interconnecting element connected to the second quantum circuit on the second substrate includes: planarizing the second substrate to obtain a second surface; etching the second surface to obtain a third surface and the support element located on the third surface; and forming the second quantum circuit and the second interconnecting element connected to the second quantum circuit on the third surface.

[0033] In some implementations of the quantum device fabrication method described above, forming a second quantum circuit and a second interconnecting element connected to the second quantum circuit on the third surface includes: forming a second superconducting material layer on the third surface; forming a second barrier material layer on the second superconducting material layer; patterning the second barrier material layer and the second superconducting material layer to obtain the second barrier layer and the second quantum circuit; and forming a second solder layer on the second barrier layer.

[0034] In some implementations of the quantum device fabrication method described above, prior to the step of forming the second barrier material layer on the second superconducting material layer, the method further includes: removing the natural oxide film located on the surface of the second superconducting material layer.

[0035] In some implementations of the quantum device fabrication method described above, the step of removing the natural oxide film on the surface of the second superconducting material layer includes: ion beam etching of the surface of the second superconducting material layer.

[0036] In some implementations of the quantum device fabrication method described above, prior to the step of forming the second solder layer on the second barrier layer, the method further includes: removing the natural oxide film located on the surface of the second barrier layer.

[0037] In some implementations of the quantum device fabrication method described above, the step of removing the native oxide film on the surface of the second barrier layer includes: ion beam etching of the surface of the second barrier layer.

[0038] In some implementations of the quantum device fabrication method described above, prior to the step of applying force between the first substrate and the second substrate, the method further includes: removing the natural oxide film located on the surfaces of the first interconnect element and the second interconnect element.

[0039] In some implementations of the quantum device fabrication method described above, the supporting element is a non-superconducting pillar.

[0040] In some implementations of the quantum device fabrication method described above, the step of providing a support element between the first substrate and the second substrate includes: forming the pillar on the surface of the first substrate or the surface of the second substrate; or, forming at least one pillar on the surface of the first substrate and forming at least one pillar on the surface of the second substrate.

[0041] In some implementations of the quantum device fabrication method described above, the pillar includes at least one of a silicon pillar and a silicon dioxide pillar.

[0042] In some implementations of the quantum device fabrication method described above, the silicon pillar is an integral structure with the first substrate or the second substrate.

[0043] The third embodiment provided in this application provides a quantum computer, which includes the quantum device described above, or the quantum device obtained according to the quantum device fabrication method described above. Attached Figure Description

[0044] Figure 1A , Figure 1B and Figure 1C This is a schematic diagram of the structure of the quantum device provided in the embodiments of this application;

[0045] Figure 2 A flowchart illustrating the steps of a quantum device fabrication method provided in this application embodiment;

[0046] Figures 3A to 3D A schematic diagram of the quantum device fabrication method provided in the embodiments of this application;

[0047] Figures 4A to 4C A schematic diagram illustrating a fabrication process for a second substrate provided in an embodiment of this application;

[0048] Figures 5A to 5C This is a schematic diagram of another fabrication process for a second substrate provided in an embodiment of this application.

[0049] Explanation of reference numerals in the attached figures:

[0050] 1-First substrate, 11-First quantum circuit, 12-First interconnect element,

[0051] 2-Second substrate, 21-Second quantum circuit, 22-Second interconnect element,

[0052] 3-Supporting elements. Detailed Implementation

[0053] The following detailed description is illustrative only and is not intended to limit the embodiments and / or their application or use. Furthermore, it is not intended to be construed as being bound by any express or implied information presented in the preceding "Background Art" or "Summary of the Invention" or "Detailed Description" sections.

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a more thorough understanding of one or more embodiments. However, it will be apparent that one or more embodiments may be practiced in various circumstances without these specific details, and the various embodiments may be combined with and referenced to each other without contradiction.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] Additionally, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Furthermore, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Additionally, references to "on" and "under" the layers may be made based on the accompanying drawings.

[0057] Quantum computing possesses parallel processing capabilities unmatched by classical computing. Internationally, the physical systems being explored for quantum computing include ion traps, superconductivity, ultracold atoms, polarized molecules, linear optics, diamond color centers, and electron or nuclear spin in silicon-28. Among these, superconducting quantum computing represents the most advanced and successful solid-state quantum computing approach to date. In this system, the energy level structure of quantum circuits formed using superconducting materials can be controlled by applied electromagnetic signals, and the design and fabrication of these quantum circuits offer high controllability. Furthermore, superconducting systems can be based on existing mature integrated circuit technologies, giving superconducting quantum circuits unparalleled scalability compared to other physical systems.

[0058] In quantum computing within superconducting systems, qubits (qubits) are TLS systems built on Josephson structures. The superconducting materials involved include those exhibiting superconductivity below their corresponding superconducting critical temperatures, such as aluminum (e.g., a superconducting critical temperature of 1.2 K) or niobium (e.g., a superconducting critical temperature of 9.3 K). Circuit elements in a quantum circuit can be formed from one or more layers of material (e.g., superconducting material and dielectric). To reduce energy loss and decoherence, the substrates forming the circuit elements in a quantum circuit can be formed from low-loss dielectric materials (e.g., single-crystal silicon substrates or sapphire substrates).

[0059] In order to expand the computing and storage capabilities of quantum computing, it has become an inevitable trend to expand and integrate more and more qubits on quantum chips of superconducting systems. The embodiments provided in this application relate to a quantum device that facilitates the integration and expansion of qubits.

[0060] Figure 1A , Figure 1B and Figure 1C These are schematic diagrams of the structure of quantum devices provided in different embodiments of this application.

[0061] refer to Figures 1A to 1C As shown, this application provides a quantum device comprising:

[0062] A first substrate 1, on which a first quantum circuit 11 and a first interconnecting element 12 connected to the first quantum circuit 11 are formed;

[0063] A second substrate 2, on which a second quantum circuit 21 and a second interconnecting element 22 connected to the second quantum circuit 21 are formed, wherein the second interconnecting element 22 and the first interconnecting element 12 are coupled to achieve an electrical connection, such as an electrical contact or coupling, between the first quantum circuit 11 and the second quantum circuit 21; and

[0064] A support element 3 is located between the first base 1 and the second base 2, and the support element 3 defines the first base 1 and the second base 2 as being relatively parallel.

[0065] To address the problem of uneven inter-substrate distances in multi-layer interconnected quantum chips due to inconsistent thicknesses of the interconnect structures relative to the substrate surface, this application provides a quantum device comprising a first substrate 1 with a first interconnect element 12, a second substrate 2 with a second interconnect element 22, and a support element 3 located between the first substrate 1 and the second substrate 2. The support element 3 provides relative rigid support for the first substrate 1 and the second substrate 2, thereby defining that the planes on which the first substrate 1 and the second substrate 2 are located are relatively parallel. Thus, while achieving the bonding of the first interconnect element 12 and the second interconnect element 22, it ensures that the sum of the thicknesses of the first interconnect element 12 and the second interconnect element 22 is the same as the thickness of the support element 3, thereby ensuring a high degree of consistency in the thickness of the interconnect structure formed by bonding the first interconnect element 12 and the second interconnect element 22, and avoiding the problem of uneven inter-substrate distances.

[0066] In some embodiments of this application, the superconducting material used as interconnecting elements (e.g., the first interconnecting element 12 and the second interconnecting element 22) includes indium or niobium, and the superconducting material used to manufacture quantum circuits (e.g., the first quantum circuit 11 and the second quantum circuit 21) can be formed of aluminum, or it can be formed of materials such as aluminum, niobium, or titanium nitride.

[0067] In some quantum device embodiments provided in this application, the first interconnect element 12 includes a first barrier layer formed on the first quantum circuit 11 and a first solder layer formed on the first barrier layer, and the second interconnect element 22 includes a second barrier layer formed on the second quantum circuit 21 and a second solder layer formed on the second barrier layer, wherein the first solder layer and the second solder layer are bonded. In some embodiments, the first barrier layer, the first solder layer, the second barrier layer, and the second solder layer are all patterned superconducting material layers, which are formed by electroplating, evaporating, depositing, or sputtering superconducting material on the surface of a substrate or on the surface of other media. For example, the first barrier layer and the second barrier layer are both patterned titanium nitride layers, and the first solder layer and the second solder layer are patterned indium layers.

[0068] When the indium and aluminum layers come into contact, diffusion between indium and aluminum can lead to the formation of a non-superconducting alloy. This non-superconducting alloy increases decoherence effects and can also cause problems such as voids and pitting. To avoid the formation of non-superconducting alloys between the first interconnect element 12 and the first quantum circuit 11, and between the second interconnect element 22 and the second quantum circuit 21, barrier layers (e.g., the first barrier layer and the second barrier layer) can be formed between the interconnect elements and the quantum circuits. The first barrier layer and the second barrier layer comprise a superconducting material, which also serves to prevent diffusion between the material forming the superconducting circuit and the material forming the solder layer.

[0069] In some quantum device embodiments provided in this application, the support element 3 is a non-superconducting pillar. The pillar can be made of materials such as photoresist, plastic metal, or silicon and its oxides. There can be more than one pillar, as long as the two ends of the pillar can define the planes where the first substrate 1 and the second substrate 2 are located to be relatively parallel. Alternatively, the end faces of the pillar can be tested after its formation to ensure that the end faces are straight, thereby ensuring that the planes where the first substrate 1 and the second substrate 2 are located are relatively parallel. In order to provide sufficient resistance to limit the first substrate 1 and the second substrate 2 to be in relatively parallel planes during bonding, the pillar is formed of a relatively hard material, such as silicon, silicon dioxide (SiO2), or silicon nitride (SiN), as long as the hardness of the support element 3 is greater than the hardness of the first interconnect element 12 and the second interconnect element during bonding. Each pillar has the same thickness. It should be noted that the thickness of any element on the substrate refers to the dimension of the element in the direction perpendicular to the surface of the substrate. In some embodiments, all of the pillars are formed on the surface of the first substrate 1 or the surface of the second substrate 2; or, at least one pillar is formed on the surface of the first substrate 1 and at least one pillar is formed on the surface of the second substrate 2. In other embodiments, the pillars include at least one of silicon pillars, sapphire pillars, and silicon dioxide pillars. See, for example... Figure 1C As shown, the pillar, which is made of silicon or sapphire, is an integral structure with the first substrate 1 or the second substrate 2. That is, the support element 3 is a single unit with the first substrate 1 or the second substrate 2. For example, when the second substrate 2 is a monocrystalline silicon substrate, the support element 3 can be a silicon pillar structure formed by directly removing a portion of the material from the monocrystalline silicon substrate. When the second substrate 2 is a sapphire substrate, the support element 3 can be a sapphire pillar structure formed by directly removing a portion of the material from the sapphire substrate 2. It is understood that the support element 3 can also be an integral structure with the first substrate 1.

[0070] In embodiments of this application, the circuit elements in the first quantum circuit 11 and the second quantum circuit 21 may include qubits, coplanar waveguide transmission lines, or SQUIDS, etc. In some quantum device embodiments provided in this application, the first quantum circuit 11 includes a circuit of qubits, and the second quantum circuit 21 includes a coplanar waveguide transmission line.

[0071] In some quantum device embodiments provided in this application, the first substrate 1 and the second substrate 2 can be formed of low-loss dielectric materials such as sapphire or single-crystal silicon, and can be in the form of wafers or diced chips, that is, the first substrate 1 and the second substrate 2 can be one of single-crystal silicon substrates and sapphire substrates.

[0072] It should be noted that, Figure 1AThe diagram schematically illustrates that the support element 3 formed on the surface of the second base 2 defines the first base 1 and the second base 2 as being in relatively parallel planes. Figure 1B The schematic diagram illustrates that the support element 3 formed on the second quantum circuit 21 defines the first substrate 1 and the second substrate 2 as being in relatively parallel planes. Figure 1C The illustration schematically shows that the support element 3, which is integrally formed with the second base 2, defines the first base 1 and the second base 2 in relatively parallel planes. Schematically, in... Figure 1A In the diagram, the support element 3 and the second base 2 have a clear interface distinction. (Illustratively, in...) Figure 1B In the diagram, the supporting element 3 and the second quantum circuit 21 have a clear interface distinction. (Illustratively, in...) Figure 1C In the middle, there is no interface between the support element 3 and the second base 2. Figure 1A , Figure 1B and Figure 1C Different implementation methods are illustrated schematically, and it is understood that the support element 3 may also be formed on the surface of the first substrate 1, on the first quantum circuit 11 formed on the first substrate 1, or be an integral structure with the first substrate 1.

[0073] Figure 2 A flowchart illustrating the steps of a quantum device fabrication method provided in this application embodiment.

[0074] Figures 3A to 3D This is a schematic diagram of a quantum device fabrication method provided in an embodiment of this application.

[0075] refer to Figure 2 , Figures 3A to 3D As shown, and in combination Figures 1A to 1C As shown, this application provides a method for fabricating a quantum device, including steps S201 to S204, wherein:

[0076] S201. A first substrate 1 is provided, and a first quantum circuit 11 and a first interconnecting element 12 connected to the first quantum circuit 11 are formed on the first substrate 1.

[0077] S202, Provide a second substrate 2, and form a second quantum circuit 21 and a second interconnecting element 22 connected to the second quantum circuit 21 on the second substrate 2;

[0078] S203, providing a support element 3 between the first substrate 1 and the second substrate 2; and

[0079] S204. Apply a force F to the first substrate 1 and / or the second substrate 2 such that the first interconnecting element 12 and the second interconnecting element 22 are engaged when the first substrate 1 and the second substrate 2 are defined as relatively parallel by the support element 3.

[0080] To address the problem of uneven inter-substrate distances in multi-layer interconnected quantum chips due to inconsistent thicknesses of the interconnect structures relative to the substrate surface, this application provides a quantum device fabrication method. This method involves providing a first substrate 1 with first interconnect elements 12, a second substrate 2 with second interconnect elements 22, and a support element 3 located between the first substrate 1 and the second substrate 2. Then, a relative force F is applied to the first substrate 1 and / or the second substrate 2. Under the action of force F, the first substrate 1 and the second substrate 2 move closer together. The force F compresses and fuses the first interconnect elements 12 and the second interconnect elements 22, achieving bonding. Furthermore, it presses the first substrate 1 and the second substrate 2 onto a relatively parallel plane defined by the support element 3. This compresses the sum of the thicknesses of the first interconnect elements 12 and the second interconnect elements 22 to the same thickness as the support element 3, ensuring a high degree of thickness uniformity in the interconnect structure formed by the bonding of the first interconnect elements 12 and the second interconnect elements 22, thus avoiding the problem of uneven inter-substrate distances. It should be noted that, referring to… Figure 3C As shown, the ends of the first interconnecting element 12 and the second interconnecting element 22 come into contact under the applied force F. Figure 3C There is a clear boundary between the first interconnecting element 12 and the second interconnecting element 22, and due to the compressive effect of force F, the reference... Figure 3D As shown, the ends of the first interconnecting element 12 and the second interconnecting element 22 are inter-fused and the cross-sectional area of ​​the inter-fused portion may be slightly expanded and increased. The applied force F will deform the first interconnecting element 12 and the second interconnecting element 22 to match the thickness of the support element 3.

[0081] In some embodiments of quantum device fabrication methods provided in this application, the formation of the first quantum circuit 11 and the first interconnecting element 12 connected to the first quantum circuit 11 on the first substrate in step S201 includes: planarizing the first substrate 1 using chemical mechanical polishing (CMP) or global planarization process to obtain a relatively flat first surface; and forming the first circuit 11 and the first interconnecting element 12 connected to the first quantum circuit 11 on the first surface.

[0082] In some embodiments of this application, forming the first quantum circuit 11 and the first interconnecting element 12 connected to the first quantum circuit 11 on the first surface includes: forming a first superconducting material layer on the first surface; forming a first barrier material layer on the first superconducting material layer; patterning the first barrier material layer and the first superconducting material layer to obtain the first barrier layer and the first quantum circuit 11, wherein the first barrier layer is located on the first quantum circuit 11; and forming a first solder layer on the first barrier layer, wherein the first solder layer is formed by patterning the first solder material layer formed on the first barrier layer.

[0083] In some embodiments, prior to the step of forming the first barrier material layer on the first superconducting material layer, the method further includes: removing the native oxide film located on the surface of the first superconducting material layer. For example, the step of removing the native oxide film located on the surface of the first superconducting material layer includes: performing ion beam etching on the surface of the first superconducting material layer.

[0084] In other embodiments, prior to the step of forming the first solder layer on the first barrier layer, the method further includes: removing the native oxide film located on the surface of the first barrier layer. For example, the step of removing the native oxide film located on the surface of the first barrier layer includes: performing ion beam etching on the surface of the first barrier layer.

[0085] The native oxide film on the surface of the first superconducting material layer is the native oxide layer formed on the surface of the quantum circuit. For example, the surface of a quantum circuit formed using aluminum may include a native oxide film layer of AlOx. The native oxide film layer is insulating, thereby reducing the conductivity to the connection of the circuit elements. To remove the native oxide film, the surface of the quantum circuit is exposed to an ion beam for etching. The ion beam etching process includes: under vacuum conditions, delivering ions (e.g., Ar ions) at an angle to the surface of the quantum circuit, thereby sputtering away the native oxide film from the surface. Once the native oxide film is sputtered away, a barrier material is immediately deposited on the fabricated surface of the quantum circuit. The barrier material includes materials that prevent material diffusion. To reduce decoherence that may be caused by the barrier layer, the barrier material may include a superconducting material. For example, the barrier material may be titanium nitride (e.g., with a superconducting critical temperature of about 4.2 K).

[0086] Forming a barrier layer can include performing effective reactive sputtering, a process in which a target chemical composition is sputtered in the presence of a gas or gas mixture (e.g., Ar ions or N2) that reacts with the target material to form a coating with a different chemical composition. Argon is the predominant gas in most cases, and the amount of reactive gas introduced into the processing chamber is controlled to produce a fully reacted compound. As an example, a mixture of Ar and N2 can be used to perform reactive sputtering at a temperature of approximately 25°C. After forming the barrier layer, it can be patterned to form a barrier layer that covers only the desired area. Patterning the barrier layer may require wet and / or dry etching; alternatively, a lift-off process can be used, in which the barrier layer is deposited on a patterned photoresist layer, and then a solvent is used to effectively lift off the photoresist and the barrier layer. In either case, after patterning the barrier layer, the sample is exposed to O2 plasma to remove any residual photoresist and / or other organic materials that may be present on the sample surface.

[0087] After patterning the barrier material layer to form the barrier layer, the exposed surface of the barrier layer can optionally be ion-beam etched. Ion-beam etch removes the native oxide film on the barrier layer to improve the conductivity and reliability of the interconnect. Subsequently, a superconducting material forming a solder layer for bonding is deposited on the surface of the barrier layer. The superconducting material forming the solder layer for bonding may include indium (e.g., at a superconducting critical temperature of about 3.4 K). The superconducting material can be deposited in a vacuum (e.g., at about 1 × 10⁻⁶ Torr) using, for example, a thermal evaporation deposition process. The superconducting material thus deposited can be patterned using a combination of photolithography and wet or dry etching techniques. Alternatively, the superconducting material forming the solder layer for bonding can also be patterned using a lift-off process, in which a photoresist layer is deposited and patterned before the superconducting material is deposited, and then, after the superconducting material is deposited, a solvent is used to remove the resist and the superconducting material covering the resist.

[0088] Figure 4 is a schematic diagram of a fabrication process for a second substrate provided in an embodiment of this application.

[0089] Figure 5 is a schematic diagram of another fabrication process for the second substrate provided in an embodiment of this application.

[0090] In some embodiments of quantum device fabrication methods provided in this application, the support element 3 is a non-superconducting pillar. The pillar can be made of materials such as photoresist, plastic metal, or silicon and its oxides with a high dielectric constant. There can be more than one pillar, as long as the two ends of the pillar can define the planes where the first substrate 1 and the second substrate 2 are located to be relatively parallel. In order to provide sufficient resistance to define the first substrate 1 and the second substrate 2 to be in relatively parallel planes during bonding, the pillar is formed of a relatively hard material, such as silicon, silicon dioxide (SiO2), or silicon nitride (SiN), and each pillar has the same thickness.

[0091] In some examples, silicon dioxide material can be deposited on the surfaces of the first substrate 1 and the second substrate 2 using plasma-enhanced chemical vapor deposition (PECVD) to form silicon dioxide pillars, and silicon nitride generated by mixing and reacting gaseous substances in a reaction chamber using chemical vapor deposition can be deposited. When the support element 3 is a non-superconducting pillar, the step of providing the support element 3 between the first substrate 1 and the second substrate 2 includes: referencing Figures 4A to 4C As shown, all the pillars are formed on the surface of the second base 2. Figure 4C In this configuration, the support element 3 and the second base 2 have a clearly defined interface. Alternatively, all of the pillars may be formed on the surface of the first base 1. Or, alternatively, at least one pillar may be formed on the surface of the first base 1 and at least one pillar may be formed on the surface of the second base 2. Taking the fabrication of the support element 3 on the surface of a first substrate 1 as an example, specifically, it can be as follows: a photoresist layer is formed on the surface of the first substrate 1, and then one or more exposure techniques are used to pattern the first photoresist layer to define the dimensions of the pillar. The exposure techniques can include electron beam lithography, deep-UV (DUV) lithography, or other techniques for exposing the photoresist layer; after exposing the first photoresist layer, the first photoresist layer is developed to remove the photoresist material and form a window that exposes the desired area on the first substrate 1, and the pillar will be formed in the window. The development process depends on the material of the first photoresist layer (e.g., negative or positive photoresist). In one example, an AZ300MIF is used to develop the first photoresist layer; then a deposition process is performed on the first substrate 1 through the window in the first photoresist layer to form the pillar. The deposited material can include, for example, non-conductive materials, including silicon, silicon dioxide (SiO2), and silicon nitride (SiN). The first photoresist layer and excess deposited material can be removed by a stripping process or by an etch-back process. In this process, as an alternative to exposure and development, in some implementations, dry etching (e.g., using plasma etching) can be used to form the window.

[0092] In other examples, the pillar comprises at least one of silicon pillars, sapphire pillars, and silicon dioxide pillars. As an exemplary example, refer to... Figures 5A to 5C As shown, and in combination Figure 1C and Figures 3A to 3D As shown, the silicon pillar is an integral structure with the first substrate 1 or the second substrate 2. As an example, the sapphire pillar is also an integral structure with the first substrate 1 or the second substrate 2, meaning the support element 3 is a single unit with the first substrate 1 or the second substrate 2. For example, when the second substrate 2 is a monocrystalline silicon substrate, the support element 3 can be a silicon pillar structure formed by directly removing a portion of the material from the monocrystalline silicon substrate; when the second substrate 2 is a sapphire substrate, the support element 3 can be a sapphire pillar structure formed by directly removing a portion of the material from the sapphire substrate 2. It is understood that the support element 3 can also be an integral structure with the first substrate 1.

[0093] In some embodiments of quantum device fabrication methods provided in this application, the integral support element 3 and substrate are formed by removing a portion of the substrate material. Exemplarily, the step of forming the second quantum circuit 21 and the second interconnecting element 22 connected to the second quantum circuit 21 on the second substrate 2 includes: referencing... Figures 5A to 5C As shown, the second substrate 2 is planarized using chemical mechanical polishing (CMP) or global planarization to obtain a relatively flat second surface; the second surface is etched to obtain a third surface and the support element 3 located on the third surface. The third surface is parallel to the second surface. It can be understood that, defined by the support element 3, the first substrate 1 after bonding is located on the second surface, thereby ensuring that the first substrate 1 and the second substrate 2 are parallel; a second quantum circuit 21 and a second interconnecting element 22 connected to the second quantum circuit 21 are formed on the third surface. In this embodiment, a portion of the material of the second substrate 2 is removed by mechanical cutting, laser cutting, or chemical etching to form the support element 3. The shape of the support element 3 can be a cylinder, cuboid, cube, or prism. When the second substrate 2 is a single-crystal silicon substrate, the support element 3 formed on the substrate surface by removing a portion of the substrate material is a silicon pillar; when the second substrate 2 is a sapphire substrate, the support element 3 formed on the substrate surface by removing a portion of the substrate material is a sapphire pillar.

[0094] In some embodiments of this application, forming the second quantum circuit 21 and the second interconnecting element 22 connected to the second quantum circuit 21 on the third surface includes: forming a second superconducting material layer on the third surface; forming a second barrier material layer on the second superconducting material layer; patterning the second barrier material layer and the second superconducting material layer to obtain the second barrier layer and the second quantum circuit 21; and forming a second solder layer on the second barrier layer, wherein the second solder layer is formed by patterning the second solder material layer formed on the second barrier layer.

[0095] In some embodiments, prior to the step of forming the second barrier material layer on the second superconducting material layer, the method further includes: removing the native oxide film located on the surface of the second superconducting material layer. For example, the step of removing the native oxide film located on the surface of the second superconducting material layer includes: performing ion beam etching on the surface of the second superconducting material layer.

[0096] In other embodiments, prior to the step of forming the second solder layer on the second barrier layer, the method further includes: removing the native oxide film located on the surface of the second barrier layer. For example, the step of removing the native oxide film located on the surface of the second barrier layer includes: ion beam etching the surface of the second barrier layer.

[0097] The native oxide film on the surface of the quantum circuit can be removed using the method described above, and a barrier material layer can be deposited immediately on the fabrication surface of the quantum circuit. After patterning the barrier material layer to form the barrier layer, the exposed surface of the barrier layer can optionally be ion-beam etched to remove the native oxide film on the barrier layer, thereby improving the conductivity and reliability of the interconnect. Immediately after removing the native oxide film on the barrier layer, a superconducting material for forming a solder layer for bonding is deposited on the surface of the barrier layer.

[0098] In some embodiments of this application, prior to the step of applying force between the first substrate 1 and the second substrate 2, the method further includes: removing the native oxide film located on the surfaces of the first interconnect element 12 and the second interconnect element 22. The surfaces of the interconnect elements formed on one or both substrates are exposed to H2 plasma, which removes oxides from the surfaces of the interconnect elements, thereby promoting mutual solubility and achieving good electrical bonding. After exposure to H2 plasma, the interconnect elements of the two substrates are aligned together, and they can be joined using thermocompression to achieve a stacked interconnect of the first substrate 1 and the second substrate 2.

[0099] The fabrication process of a superconducting quantum chip provided in this application may require the deposition of one or more materials to form a layer of a specific material, such as a superconductor, dielectric, and / or metal. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), epitaxial techniques, or other deposition processes. The fabrication process of a superconducting quantum chip provided in this application may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching, dry etching, or lift-off processes. The materials forming the circuit elements described herein may be patterned using known lithographic techniques (e.g., photolithography or electron beam lithography).

[0100] This application provides a quantum computer, which includes a quantum device in the quantum device embodiment or a quantum device obtained according to the quantum device fabrication method embodiment.

[0101] It should be noted that the quantum devices involved in the above quantum computer embodiments have similar structures to those in the above embodiments and have the same beneficial effects as the above quantum device embodiments and / or quantum device fabrication method embodiments, therefore, they will not be described in detail here. For technical details not disclosed in the quantum computer embodiments of this application, those skilled in the art should refer to the description of the above quantum computing circuit for understanding; for the sake of brevity, they will not be repeated here.

[0102] This application recognizes certain drawbacks of currently available methods for assembling quantum devices. For example, bonding during the manufacturing process can easily lead to substrate warping, resulting in inefficient electrical connections. For instance, in currently available methods, the natural oxidation of metal deposits affects the electrical properties of the connections. In conjunction with the description in this application, compared to the prior art, the quantum device provided in this application includes a first substrate with first interconnect elements, a second substrate with second interconnect elements, and a support element located between the first and second substrates. This support element provides relative rigid support to the first and second substrates, thereby defining that the planes on which the first and second substrates lie are relatively parallel. Therefore, when the first and second interconnect elements are joined, it can be ensured that the sum of the thicknesses of the first and second interconnect elements is the same as the thickness of the support element, ensuring a high degree of consistency in the thickness of the interconnect structure and avoiding substrate warping problems.

[0103] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A quantum device, characterized in that, The quantum device comprises: a first substrate, a first quantum circuit and a first interconnection element connected to the first quantum circuit are formed on the first substrate; a second substrate, a second quantum circuit and a second interconnection element connected to the second quantum circuit are formed on the second substrate, and the second interconnection element and the first interconnection element are joined; and a support element is provided between the first substrate and the second substrate, the hardness of the support element is greater than that when the first interconnection element and the second interconnection element are joined, and the support element defines that the first substrate and the second substrate are relatively parallel when the second interconnection element and the first interconnection element are joined; the support element is a non-superconducting column, and the column comprises at least one of a silicon column and a silicon dioxide column; the column is formed on the surface of the first substrate or the surface of the second substrate; or at least one of the columns is formed on the surface of the first substrate and at least one of the columns is formed on the surface of the second substrate.

2. The quantum device according to claim 1, wherein: the first interconnection element comprises a first barrier layer formed on the first quantum circuit and a first solder layer formed on the first barrier layer, the second interconnection element comprises a second barrier layer formed on the second quantum circuit and a second solder layer formed on the second barrier layer, and the first solder layer and the second solder layer are joined.

3. The quantum device of claim 2, wherein, The first barrier layer, the first solder layer, the second barrier layer and the second solder layer are all patterned superconducting material layers.

4. The quantum device of claim 2 or 3, wherein, The first barrier layer and the second barrier layer are both patterned titanium nitride layers.

5. The quantum device of claim 2 or 3, wherein, The first solder layer and the second solder layer are patterned indium layers.

6. The quantum device of claim 5, wherein, The silicon column is an integral structure with the first substrate or the second substrate.

7. The quantum device of claim 1, wherein, The first quantum circuit comprises a quantum bit circuit, and the second quantum circuit comprises a coplanar waveguide transmission line.

8. The quantum device of claim 1, wherein, The first substrate and the second substrate are one of a single crystal silicon substrate and a sapphire substrate.

9. A method for fabricating a quantum device, characterized in that, The quantum device comprises: providing a first substrate, forming a first quantum circuit and a first interconnection element connected to the first quantum circuit on the first substrate; providing a second substrate, forming a second quantum circuit and a second interconnection element connected to the second quantum circuit on the second substrate; providing a support element between the first substrate and the second substrate, the hardness of the support element is greater than that when the first interconnection element and the second interconnection element are joined, and the support element is a non-superconducting column, and the column comprises at least one of a silicon column and a silicon dioxide column; and applying force to the first substrate and / or the second substrate to achieve the joining of the first interconnection element and the second interconnection element, and pressing the first substrate and the second substrate to the relatively parallel plane defined by the support element; the step of providing a support element between the first substrate and the second substrate comprises: forming the column on the surface of the first substrate or the surface of the second substrate; or, forming at least one of the pillars on a surface of the first substrate and forming at least one of the pillars on a surface of the second substrate.

10. The quantum device fabrication method of claim 9, wherein, The forming the first quantum circuit and the first interconnection element connected with the first quantum circuit on the first substrate comprises: planarizing the first substrate to obtain a first surface; forming the first quantum circuit and the first interconnection element connected with the first quantum circuit on the first surface.

11. The quantum device fabrication method of claim 10, wherein, The forming the first quantum circuit and the first interconnection element connected with the first quantum circuit on the first surface comprises: forming a first superconducting material layer on the first surface; forming a first barrier material layer on the first superconducting material layer; patterning the first barrier material layer and the first superconducting material layer to obtain a first barrier layer and the first quantum circuit, and the first barrier layer is on the first quantum circuit; and forming a first solder layer on the first barrier layer.

12. The quantum device fabrication method of claim 11, wherein, Before the step of forming the first barrier material layer on the first superconducting material layer, the method further comprises: removing a natural oxide film on a surface of the first superconducting material layer.

13. The quantum device fabrication method of claim 12, wherein, The step of removing the natural oxide film on the surface of the first superconducting material layer comprises: performing ion beam etching on the surface of the first superconducting material layer.

14. The quantum device fabrication method of claim 11, wherein, Before the step of forming the first solder layer on the first barrier layer, the method further comprises: removing a natural oxide film on a surface of the first barrier layer.

15. The quantum device fabrication method of claim 14, wherein, The step of removing the natural oxide film on the surface of the first barrier layer comprises: performing ion beam etching on the surface of the first barrier layer.

16. The quantum device fabrication method of claim 9, wherein, The step of forming the second quantum circuit and the second interconnection element connected with the second quantum circuit on the second substrate comprises: planarizing the second substrate to obtain a second surface; etching the second surface to obtain a third surface and the support element on the third surface; forming the second quantum circuit and the second interconnection element connected with the second quantum circuit on the third surface.

17. The quantum device fabrication method of claim 16, wherein, The forming the second quantum circuit and the second interconnection element connected with the second quantum circuit on the third surface comprises: forming a second superconducting material layer on the third surface; forming a second barrier material layer on the second superconducting material layer; patterning the second barrier material layer and the second superconducting material layer to obtain a second barrier layer and the second quantum circuit; and forming a second solder layer on the second barrier layer.

18. The quantum device fabrication method of claim 17, wherein, Before the step of forming the second barrier material layer on the second superconducting material layer, the method further comprises: removing a natural oxide film on a surface of the second superconducting material layer.

19. The quantum device fabrication method of claim 18, wherein, The step of removing the natural oxide film on the surface of the second superconducting material layer comprises: performing ion beam etching on the surface of the second superconducting material layer.

20. The quantum device fabrication method of claim 17, wherein, Before the step of forming the second solder layer on the second barrier layer, the method further comprises: removing a natural oxide film on a surface of the second barrier layer.

21. The quantum device fabrication method of claim 20, wherein, The step of removing the natural oxide film on the surface of the second barrier layer comprises: performing ion beam etching on the surface of the second barrier layer.

22. The quantum device fabrication method of claim 9, wherein, Before the step of applying a force between the first substrate and the second substrate, the method further comprises: removing a native oxide film located on a surface of the first interconnection element and the second interconnection element.

23. The quantum device fabrication method of claim 22, wherein, The silicon pillar is an integral structure with the first substrate or the second substrate.

24. A quantum computer, comprising: The quantum computer comprises a quantum device according to any one of claims 1-8, or a quantum device obtained according to the method of any one of claims 9-23.

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