III-nitride multi-wavelength LED array with etch stop layer

Abstract

An LED array includes a first mesa, the first mesa including: a top surface, at least one first LED, and a tunnel junction on the first LED, the at least one first LED including a first p-type layer, a first n-type layer, and a first color active region; a second n-type layer on the tunnel junction, the second n-type layer including at least one n-type III-nitride layer with an Al mole fraction >10% and at least one n-type III-nitride layer with an Al mole fraction <10%. The LED array also includes an adjacent mesa, the adjacent mesa including a top surface, a first LED, a second LED, the second LED including a second n-type layer, a second p-type layer, and a second color active region. A first groove separates the first mesa and the adjacent mesa, a cathode metallization is in the first groove and electrically contacts the first and second color active regions of the adjacent mesa, and an anode metallization contacts the n-type layer of the first mesa and the anode layer of the adjacent mesa. The device and its manufacturing method include a thin film transistor (TFT).

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to light emitting diode (LED) device arrays and methods of making the same. More particularly, embodiments relate to light emitting diode device arrays including a group III nitride layer on a wafer that provide microLEDs including tunnel junctions. Background Art

[0002] A light emitting diode (LED) is a semiconductor light source that emits visible light when an electric current flows through it. LEDs combine a p-type semiconductor with an n-type semiconductor. LEDs typically use Group III compound semiconductors. Group III compound semiconductors provide stable operation at higher temperatures than devices using other semiconductors. Group III compounds are typically formed on a substrate formed of sapphire or silicon carbide (SiC).

[0003] A variety of emerging display applications, including wearable devices, head-mounted displays, and large-area displays, require miniaturized chips consisting of high-density microLED (μLED or uLED) arrays with lateral dimensions as low as less than 100μm×100μm. The diameter or width of a microLED (uLED) is typically about 50μm or less, and is used to make color displays by closely arranging microLEDs containing red, blue, and green wavelengths. Generally, two methods have been used to assemble displays consisting of individual microLED dies. The first is a pick-and-place method that includes picking up each individual blue, green, and red wavelength microLED and then aligning and attaching each individual blue, green, and red wavelength microLED to a backplane, which is then electrically connected to a driver integrated circuit. Due to the small size of each microLED, this assembly sequence is slow and prone to manufacturing errors. In addition, as the die size decreases to meet the ever-increasing resolution requirements of displays, an increasing number of dies must be transferred in each pick-and-place operation to populate the required size of the display.

[0004] Alternatively, to avoid complex pick and place mass transfer processes, various monolithic fabrication methods have been proposed to realize microLED displays. It would be desirable to provide LED devices and methods of manufacturing LED devices that provide monolithic fabrication methods. Summary of the invention

[0005] Embodiments of the present disclosure are directed to LED arrays and methods for manufacturing LED arrays. In a first embodiment, a light emitting diode (LED) array includes: a first mesa, the first mesa including a top surface, at least one first LED, and a first tunnel junction on the first LED, the at least one first LED including a first p-type layer, a first n-type layer, and a first color active region, the top surface of the first mesa including a second n-type layer on the first tunnel junction, the second n-type layer including at least one n-type III-nitride layer with an Al mole fraction > 10% and at least one n-type III-nitride layer with an Al mole fraction < 10%; an adjacent mesa, which includes a top surface, a first LED, a second LED, the second LED including a second n-type layer, a second p-type layer, and a second color active region; a second tunnel junction on the second LED of the adjacent mesa, and a third n-type layer on the second tunnel junction of the adjacent mesa; a first trench separating the first mesa and the adjacent mesa; and an anode contact on the second n-type layer of the first mesa and on the top surface of the adjacent mesa. In some embodiments, the LED array also includes a TFT driver, the TFT driver including a drive transistor, a capacitor, and a select transistor, the drive transistor having a second electrode and a capacitor connected to V DD A first electrode of the line, the capacitor is connected to a second electrode of the drive transistor and to a first electrode of a select transistor, the select transistor having a first electrode and a second electrode, the second electrode of the select transistor being connected to the data line, wherein the select transistor is configured to be controlled by the select line, wherein the second electrode of the drive transistor is connected to one of the anode contacts.

[0006] In a second embodiment, the first embodiment is modified so that the top surfaces of adjacent mesas include a third n-type layer.

[0007] In a third embodiment, the first embodiment also includes: a third color active area on the n-type layer of an adjacent mesa, and the adjacent mesa includes a top surface including a third p-type layer; a third mesa including a first LED, a second LED, a second tunnel junction, and a third n-type layer on the second tunnel junction; a second trench separating the adjacent mesa and the third mesa; cathode metallization in the first trench and in electrical contact with the first color active area and the second color active area of ​​the adjacent mesa; cathode metallization in the second trench and in electrical contact with the first color active area and the second color active area of ​​the third mesa, and cathode metallization in the first trench in electrical contact with the first color active area, the second color active area, and the third color active area of ​​the adjacent mesa; and an anode contact on the third n-type layer of the third mesa.

[0008] In a fourth embodiment, the third embodiment includes the following features: the third p-type layer of the adjacent mesa is a non-etched p-type layer. In a fifth embodiment, the third or fourth embodiment is modified, wherein the first color active area is a blue active area, and the second color active area is a green active area. In a sixth embodiment, the third or fourth embodiment is modified, wherein the first color active area is a blue active area, the second color active area is a green active area, and the third color active area is a red active area.

[0009] In a seventh embodiment, any one of the first to sixth embodiments is modified such that the first p-type layer, the second p-type layer, the first n-type layer, and the second n-type layer include a Group III nitride material. In an eighth embodiment, the seventh embodiment includes the following features: the Group III nitride material includes GaN. In a ninth embodiment, any one of the third to sixth embodiments includes the following features: the first p-type layer, the second p-type layer, the third p-type layer, the first n-type layer, the second n-type layer, and the third n-type layer include a Group III nitride material. In a tenth embodiment, the ninth embodiment includes the Group III nitride material including GaN.

[0010] In an eleventh embodiment, any one of the first to tenth embodiments includes the following features: the first mesa has a sidewall and the adjacent mesa has a sidewall, and the first mesa sidewall and the adjacent mesa sidewall form an angle in a range from 60 degrees to less than 90 degrees with the top surface of the substrate on which the mesa is formed.

[0011] In a twelfth embodiment, any one of the first to eleventh embodiments includes the following features: the n-type III-nitride layer having an Al mole fraction of >10% has a molecular formula of Al x Ga 1-x N, wherein x is in the range from 0.20 to 0.25.

[0012] Another aspect of the present disclosure relates to an electronic system, and in a thirteenth embodiment, the electronic system includes the LED array of any one of the first to twelfth embodiments and a driver circuit configured to provide independent voltages to one or more anode contacts. In a fourteenth embodiment, the thirteenth embodiment includes the feature that the electronic system is selected from the group consisting of an LED-based lamp, a light strip, a light sheet, an optical display, and a microLED display.

[0013] Another aspect relates to a method for manufacturing an LED array. In a fifteenth embodiment, a method includes: forming a first mesa, the first mesa including a top surface, at least one first LED, and a first tunnel junction on the first LED, the at least one first LED including a first p-type layer, a first n-type layer, and a first color active region, the top surface including a second n-type layer on the first tunnel junction; forming an adjacent mesa, the adjacent mesa including a first LED, a second LED, the second LED including a second n-type layer, a second p-type layer, and a second color active region, the second n-type layer including at least one n-type III-nitride layer with an Al mole fraction > 10% and at least one n-type III-nitride layer with an Al mole fraction < 10%; forming a second tunnel junction on the second LED of the adjacent mesa, and forming a third n-type layer on the second tunnel junction of the p-type layer of the adjacent mesa; forming a first trench separating the first mesa and the adjacent mesa; and forming an anode contact on the second n-type layer of the first mesa and on the third n-type layer of the adjacent mesa.

[0014] In a sixteenth embodiment, the fifteenth embodiment further includes forming a top surface of the adjacent mesa including a third n-type layer. In the seventeenth embodiment, the fifteenth or sixteenth embodiment also includes forming a third color active area on the n-type layer of an adjacent mesa, and the adjacent mesa includes a top surface including a third p-type layer; forming a third mesa, the third mesa including a top surface, a first LED, a second LED, a second tunnel junction, and including a third n-type layer on the second tunnel junction, and a third color active area, the top surface of the third mesa including the third n-type layer; forming a second trench separating the adjacent mesa and the third mesa; forming a cathode metallization in the first trench, which is electrically in contact with the first color active area and the second color active area of ​​the adjacent mesa; forming a cathode metallization in the second trench that is electrically in contact with the first color active area and the second color active area of ​​the third mesa, and forming an n-type metallization in the first trench that is electrically in contact with the first color active area, the second color active area and the third color active area of ​​the second adjacent mesa, and forming a cathode metallization in the first trench that is electrically in contact with the third color active area; and forming an anode contact on the third n-type layer of the third mesa. In some embodiments, the method further includes forming a TFT driver, the TFT driver including a drive transistor, a capacitor, and a select transistor, the drive transistor having a second electrode and a capacitor connected to V DD A first electrode of the line, the capacitor is connected to a second electrode of the drive transistor and to a first electrode of a select transistor, the select transistor having a first electrode and a second electrode, the second electrode of the select transistor being connected to the data line, wherein the select transistor is configured to be controlled by the select line, wherein the second electrode of the drive transistor is connected to one of the anode contacts.

[0015] In an eighteenth embodiment, the seventeenth embodiment is such that each of the first LED, the second LED, and the third LED comprises an epitaxially deposited III-nitride material. In a nineteenth embodiment, the first LED, the second LED, and the third LED are formed on a substrate. In a twentieth embodiment, the nineteenth embodiment is such that the first trench and the second trench are formed by etching a trench to form a first mesa, an adjacent mesa, and a third mesa. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To facilitate a detailed understanding of the above-listed features of the present disclosure, the present disclosure briefly summarized above may be described in more detail with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and therefore should not be considered to limit its scope, as the present disclosure may allow for other equivalent embodiments. The embodiments as described herein are illustrated in the figures of the accompanying drawings by way of example and not limitation, in which similar reference numerals indicate similar elements.

[0017] Figure 1 shows a cross-sectional view of red, green and blue LED devices including multiple quantum wells according to one or more embodiments;

[0018] Figure 2 Shown in Figure 1 A sacrificial layer and an etching mask formed on the LED device;

[0019] Figure 3 Shows Figure 2 The device provides three mesas after an etching process to form an LED array;

[0020] Figure 4A Shows Figure 3 A conformal dielectric layer on three mesas of an LED array;

[0021] Figure 4B Shows Figure 4A an enlarged view of region 117;

[0022] Figure 4C Shows Figure 4A Alternative embodiments of LED arrays;

[0023] Figure 4D Shows Figure 4C an enlarged view of region 119;

[0024] Figure 5 Shown in Figure 4A After etching openings in the dielectric layer of the device, Figure 4A LED array;

[0025] Figure 6shows the cathode metallization deposited in the opening Figure 5 LED array;

[0026] Figure 7 shows that after electrodeposition of the conductive metal Figure 6 LED array;

[0027] Fig. 8A An LED array including a first mesa and a second mesa after anode formation is shown;

[0028] Figure 8B shows that after the p-contact is formed Figure 7 LED array;

[0029] Fig. 9 shows the connection to the backplane Figure 7 LED array;

[0030] Fig.10 shows a top view of an electronic device including an LED array configured to emit two or more colors according to one embodiment;

[0031] Fig.11 Shows Fig.10 Part A of

[0032] Fig.12 shows a side view of an electronic device including an LED array and one or more TFT drivers according to one embodiment;

[0033] Fig.13 An embodiment of an electronic device including an LED array and a TFT driver is shown; and

[0034] Fig.14 Shows Fig.13 Part B of DETAILED DESCRIPTION

[0035] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0036] According to one or more embodiments, the term "substrate" as used herein refers to an intermediate or final structure having a surface or a portion of a surface on which a process is performed. Additionally, in some embodiments, reference to a substrate also refers to only a portion of a substrate, unless the context clearly indicates otherwise. Furthermore, according to some embodiments, reference to depositing on a substrate includes depositing on a bare substrate, or depositing on a substrate having one or more layers, films, features, or materials deposited or formed thereon.

[0037] In one or more embodiments, "substrate" means any substrate or material surface formed on a substrate on which film processing is performed during a fabrication process. In exemplary embodiments, depending on the application, the substrate surface on which processing is performed includes materials such as silicon, silicon oxide, silicon on insulator (SOI), strained silicon, amorphous silicon, doped silicon, carbon-doped silicon oxide, germanium, gallium arsenide, glass, sapphire, and any other suitable material (such as metals, metal nitrides, group III-nitrides (e.g., GaN, AlN, InN, and other alloys), metal alloys, and other conductive materials). Substrates include, but are not limited to, light emitting diode (LED) devices. In some embodiments, the substrate is exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in some embodiments, any of the disclosed film processing steps is also performed on an underlying layer formed on the substrate, and the term "substrate surface" is intended to include such an underlying layer as indicated by the context. Thus, for example, where a film / layer or portion of a film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0038] In this disclosure, the terms "wafer" and "substrate" will be used interchangeably. Thus, as used herein, a wafer is used as a substrate to form the LED devices described herein.

[0039] The embodiments described herein describe arrays of LED devices and methods for forming arrays of LED devices (or LED arrays). In particular, the present disclosure describes LED devices and methods for manufacturing LED devices that emit multiple colors or wavelengths from a single wafer. The position and size of LED devices that emit multiple colors or wavelengths are controlled by adjusting the photolithography steps and etching depth after epitaxial deposition of the material forming the LED device. In some embodiments, adjacent LEDs that emit multiple colors or wavelengths use a common n-type electrical contact. In some embodiments, LEDs can be formed using a process that does not require substrate removal. One or more embodiments of the present disclosure can be used to make microLED displays.

[0040] In one or more embodiments, a less complex microLED manufacturing process is provided by utilizing LED devices and methods for manufacturing the same, i.e., integrating two or more active regions emitting different wavelengths on a single wafer. The devices and methods described in accordance with one or more embodiments utilize Group III nitride materials, such as materials in the AlInGaN material system, which can be manufactured to form blue, green, and red LEDs. The embodiments described herein provide a multicolor device (e.g., a chip) that can be used in a microLED display. In one or more embodiments, multiple layers are stacked in a single epitaxial growth process, and the multiple layers are configured to emit at different wavelengths. A device configured such that the corresponding emission intensity ratio between emitters of different wavelengths can be changed is provided.

[0041] According to one or more embodiments, devices and methods provide a multiple quantum well (MQW) configured to emit red, green, and blue light within a single active region (i.e., between the p-layer and n-layer of a pn junction). In one or more embodiments, two or more pixels of different wavelengths are formed in the same LED device, which includes several pn junctions on the same epitaxial wafer. By etching the mesa using multiple steps as further described herein, an embodiment provides for the formation of independent electrical contacts to each pn junction. According to one or more embodiments, one or more emitter layers of different wavelengths are embedded in separate pn junctions with separate current paths, so that the wavelength and radiation are independently controlled.

[0042] Figure 3 Exemplary embodiments of LED arrays are shown that are configured to emit two or more different colors adjacent to each other on the same wafer. Several pn junctions and active regions are stacked on top of each other, which are made sequentially by epitaxial growth in some embodiments, with unnecessary layers removed by post-growth etching. In one or more embodiments, methods are provided for opening trenches for contacting buried layers using dry etching. However, it has been found that the dry etching process introduces atomic-level damage to the III-nitride crystal structure of the epitaxial layer, which changes the conductivity type of the p-type layer to the n-type layer.

[0043] Due to this conductivity type conversion during dry etching, it is not possible to obtain a low resistance ohmic contact with the buried p-type nitride surface that has been exposed by dry etching. Figure 3In an LED array 109 of the type shown, damage to the p-GaN surface is caused by dry etching processing, and the non-ohmic contact with the dry-etched p-GaN surface causes a forward voltage loss of one volt or more in the blue and green active regions. Even if the voltage loss is acceptable to the device manufacturer, the p-GaN layer will have to be grown much thicker than the optimal thickness to provide sufficient error margin in controlling the etch rate to ensure that the etch stops in the p-GaN layer.

[0044] According to one or more embodiments, by incorporating tunnel junctions into the epitaxial layer, Figure 3 The functionality shown, but without the difficulties associated with trying to make electrical contact to an etched p-GaN surface. In a specific embodiment, electrical contact is made to an n-type GaN layer, which can be grown to a considerable thickness without damaging the active area or incurring optical absorption losses. Embodiments of the lithography and etching methods described herein allow for the fabrication of LEDs configured to emit different colors at adjacent locations on the same wafer. A common n-type electrical contact is made to a set of different LED colors without requiring substrate removal.

[0045] According to one or more embodiments, an LED array and a manufacturing process thereof are provided that result in a reduction in the number of separate epitaxial recipes that must be manufactured to produce source dies for a microLED display, as compared to existing methods. The reduction in the number of epitaxial recipes reduces the cost and complexity in the epitaxial manufacturing stage of LED array manufacturing. Existing methods require the generation of separate blue, green, and red epitaxial recipes. In one or more embodiments, the number of pick and place operations required to populate a display is reduced because the pixel array can be transferred together, rather than just one pixel at a time. Fewer pick and place operations will result in improved costs and yields in the display assembly stage. In some embodiments, the need for pick and place operations is completely eliminated, and embodiments instead allow for the transfer of pixels on a display at the entire wafer level, because each wafer can contain all three required colors (red, blue, and green). In such an embodiment, the entire processed wafer or a large piece of it can be directly incorporated into the display. According to one or more embodiments, the problem of having to make ohmic electrical contacts to the etched p-GaN surface is avoided, making lower operating voltages and higher wall plug efficiency possible. In some embodiments, since all etched contacts in the tunnel junction are made of n-GaN layers, which can be grown much thicker than p-GaN layers while maintaining high LED efficiency, the constraints on the control of the etch rate are relaxed.

[0046] Thus, one or more embodiments provide a III-nitride based LED, such as a GaN based LED wafer, comprising two or more separate active regions configured to emit different colors, the active regions being grown sequentially and connected by a tunnel junction. Embodiments provide a multi-level mesa etching process that allows independent electrical contact to be made to each separate active region, thereby producing two or three different color LEDs in close proximity to each other on the same wafer. One or more embodiments include making n-type electrical contacts to the sidewalls of the etched mesas, rather than making contacts to the planar n-type III-nitride (e.g., GaN) surface. A common n-contact made from the side of the wafer opposite the substrate side can be used for the entire array of red, green, and blue LED mesas.

[0047] One aspect of the present disclosure relates to a method for manufacturing an LED array. Figure 1 , an LED device 100 is manufactured by forming a plurality of Group III nitride layers on a substrate 101 to form a plurality of LEDs on a substrate including color active regions. The color active regions include a first color active region 124, a second color active region 114, and a third color active region 104. Although any order of stacking different color active regions is within the scope of the present disclosure, in a specific embodiment, for a device emitting toward a substrate 101 on which these layers are formed, the color active region of the shortest emission wavelength is the first color active region grown in the order in which two or more color active regions are formed. Therefore, in one or more embodiments, the first color active region 124 is first formed on the substrate and is a blue active region, and then the second color active region 114 (which is a green active region) is formed, and then the third color active region 104 (which is a red active region) is formed. This order of first color active region 124 being blue, second color active region 114 being green, and third color active region 104 being red avoids emission from blue active region 124 being internally absorbed by longer wavelength color active regions.

[0048] Thus, according to some specific embodiments, the LED device 100 includes a first LED, which includes a first n-type layer 126 formed on a substrate, a first p-type layer 122 formed on the first n-type layer 126, and a first color active region 124 between the first n-type layer 126 and the first p-type layer 122. In one or more embodiments, the first color active region 124 is a blue active region. In the illustrated embodiment, a first tunnel junction 120 is present on the first LED, particularly on the first p-type layer 122. A tunnel junction is a structure that allows electrons to tunnel from the valence band of the p-type layer to the conduction band of the n-type layer under reverse bias. The location where the p-type layer and the n-type layer are adjacent to each other is called a p / n junction. When electrons tunnel, holes are left in the p-type layer, so that carriers are generated in both regions. Therefore, in a diode-like electronic device, in which only a small leakage current flows under reverse bias, a large current can be transmitted across the tunnel junction under reverse bias. The tunnel junction includes a specific alignment of the conduction band and the valence band at the p / n tunnel junction. This can be achieved by using very high doping (e.g., in a p++ / n++ junction). In addition, III-nitride materials have an intrinsic polarization that generates an electric field at the heterointerface between the different alloy components. This polarization field can also be used to achieve band alignment for tunneling.

[0049] Still refer to Figure 1 , the LED device 100 further includes a second LED, which includes a second n-type layer(s) 116 on the first tunnel junction 120, a second p-type layer 112 formed on the second n-type layer(s) 116, and a second color active region 114 between the second n-type layer(s) 116 and the second p-type layer 112. In one or more embodiments, the second color active region 114 is a green active region. In the illustrated embodiment, there is a second tunnel junction 110 on the second LED, particularly on the second p-type layer 112. The LED device 100 further includes a third LED, which includes a third n-type layer 106 formed on the second tunnel junction 110, a third p-type layer 102 formed on the third n-type layer 106, and a third color active region 104 between the third n-type layer 106 and the third p-type layer 102. In one or more embodiments, the third color active region 104 is a green active region.

[0050] The substrate 101 can be any substrate known to those skilled in the art, which is configured to be used in the formation of a III-nitride LED device. In one or more embodiments, the substrate includes one or more of sapphire, silicon carbide, silicon dioxide (Si), quartz, magnesium oxide (MgO), zinc oxide (ZnO), spinel, etc. In a specific embodiment, the substrate 101 includes sapphire. In one or more embodiments, the substrate 101 is not patterned before the LED is formed on the top surface 101t of the substrate 101. Therefore, in some embodiments, the substrate 101 is not patterned and can be considered to be flat or substantially flat. In other embodiments, the substrate 101 is a patterned substrate.

[0051] In one or more embodiments, the n-type layer and the p-type layer of each of the first LED, the second LED, and the third LED each include a layer of a group III nitride material. In some embodiments, the group III nitride material includes one or more of gallium (Ga), aluminum (Al), and indium (In). Therefore, in some embodiments, the n-type layer and the p-type layer of the corresponding LED include one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), gallium aluminum nitride (GaAlN), gallium indium nitride (GaInN), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), indium aluminum nitride (InAlN), etc. In a specific embodiment, the n-type layer and the p-type layer of the corresponding LED include n-doped GaN and p-doped GaN.

[0052] In one or more embodiments, the III-nitride material layer forming the first LED, the second LED and the third LED is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0053] As used herein, "sputter deposition" refers to a physical vapor deposition (PVD) method of thin film deposition by sputtering. In sputter deposition, a material, such as a Group III nitride, is ejected from a target as a source onto a substrate. The technique is based on ion bombardment of the source material (target). The ion bombardment generates vapor due to a purely physical process, i.e., sputtering of the target material.

[0054] As used in accordance with some embodiments herein, "atomic layer deposition" (ALD) or "cyclic deposition" refers to a vapor phase technique for depositing a thin film on a substrate surface. The ALD process involves exposing a substrate surface or a portion of a substrate to alternating precursors, i.e., two or more reactive compounds, to deposit a layer of material on the substrate surface. When the substrate is exposed to alternating precursors, the precursors are introduced sequentially or simultaneously. The precursors are introduced into a reaction zone of a process chamber, and the substrate or a portion of the substrate is exposed to the precursors individually.

[0055] As used herein according to some embodiments, "chemical vapor deposition" refers to the process of depositing a film of material from a vapor phase by decomposition of a chemical on a substrate surface. In CVD, the substrate surface is exposed to precursors and / or co-reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" means that a large portion of the exposure of the precursors co-flows or there is overlap.

[0056] As used herein according to some embodiments, "plasma enhanced atomic layer deposition (PEALD)" refers to a technique for depositing a thin film on a substrate. In some examples of the PEALD process relative to the thermal ALD process, the material can be formed from the same chemical precursor, but at a higher deposition rate and a lower temperature. In general, the PEALD process introduces a reactant gas and a reactant plasma sequentially into a process chamber having a substrate in the chamber. The first reactant gas is pulsed in the processing chamber and adsorbed onto the surface of the substrate. Thereafter, the reactant plasma is pulsed into the processing chamber and reacts with the first reactant gas to form a deposited material, such as a thin film on a substrate. Similar to the thermal ALD process, a purge step can be performed between the delivery of each reactant.

[0057] As used herein according to one or more embodiments, "plasma enhanced chemical vapor deposition (PECVD)" refers to a technique for depositing a thin film on a substrate. In a PECVD process, a source material in a gas phase or liquid phase, such as a vapor of a gas phase III-nitride material or a liquid phase III-nitride material, is introduced into a PECVD chamber, where the gas phase or liquid phase III-nitride material has been entrained in a carrier gas. A plasma-induced gas is also introduced into the chamber. The generation of a plasma in the chamber generates excited free radicals. The excited free radicals chemically bond to the surface of the substrate located in the chamber, forming a desired film thereon.

[0058] In one or more embodiments, the LED device 100 that will form the LED array is manufactured by placing the substrate 101 in a metal organic vapor phase epitaxy (MOVPE) reactor so that the LED device layer is epitaxially grown. The first n-type layer 126 includes one or more layers of semiconductor materials including different compositions and doping concentrations. In a specific embodiment, the first n-type layer 126 is formed by growing an epitaxial layer of a group III nitride (e.g., n-GaN). The first p-type layer 122 includes one or more layers of semiconductor materials including different compositions and doping concentrations. In a specific embodiment, the first p-type layer 122 is formed by growing an epitaxial layer of a group III nitride (e.g., p-GaN). In use, a current is passed through the pn junction in the first color active region 124, and the first color active region 124 generates light of a first wavelength determined in part by the band gap energy of the material. In some embodiments, the first LED including the first n-type layer 126, the first p-type layer 122, and the first color active region 124 includes one or more quantum wells. In one or more embodiments, the first color active region 124 is configured to emit blue light.

[0059] In a specific embodiment, after the formation of the first p-type layer 122 including the p-GaN layer of the blue LED is completed, the epitaxial growth conditions are then modified to grow the first tunnel junction 120. A second LED is then formed, which includes a second n-type layer(s) 116, a second p-type layer 112, and a second color active region 114 between the second n-type layer(s) 116 and the second p-type layer 112. The second n-type layer(s) 116 are formed by growing an epitaxial layer of a Group III nitride, such as n-GaN.

[0060] In one or more embodiments, it is necessary to substantially increase the thickness of the second n-type layer(s) 116 to offset any increase in the thickness of the third n-type layer 106, thereby ensuring sufficient etching margin in both layers. For etching margin purposes, it is not practical to arbitrarily increase the thickness of the third n-type layer 106 and the second n-type layer(s), 116, because the internal quantum efficiency (IQE) of the second color active region 114 and the first color active region 124 may be reduced due to the long growth time of the third n-type layer 106 and the second n-type layer(s), 116.

[0061] In one or more embodiments, Figure 1As shown, the design of the second n-type layer(s) 116 may be modified instead of increasing the thickness of the third n-type layer 106 and the second n-type layer(s) 116. The second n-type layer(s) 116 may be a multilayer system comprising at least one n-type III-nitride layer 116b having an Al mole fraction of >10% and at least one n-type III-nitride layer 116a having an Al mole fraction of <10%. In one or more specific embodiments, the n-type III-nitride layer 116b having an Al mole fraction of >10% has a molecular formula of Al x Ga 1-x N, wherein x is in the range from 0.20 to 0.25.

[0062] In one or more embodiments, the thickness of the at least one n-type III-nitride layer 116c having an Al mole fraction <10% is selected to provide sufficient current spreading across the first mesa 103, plus a small margin associated with the thickness that can be removed when etching through the Al-containing layer under non-selective conditions (if applicable). Although the actual thickness used will depend on factors such as the area of ​​the pixel and the conductivity of the at least one n-type III-nitride layer 116c having an Al mole fraction <10%, a thickness in the range of from 50 to 500 nm may be relevant for some applications.

[0063] In one or more embodiments, the thickness of at least one n-type III-nitride layer 116a with an Al mole fraction > 10% is in the range from 25 to 75 nm, but the actual thickness used will depend on the distance from the top of the third p-type layer 102 to the (multiple) second n-type layer 116 and the etch rate selectivity specific to the process conditions. In one or more embodiments, at least one n-type III-nitride layer 116a with an Al mole fraction < 10% is optionally used to avoid possible internal quantum efficiency (IQE) losses associated with growing active region layers directly on Al-containing layers. In one or more embodiments, the thickness of at least one n-type III-nitride layer 116a with an Al mole fraction < 10% is in the range from 5 nm to 50 nm. In one or more embodiments, the layer 116b with > 10% Al is etched slowly ("etch stop" layer) and ensures that the etching ends at almost the same depth at all locations on the substrate, despite variations in etch rate or epitaxial layer thickness across the substrate radius. In one or more embodiments, an optional layer 116a with <10% Al may be placed between the higher percentage Al layer and the active region to avoid IQE loss in the active region.

[0064] The second p-type layer 112 includes one or more layers of semiconductor materials including different compositions and doping concentrations. In a specific embodiment, the second p-type layer 112 is formed by growing an epitaxial layer of a group III nitride (e.g., p-GaN). In use, a current is passed through the pn junction in the second color active region 114, and the second color active region 114 generates light of a second wavelength determined in part by the bandgap energy of the material. In some embodiments, a second LED including (multiple) second n-type layers 116, a second p-type layer 112, and a second color active region 114 includes one or more quantum wells. In one or more embodiments, the second color active region 114 is configured to emit green light. According to some embodiments, the formation of the second LED includes changing the thickness and / or growth conditions of (multiple) second n-type layers 116. In one or more embodiments, the LED device 100 to form the LED array is manufactured by placing the substrate 101 in a metal organic vapor phase epitaxy (MOVPE) reactor so that the LED device layer grows epitaxially. In one or more embodiments, the aluminum mole fraction of the second n-type layer(s) 116a, 116b, 116c is controlled by adjusting the flow of precursor molecules (eg, trimethylaluminum) relative to the flow of other Group III element precursor molecules.

[0065] In a specific embodiment, after the formation of the second p-type layer 112 comprising the p-GaN layer of the green LED is completed, the epitaxial growth conditions are then modified to grow the second tunnel junction 110. A third LED is then formed, which includes a third n-type layer 106, a third p-type layer 102, and a third color active region 104 between the third n-type layer 106 and the third p-type layer 102. The third n-type layer 106 is formed by growing an epitaxial layer of a group III nitride (e.g., n-GaN). The third p-type layer 102 includes one or more layers of semiconductor materials comprising different compositions and doping concentrations. In a specific embodiment, the third p-type layer 102 is formed by growing an epitaxial layer of a group III nitride (e.g., p-GaN). In use, a current is caused to flow through the pn junction in the third color active region 104, and the third color active region 104 generates light of a third wavelength determined in part by the bandgap energy of the material. In some embodiments, a third LED including a third n-type layer 106, a third p-type layer 102, and a third color active region 104 includes one or more quantum wells. In one or more embodiments, the third color active region 104 is configured to emit red light. According to some embodiments, the formation of the third LED includes changing the thickness and / or growth conditions of the third n-type layer 106.

[0066] The present disclosure is not limited to any particular epitaxial design of the first tunnel junction 120 and the second tunnel junction 110 or the LED color active region. According to one or more embodiments, after the epitaxial growth of the first LED, the second LED, and the third LED, a series of photolithography and dry etching processes are used to form the LED array 109, such as Figure 2 - Figure 8. The final result of the photolithography and dry etching process is an array of mesas with different heights, such as Figure 8B For a specific emission color, the unneeded quantum wells and pn junctions are etched away in some of the mesas, which results in mesas with different heights.

[0067] Depending on the embodiment, various options may be used in the photolithography and dry etching processes, as will be discussed below. Figure 2 - Conventional processing steps, such as photoresist exposure, development, stripping and cleaning steps, have been omitted in FIG8. In one embodiment of the etching process, the first sacrificial layer 125a is patterned over a portion of the third p-type layer 102 where a mesa with a maximum height is desired, such as Figure 2 The second sacrificial layer 125b is patterned by a portion of the third p-type layer 102, wherein the height of the adjacent mesas is greater than the height of the first mesas. The height of the first sacrificial layer 125a is greater than the height of the second sacrificial layer 125b.

[0068] After forming the first sacrificial layer 125a and the second sacrificial layer 125b, an etching mask layer 127 is deposited on the third p-type layer 102 not covered by the first sacrificial layer 125a and the second sacrificial layer 125b, as shown in FIG. Figure 2 As shown. In the illustrated embodiment, both the material forming the etch mask layer 127 and the material forming the first sacrificial layer 125a and the second sacrificial layer 125b are affected by the dry etching chemistry. Therefore, for an etching time that is long enough to etch through the etch mask layer 127 and / or the sacrificial layer, the depth of etching into the epitaxial wafer depends on the thickness of the etch mask layer and the sacrificial layer. Adjacent mesas with different heights can then be obtained by a single dry etching step using the thickness of the sacrificial layer and the difference in etching rates between the sacrificial layer, the etch mask layer, and the epitaxial forming layers of the first LED, the second LED, and the third LED to control the height of each mesa. Reference Figure 3, the first mesa 103 has a first height represented by H, the adjacent mesa 105 has a second height, and the third mesa 107 has a third height. In the illustrated embodiment, the first height H of the first mesa 103 is less than the second height of the adjacent mesa 105 and the third height of the third mesa 107. The second height of the adjacent mesa 105 is greater than the third height of the third mesa 107. Therefore, the first mesa 103 is the shortest of the three mesas. The first trench 111 separates the first mesa 103 and the adjacent mesa 105, and the second trench 113 separates the adjacent mesa 105 and the third mesa 107. The first mesa 103 has a sidewall 103s, the adjacent mesa 105 has a sidewall 105s, and the third mesa 107 has a sidewall 107s. In one or more embodiments, the sidewalls 103s, 105s, and 107s are angled relative to the top surface 101t of the substrate. The sidewall 103 s of the first mesa 103 , the sidewall 105 s of the adjacent mesa 105 , and the sidewall 107 s of the third mesa 107 each form an angle “a” in a range from 75 degrees to less than 90 degrees with the top surface 101 t of the substrate 101 .

[0069] In referring to Fig. 8A In some of the embodiments discussed, there is a first mesa 103 and an adjacent mesa 105. Thus, in such embodiments, during the manufacturing process, only the first sacrificial layer is utilized and only the first trench is formed.

[0070] At the first trench 111 and the second trench 113, the etching process actually stops at the substrate 101 because the substrate is hardly affected by the etching under the conditions used to etch the III-nitride epitaxial layer. In one or more embodiments, the etching mask layer 127, the first sacrificial layer 125a and the second sacrificial layer 125b are made of the same material or different materials. Photoresist or dielectric materials (such as silicon dioxide and silicon nitride) can be used as suitable etching mask materials for the mask and etching process.

[0071] In an alternative embodiment of the etching process, the first mesa 103, the adjacent mesa 105, and the third mesa 107, each having a different height, are processed in separate dry etching steps. In the first etching step, mesas of the same height are produced. The first etching step is stopped, and some of the mesas are re-masked to prevent their height from being reduced in subsequent etching steps. The mask layer is not completely etched through during the process, and in some embodiments includes a material that is not affected by the etching chemistry. This alternative embodiment shows a slower manufacturing yield than the embodiment described in the previous paragraph, but shows less stringent control over parameters such as mask and sacrificial layer thickness and etching rate selectivity.

[0072] exist Figure 3After the mesa etching process shown and appropriate cleaning steps are completed, activation of the buried p-type layer is achieved by laterally diffusing hydrogen through the etched sidewalls of the buried p-type layer. According to one or more embodiments, the mesas are annealed after the mesa etching rather than earlier in the process because the spaces between the mesas allow efficient paths for lateral diffusion and escape of hydrogen from the p-type layer. The annealing can be similar to the annealing of conventional LEDs, or higher temperatures and / or longer times can be used.

[0073] Reference Figure 4A After the activation annealing of the p-type layer, a conformal coating of a dielectric layer 130 (e.g., silicon dioxide) is deposited over the mesas and their sidewalls using methods such as plasma enhanced chemical vapor deposition, atomic layer deposition, or sputtering. The dielectric layer 130 isolates the metal contacts from each other, which will be fabricated in later process steps.

[0074] As used herein, the term "dielectric" refers to an electrical insulator material that can be polarized by an applied electric field. In one or more embodiments, the dielectric layer includes, but is not limited to, oxides, such as silicon oxide (SiO2), aluminum oxide (Al2O3); nitrides, such as silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes silicon nitride (Si3N4). In one or more embodiments, the dielectric layer includes silicon oxide (SiO2). In some embodiments, the dielectric layer components are non-stoichiometric relative to the ideal chemical formula. For example, in some embodiments, the dielectric layer includes, but is not limited to, oxides (e.g., silicon oxide, aluminum oxide), nitrides (e.g., silicon nitride (SiN)), carbon oxides (e.g., silicon oxycarbide (SiOC)) and nitrogen oxides (e.g., silicon oxycarbonitride (SiNCO)).

[0075] In one or more embodiments, the dielectric layer 130 is deposited by one or more of sputtering deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced atomic layer deposition (PEALD), and plasma enhanced chemical vapor deposition (PECVD).

[0076] Manufactured with high manufacturing yields Figure 4A The LED arrays shown require precise control of the etch depth, which can sometimes be challenging to implement depending on the etching equipment used. In some embodiments, there is a variation in the etch rate from the center to the edge of the wafer. There may also be wafer center / edge variations in the thickness of the epitaxial layer that needs to be etched.

[0077] The production of third mesa 107 requires an etch ("etch A") which should ideally end within third n-type layer 106. If etch A does not completely remove layer 104, the result is a rectifying anode contact which results in a high V fOn the other hand, if etch A proceeds too deeply, etching mostly or completely through third n-type layer 106, then the result will also be high V due to high current diffusion resistance and / or contact resistance. f Making the etch A repeatable from wafer to wafer and uniform across wafer area can be important in some embodiments for obtaining a etch with acceptable V f In one or more embodiments, increasing the thickness of the third n-type layer 106 solves these problems. However, in some embodiments, increasing the thickness of the third n-type layer 106 increases the difficulty of manufacturing the first mesa 103.

[0078] In one or more embodiments, the first mesa 103 is made in the same etch A as the third mesa 107. Due to the time required to etch through the sacrificial layer, a sacrificial layer is coated on top of the third mesa 107 prior to etching so that the depth of the third mesa 107 is shallower than the first mesa 103. The negative consequences of over-etching or under-etching in the first mesa 103 are the same as those discussed above for the third mesa 107. In one or more embodiments, the first mesa 103 is more difficult because the required etching is deeper. For a given etch rate non-uniformity, the difference in absolute depth of etching between the center and edge of the wafer increases with the etching duration. Excessive height differences between the mesas 103, 105 and 107 can also make it difficult to effectively integrate the RGB emitter unit with the driver circuit and collection optical devices.

[0079] As described above, in one or more embodiments, Figure 4A and Figure 4B As shown, the design of the second n-type layer(s) 116 may be modified instead of increasing the thickness of the third n-type layer 106 and the second n-type layer 116. In one or more embodiments, the second n-type layer(s) 116 is a multilayer system comprising at least one n-type III-nitride layer 116b having an Al mole fraction of >10% and at least one n-type III-nitride layer 116c having an Al mole fraction of <10%. In one or more specific embodiments, the n-type III-nitride layer 116b having an Al mole fraction of >10% has a molecular formula of Al x Ga 1-x N, wherein x is in the range from 0.20 to 0.25.

[0080] In one or more embodiments, for dry etching conditions with high chemical composition (low sputtering composition), GaN can be etched at a rate more than 5 times faster than AlGaN. The large difference in etching rate makes it possible for the etching process to always end up in the (multiple) second n-type layers 116 as expected, regardless of non-uniformities in the etching tool or the presence of Figure 4AThe thickness non-uniformity of the epitaxial layer above the second n-type layer 116 in the wafer is reduced. The anode contact of the first mesa 103 can be made directly to the exposed Al-containing layer. Alternatively, a short etching can be performed using non-selective etching conditions to penetrate the relatively thin Al-containing layer. Due to the consistent physical contact of the anode to the correct semiconductor layer, a tight distribution of forward voltage is obtained for pixels made at all locations on the wafer.

[0081] In one or more embodiments, the deep trenches 111, 113 extending to the substrate 101 are etched at a high etch rate condition with low selectivity. Due to the non-selective condition for the trench etching, it is not adversely affected by the inclusion of the Al-containing layer.

[0082] refer to Figure 4B , Figure 4B for Figure 4A 117, in one or more embodiments, the thickness of the at least one n-type III-nitride layer 116c having an Al mole fraction <10% is selected to provide sufficient current spreading across the first mesa 103, plus a small margin associated with the thickness that can be removed when etching through the Al-containing layer under non-selective conditions (if applicable). Although the actual thickness used will depend on factors such as the area of ​​the pixel and the conductivity of the at least one n-type III-nitride layer 116c having an Al mole fraction <10%, a thickness in the range of from 50 to 500 nm may be relevant for some applications.

[0083] In one or more embodiments, the thickness of the at least one n-type III-nitride layer 116a with an Al mole fraction > 10% is in a range from 25 to 75 nm, but the actual thickness used will depend on the distance from the top of the third p-type layer 102 to the (multiple) second n-type layer 116 and the etch rate selectivity specific to the process conditions. In one or more embodiments, the at least one n-type III-nitride layer 116a with an Al mole fraction < 10% is optionally used to avoid possible IQE losses associated with growing active region layers directly on Al-containing layers. In one or more embodiments, the thickness of the at least one n-type III-nitride layer 116a with an Al mole fraction < 10% is in a range from 5 nm to 50 nm.

[0084] refer to Figure 4C and Figure 4D In one or more embodiments, the third n-type layer 106 (in addition to the second n-type layer 116 ) may also be modified in the same manner as the second n-type layer 116 . Figure 4C and Figure 4DThe n-type layers 106a, 106b, and 106c are shown, wherein at least one n-type III-nitride layer 106a, 106b having an Al mole fraction of >10% and at least one n-type III-nitride layer 106c having an Al mole fraction of <10%. In one or more specific embodiments, the n-type III-nitride layer 106b having an Al mole fraction of >10% has a molecular formula of Al x Ga 1-x N, wherein x is in the range from 0.20 to 0.25.

[0085] For the same reasons as above, this change combined with the selective etching conditions will ensure the placement depth of the anode contact of the third mesa 107. However, the need for an etch stop layer in the third n-type layer 106 may be less critical because the required etching depth is much shallower in the first mesa 103 than in the third mesa 107. In one or more embodiments, as Figure 4C and Figure 4D As shown, modifying the third n-type layer 106 would require a more complex dry etching process that switches back and forth from selective to non-selective conditions several times. Alternatively, in other embodiments, the thickness of the third n-type layer 106 is increased to provide the margin required for non-selective etching.

[0086] Reference Figure 5 , portions of the mesa are then masked with resist and openings are dry etched in dielectric layer 130. Figure 5 As shown, the dielectric layer 130 covers only the sidewall 105s of the adjacent mesa 105 at the third p-type layer 102 and the third color active region 104 (red active region) of the adjacent mesa 105. On the third mesa 107, the dielectric layer 130 extends only over the sidewall 107s at the third n-type layer 106, the second tunnel junction 110, the second p-type layer 112, and the second color active region 114 (green active region). On the first mesa 103, the dielectric layer 130 covers only the sidewall 103s at the second n-type layer(s) 116, the first tunnel junction 120, the first p-type layer 122, and the first color active region 124 (blue active region).

[0087] Reference Figure 6 , the cathode metallization layer 132 is deposited on Figure 5 In one or more embodiments, cathode metallization layer 132 comprises an aluminum-containing metal layer and is deposited by physical vapor deposition and as shown. Figure 6The n-contact metallization layer 132 covers the sidewalls of the first mesa 103 and the n-type layer 126 of the adjacent mesa 105. The n-contact metallization layer 132 extends to and covers the sidewalls of the third n-type layer 106 of the adjacent mesa 105. The n-contact metallization layer 132 extends to and covers the sidewalls of the third mesa 107 to the second n-type layer(s) 116.

[0088] Reference Figure 7 The first trench 111 and the second trench 113 between adjacent mesas are partially filled using solution-based electrodeposition of a metal such as copper, using the previously deposited aluminum-containing metal as a seed layer. If desired, the electrodeposited metal can be planarized using chemical mechanical planarization in a subsequent processing step.

[0089] Reference Figure 8B After cleaning, the LED array 109 is masked again and a set of openings for the anode metallization contacts are patterned and another set of openings are etched in the dielectric layer 130. Then, the anode metallization contacts comprising a conductive metal (such as silver) are patterned into openings, such as Figure 8B Alternatively, if it is desired to use different contact metals for the electrode contact on the third p-type layer 102 (red LED) on the first mesa 103 and the p-type metallization contact 136 on the n-GaN tunnel junction contact of the blue LED of the third mesa 107 and the green LED of the adjacent mesa 105, this can be performed in separate lithography and deposition steps. Figure 8B The patterning shown.

[0090] exist Figure 8B , the cathode metallization layer 132 of the green LED in the third mesa 107 also contacts the blue LED layer in the adjacent mesa 105, and the cathode metallization layer 132 of the blue LED in the first mesa 103 also contacts the green and blue LED layers in the adjacent mesa 105. However, such contact does not prevent independent operation of adjacent LEDs sharing a common cathode. The bias voltage in a typical application will not exceed 4V, which is insufficient to inject holes beyond the active area closest to the anode, even if the cathode metal contacts deeper layers within the epitaxial structure. Figure 8B The dashed arrows 150 in FIG. 1 show the current path for a typical bias voltage of less than 4V.

[0091] Another aspect of the present disclosure relates to Fig. 8A and Figure 8B The LED array shown. Fig. 8AIn the first embodiment shown, the LED array 109b includes a first mesa 103, the first mesa 103 includes a top surface 103t, at least one first LED, and a first tunnel junction 120 on a p-type layer 122 of the first LED, wherein the at least one first LED includes a first p-type layer 122, a first n-type layer 126, and a first color active region 124, and the top surface 103t of the first mesa 103 includes (a plurality of) second n-type layers 116 on the first tunnel junction 120. Still referring to Fig. 8A , there is an adjacent mesa 105 including a top surface 105t, a first LED, a second LED including a second n-type layer(s) 116, a second p-type layer 112, and a second color active region 114. There is a second tunnel junction 110 on the second LED of the adjacent mesa 105, and there is a third n-type layer 106 on the second tunnel junction 110 of the adjacent mesa 105. There is a first trench 111 separating the first mesa 103 and the adjacent mesa 105. A cathode metallization 134 is present in the first trench 111 and is in electrical contact with the first color active region 124 and the second color active region 114 of the adjacent mesa 105. There is an anode metallization contact 136 on the second n-type layer(s) 116 of the first mesa 103 and on the third n-type layer 106 of the adjacent mesa 105. Fig. 8A In the illustrated embodiment, the top surface 105 t of the adjacent mesa 105 includes the third n-type layer 106 .

[0092] Thus, the LED array 109 b shown in FIG. 8 includes a single-color (blue) LED formed by the first mesa 103 and a dual-color LED (blue and green) formed by the adjacent mesa 105 .

[0093] Figure 8BAnother embodiment of an LED array 109 is shown, the LED array 109 comprising a first mesa 103 including a top surface 103t, at least one first LED, and a first tunnel junction 120 on a p-type layer 122 of the first LED, the at least one first LED comprising a first p-type layer 122, a first n-type layer 126, and a first color active region 124, the top surface 103t of the first mesa 103 comprising a second n-type layer(s) 116 on the first tunnel junction 120. An adjacent mesa 105 comprises a top surface 105t, a first LED, a second LED comprising a second n-type layer(s) 116, a second p-type layer 112, and a second color active region 114. A second tunnel junction 110 is present on the second LED of the adjacent mesa 105 (i.e., on the p-type layer 112), and a third n-type layer 106 is present on the second tunnel junction 110 of the adjacent mesa 105. There is a first trench 111 separating the first mesa 103 and the adjacent mesa 105. An n-type metallization 134 is present in the first trench 111 and is in electrical contact with the first color active area 124 and the second color active area 114 of the adjacent mesa 105. There is a p-type metallization contact 136 on the second n-type layer of the first mesa and on the top surface 105t of the adjacent mesa 105.

[0094] Figure 8B The LED array 109 shown also includes a third color active region 104 on the n-type layer 106 of the adjacent mesa 105, and the adjacent mesa includes a top surface 105t including a third p-type layer 102. The LED array 109 also includes a third mesa 107, which includes a first LED, a second LED, a second tunnel junction 110, and a third n-type layer 106 on the second tunnel junction 110. There is a second trench 113 separating the adjacent mesa 105 and the third mesa 107. A cathode metallization 134 is present in the second trench 113 and in electrical contact with the first color active region 124 and the second color active region 114 of the third mesa 107, and there is a cathode metallization 134 in electrical contact with the first color active region 124, the second color active region 114, and the third color active region 104 of the adjacent mesa 105 in the first trench 111. Furthermore, an anode metallization contact 136 is present on the third n-type layer 106 of the third mesa 107 .

[0095] In some embodiments, the third p-type layer 102 of the adjacent mesa 105 is a non-etched p-type layer. In some embodiments, the first color active region 124 is a blue active region, and the second color active region 114 is a green active region. In some embodiments, the first color active region 124 is a blue active region, the second color active region 114 is a green active region, and the third color active region 104 is a red active region.

[0096] In embodiments where light is emitted toward the substrate side of the structure, the heights of the mesas increase in order of increasing emission wavelength (red>green>blue in this example).

[0097] Reference Fig. 9 , the electronic system or device 200 includes Figure 8B The LED array 109 is configured to provide an independent voltage to one or more anode contacts 136 of the first mesa 103, the adjacent mesa 105, and the third mesa. This can be achieved by a backplane 190, such as a CMOS backplane 190 connected to the anode contacts 136 by metal 192 (e.g., metal solder bumps). In one or more embodiments, the electronic system is selected from the group consisting of an LED-based lamp, a light strip, a light sheet, an optical display, and a microLED display.

[0098] Reference Figures 10 to 14 , the electronic device 800 including a thin film transistor (TFT) driving circuit shown includes an LED array 809 integrated with one or more TFT drivers 850. In one or more embodiments, the TFT driving circuit including one or more TFT drivers 850 is combined with any embodiment of the LED array described herein.

[0099] Fig.10 A partial top view of an LED array 809 configured to emit two or more colors is shown. Fig.10 854B), red (854R), and green (854G) columns of LEDs to provide multiple rows (top row 855A, middle row 855B, and bottom row 855C). Each cell includes an anode metallization contact 836 (at Figure 12-14 The anode metallization contact 836 is disposed on the table of the LED of any embodiment described herein. Each electrode contact 853 of each unit cell is surrounded by an n-type material 852 (eg, n-type GaN).

[0100] The grid 802 also includes at least a plurality of select lines 856 extending parallel to each row 855A, 855B, 855C, and a plurality of V lines extending perpendicular to each row. DD Line 858 and multiple data lines 860. Multiple V DD Line 858 and a plurality of data lines 860 are deposited at least one layer above select line 856, as described in further detail below. In one or more embodiments, the plurality of VDD Each of the lines 858 provides a constant voltage above the threshold "on" voltage for each LED. There is one select line 856 for each row of the display and one V for each display column. DD Lines 858, but all connected to a common external power supply. There is one data line 860 (on each display column) for each column driver connected to an external CMOS column driver. The LED common cathode is connected to ground external to the device (such as a display).

[0101] Fig.11 A schematic diagram of one or more TFT drivers 850 is shown, as shown by Fig.10 850 is indicated by the dashed line in the middle. For the purpose of clarity, the insulator material is not drawn. As shown in the figure, each TFT driver 850 includes at least two transistors, a capacitor, one of the select lines 856, V DD One of the data lines 858 and one of the data lines 860. DD Line 858 is connected to a first electrode 868 of a drive transistor 865, which is configured as the gate of the device. The drive transistor 865 is connected to a capacitor 864, which in turn is connected to a first electrode 867 of a select transistor 863. A second electrode 869 of the select transistor 863 is connected to a data line 860. A second electrode 866 of the drive transistor 865 is connected to an anode metallization contact 836 ( Figure 12-14 ).

[0102] According to one or more embodiments, V DD Line 858 is configured as a source, which provides a constant supply voltage above the conduction threshold of each LED; and select line 856 is configured as a drain. Data line 860 is configured to charge capacitor 864 to the required voltage, and select line 856 is configured to turn on drive transistor 865. In operation, V DD Line 858 provides a constant supply voltage. The circulating voltage to select line 856 turns on select transistor 863, and the voltage to data line 860 charges capacitor 864. The current through each LED is controlled by the voltage stored in capacitor 864. In one or more embodiments, the exemplary voltage is 3.5V.

[0103] Fig.12 Shown with Figure 8BAn LED array 809 is similar to the LED array shown, and includes a first mesa 803, the first mesa 803 including a top surface 803t, at least one first LED including a first p-type layer 822, a first n-type layer 826, and a first color active region 824, and a first tunnel junction 820 on the p-type layer 822 of the first LED, and the top surface 803t of the first mesa 803 includes a second n-type layer 816 on the first tunnel junction 820. An adjacent mesa 805 includes a top surface 805t, a first LED, and a second LED including a second n-type layer 816, a second p-type layer 812, and a second color active region 814. A second tunnel junction 810 is present on the second LED of the adjacent mesa 805 (i.e., on the p-type layer 812), and a third n-type layer 806 is present on the second tunnel junction 810 of the adjacent mesa 805. A first trench is present that separates the first mesa 803 from the adjacent mesa 805. An n-type metallization 834 is present in the first trench and is in electrical contact with the first color active area 824 and the second color active area 814 of the adjacent mesa 804. An anode metallization contact 836 is present on the second n-type layer of the first mesa and on the top surface 805t of the adjacent mesa 805. A common ground electrode 847 is deposited over the first and second trenches and is in contact with the cathode metallization 834.

[0104] A conformal coating of a dielectric layer 830 (e.g., silicon dioxide) is deposited over the mesas and their sidewalls using a method such as plasma enhanced chemical vapor deposition, atomic layer deposition, or sputtering. The dielectric layer 830 isolates the metal contacts from each other, which will be fabricated in a later process step. A planarization material 845 (which in some embodiments includes a dielectric material) is deposited over the dielectric layer 830, the mesas, and a common ground electrode 847. Electrical contacts extend through the planarization material 845, which connect the p-type metallization contacts 836 of the first mesa 803, the adjacent mesa 805, and the third mesa 807 to the second electrode 866 of the drive transistor 865 of the one or more TFT drivers 850, thereby powering the LED.

[0105] Fig.13 and Fig.14 A stack of layers including one or more TFT drivers 850 is shown, wherein Fig.14 The stack is shown in more detail, as Fig.13 For reference, the LED Fig.12 All details are in Fig.13 and Fig.14 There is no repetition in it. You will understand that Fig.12 The capacitor 864 is shown in Fig.13 and Fig.14863 and the source and drain of the drive transistor 865. Fig.13 and Fig.14 As shown, the selection transistor 863 includes a semiconductor material 863S on the lower TFT dielectric layer 870. The driving transistor 865 includes a semiconductor material 865S on the second portion 872b and the third portion 872c of the lower TFT metallization layer 872. There is an upper TFT metallization layer 877, which includes a first portion 877a, a second portion 877b, and a third portion 877c, which in some embodiments serve as the gate of the selection transistor and the source and drain of the driving transistor 865, respectively. There is a TFT upper dielectric layer 879 on the semiconductor material 865S of the driving transistor 865, which in some embodiments serves as an insulator for the gate of the driving transistor 865. There is also an upper TFT metallization layer 881, which includes a first portion 881a, a second portion 881b, and a third portion 881c, which in some embodiments serve as the source (881a) and drain (881b) of the selection transistor 863 and the gate (881c) of the driving transistor 865, respectively. Although not shown in Fig.13 and Fig.14 864, and the first portion 872a of the lower metallization layer is connected to the select line 856. The electronic device 800 includes an LED array 809 and a driver circuit configured to provide independent voltages to one or more of the anode metallization contacts 836 of the first mesa 803, the adjacent mesa 805, and the third mesa 807. This can be achieved by the TFT circuit shown and described herein according to one or more embodiments. In one or more embodiments, the electronic device 800 is selected from the group consisting of an LED-based lamp, a light-emitting strip, a light-emitting sheet, an optical display, and a microLED display.

[0106] According to the embodiments provided herein, the CMOS gate and column drivers acquire video input signals and convert the video input signals into voltages on data lines, which program the LEDs to emit the light levels required to produce an image. In the embodiments described herein, the operation of the device 800 is divided between "programming" and "display" cycles. In the "programming" cycle, the voltage to the select line turns on the select transistors along the specified row, and the voltage to the data line charges each capacitor on the column with the desired voltage. In one or more embodiments, the programming of the device 800 is performed one row at a time. In the "display" cycle, the current through each LED is controlled by the voltage stored on the capacitor in the "programming" cycle.

[0107] According to an embodiment, the transistor is an amorphous silicon N-channel transistor. The source and drain contacts can be separately deposited amorphous silicon films with high n-type (phosphorus) doping. The non-source and drain semiconductor regions are unintentionally doped amorphous Si with weak p-type conductivity. In some embodiments, the applied gate voltage inverts the p-type material under the gate to n-type, thereby switching on current in the lateral direction. In some embodiments, the dielectric material is SiN made by plasma enhanced chemical vapor deposition. x , which is also the method used to deposit amorphous Si. The metal of some embodiments is typically Cr or Mo and is deposited by electron beam evaporation or sputtering.

[0108] In one or more embodiments, semiconductor materials that can be used to make TFTs - whose processing temperatures are suitable for LED wafers - include amorphous silicon, laser crystallized polysilicon, amorphous conductive oxides (such as indium gallium zinc oxide), or II-VI compounds (such as CdS). In general, TFTs can be N-channel or P-channel, but amorphous Si transistors are always N-channel (due to low hole mobility). In some embodiments, polysilicon can allow smaller physical dimensions of TFTs, thereby allowing smaller pixel pitches. In addition, polysilicon has better long-term reliability and can improve the electrical efficiency of the display.

[0109] Simpler embodiments of the present disclosure include epitaxial growth sequences featuring only one tunnel junction (rather than two) and active regions of only two colors (rather than three). Although the figures show an architecture where the substrate remains attached in the finished device, in some embodiments, laser lift-off or other epitaxial film separation processes may be applied such that the substrate is removed in the finished device. Photoelectrochemical etching may be applied after the substrate is removed to roughen the exposed GaN surface and improve light extraction efficiency.

[0110] Example

[0111] Various embodiments are listed below. It will be understood that the embodiments listed below can be combined with all aspects of the scope of the present invention and other embodiments.

[0112] Embodiment (a). A light emitting diode (LED) array comprises: a first mesa comprising a top surface, at least one first LED, and a first tunnel junction on the first LED, the at least one first LED comprising a first p-type layer, a first n-type layer, and a first color active region, the top surface of the first mesa comprising a second n-type layer on the first tunnel junction, the second n-type layer comprising at least one n-type III-nitride layer having an Al mole fraction > 10% and at least one n-type III-nitride layer having an Al mole fraction < 10%; an adjacent mesa comprising a top surface, a first LED, a second LED, the second LED comprising a second n-type layer, a second p-type layer, and a second color active region; a second tunnel junction on the second LED of the adjacent mesa, and a third n-type layer on the second tunnel junction of the adjacent mesa; a first trench separating the first mesa and the adjacent mesa; and an anode metallization contact on the second n-type layer of the first mesa and on the top surface of the adjacent mesa.

[0113] Embodiment (b) The LED array according to embodiment (a), wherein top surfaces of adjacent mesas include a third n-type layer.

[0114] Embodiment (c). The LED array according to embodiments (a) to (b) further includes: a third color active region on the n-type layer of an adjacent mesa, and the adjacent mesa includes a top surface including a third p-type layer; a third mesa including a first LED, a second LED, a second tunnel junction, and a third n-type layer on the second tunnel junction; a second trench separating the adjacent mesa and the third mesa; a cathode metallization in the first trench and in electrical contact with the first color active region and the second color active region of the adjacent mesa; a cathode metallization in the second trench and in electrical contact with the first color active region and the second color active region of the third mesa, and a cathode metallization in the first trench in electrical contact with the first color active region, the second color active region, and the third color active region of the adjacent mesa; and an anode metallization contact on the third n-type layer of the third mesa.

[0115] Embodiment (d) The LED array according to embodiments (a) to (c), wherein the third p-type layer of the adjacent mesa is a non-etched p-type layer.

[0116] Embodiment (e) The LED array of embodiments (a) to (d), wherein the first color active region is a blue active region, and the second color active region is a green active region.

[0117] Embodiment (f) The LED array of embodiments (a) to (e), wherein the first color active area is a blue active area, the second color active area is a green active area, and the third color active area is a red active area.

[0118] Embodiment (g) The LED array of embodiments (a) to (f), wherein the first p-type layer, the second p-type layer, and the first n-type layer comprise a Group III nitride material.

[0119] Embodiment (h) The LED array of embodiments (a) to (g), wherein the Group III nitride material comprises GaN.

[0120] Embodiment (i) The LED array of embodiments (a) to (h), wherein the first p-type layer, the second p-type layer, the third p-type layer, the first n-type layer, the second n-type layer, and the third n-type layer comprise a Group III nitride material.

[0121] Embodiment (j) The LED array of embodiments (a) to (i), wherein the Group III nitride material comprises GaN.

[0122] Embodiment (k) The LED array according to embodiments (a) to (j), wherein the first mesa has a sidewall and the adjacent mesa has a sidewall, and the first mesa sidewall and the adjacent mesa sidewall form an angle ranging from 60 degrees to less than 90 degrees with the top surface of the substrate on which the mesa is formed.

[0123] Embodiment (l) According to the LED array of embodiments (a) to (k), the n-type III-nitride layer with an Al mole fraction of more than 10% has a molecular formula of Al x Ga 1-x N, wherein x is in the range from 0.20 to 0.25.

[0124] Embodiment (m). The LED array according to embodiments (a) to (l) further comprises a thin film transistor (TFT) driver, the thin film transistor driver comprising a driving transistor, a capacitor and a selection transistor, the driving transistor having a second electrode and a capacitor connected to V DD A first electrode of the data line, the capacitor is connected to a second electrode of the drive transistor and to a first electrode of a select transistor, the select transistor having a first electrode and a second electrode, the second electrode of the select transistor being connected to the data line, wherein the select transistor is configured to be controlled by the select line, wherein the second electrode of the drive transistor is connected to one of the anode metallization contacts.

[0125] Embodiment (n) An electronic system comprises: an LED array according to embodiments (a) to (m); and a driver circuit configured to provide independent voltages to one or more anode contacts.

[0126] Embodiment (o) The electronic system of embodiment (n), wherein the electronic system is selected from the group consisting of an LED-based lamp, a light strip, a light sheet, an optical display, and a microLED display.

[0127] Embodiment (p). A method for manufacturing an LED array, the method comprising: forming a first mesa, the first mesa comprising a top surface, at least one first LED, and a first tunnel junction on the first LED, the at least one first LED comprising a first p-type layer, a first n-type layer, and a first color active region, the top surface comprising a second n-type layer on the first tunnel junction, the second n-type layer comprising at least one n-type III-nitride layer having an Al mole fraction > 10% and at least one n-type III-nitride layer having an Al mole fraction < 10%; forming an adjacent mesa, the adjacent mesa comprising a first LED, a second LED, the second LED comprising a second n-type layer, a second p-type layer, and a second color active region; forming a second tunnel junction on the second LED of the adjacent mesa, and forming a third n-type layer on the second tunnel junction of the p-type layer of the adjacent mesa; forming a first trench separating the first mesa and the adjacent mesa; and forming an anode metallization contact on the second n-type layer of the first mesa and on the third n-type layer of the adjacent mesa.

[0128] Embodiment (q). The method of embodiment (p), further comprising forming a top surface of the adjacent mesa comprising a third n-type layer.

[0129] Embodiment (r). The method according to embodiments (p) to (q) further includes: forming a third color active region on the n-type layer of an adjacent mesa, and the adjacent mesa includes a top surface including a third p-type layer; forming a third mesa, the third mesa including a top surface, a first LED, a second LED, a second tunnel junction, and including a third n-type layer on the second tunnel junction, and a third color active region, the top surface of the third mesa including a third n-type layer; forming a second trench separating the adjacent mesa and the third mesa; forming a cathode metallization in the first trench, which is in electrical contact with the first color active region and the second color active region of the adjacent mesa; forming a cathode metallization in electrical contact with the first color active region and the second color active region of the third mesa in the second trench, and forming a cathode metallization in electrical contact with the first color active region, the second color active region and the third color active region of the second adjacent mesa in the first trench, and forming an n-type metallization in electrical contact with the third color active region in the first trench; and forming an anode metallization contact on the third n-type layer of the third mesa.

[0130] Embodiment (s) The method of embodiments (p) to (r), wherein each of the first LED, the second LED, and the third LED comprises an epitaxially deposited Group III-nitride material.

[0131] Embodiment (t) The method of embodiments (p) to (s), wherein the first LED, the second LED, and the third LED are formed on a substrate.

[0132] In the context of describing the materials and methods discussed herein (especially in the context of the following claims), the use of the terms "one" and "an" and "the" and similar references should be interpreted as covering both the singular and the plural, unless otherwise indicated herein or clearly contradicted by the context. Unless otherwise indicated herein, the description of the range of values ​​herein is intended only to be used as a shorthand method for individually referring to each individual value falling within the range, and each individual value is incorporated into this specification as if it were individually described herein. Unless otherwise indicated herein or clearly contradicted by the context otherwise, all methods described herein can be performed in any suitable order. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and unless otherwise claimed, does not limit the scope. Any language in this specification should not be interpreted as indicating that any unclaimed element is essential for practicing the disclosed materials and methods.

[0133] Throughout the specification, the terms first, second, third, etc. may be used to describe various elements herein, and these elements should not be limited by these terms. These terms may be used to distinguish one element from another.

[0134] Throughout this specification, reference to a layer, region, or substrate being "on" or extending to another element means that it may be directly on or directly extending to another element, or there may be intermediate elements. When an element is referred to as being "directly on" or "directly extending to" another element, there may be no intermediate elements. In addition, when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to another element and / or connected or coupled to another element via one or more intermediate elements. When an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element between the element and the other element. It will be understood that these terms are intended to cover different orientations of elements, in addition to any orientation depicted in the figures.

[0135] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0136] Throughout this specification, reference to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in an embodiment," or "in an embodiment" throughout this specification does not necessarily refer to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics are combined in any suitable manner.

[0137] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrations of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, it is intended that the present disclosure include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A light emitting diode (LED) array, comprising: a first mesa, the first mesa comprising a top surface, at least one first LED, and a first tunnel junction on the first LED, the at least one first LED comprising a first p-type layer, a first n-type layer, and a first color active region, the top surface of the first mesa comprising a second n-type layer on the first tunnel junction, the second n-type layer comprising at least one n-type III-nitride layer having an Al mole fraction > 10% and at least one n-type III-nitride layer having an Al mole fraction < 10%; an adjacent mesa, the adjacent mesa comprising a top surface, a first LED, a second LED, a second tunnel junction on the second LED, and a third LED, the second LED comprising the second n-type layer, a second p-type layer, and a second color active region, the third LED comprising a third n-type layer, a third color active region, and a third p-type layer, the third n-type layer being on the second tunnel junction of the adjacent mesa, the third color active region being on the third n-type layer of the adjacent mesa, the adjacent mesa comprising a top surface comprising the third p-type layer; a first groove separating the first mesa and the adjacent mesa; an anodic metallization contact on the second n-type layer of the first mesa and on a top surface of the adjacent mesa; a third mesa comprising the first LED, the second LED, the second tunnel junction, and a third n-type layer on the second tunnel junction of the third mesa; a second groove separating the adjacent mesas and the third mesas; cathode metallization in the first trench in electrical contact with the first color active area of ​​the first mesa and in electrical contact with the first color active area, the second color active area, and the third color active area of ​​the adjacent mesa; cathode metallization in the second trench in electrical contact with the first color active area and the second color active area of ​​the third mesa and in electrical contact with the first color active area, the second color active area, and the third color active area of ​​the adjacent mesa; and An anode metallization contact is formed on the third n-type layer of the third mesa.

2. The LED array according to claim 1, wherein: The third p-type layer of the adjacent mesa is a non-etched p-type layer.

3. The LED array according to claim 1, wherein: The first color active area is a blue active area, and the second color active area is a green active area.

4. The LED array according to claim 1, wherein: The first color active area is a blue active area, the second color active area is a green active area, and the third color active area is a red active area.

5. The LED array according to claim 1, wherein: The first p-type layer, the second p-type layer, and the first n-type layer include a Group III nitride material.

6. The LED array according to claim 5, wherein: The Group III nitride material includes GaN. 7 . The LED array of claim 1 , wherein the first p-type layer, the second p-type layer, the third p-type layer, the first n-type layer, the second n-type layer, and the third n-type layer comprise a Group III nitride material.

8. The LED array of claim 7, wherein the Group III nitride material comprises GaN.

9. The LED array according to claim 1, wherein: The first mesa has a sidewall and the adjacent mesa has a sidewall, and the first mesa sidewall and the adjacent mesa sidewall form an angle ranging from 60 degrees to less than 90 degrees with a top surface of a substrate on which the mesa is formed.

10. The LED array according to claim 1, wherein: The n-type III-group nitride layer with an Al mole fraction of more than 10% has a molecular formula of Al x Ga 1-x N, wherein x is in the range from 0.20 to 0.

25.

11. The LED array of claim 1 , further comprising a thin film transistor (TFT) driver, the thin film transistor driver comprising a drive transistor, a capacitor, and a select transistor, the drive transistor having a second electrode and a capacitor connected to V DD a first electrode of a data line, the capacitor being connected to a second electrode of a drive transistor and to a first electrode of a select transistor, the select transistor having a first electrode and a second electrode, the second electrode of the select transistor being connected to a data line, wherein the select transistor is configured to be controlled by the select line, wherein the second electrode of the drive transistor is connected to one of the anode metallization contacts.

12. An electronic system comprising: The LED array according to claim 1; and A driver circuit is configured to provide an independent voltage to one or more anode metallization contacts.

13. The electronic system of claim 12, wherein the electronic system is selected from the group consisting of an LED-based lamp, a light strip, a light sheet, an optical display, and a microLED display.

Images