Array substrate, display panel and electronic device

Abstract

The application provides an array substrate, a display panel and an electronic device. Two switching devices in a same first demultiplexing unit are connected in parallel to provide a signal for a same first driving unit column, and input ends of two adjacent first demultiplexing units are connected in parallel, so that the two first demultiplexing units demultiplex signals transmitted by a same fan-out wire. Thus, compared with a scheme of arranging dummy demultiplexing units, the scheme provided by the embodiment can reduce the trench width of the switching devices while keeping the effective size of the switching devices unchanged, leave more wire space for the fan-out wire, and enable the narrow-frame design to be applied to the display panel with high refresh rate.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and more specifically, to an array substrate, a display panel, and an electronic device. Background Technology

[0002] Typically, in the array substrate of a display panel, the multi-column drive units that transmit signals along the column direction need to be connected to the bonding area folded to the back of the display surface via fan-out traces after being connected to the de-mux unit. As the refresh rate of the display panel increases, the trench width of the switching devices in the de-mux unit increases, and the linewidth of the fan-out traces increases, resulting in insufficient trace space for the fan-out traces, making it difficult to achieve a narrow bezel design. Summary of the Invention

[0003] To overcome the aforementioned shortcomings in the prior art, the present application aims to provide an array substrate, the array substrate comprising:

[0004] Multiple rows of first drive units extending along a first direction;

[0005] Multiple first demultiplexing units are located at one end of multiple columns of first driving units, and each first demultiplexing unit includes two switching devices;

[0006] At least two demultiplexing signal lines;

[0007] Multiple fan-out traces located on the side of the first demultiplexing unit away from the first drive unit column;

[0008] In this configuration, the control terminals of the two switching devices in the same first demultiplexing unit are electrically connected to the same demultiplexing signal line, the input terminals of the two switching devices in the same first demultiplexing unit are connected in parallel to form the input terminal of the first demultiplexing unit, and the output terminals of the two switching devices in the same first demultiplexing unit are connected in parallel to form the output terminal of the first demultiplexing unit.

[0009] Each pair of adjacent first demultiplexing units forms a group. The input terminals of the first demultiplexing units in the same group are electrically connected to the same fan-out routing line. The output terminals of the first demultiplexing units in the same group are electrically connected to different columns of the first driving unit. The control terminals of the first demultiplexing units in the same group are electrically connected to different demultiplexing signal lines.

[0010] In one possible implementation, the array substrate further includes:

[0011] The second demultiplexing unit and the plurality of first demultiplexing units are arranged along a second direction, which intersects with the first direction;

[0012] The groove width of the switching device in the first demultiplexing unit in the first direction is smaller than the groove width of the switching device in the second demultiplexing unit in the first direction.

[0013] In one possible implementation, the trench width of the switching device in the second demultiplexing unit is twice the trench width of the switching device in the first demultiplexing unit.

[0014] In one possible implementation, the plurality of first drive unit columns are arranged along the second direction to form a rectangular array region of the array substrate, and the array substrate further includes an arc-edge array region located on at least one side of the rectangular array region, and the second demultiplexing unit is electrically connected to the second drive unit column located in the arc-edge array region.

[0015] In one possible implementation, the control terminal of the switching device includes a gate electrode line extending along the first direction, and the gate electrode lines of both switching devices in the same first demultiplexing unit extend to be connected to a demultiplexing signal line.

[0016] In one possible implementation, the control terminal of the switching device includes a gate electrode line extending along the first direction. The switching devices in the same first demultiplexing unit include a first switching device and a second switching device. The gate electrode line of the first switching device extends to be connected to a demultiplexing signal line. The gate electrode line of the second switching device is electrically connected to the gate electrode line of the first switching device through a lap trace.

[0017] In one possible implementation, the array substrate includes a substrate, a semiconductor material layer and at least one metal layer located on one side of the substrate, the overlapping trace and the gate electrode line are located on the same metal layer, and the orthographic projection of the overlapping trace on the substrate does not coincide with the orthographic projection of the semiconductor material layer on the substrate.

[0018] In one possible implementation, the array substrate further includes a folded bonding region located on the side of the first demultiplexing unit away from the first drive unit column, and the first demultiplexing unit is connected to the folded bonding region via a fan-out trace.

[0019] This application also provides a display panel, which includes the array substrate provided in this application.

[0020] This application also provides an electronic device, which includes the display panel provided in this application.

[0021] Compared with the prior art, this application has the following beneficial effects:

[0022] This application provides an array substrate, display panel, and electronic device. By connecting two switching devices in the same first demultiplexing unit in parallel, signals are provided to the same first driving unit column. Furthermore, by connecting the input terminals of two adjacent first demultiplexing units in parallel, the two first demultiplexing units demultiplex the signals transmitted through the same fan-out trace. Thus, compared to a solution with a virtual demultiplexing unit, the solution provided in this embodiment can reduce the groove width of the switching devices while maintaining the effective size of the switching devices in the demultiplexing unit. This provides more routing space for the fan-out trace, allowing narrow bezel designs to be applied to high refresh rate display panels. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of an array substrate in the prior art;

[0025] Figure 2 This is a schematic diagram of the demultiplexing cell layout of an array substrate in the prior art;

[0026] Figure 3 This is a circuit diagram of an array substrate in the prior art;

[0027] Figure 4 This is a perspective view of a partial circuit structure of an array substrate in the prior art;

[0028] Figure 5 This is a schematic diagram of the region division of the array substrate provided in this embodiment;

[0029] Figure 6 This is a circuit diagram of the array substrate provided in this embodiment;

[0030] Figure 7 This is a schematic diagram of the demultiplexing unit layout provided in this embodiment;

[0031] Figure 8 This is one of the perspective views of the partial circuit structure provided in this embodiment;

[0032] Figure 9 This is the second perspective view of the partial circuit structure provided in this embodiment;

[0033] Figure 10 This is the third perspective view of the partial circuit structure provided in this embodiment;

[0034] Figure 11 This is the fourth perspective view of the partial circuit structure provided in this embodiment. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0036] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0037] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0038] In the description of this application, it should be noted that the terms "center," "upper," "lower," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. In addition, the terms "first," "second," and "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0039] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0040] Please see Figure 1 In some display panels, the array substrate may include a driving unit array area 9100, a demultiplexing area 9200, a fan-out area 9300, and a flip-bonding area 9400.

[0041] Specifically, please refer to Figure 2 and Figure 3The driving unit array area 9100 includes driving units arranged in an array, which are used to drive pixels to emit light. For a display panel with curved edges, the driving unit array area 9100 may include a rectangular array area formed by arranging first driving unit columns 9110 and a curved edge array area formed by arranging second driving unit columns 9120, wherein at least two of the second driving unit columns 9120 are arranged in a stepped manner at one end to form a curved corner area.

[0042] The demultiplexing area 9200 is located on one side of the drive unit array area 9100. The demultiplexing area 9200 includes multiple demultiplexing units, which are respectively connected to the drive unit and the fan-out line of the fan-out area 9300. The demultiplexing unit is used to demultiplex the signal of the fan-out line 9310 in the fan-out area 9300 so as to transmit the signal transmitted by one fan-out line 9310 to two column drive unit columns in a time-division manner.

[0043] The fan-out trace 9310 is also connected to the folded bonding area 9400, which is used for bonding with a driver chip or other circuits.

[0044] In this type of display panel, because the driving units of the arc-edge array area need to be arranged to form an arc-corner profile, one effective demultiplexing unit 9210 needs to correspond to two second driving unit columns 9120. In order to ensure the performance uniformity of the arc-edge array area and the rectangular array area (e.g., having approximately the same threshold voltage), the demultiplexing unit corresponding to the rectangular array area also needs to be set so that one effective demultiplexing unit 9210 corresponds to two first driving unit columns 9110. Therefore, a dummy demultiplexing unit 9220 also needs to be set in the demultiplexing area 9200 corresponding to the rectangular array area. The dummy demultiplexing unit 9220 is arranged sequentially and alternately with the effective demultiplexing unit 9210. The dummy demultiplexing unit 9220 is not connected to the fan-out trace 9310 and the driving unit.

[0045] Please refer to Figure 3 and Figure 4 Each demultiplexing unit includes two switching devices. The control terminals of the two switching devices in the same effective demultiplexing unit 9210 are typically connected to two demultiplexing signal lines 9230 extending along the second direction D2, respectively. The input terminals of the two switching devices in the same effective demultiplexing unit 9210 are typically connected to the same fan-out trace 9310, and the output terminals of the two switching devices in the same effective demultiplexing unit 9210 are typically connected to different drive unit columns. Thus, under the time-division driving signal of the two demultiplexing signal lines 9230, the two switching devices can transmit the signal of the same fan-out trace 9310 to different drive unit columns in a time-division manner.

[0046] However, in such display panels, if a higher display refresh rate is required, the groove width of the switching device in the demultiplexing unit on the first direction D1 needs to be increased, and the fan-out trace 9310 needs to have a larger line width, resulting in insufficient wiring space for the fan-out trace 9310 and making it difficult to achieve a narrow bezel.

[0047] In view of this, this embodiment provides a solution that can improve the wiring space of fan-out cabling. The solution provided in this embodiment will be described in detail below.

[0048] Please see Figure 5 , Figure 5 This embodiment provides a circuit diagram of an array substrate, which may include a driving unit array area 100, a demultiplexing area 200, a fan-out area 300, and a folded bonding area 400.

[0049] Specifically, the driving unit array region 100 includes driving units arranged in an array. The demultiplexing region 200 is located on one side of the driving unit array region 100. The demultiplexing region 200 includes multiple demultiplexing units, which are respectively connected to the driving units and the fan-out lines of the fan-out region 300. The fan-out lines 310 are also connected to the flip-bond region 400, which is used for bonding with the driving chip or other circuits.

[0050] Please refer to Figure 6 and Figure 7 The array substrate includes multiple first driving unit columns 110, at least two demultiplexed signal lines 230, multiple first demultiplexed units 211, and multiple fan-out traces 310.

[0051] Multiple first drive unit columns 110 extend along a first direction D1, and each first drive unit column 110 may include multiple drive units. Drive units in the same first drive unit column 110 may be connected to the same data signal line.

[0052] The plurality of first demultiplexing units 211 are located at one end of the plurality of first driving unit columns 110, and each first demultiplexing unit 211 includes two switching devices. The switching devices may be composed of semiconductor layer materials and metal traces in different film layers of the array substrate.

[0053] The at least two demultiplexed signal lines 230 are used for time-division multiplexing of the demultiplexed clock signal. The at least two demultiplexed signal lines 230 may be located at one end of a plurality of the first drive unit columns 110. The demultiplexed signal lines 230 may extend along a second direction D2, which intersects with the first direction D1.

[0054] The plurality of fan-out traces 310 are located on the side of the first demultiplexing unit 211 away from the first driving unit column 110. Optionally, the array substrate further includes a folded bonding area 400 located on the side of the first demultiplexing unit 211 away from the first driving unit column 110, and the first demultiplexing unit 211 is connected to the folded bonding area 400 via the fan-out traces 310.

[0055] Please refer to this again. Figure 6 In this embodiment, the control terminals of the two switching devices in the same first demultiplexing unit 211 are electrically connected to the same demultiplexing signal line 230, the input terminals of the two switching devices in the same first demultiplexing unit 211 are connected in parallel to form the input terminal of the first demultiplexing unit 211, and the output terminals of the two switching devices in the same first demultiplexing unit 211 are connected in parallel to form the output terminal of the first demultiplexing unit 211.

[0056] Each pair of adjacent first demultiplexing units 211 forms a group. The input terminals of the first demultiplexing units 211 in the same group are electrically connected to the same fan-out routing line 310. The output terminals of the first demultiplexing units 211 in the same group are electrically connected to different first drive unit columns 110. The control terminals of the first demultiplexing units 211 in the same group are electrically connected to different demultiplexing signal lines 230.

[0057] That is, in this embodiment, two switching devices in the same first demultiplexing unit 211 are connected in parallel, the input and output terminals of the two switching devices are the same, and the control terminal is driven by the same demultiplexing signal line 230. Then, the two first demultiplexing units 211 in the same group are driven by different demultiplexing signal lines 230 in a time-division manner. That is, the two first demultiplexing units 211 in the same group of first demultiplexing units 211 realize the demultiplexing of signals on the same fan-out routing line 310.

[0058] Based on the above design, in this embodiment, by connecting two switching devices in the same first demultiplexing unit 211 in parallel, a signal is provided to the same first driving unit column 110. Furthermore, by connecting the input terminals of two adjacent first demultiplexing units 211 in parallel, the two first demultiplexing units 211 demultiplex the signal transmitted by the same fan-out trace 310. Thus, compared to the scheme of setting a virtual demultiplexing unit 220, the solution provided in this embodiment can reduce the groove width of the switching devices while maintaining the effective size of the switching devices in the demultiplexing unit, leaving more routing space for the fan-out trace 310, allowing narrow bezel designs to be applied to high refresh rate display panels.

[0059] Furthermore, please refer to again Figure 6 and Figure 7The array substrate provided in this embodiment may further include a second demultiplexing unit 212, wherein the second demultiplexing unit 212 and the plurality of first demultiplexing units 211 are arranged along the second direction D2.

[0060] The plurality of first drive unit columns 110 are arranged along the second direction D2 to form a rectangular array region of the array substrate. The array substrate also includes an arc-edge array region located on at least one side of the rectangular array region. The second demultiplexing unit 212 is electrically connected to the second drive unit column 120 located in the arc-edge array region.

[0061] Please refer to this again. Figure 6 The control terminals of the two switching devices in the same second demultiplexing unit 212 can be connected to different demultiplexing signal lines 230, the input terminals of the two switching devices in the same second demultiplexing unit 212 can be connected to the same fan-out routing line 310, and the output terminals of the two switching devices in the same second demultiplexing unit 212 can be electrically connected to different second driving unit columns 120 respectively. That is, in this embodiment, the two switching devices in the same second demultiplexing unit 212 are driven by different demultiplexing signal lines 230 in a time-division manner to demultiplex the signals on the same fan-out routing line 310.

[0062] Based on the above design, please refer to Figure 8 The groove width of the switching device in the first demultiplexing unit 211 in the first direction D1 is smaller than the groove width of the switching device in the second demultiplexing unit 212 in the first direction D1.

[0063] Specifically, in the second demultiplexing unit 212, one switching device corresponds to one column of the second driving unit 120. Therefore, each switching device needs to have a larger groove width, such as... Figure 8 The width W2 is shown. Compared to the second demultiplexing unit 212, the first demultiplexing unit 211 uses two switching devices side by side, thereby reducing the groove width of a single switching device in the first demultiplexing unit 211, such as... Figure 8 The width W1 shown. The sum of the effective trench widths of the two switching devices in the first demultiplexing unit 211 after parallel connection is equivalent to the effective trench width of one switching device in the second demultiplexing unit 212, thereby ensuring the uniformity of performance between the arc-edge array region and the rectangular array region.

[0064] Therefore, please refer to Figure 2 and Figure 7 Since the solution provided in this embodiment can reduce the groove width of the switching device in the first demultiplexing unit 211 in the second direction D2, compared to Figure 2The scheme shown, which sets up a virtual demultiplexing unit 220, can reduce the wiring space width of the fan-out traces 310 corresponding to the rectangular array area on the first direction D1 from... Figure 2 H1 is shown to increase to Figure 7 As shown in H2, while keeping the effective size of the switching device in the demultiplexing unit unchanged, the groove width of the switching device is reduced, leaving more routing space for the fan-out trace 310, so that the narrow bezel design can also be applied to display panels with high refresh rates.

[0065] In one possible implementation, the trench width of the switching device in the second demultiplexing unit 212 is twice the trench width of the switching device in the first demultiplexing unit 211. For example, in Figure 8 In the second demultiplexing unit 212, the groove width W2 of a single switching device can be the groove width W1 of a single switching device in the first demultiplexing unit 211.

[0066] In one possible implementation, please refer to Figure 9 The switching device can be a thin-film transistor, and the control terminal of the switching device includes a gate electrode line extending along the first direction D1. The gate electrode lines of the two switching devices in the same first demultiplexing unit 211 both extend to be connected to a demultiplexing signal line 230. Thus, the control terminals of the two switching devices in the same first demultiplexing unit 211 can be driven simultaneously by the same demultiplexing signal line 230.

[0067] In another possible implementation, please refer to Figure 10 The control terminal of the switching device includes a gate electrode line extending along the first direction D1. The switching devices in the same first demultiplexing unit 211 include a first switching device and a second switching device. The gate electrode line of the first switching device extends to be connected to a demultiplexing signal line 230. The gate electrode line of the second switching device is electrically connected to the gate electrode line of the first switching device through an overlapping trace 240 extending along the second direction D2.

[0068] Furthermore, the array substrate includes a substrate, a semiconductor material layer located on one side of the substrate, and at least one metal layer. The overlapping trace 240 and the gate electrode line are located on the same metal layer, and the orthographic projection of the overlapping trace 240 on the substrate does not coincide with the orthographic projection of the semiconductor material layer on the substrate. This avoids the overlapping trace 240 from overlapping with the semiconductor material to form a new thin-film transistor.

[0069] In another example, please refer to... Figure 10The connection line can be located at the end of the gate electrode line of the second switching device away from the demultiplexing signal line 230. In another example, please refer to... Figure 11 The connection line can be located at one end of the gate electrode line of the second switching device near the demultiplexing signal line 230.

[0070] This embodiment also provides a display panel, which includes the array substrate provided in this embodiment. The display panel may further include a light-emitting layer and other encapsulation film layers located on the array substrate.

[0071] This embodiment also provides an electronic device, which includes the display panel provided in this embodiment.

[0072] In summary, the array substrate, display panel, and electronic device provided in this application embodiment provide signals to the same first driving unit column by connecting two switching devices in parallel within the same demultiplexing unit, and by connecting the input terminals of two adjacent first demultiplexing units in parallel, enabling the two first demultiplexing units to demultiplex the signals transmitted through the same fan-out trace. Thus, compared to the solution of setting up a dummy demultiplexing unit, the solution provided in this embodiment can reduce the groove width of the switching devices while keeping the effective size of the switching devices in the demultiplexing unit unchanged, leaving more trace space for the fan-out trace, and allowing narrow bezel designs to be applied to display panels with high refresh rates.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes: A plurality of first drive unit columns and at least one second drive unit column extending along a first direction; Multiple first demultiplexing units are located at one end of multiple columns of first driving units, and each first demultiplexing unit includes two switching devices; At least two demultiplexing signal lines; Multiple fan-out traces located on the side of the first demultiplexing unit away from the first drive unit column; In this configuration, the control terminals of the two switching devices in the same first demultiplexing unit are electrically connected to the same demultiplexing signal line, the input terminals of the two switching devices in the same first demultiplexing unit are connected in parallel to form the input terminal of the first demultiplexing unit, and the output terminals of the two switching devices in the same first demultiplexing unit are connected in parallel to form the output terminal of the first demultiplexing unit. Each pair of adjacent first demultiplexing units forms a group. The input terminals of the first demultiplexing units in the same group are electrically connected to the same fan-out routing line. The output terminals of the first demultiplexing units in the same group are electrically connected to different columns of the first driving unit. The control terminals of the first demultiplexing units in the same group are electrically connected to different demultiplexing signal lines. The array substrate further includes: The second demultiplexing unit and the plurality of first demultiplexing units are arranged along a second direction, which intersects with the first direction; the plurality of first driving unit columns are arranged along the second direction to form a rectangular array region of the array substrate, and the array substrate further includes an arc-edge array region located on at least one side of the rectangular array region; the second demultiplexing unit is electrically connected to the second driving unit column located in the arc-edge array region. The groove width of a single switching device in the first demultiplexing unit in the first direction is smaller than the groove width of a single switching device in the second demultiplexing unit in the first direction; The control terminals of the two switching devices in the same second demultiplexing unit are connected to different demultiplexing signal lines, the input terminals of the two switching devices in the same second demultiplexing unit are connected to the same fan-out routing line, and the output terminals of the two switching devices in the same second demultiplexing unit are electrically connected to different second drive unit columns.

2. The array substrate according to claim 1, characterized in that, The groove width of the switching device in the second demultiplexing unit is twice the groove width of the switching device in the first demultiplexing unit.

3. The array substrate according to claim 1, characterized in that, The control terminal of the switching device includes a gate electrode line extending along the first direction, and the gate electrode lines of the two switching devices in the same first demultiplexing unit extend to be connected to the same demultiplexing signal line.

4. The array substrate according to claim 1, characterized in that, The control terminal of the switching device includes a gate electrode line extending along the first direction. In the same first demultiplexing unit, the switching devices include a first switching device and a second switching device. The gate electrode line of the first switching device extends to be connected to a demultiplexing signal line. The gate electrode line of the second switching device is electrically connected to the gate electrode line of the first switching device through a lap trace.

5. The array substrate according to claim 4, characterized in that, The array substrate includes a substrate, a semiconductor material layer and at least one metal layer located on one side of the substrate, the overlapping trace and the gate electrode line are located on the same metal layer, and the orthographic projection of the overlapping trace on the substrate does not coincide with the orthographic projection of the semiconductor material layer on the substrate.

6. The array substrate according to claim 1, characterized in that, The array substrate further includes a folded bonding area located on the side of the first demultiplexing unit away from the first driving unit column, and the first demultiplexing unit is connected to the folded bonding area via a fan-out trace.

7. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device includes the display panel as described in claim 7.

Images