Packaging structure for improving substrate wiring space and reducing packaging size
By introducing a dummy die into a multi-die tiled package structure and eliminating or reducing the finger, the problem of limited wiring space in the package structure is solved, resulting in a reduction in package size and an improvement in signal transmission quality, while also improving heat dissipation performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- NANJING ZHENXIN RUNHE MICROELECTRONICS CO LTD
- Filing Date
- 2025-04-17
- Publication Date
- 2026-05-01
AI Technical Summary
In existing multi-die flat wire bonding packaging structures, the presence of the finger increases the spacing between the main chip and the auxiliary chip, reduces the substrate wiring space, and affects the transmission performance of electrical power and electrical signals.
A dummy die is used, with a conductive metal layer on the front and an insulating layer on the back. It is divided into a PWR die and a GND die, which are located on the top surface of the auxiliary chip. They are connected to the power and ground input terminals of the main chip through metal leads, eliminating or reducing the number of fingers and increasing the substrate wiring space.
This reduces package size, increases substrate wiring space, improves signal transmission quality, lowers packaging costs, enhances the feasibility of applications for small-sized electronic products, and improves heat dissipation performance of the package through the thermal conductivity of the dummy die.
Smart Images
Figure CN224192420U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology, specifically a packaging structure that increases substrate wiring space and reduces package size. Background Technology
[0002] like Figure 1 This illustrates a multi-die flat wire bonding package structure. Typically, DIE1 is the main chip, such as a computing SoC chip; DIE2 is the auxiliary chip, such as a DRAM chip. Two types of wire bonding exist between the right side of the main chip DIE1 and the left side of the auxiliary chip DIE2:
[0003] 1) Die-to-die bonding between the main chip DIE1 and the auxiliary chip, DIE2.
[0004] This part of the bonding wires is divided into two types according to its function: ① Functional (signal) bonding wires, such as the bonding wires that connect the memory chip address, data and other I / O to the main chip DIE1; ② Power supply bonding wires, the power supply for the auxiliary chip DIE2 is transmitted from the main chip DIE1, and the power of the main chip DIE1 is output to the auxiliary chip DIE2 through the bonding wires.
[0005] 2) Power / ground wires are laid from the finger on the substrate to the main chip DIE1.
[0006] After receiving power from the outside, the solder ball of the substrate in the packaging structure is transmitted to the finger on the top surface of the substrate through the traces inside the substrate. The power is then transmitted to the main chip DIE1 through the bonding wire between this part of the finger and the main chip DIE1.
[0007] The above solution has two main problems:
[0008] 1) Numerous fingers (metal contacts for soldering leads) are distributed between the right side of auxiliary chip DIE2 and the left side of main chip DIE1. The presence of these fingers necessitates increasing the spacing between main chip DIE1 and auxiliary chip DIE2. Figure 1 The spacing C0 in the middle.
[0009] 2) Because these fingers are added in the middle of the substrate, the signal routing space of the first layer (top layer) of the substrate becomes smaller, making routing more difficult. Routing needs to bypass these fingers, which affects the transmission performance of power and electrical signals.
[0010] Terminology Explanation:
[0011] die / DIE refers to a single unpackaged bare chip cut off from a wafer during the semiconductor manufacturing process;
[0012] In semiconductor packaging technology, "finger" refers to a metal contact used for soldering metal wires on a substrate.
[0013] Wire bonding, also known as wire bonding, is a semiconductor packaging technology that refers to the electronic interconnection technology of connecting metal leads to the chip and the packaging substrate.
[0014] solder ball, in Figure 1 The packaging structure includes power solder joints and signal solder joints used for connecting circuit boards and other application scenarios. Summary of the Invention
[0015] In existing technologies, a dummy die is a special wafer structure used to simulate the behavior of an actual chip during the manufacturing process, but it does not possess all the functions of an actual chip. It is typically used for process monitoring and ensuring manufacturability. A dummy die is usually manufactured on the same wafer as the actual chip, undergoing the same manufacturing steps and conditions, and therefore can be used as a reference to evaluate the manufacturing quality of the actual chip.
[0016] This technical solution applies dummy dies to multi-die tiled packaging structures to reduce or even eliminate fingers between adjacent tiled dies, thereby reducing package size and increasing substrate wiring space. Details are as follows.
[0017] A packaging structure that increases substrate wiring space and reduces package size includes a substrate and multiple dies; at least two of the dies are laid flat on the top surface of the substrate and connected to contact fingers on the substrate via metal leads; the multiple dies are encapsulated in the substrate by molding compound; the multiple dies are divided into main chips and auxiliary chips; the power input terminal and ground input terminal of the main chip are connected to the power contact PWR finger and ground contact GND finger on the top surface of the substrate via metal leads.
[0018] Its features include a dummy die, with a metal conductive layer on the front and a non-metallic insulating layer on the back; the dummy die is divided into a PWR die and a GND die; the back sides of the PWR die and the GND die face down and are located on the top surface of the auxiliary chip respectively.
[0019] The power input terminal and ground input terminal of the main chip are connected to the front side of the PWR die and the front side of the GND die respectively via metal leads. The PWR finger and GND finger on the top surface of the substrate are connected to the front side of the PWR die and the front side of the GND die respectively via metal leads.
[0020] The main chip's power output and ground output are connected to the auxiliary chip's power input and ground input via metal leads, respectively.
[0021] Specifically, the PWR die and GND die are two separate pieces. The PWR die is located on the front surface of the GND die, and the area of the PWR die is smaller than that of the GND die, so that the surrounding area of the front surface of the GND die can be exposed.
[0022] The optimized structure is as follows: the PWR die and GND die are an integrated structure; then the metal conductive layer on the front side of the same dummy die is divided into two mutually insulated parts, which serve as the metal conductive layers of the GND die and the PWR die, respectively.
[0023] Specifically, in the integrated PWR die and GND die structure, the insulating region between the metal conductive layers of the GND die and PWR die is composed of a non-metallic insulating layer exposed by removing the metal conductive layers. Laser grooving can be used.
[0024] Furthermore, the insulating region is ring-shaped, with the metal conductive layer of the PWR die inside the ring and the metal conductive layer of the GND die outside the ring.
[0025] Define the side containing the power output terminal and ground output terminal of the main chip as the power supply side, and define the side containing the power input terminal and ground input terminal of the auxiliary chip as the power supply side, with the power supply side of the main chip being closer to the power supply side of the auxiliary chip.
[0026] To facilitate material preparation, the specifications of the metal leads in the package structure are the same; from the perspective of current carrying capacity, the number of metal leads between the top surface of the substrate and the PWR die and between the top surface of the substrate and the GND die is the same; the number of metal leads between the top surface of the substrate and the PWR die is not less than the number of leads between the main chip and the PWR die; the number of metal leads between the top surface of the substrate and the GND die is not less than the number of leads between the main chip and the GND die.
[0027] The main technical effects of this technical solution are:
[0028] 1) Reducing package size lowers packaging costs;
[0029] 2) Reduce package size to improve the feasibility of chip application in small-size scenarios such as mobile electronic products;
[0030] 3) Reduced or even eliminated adjacent tiled die (e.g.) Figure 1The finger between the main chip DIE1 and the auxiliary chip DIE2 in the middle of the substrate greatly increases the wiring space of the first signal layer of the substrate, reduces the bending of the signal traces, and improves the signal transmission quality.
[0031] 4) The dummy die is made of silicon with an aluminum metal layer on the surface. Its thermal conductivity is much higher than that of common molding compounds. It provides better heat transfer and diffusion for the heat generated by the auxiliary chip DIE2 below, thus improving the overall heat dissipation performance of the package. Attached Figure Description
[0032] Figure 1 This is an internal schematic diagram (top view) of a multi-die flat wire bonding package structure in the prior art.
[0033] Figure 2 This is an internal schematic diagram (top view) of the packaging structure of this solution.
[0034] Figure 3 This is an internal schematic diagram (top view) of the packaging structure of the further optimized solution;
[0035] Figure 4 This is a side view comparison diagram of the structural heights of three schemes, where: the first is the existing technology scheme, compared to... Figure 1 Corresponding; the second is an embodiment, with Figure 2 Corresponding; the third is a further optimization example, with Figure 3 correspond.
[0036] In the diagram: Main chip - DIE1, Auxiliary chip - DIE2, GND die - DIE3, PWR die - DIE4, Substrate - 5, Metal lead - 6, Insulating area - 7, Contact finger on substrate - 8. Detailed Implementation
[0037] The technical solution will be further described below with reference to the accompanying drawings and specific embodiments.
[0038] refer to Figure 2 and Figure 3 A packaging structure that improves substrate wiring space and reduces package size includes a substrate 5 and multiple dies; at least two of the dies are laid flat on the top surface of the substrate and connected to the contact finger 8 on the substrate 5 via metal leads 6; the multiple dies are encapsulated in the substrate by molding compound, and solder balls can also be connected to the pads PAD on the bottom surface of the substrate; the multiple dies are divided into a main chip DIE1 and an auxiliary chip DIE2; the power input terminal and ground input terminal of the main chip are connected to the power contact PWR finger and ground contact GND finger on the top surface of the substrate 5 via metal leads 6 respectively;
[0039] It also includes a virtual chip dummy die. The front of the dummy die is a metal conductive layer, and the back of the dummy die is a non-metallic insulating layer. The dummy die is divided into PWR die DIE4 and GND die DIE3. The back of the PWR die and GND die face down and are located on the top surface of the auxiliary chip.
[0040] The power input terminal and ground input terminal of the main chip are respectively connected to the front side of the PWR die and the front side of the GND die via metal leads 6. The PWR finger and GND finger on the top surface of the substrate are respectively connected to the front side of the PWR die and the front side of the GND die via metal leads.
[0041] The power output terminal and ground output terminal of the main chip are respectively connected to the power input terminal and ground input terminal of the auxiliary chip via metal lead 6.
[0042] refer to Figure 2 In this example, the PWR die and GND die are two separate pieces. The PWR die is located on the front surface of the GND die, and the area of the PWR die is smaller than the area of the GND die.
[0043] refer to Figure 3 In a further optimized example, the PWR die and GND die are a single integrated structure. The conductive metal layer on the front side of the same dummy die is divided into two mutually insulated parts, serving as the conductive metal layers of the GND die and PWR die, respectively. In the integrated PWR die and GND die structure, the insulating region 7 between the conductive metal layers of the GND die and PWR die is composed of a non-metallic insulating layer exposed by removing the conductive metal layer. The insulating region is annular, with the conductive metal layer of the PWR die inside the annulus and the conductive metal layer of the GND die outside the annulus.
[0044] In this example, the side containing the power output terminal and ground output terminal of the main chip is defined as the power supply side, and the side containing the power input terminal and ground input terminal of the auxiliary chip is defined as the power supply side. The power supply side of the main chip is closer to the power supply side of the auxiliary chip.
[0045] In engineering implementation, the dummy die is made of aluminum on the front and silicon on the back, a common material used in packaging plants due to its low cost and ability to be manufactured into rectangles of any size. This dummy die was originally just a common material used in routine wire bonding tests at packaging plants; this solution cleverly utilizes it.
[0046] refer to Figure 2In this embodiment, two dummy dies are used as the GND die (DIE3) for grounding connection and the PWR die (DIE4) for power connection, respectively. This eliminates the need for a finger on the substrate to power the right side of the main chip DIE1 and the left side of the auxiliary chip DIE2. The distance between the main chip DIE1 and the auxiliary chip DIE2 is reduced from C0 to C1, thereby reducing the package size and increasing the substrate wiring space. The implementation process of the package structure in this embodiment is as follows:
[0047] 1) Move the power supply finger required by the main chip DIE1 to the empty space around the auxiliary chip DIE2. The power supply finger is divided into PWR (power) finger and GND (ground) finger.
[0048] 2) Connect the PWR finger to the dummy die DIE4 (i.e., the PWR die) and connect the GND finger to the dummy die DIE3 (i.e., the GND die).
[0049] 3) Since both DIE3 and DIE4 are made of a single piece of conductive aluminum, power supply interconnection is possible. DIE3 transmits power to the corresponding pad on the main chip DIE1 via wire bonding, and DIE4 transmits GND to the corresponding pad on the main chip DIE1 via wire bonding. This ultimately enables power supply to the main chip DIE1, which in turn supplies power to the auxiliary chip DIE2 via die-to-die wire bonding.
[0050] Figure 1 The existing package size shown is A0×B0. Figure 2 The package size in this example is reduced to A1×B0. This reduction in package size directly brings two major benefits: 1) a direct reduction in packaging costs; and 2) improved feasibility of chip applications in small-sized scenarios such as mobile electronic products. Furthermore, dummy dies are low-cost and simple to manufacture, and the expected increase in per-chip packaging cost is only a few cents, far less than the benefits of the reduced package size and increased substrate space.
[0051] like Figure 4 The diagrams showing the internal structure of the three package sides reveal that the package size in this example is significantly smaller. However, the package thickness increases due to the larger number of chips stacked on the left side. Further optimization is possible by integrating the PWR die and GND die planes onto a single dummy die. The PWR die portion is located on the outer ring plane of the dummy die, while the GND die portion is on the inner plane, with the PWR die and GND die planes spaced apart. This further reduces the package thickness.
[0052] The manufacturing process of this embodiment is as follows:
[0053] 1) Based on the size of the auxiliary chip DIE2, fabricate PWR / GND dies separately according to the embodiment, or fabricate a single dummy die integrating PWR / GND dies according to a further optimized scheme. Ensure that the dummy die does not press against the bonding pad of the auxiliary chip DIE2 and does not affect other bonding operations of the auxiliary chip DIE2. Stack the dummy dies upwards, with the size decreasing sequentially.
[0054] 2) Main chip DIE1 die assembly, auxiliary chip DIE2 die assembly, and dummy die assembly.
[0055] 3) Wire bonding.
[0056] 4) Plastic sealing, ball placement, and individual cutting to complete the encapsulation.
Claims
1. A packaging structure that increases substrate wiring space and reduces package size, comprising a substrate and multiple chip dies; at least two of the dies are laid flat on the top surface of the substrate and connected to contact fingers on the substrate via metal leads; the multiple dies are encapsulated in the substrate by molding compound; the multiple dies are divided into main chips and auxiliary chips; the power input terminal and ground input terminal of the main chip are connected to the power contact PWR finger and ground contact GND finger on the top surface of the substrate via metal leads. The application is characterized in that It also includes a virtual chip dummy die, the front of which is a metal conductive layer and the back of which is a non-metallic insulating layer; the dummy die is divided into a PWR die and a GND die; the back of the PWR die and the GND die face down and are located on the top surface of the auxiliary chip respectively; The power input terminal and ground input terminal of the main chip are connected to the front side of the PWR die and the front side of the GND die respectively via metal leads. The PWR finger and GND finger on the top surface of the substrate are connected to the front side of the PWR die and the front side of the GND die respectively via metal leads. The main chip's power output and ground output are connected to the auxiliary chip's power input and ground input via metal leads, respectively.
2. The packaging structure for increasing substrate wiring space and reducing package size according to claim 1, characterized in that: If the PWR die and GND die are two separate pieces, then the PWR die is located on the front surface of the GND die, and the area of the PWR die is smaller than the area of the GND die.
3. The packaging structure according to claim 1, which increases substrate wiring space and reduces package size, is characterized in that... The PWR die and GND die are a single integrated structure; therefore, the metal conductive layer on the front side of the same dummy die is divided into two mutually insulated parts, which serve as the metal conductive layers of the GND die and the PWR die, respectively.
4. The packaging structure for increasing substrate wiring space and reducing package size according to claim 1, characterized in that: In the integrated PWR die and GND die, the insulating region between the metal conductive layers of the GND die and the PWR die is composed of a non-metallic insulating layer exposed by removing the metal conductive layers.
5. The packaging structure for increasing substrate wiring space and reducing package size according to claim 4, characterized in that: The insulating region is ring-shaped, with the metal conductive layer of the PWR die inside the ring and the metal conductive layer of the GND die outside the ring.
6. The package structure for raising a substrate wiring space and reducing a package size according to claim 1, wherein Define the side containing the power output terminal and ground output terminal of the main chip as the power supply side, and define the side containing the power input terminal and ground input terminal of the auxiliary chip as the power supply side, with the power supply side of the main chip being closer to the power supply side of the auxiliary chip.