Semiconductor structure, semiconductor structure fabrication method and semiconductor power device

Abstract

This application relates to a semiconductor structure, a method for fabricating the semiconductor structure, and a semiconductor power device. The semiconductor structure includes a chip and an adapter. The chip includes a first surface along its thickness direction, and an electrode structure is disposed on one side of the first surface. The adapter includes an insulating layer and a first conductive layer and a second conductive layer disposed on both sides of the insulating layer along its thickness direction. The first conductive layer is electrically connected to the electrode structure. The adapter also includes a via structure that penetrates the insulating layer along its thickness direction, and the first and second conductive layers are electrically connected through the via structure. The semiconductor structure, the method for fabricating the semiconductor structure, and the semiconductor power device provided in this application can improve the electrical performance of the semiconductor power device and reduce the package size.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a semiconductor structure, a method for preparing the semiconductor structure, and a semiconductor power device. Background Technology

[0002] Semiconductor power devices are one of the important components in power electronics technology. They are mainly used to integrate one or more power conversion chips into the device through packaging, so as to protect the chip and provide thermal and electrical connection with the system.

[0003] In the fabrication of semiconductor power devices, it is necessary to minimize parasitic parameters generated during the packaging process to ensure the electrical performance of the semiconductor power devices. Summary of the Invention

[0004] The semiconductor structure, semiconductor structure preparation method, and semiconductor power device provided in this application embodiment can reduce the stray inductance of the semiconductor power device package.

[0005] In a first aspect, embodiments of this application provide a semiconductor structure, including: A chip, including a first surface along its thickness direction, wherein an electrode structure is disposed on one side of the first surface; The adapter includes an insulating layer and a first conductive layer and a second conductive layer disposed on both sides of the insulating layer along the thickness direction, wherein the first conductive layer is electrically connected to the electrode structure. The adapter further includes a via structure, which penetrates the insulating layer along the thickness direction, and the first conductive layer and the second conductive layer are electrically connected through the via structure.

[0006] In some embodiments, the electrode structure includes a first electrode and a second electrode spaced apart on the first surface, the first conductive layer includes a first conductive portion connected to the first electrode and a second conductive portion connected to the second electrode, and the second conductive layer includes a third conductive portion and a fourth conductive portion spaced apart. The via structure includes a first via and a second via. The first conductive part and the third conductive part are connected through the first via, and the second conductive part and the fourth conductive part are connected through the second via.

[0007] In some embodiments, the projection of the first electrode in the thickness direction and the projection of the first conductive portion in the thickness direction are at least partially overlapped. The projection shape of the first electrode in the thickness direction is consistent with the projection shape of the first conductive part in the thickness direction.

[0008] In some embodiments, the projection of the first conductive portion in the thickness direction and the projection of the third conductive portion in the thickness direction are at least partially overlapped. The projection of the first conductive part in the thickness direction overlaps at least partially with the projection of the fourth conductive part in the thickness direction. The projection of the first via in the thickness direction is located inside the overlapping area of ​​the projections of the first conductive part and the third conductive part.

[0009] In some embodiments, the projected shape of the third conductive portion in the thickness direction is different from the projected shape of the first electrode in the thickness direction; And / or, the projection shape of the third conductive portion in the thickness direction is different from the projection shape of the first conductive portion in the thickness direction; And / or, the projection shape of the fourth conductive portion in the thickness direction is different from the projection shape of the second electrode in the thickness direction; And / or, the projection shape of the fourth conductive part in the thickness direction is different from the projection shape of the second conductive part in the thickness direction.

[0010] In some embodiments, the projected outer contour of the first conductive layer in the thickness direction covers the projected outer contour of the electrode structure in the thickness direction. The projected outer contour of the second conductive layer in the thickness direction covers the projected outer contour of the first conductive layer in the thickness direction. The projection of the adapter in the thickness direction is located inside the projection of the chip in the thickness direction.

[0011] In some embodiments, a connector is further included, the connector being made of a conductive material and connected between the electrode structure and the first conductive layer, the side of the connector opposite to the electrode structure protruding from the first surface.

[0012] In some embodiments, a package is further included, the package including a first package portion filled between the insulating layer and the chip and a second package portion disposed on the side of the insulating layer facing the second conductive layer; The first encapsulation portion is disposed on the periphery of the first conductive layer, the second encapsulation portion is disposed on the periphery of the second conductive layer, and the surface of the second conductive layer away from the insulating layer protrudes from the second encapsulation portion.

[0013] Secondly, embodiments of this application provide a method for fabricating a semiconductor structure, including: A chip is provided, the chip including an electrode structure; A connector is formed on one side of the chip along the thickness direction, and the connector is correspondingly connected to the electrode structure; An adapter is provided, the adapter including an insulating layer and a first conductive layer and a second conductive layer disposed on both sides of the insulating layer along the thickness direction, the insulating layer having a through-hole structure through the thickness direction, the first conductive layer and the second conductive layer being electrically connected through the through-hole structure, and the first conductive layer being correspondingly connected to the adapter; A package is formed, wherein a portion of the package structure fills the space between the insulating layer and the chip.

[0014] Thirdly, embodiments of this application provide a semiconductor power device, including the aforementioned semiconductor structure.

[0015] According to the semiconductor structure, semiconductor structure fabrication method, and semiconductor power device provided in this application, the semiconductor structure is a structure used in the fabrication of a semiconductor power device. The semiconductor structure includes a chip and a connector. The chip includes a first surface along its thickness direction, and an electrode structure is disposed on one side of the first surface. The connector includes an insulating layer and a first conductive layer and a second conductive layer disposed on both sides of the insulating layer along its thickness direction. The first conductive layer is electrically connected to the electrode structure. When the first conductive layer is electrically connected to the electrode structure, the connector is located on one side of the chip along its thickness direction, and the connector and the chip form a sequential arrangement along the thickness direction, such that the projection of the connector in the thickness direction at least partially overlaps with the projection of the chip in the thickness direction, thereby reducing the package size of the chip. The first conductive layer and the second conductive layer are connected by a via structure disposed on both sides of the insulating layer along its thickness direction. The via structure penetrates the insulating layer, and the first conductive layer and the second conductive layer are electrically connected through the via structure. The projection of the first conductive layer in the thickness direction at least partially overlaps with the projection of the second conductive layer in the thickness direction. The projection of the via structure in the thickness direction is located within this overlapping area, so as to achieve the connection between the first and second conductive layers within the coverage area of ​​the adapter itself. This avoids increasing the size of the adapter due to connecting the first and second conductive layers, thereby reducing the package size of the chip. The first conductive layer, the via structure, and the second conductive layer form the lead-out line of the counter electrode structure. In actual installation, the extension dimension of the first conductive layer, the diameter dimension of the via structure, and the extension dimension of the second conductive layer are all larger than the diameter dimension of the lead. Compared with the lead-connection method in related technologies, the adapter generates less parasitic inductance and parasitic resistance while forming the lead-out line, which can improve current transmission and thus improve the electrical performance of semiconductor power devices. Attached Figure Description

[0016] The features, advantages, and technical effects of exemplary embodiments of this application will now be described with reference to the accompanying drawings.

[0017] Figure 1 This application provides a schematic diagram of the structure of a semiconductor power device according to some embodiments; Figure 2 This application provides a schematic diagram of a semiconductor structure according to some embodiments; Figure 3 This application provides a schematic diagram of the structure of a chip in a semiconductor structure, as shown in some embodiments. Figure 4 A perspective structural schematic diagram of a connector in a semiconductor structure provided for some embodiments of this application; Figure 5 A cross-sectional view of a semiconductor structure provided for some embodiments of this application; Figure 6 This is another schematic diagram of a semiconductor structure provided in some embodiments of this application; Figure 7 This is a schematic cross-sectional view of another semiconductor structure provided in some embodiments of this application; Figure 8 This is a schematic diagram illustrating another structure of a semiconductor power device provided for some embodiments of this application; Figure 9 This is a schematic diagram illustrating another structure of a semiconductor power device provided for some embodiments of this application; Figure 10 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this application.

[0018] Marker explanation: 100. Semiconductor structure; 10. Chip; 11. Electrode structure; 111. First electrode; 112. Second electrode; 20. Adapter; 21. Insulating layer; 22. First conductive layer; 221. First conductive part; 222. Second conductive part; 23. Second conductive layer; 231. Third conductive part; 232. Fourth conductive part; 30. Connectors; 40. Package component; 41. First package part; 42. Second package part; 43. Third package part; M1, First Surface; K1, via structure; K11, first via; K12, second via; Z, thickness direction; 200. Semiconductor power devices; 201, drive pin; 202, connecting bridge; 203, connecting pin.

[0019] In the accompanying drawings, the same parts use the same reference numerals. The drawings are not drawn to scale. Detailed Implementation

[0020] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0022] Semiconductor power devices are one of the important components in power electronics technology. They are mainly used to integrate one or more power conversion chips into the device through packaging, so as to protect the chip and provide thermal and electrical connection with the system.

[0023] In the fabrication process of semiconductor power devices, the main packaging connection methods include wire bonding and press-fit packaging. Both wire bonding and press-fit packaging inevitably use leads. Since the ratio between the cross-sectional area and length of the leads is relatively large, it will generate large parasitic inductance and parasitic resistance, which will have an adverse effect on the electrical performance of semiconductor power devices.

[0024] In view of this, firstly, please refer to Figures 1 to 5This application provides a semiconductor structure 100, including a chip 10 and an adapter 20. The chip 10 includes a first surface M1 along its thickness direction Z, and an electrode structure 11 is disposed on one side of the first surface M1. The adapter 20 includes an insulating layer 21 and a first conductive layer 22 and a second conductive layer 23 disposed on both sides of the insulating layer 21 along the thickness direction Z. The first conductive layer 22 is electrically connected to the electrode structure 11. The adapter 20 also includes a via structure K1, which penetrates the insulating layer 21 along the thickness direction Z, and the first conductive layer 22 and the second conductive layer 23 are electrically connected through the via structure K1.

[0025] The semiconductor structure 100 provided in this application embodiment is one structure in the fabrication process of the semiconductor power device 200. The semiconductor structure 100 includes a chip 10 and an adapter 20. The chip 10, as the core structural component of the semiconductor structure 100, is used to control and convert electrical energy. In the conventional fabrication process of the semiconductor power device 200, the chip 10 is mainly packaged using wire bonding and press-fit bonding.

[0026] In wire bonding packages, relatively complex interconnection lines need to be set inside the semiconductor power device 200 to achieve electrical connections between different chips 10, which occupies a large package area. Due to the wire connection, significant parasitic inductance and resistance will be generated, affecting the electrical performance of the semiconductor power device 200. In press-fit packages, since the driving electrodes of the chips 10 are generally small and difficult to directly withstand pressure, wire connections are still used at the driving electrodes, which will also generate certain parasitic inductance and resistance, affecting the electrical performance of the semiconductor power device 200.

[0027] To improve the electrical performance of the semiconductor power device 200, the semiconductor structure 100 provided in this embodiment includes a chip 10 and an adapter 20. The chip 10 has corresponding electrode structures 11, and the adapter 20 has corresponding conductor layers. The conductor layers on the adapter 20 are electrically connected to the electrode structures 11 on the chip 10. Other structures in the semiconductor power device 200, such as pins, can be directly electrically connected to the electrode structures 11 on the chip 10 through the conductor layers on the adapter 20. The adapter 20 reduces the number of leads in the semiconductor power device 200, thereby reducing parasitic inductance and resistance caused by the leads and improving the electrical performance of the semiconductor power device 200.

[0028] Optionally, the semiconductor power device 200 includes the aforementioned chip 10, adapter 20, and drive pin 201. The drive pin 201 is directly connected to the conductor layer of the adapter 20 to achieve electrical connection with the electrode structure 11 on the chip 10. For example, the drive pin 201 can be connected to the conductor layer of the adapter via ultrasonic terminal soldering or soldering. Optionally, the semiconductor power device 200 includes the aforementioned chip 10, adapter 20, and connecting bridge 202. The connecting bridge 202 is directly connected to the conductor layer of the adapter 20. The connecting bridge 202 can be connected to the conductor layer of the adapter via ultrasonic terminal soldering or soldering to achieve electrical connection with the electrode structure 11 on the chip 10. This eliminates the need for other adapter structures such as molybdenum sheets, simplifying the structure of the semiconductor power device 200. Optionally, the semiconductor power device 200 includes the aforementioned chip 10, adapter 20, drive pin 201, and connecting bridge 202. Both drive pin 201 and connecting bridge 202 are directly connected to the conductor layer of the adapter, achieving electrical connection with the electrode structure 11 on the chip 10. Furthermore, the conductor layer on the adapter 20 can be made of the same material as the drive pin 201 or connecting bridge 202, thereby reducing damage at the connection point due to differences in thermal expansion between different materials.

[0029] Specifically, the chip 10 includes a first surface M1 along the thickness direction Z, and an electrode structure 11 is disposed on one side of the first surface M1. The adapter 20 includes an insulating layer 21 and a first conductive layer 22 and a second conductive layer 23 disposed on both sides of the insulating layer 21 along the thickness direction Z. The first conductive layer 22 is electrically connected to the electrode structure 11. It can be understood that the chip 10 has the electrode structure 11 disposed on one side of its thickness direction Z, and the adapter 20 has the first conductive layer 22 disposed on one side of its thickness direction Z. When the first conductive layer 22 is electrically connected to the electrode structure 11, the adapter 20 is located on one side of the chip 10 along the thickness direction Z. The adapter 20 and the chip 10 form a layout in which they are sequentially disposed along the thickness direction Z, such that the projection of the adapter 20 in the thickness direction Z at least partially overlaps with the projection of the chip 10 in the thickness direction Z, thereby reducing the package volume of the chip 10. Furthermore, based on the electrode structure 11, the projection of the electrode structure 11 on one side of the chip 10 along the thickness direction Z is located inside the projection of the chip 10 in the thickness direction Z. This can reduce the volume of the adapter 20, making the projection of the adapter 20 in the thickness direction Z inside the projection of the chip 10 in the thickness direction Z, so that the projection area of ​​the chip 10 in the thickness direction Z is as close as possible to the package area, thereby reducing the package volume of the chip 10.

[0030] In order to reduce the size of the adapter 20, the first conductive layer 22 and the second conductive layer 23 are connected by a via structure K1 provided in the insulating layer 21. The first conductive layer 22 and the second conductive layer 23 are provided on both sides of the insulating layer 21 along the thickness direction Z. The via structure K1 is provided through the insulating layer 21, and the first conductive layer 22 and the second conductive layer 23 are electrically connected through the via structure K1. In other words, during the fabrication of the first conductive layer 22 and the second conductive layer 23, the projections of the first conductive layer 22 and the second conductive layer 23 in the thickness direction Z at least partially overlap. The projection of the via structure K1 in the thickness direction Z is located within this overlapping area. The via structure K1 is filled with a conductive structure, and the first conductive layer 22 and the second conductive layer 23 are electrically connected through the conductive structure inside the via structure K1. This achieves the connection between the first conductive layer 22 and the second conductive layer 23 within the coverage area of ​​the adapter 20, avoiding an increase in the volume of the adapter 20 due to the connection between the first conductive layer 22 and the second conductive layer 23, thereby reducing the package size of the chip 10. Optionally, the insulating layer 21 can be made of ceramic material. Ceramic material has a low coefficient of thermal expansion, and after being connected to the chip 10, it will not generate excessive thermal stress, thereby reducing damage to the chip 10. At the same time, ceramic material also has a relatively large thermal fusion capacity, which can reduce the temperature difference between the two surfaces of the chip 10 along the thickness direction Z, thereby reducing the probability of damage to the chip 10 due to inconsistent thermal expansion.

[0031] The first conductive layer 22 on the adapter 20 is connected to the electrode structure 11 on the chip 10, and the second conductive layer 23 is connected to the first conductive layer 22 through the via structure K1. The first conductive layer 22, the via structure K1, and the second conductive layer 23 form the lead-out line of the electrode structure 11. In actual setup, a larger area of ​​the first conductive layer 22 and the second conductive layer 23 can be provided on both sides of the insulating layer 21. The extension dimension of the first conductive layer 22, the diameter dimension of the via structure K1, and the extension dimension of the second conductive layer 23 are all larger than the diameter dimension of the lead. Compared with the lead-connection method in related technologies, the adapter 20 can form a shorter connection of the lead-out line through vertical connection, thereby reducing the parasitic inductance and parasitic resistance generated by the lead-out line, improving current throughput, and thus improving the electrical performance of the semiconductor power device 200.

[0032] In summary, in this embodiment, the semiconductor structure 100 is a structure used in the fabrication of the semiconductor power device 200. The semiconductor structure 100 includes a chip 10 and a connector 20. The chip 10 includes a first surface M1 along the thickness direction Z, and an electrode structure 11 is disposed on one side of the first surface M1. The connector 20 includes an insulating layer 21 and a first conductive layer 22 and a second conductive layer 23 disposed on both sides of the insulating layer 21 along the thickness direction Z. The first conductive layer 22 is electrically connected to the electrode structure 11. When the first conductive layer 22 is electrically connected to the electrode structure 11, the connector 20 is located on one side of the chip 10 along the thickness direction Z. The connector 20 and the chip 10 are arranged sequentially along the thickness direction Z, such that the projection of the connector 20 in the thickness direction Z at least partially overlaps with the projection of the chip 10 in the thickness direction Z, thereby reducing the package size of the chip 10. The first conductive layer 22 and the second conductive layer 23 are connected by a via structure K1 provided in the insulating layer 21. The first conductive layer 22 and the second conductive layer 23 are disposed on opposite sides of the insulating layer 21 along the thickness direction Z. The via structure K1 penetrates the insulating layer 21, and the first conductive layer 22 and the second conductive layer 23 are electrically connected through the via structure K1. The projection of the first conductive layer 22 in the thickness direction Z at least partially overlaps with the projection of the second conductive layer 23 in the thickness direction Z. The projection of the via structure K1 in the thickness direction Z is located within the overlapping area, so that the connection between the first conductive layer 22 and the second conductive layer 23 can be achieved within the coverage area of ​​the adapter 20 itself. This avoids increasing the volume of the adapter 20 due to the connection of the first conductive layer 22 and the second conductive layer 23, thereby reducing the package size of the chip 10. The first conductive layer 22, the via structure K1, and the second conductive layer 23 form the lead-out line of the counter electrode structure 11. In actual setup, the extension dimensions of the first conductive layer 22, the diameter of the via structure K1, and the extension dimensions of the second conductive layer 23 are all larger than the diameter of the lead wire. Compared with the lead wire connection method in related technologies, the adapter 20 generates less parasitic inductance and parasitic resistance while forming the lead wire, which can improve the current flow and thus improve the electrical performance of the semiconductor power device 200.

[0033] In some embodiments, please refer to Figures 2 to 5 The electrode structure 11 includes a first electrode 111 and a second electrode 112 spaced apart on the first surface M1. The first conductive layer 22 includes a first conductive portion 221 corresponding to and connected to the first electrode 111 and a second conductive portion 222 corresponding to and connected to the second electrode 112. The second conductive layer 23 includes a third conductive portion 231 and a fourth conductive portion 232 spaced apart. The via structure K1 includes a first via K11 and a second via K12. The first conductive portion 221 and the third conductive portion 231 are connected through the first via K11, and the second conductive portion 222 and the fourth conductive portion 232 are connected through the second via K12.

[0034] In a semiconductor chip 10, different types of electrode structures 11 are typically included, each performing a different function in the circuit. In this embodiment, the electrode structures 11 on the chip 10 include a first electrode 111 and a second electrode 112 on a first surface M1, spaced apart. It is understood that both the first electrode 111 and the second electrode 112 are electrode structures 11. Due to the different types of electrodes, insulation is required between them to ensure the smooth operation of the circuit. The first electrode 111 represents one type of electrode in the electrode structure 11, while the second electrode 112 represents another type. For ease of description, one type of electrode is defined as the first electrode 111, and the other as the second electrode 112. For example, the first electrode 111 may be a drive control electrode, and the second electrode 112 may be a power conduction electrode.

[0035] Different types of first electrodes 111 and second electrodes 112 require different lead-out lines. Based on the first electrodes 111 and 112, the first conductive layer 22 includes a first conductive portion 221 corresponding to the first electrode 111 and a second conductive portion 222 corresponding to the second electrode 112, with an insulating gap between the first conductive portion 221 and the second conductive portion 222. Simultaneously, the second conductive layer 23 includes a third conductive portion 231 and a fourth conductive portion 232 spaced apart, with an insulating gap between the third conductive portion 231 and the fourth conductive portion 232.

[0036] The projection of the third conductive part 231 in the thickness direction Z at least partially overlaps with the projection of the first conductive part 221 in the thickness direction Z. The via structure K1 includes a first via K11, through which the first conductive part 221 and the third conductive part 231 are connected. The projection of the fourth conductive part 232 in the thickness direction Z at least partially overlaps with the projection of the second conductive part 222 in the thickness direction Z. The via structure K1 also includes a second via K12, through which the second conductive part 222 and the fourth conductive part 232 are connected.

[0037] The first conductive part 221, the first via K11, and the third conductive part 231 form the lead-out line of the first electrode 111, and the second conductive part 222, the second via K12, and the fourth conductive part 232 form the lead-out line of the second electrode 112. Optionally, multiple first vias K11 can be provided, forming multiple connection positions between the first conductive part 221 and the third conductive part 231 to improve the connection stability between the first conductive part 221 and the third conductive part 231 and improve the reliability of the lead-out line of the first electrode 111. Similarly, multiple second vias K12 can be provided, forming multiple connection positions between the second conductive part 222 and the fourth conductive part 232 to improve the connection stability between the second conductive part 222 and the fourth conductive part 232 and improve the reliability of the lead-out line of the second electrode 112.

[0038] In some embodiments, please refer to Figures 2 to 5 The projection of the first electrode 111 in the thickness direction Z at least partially overlaps with the projection of the first conductive portion 221 in the thickness direction Z. The shape of the projection of the first electrode 111 in the thickness direction Z is consistent with the shape of the projection of the first conductive portion 221 in the thickness direction Z.

[0039] By at least partially overlapping the projection of the first electrode 111 in the thickness direction Z with the projection of the first conductive part 221 in the thickness direction Z, the first electrode 111 and the first conductive part 221 are connected at the overlapping position of their projections. To ensure the connection stability between the first electrode 111 and the first conductive part 221, the overlapping area of ​​their projections can be enlarged, thereby increasing the connection area between the first electrode 111 and the first conductive part 221 and improving the connection stability between them.

[0040] Furthermore, the projection shape of the first conductive portion 221 in the thickness direction Z can be set to be consistent with the projection shape of the first electrode 111 in the thickness direction Z, so that the first conductive portion 221 and the first electrode 111 can be adapted in projection shape. Optionally, the projection area of ​​the first conductive portion 221 in the thickness direction Z can be equal to the projection area of ​​the first electrode 111 in the thickness direction Z, and the projection of the first conductive portion 221 in the thickness direction Z coincides with the projection of the first electrode 111 in the thickness direction Z, so that the first electrode 111 and the first conductive portion 221 are fully conductive within the set range. Optionally, considering that the first electrode 111 and the second electrode 112 are distributed at intervals on the first surface M1, the projection area of ​​the first conductive portion 221 can be slightly larger than the projection area of ​​the first electrode 111. It can be understood that the projection of the first conductive portion 221 in the thickness direction Z covers and exceeds the projection of the first electrode 111 in the thickness direction Z, and the projection of the first conductive portion 221 in the thickness direction Z and the projection of the second electrode 112 in the thickness direction Z are distributed at intervals.

[0041] In actual setup, there may be a certain degree of alignment deviation between the adapter 20 and the chip 10, resulting in a certain degree of alignment deviation between the first conductive part 221 and the first electrode 111. Covering and extending the projection of the first conductive part 221 in the thickness direction Z beyond the projection of the first electrode 111 in the thickness direction Z ensures a large connection area between them. Simultaneously, the spaced distribution of the projections of the first conductive part 221 and the second electrode 112 in the thickness direction Z also prevents electrical connection between them, thus ensuring the independence of the lead-out lines between the first electrode 111 and the second electrode 112.

[0042] Optionally, the relative arrangement between the second electrode 112 and the second conductive part 222 can be the same as the relative arrangement between the first electrode 111 and the first conductive part 221. For specific arrangements, please refer to the above description of the relative arrangement between the first electrode 111 and the first conductive part 221, which will not be repeated here.

[0043] In some embodiments, please refer to Figure 4 The projection of the first conductive portion 221 in the thickness direction Z at least partially overlaps with the projection of the third conductive portion 231 in the thickness direction Z. The projection of the first conductive portion 221 in the thickness direction Z at least partially overlaps with the projection of the fourth conductive portion 232 in the thickness direction Z. The projection of the first via K11 in the thickness direction Z is located inside the overlapping area of ​​the projections of the first conductive portion 221 and the third conductive portion 231.

[0044] In the lead-out line of the first electrode 111, after the first conductive part 221 is connected to the first electrode 111, the first conductive part 221 is connected to the third conductive part 231 through the first via K11, and an insulating layer 21 is also provided between the first conductive part 221 and the third conductive part 231. During the installation of the adapter 20, the first conductive part 221 only needs to be insulated from the second conductive part 222 and electrically connected to the third conductive part 231 through the first via K11. The arrangement of the first conductive part 221, the third conductive part 231, and the fourth conductive part 232 on the adapter 20 can be flexibly configured.

[0045] In this embodiment, to facilitate the connection between the first conductive part 221 and the third conductive part 231 via K11, the projection of the first conductive part 221 in the thickness direction Z and the projection of the third conductive part 231 in the thickness direction Z are at least partially overlapped. The projection of the first via K11 in the thickness direction Z is located inside the overlapping area of ​​the projections of the first conductive part 221 and the third conductive part 231 in the thickness direction Z. The above arrangement can make the first conductive part 221 and the second conductive part 222 conduction in the form that the first via K11 is vertically arranged along the thickness direction Z, which facilitates the preparation and production of the adapter 20.

[0046] Meanwhile, the projection of the first conductive part 221 in the thickness direction Z can at least partially overlap with the projection of the fourth conductive part 232 in the thickness direction Z. Since the first conductive part 221 and the fourth conductive part 232 are located in two separate conductive layers, separated by an insulating layer 21, and there are no vias connecting the first conductive part 221 and the fourth conductive part 232, insulation between the first conductive part 221 and the fourth conductive part 232 can be ensured. The relative positions of the first conductive part 221 and the fourth conductive part 232 can be flexibly adjusted based on specific circumstances.

[0047] Optionally, the projection of the second conductive portion 222 in the thickness direction Z at least partially overlaps with the projection of the fourth conductive portion 232 in the thickness direction Z, and the projection of the second via K12 in the thickness direction Z is located within the overlapping area of ​​the projections of the second conductive portion 222 and the fourth conductive portion 232 in the thickness direction Z. The projection of the second conductive portion 222 in the thickness direction Z may also at least partially overlap with the projection of the third conductive portion 231 in the thickness direction Z.

[0048] Based on the insulating layer 21 in the adapter 20, the first conductive layer 22 and the second conductive layer 23 are respectively disposed on both sides of the insulating layer 21 along the thickness direction Z. The first conductive part 221 and the second conductive part 222 are disposed corresponding to the positions of the first electrode 111 and the second electrode 112. The third conductive part 231 and the fourth conductive part 232 can change their positions relative to the first conductive part 221 and the second conductive part 222 to facilitate the subsequent setting of the drive pin 201 and the connecting bridge 202 in the semiconductor power device 200.

[0049] In some embodiments, please refer to Figures 2 to 5 The projection shape of the third conductive portion 231 in the thickness direction Z is different from the projection shape of the first electrode 111 in the thickness direction Z. And / or, the projection shape of the third conductive portion 231 in the thickness direction Z is different from the projection shape of the first conductive portion 221 in the thickness direction Z. And / or, the projection shape of the fourth conductive portion 232 in the thickness direction Z is different from the projection shape of the second electrode 112 in the thickness direction Z. And / or, the projection shape of the fourth conductive portion 232 in the thickness direction Z is different from the projection shape of the second conductive portion 222 in the thickness direction Z.

[0050] In the lead-out line of the first electrode 111, after the first conductive part 221 is connected to the first electrode 111, the first conductive part 221 is connected to the third conductive part 231 through the first via K11. The subsequent lead-out structure of the semiconductor power device 200 related to the first electrode 111 is connected to the third conductive part 231. During the chip 10 setup process, based on the specific structure of the chip 10, the first electrode 111 has a specific shape. However, there is a problem that the shape of the first electrode 111 is not convenient for subsequent connections. The projection shape of the third conductive part 231 in the thickness direction Z can be set to a different form from the projection shape of the first electrode 111 in the thickness direction Z. By changing the shape of the third conductive part 231, the connection shape of the lead-out line of the first electrode 111 can be changed, so as to facilitate the connection of the subsequent lead-out structure of the first electrode 111 in the semiconductor power device 200. For example, the shape of the first electrode 111 is elongated, and the shape of the third conductive part 231 can be square, so as to widen a certain size in a specific direction to facilitate the connection of the subsequent lead-out structure.

[0051] Optionally, since the third conductive part 231 and the first conductive part 221 are relatively independently arranged, the projection shape of the third conductive part 231 in the thickness direction Z and the projection shape of the first conductive part 221 in the thickness direction Z can also be set to different forms. The third conductive part 231 changes its setting shape relative to the first conductive part 221 in order to facilitate the setting of the driving pin 201 and the connecting bridge 202 in the subsequent semiconductor power device 200.

[0052] In the lead-out line of the second electrode 112, after the second conductive part 222 is connected to the second electrode 112, the second conductive part 222 is connected to the fourth conductive part 232 through the second via K12. The subsequent lead-out structure of the semiconductor power device 200 related to the second electrode 112 is connected to the fourth conductive part 232. During the chip 10 setup process, based on the specific structure of the chip 10, the second electrode 112 has a specific shape. However, there is a problem that the shape of the second electrode 112 is not convenient for subsequent connections. The projection shape of the fourth conductive part 232 in the thickness direction Z can be set to a different form from the projection shape of the second electrode 112 in the thickness direction Z. By changing the shape of the fourth conductive part 232, the connection shape of the lead-out line of the second electrode 112 can be changed, so as to facilitate the connection of the subsequent lead-out structure of the second electrode 112 in the semiconductor power device 200. For example, the shape of the second electrode 112 is semi-circular, and the shape of the fourth conductive part 232 can be square, so as to widen a certain dimension in a specific direction to facilitate the connection of the subsequent lead-out structure. Optionally, multiple second electrodes 112 may be provided, and all multiple second electrodes 112 are connected to the fourth conductive part 232.

[0053] Optionally, since the fourth conductive part 232 and the second conductive part 222 are relatively independently arranged, the projection shape of the fourth conductive part 232 in the thickness direction Z and the projection shape of the second conductive part 222 in the thickness direction Z can also be set to different forms. The fourth conductive part 232 changes its setting shape relative to the second conductive part 222 to facilitate the setting of the driving pin 201 and the connecting bridge 202 in the subsequent semiconductor power device 200.

[0054] In some embodiments, please refer to Figures 2 to 5 The outer contour of the projection of the first conductive layer 22 in the thickness direction Z covers the outer contour of the projection of the electrode structure 11 in the thickness direction Z. The outer contour of the projection of the second conductive layer 23 in the thickness direction Z covers the outer contour of the projection of the first conductive layer 22 in the thickness direction Z. The projection of the adapter 20 in the thickness direction Z is located inside the projection of the chip 10 in the thickness direction Z.

[0055] To facilitate the subsequent setup of the drive pins 201 and the connecting bridge 202 in the semiconductor power device 200, the projection of the lead-out lines of the electrode structure 11 in the thickness direction Z is made to increase the connection area of ​​the lead-out lines of the electrode structure 11, thereby facilitating the subsequent setup of the drive pins 201 and the connecting bridge 202 in the semiconductor power device 200.

[0056] Specifically, in the connection line between the first conductive layer 22 and the electrode structure 11, the projected outer contour of the first conductive layer 22 in the thickness direction Z covers and extends the projected outer contour of the electrode structure 11 in the thickness direction Z; in the connection line between the second conductive layer 23 and the first conductive layer 22, the projected outer contour of the second conductive layer 23 in the thickness direction Z covers and extends the projected outer contour of the first conductive layer 22 in the thickness direction Z. The connection areas of the electrode structure 11, the first conductive layer 22, and the second conductive layer 23 increase sequentially, which facilitates the connection and configuration of the drive pin 201 and the connecting bridge 202 in the subsequent semiconductor power device 200.

[0057] In order not to affect the packaging volume of the semiconductor structure 100, the projection of the adapter 20 in the thickness direction Z is located inside the projection of the chip 10 in the thickness direction Z, so that the edge of the adapter 20 in the thickness direction Z does not exceed the edge of the chip 10 in the thickness direction Z. In the subsequent packaging process, the packaging can be based on the volume of the chip 10, and the packaging volume of the semiconductor structure 100 can be reduced as much as possible.

[0058] In some embodiments, please refer to Figure 5 It also includes a connector 30, which is made of conductive material. The connector 30 is connected between the electrode structure 11 and the first conductive layer 22. The side of the connector 30 facing away from the electrode structure 11 protrudes from the first surface M1.

[0059] Since the chip 10 and the adapter 20 are two relatively independent structural components, in order to improve the connection reliability between the first conductive layer 22 and the electrode structure 11, the semiconductor structure 100 also includes a connector 30, which is disposed between the first conductive layer 22 and the electrode structure 11. The connector 30 is made of a conductive material. When the connector 30 is connected to the electrode structure 11, the side of the connector 30 facing away from the electrode structure 11 protrudes from the first surface M1, so that the first conductive layer 22 can form good contact with the connector 30, reducing the probability that other positions on the first surface M1 will affect the connection between the first conductive layer 22 and the electrode structure 11 due to their high protrusion.

[0060] Optionally, the connector 30 is made of silver and is connected to the electrode structure 11 by silver film transfer or silver paste screen printing. Optionally, the connecting layer may also include materials with good electrical and thermal conductivity, such as solder paste or solder sheets. In the actual fabrication process, the connector 30 can be pre-connected to either the first conductive layer 22 or the electrode structure 11 to ensure reliable connection between the first conductive layer 22 and the electrode structure 11 during the connection process between the chip 10 and the adapter 20.

[0061] In some embodiments, please refer to Figure 5It also includes a package 40, which includes a first package portion 41 filled between the insulating layer 21 and the chip 10, and a second package portion 42 disposed on the side of the insulating layer 21 facing the second conductive layer 23. The first package portion 41 is disposed on the periphery of the first conductive layer 22, and the second package portion 42 is disposed on the periphery of the second conductive layer 23. The surface of the second conductive layer 23 away from the insulating layer 21 protrudes from the second package portion 42.

[0062] The package 40 is disposed around the chip 10 and the adapter 20. After the chip 10 and the adapter 20 are connected together, there is a certain gap between them, which is not conducive to the thermal conductivity of the semiconductor structure 100 and has poor support strength. Therefore, the package 40 is formed by injection molding to fill the gap between the chip 10 and the adapter 20. Optionally, the package 40 can also be formed by gap filling. The package 40 may include epoxy resin, or the package 40 may also include encapsulation materials such as insulating thermally conductive adhesive with good flowability and low coefficient of thermal expansion.

[0063] During the encapsulation process of the package 40 for the chip 10 and the adapter 20, the package 40 includes a first encapsulation portion 41 filled between the insulating layer 21 and the chip 10, and a second encapsulation portion 42 on the side where the insulating layer 21 faces the second conductive layer 23. The first encapsulation portion 41 is disposed around the first conductive layer 22 to insulate and encapsulate the first conductive layer 22, and fills the gap between the insulating layer 21 and the chip 10, thereby improving the support strength of the semiconductor structure 100. The second encapsulation portion 42 is disposed around the second conductive layer 23 to insulate and encapsulate the second conductive layer 23. In order to facilitate the installation of subsequent structures in the semiconductor power device 200, the surface of the second conductive layer 23 away from the insulating layer 21 is provided to protrude from the second encapsulation portion 42, thereby reducing the probability that the second encapsulation portion 42 covers the second conductive layer 23 in the thickness direction Z, so that the surface of the second conductive layer 23 can be exposed to facilitate the installation of subsequent structures.

[0064] Optionally, the package 40 further includes a third package portion 43, which is integrally formed with the first package portion 41 and the second package. The third package portion 43 is located at the edge of the chip 10 and the adapter 20 in the thickness direction Z, so as to encapsulate and protect the edge of the chip 10 and the adapter 20 in the thickness direction Z.

[0065] Optionally, please refer to Figures 6 to 9The package 40 may consist only of a first package portion 41, which is disposed around the first conductive layer 22 to insulate and encapsulate the first conductive layer 22 and fill the gap between the insulating layer 21 and the chip 10, thereby improving the support strength of the semiconductor structure 100. When the package 40 consists only of the first package portion 41, there is no package 40 around the second conductive layer 23, and subsequent connection structures are directly connected to the second conductive layer 23.

[0066] Secondly, please refer to Figure 10 This application provides a method for fabricating a semiconductor structure 100, comprising: S10, a chip 10 is provided, the chip 10 including an electrode structure 11; S20. A connector 30 is formed on one side of the chip 10 along the thickness direction Z, and the connector 30 is connected to the electrode structure 11. S30. Provide an adapter 20. The adapter 20 includes an insulating layer 21 and a first conductive layer 22 and a second conductive layer 23 disposed on both sides of the insulating layer 21 along the thickness direction Z. The insulating layer 21 is provided with a through-hole structure K1 along the thickness direction Z. The first conductive layer 22 and the second conductive layer 23 are electrically connected through the through-hole structure K1. The first conductive layer 22 is correspondingly connected to the connector 30. S40, forming a package 40, with a portion of the structure of the package 40 filling the space between the insulating layer 21 and the chip 10.

[0067] In the fabrication process of the semiconductor structure 100, a chip 10 is first provided, on which a preset electrode structure 11 is provided. Then, a connector 30 is formed at the corresponding electrode structure 11 on the chip 10. The side of the connector 30 facing away from the electrode structure 11 protrudes from the rest of the chip 10 to facilitate the subsequent installation of the adapter 20. Next, the adapter 20 is provided, with a first conductive layer 22 on the adapter 20 correspondingly connected to the connector 30. A second conductive layer 23 on the adapter 20 is connected to the first conductive layer 22 through a via structure K1. After the first conductive layer 22 on the adapter 20 is connected to the connector 30, the electrode structure 11 becomes conductive to the second conductive layer 23 on the adapter. Finally, a package 40 is formed, with a portion of the package 40 filling the space between the insulating layer 21 and the chip 10, encapsulating and insulating the first conductive layer 22 to form a reliable lead-out line between the electrode structure 11 and the second conductive layer 23.

[0068] Thirdly, please refer to Figure 1 , Figure 8 and Figure 9This application provides a semiconductor power device 200, which includes the semiconductor structure 100 described in the first aspect of this application. The semiconductor power device 200 includes all the technical features and effects of the semiconductor structure 100, and will not be repeated here.

[0069] In some embodiments, the semiconductor power device 200 includes the chip 10, the adapter 20, and a drive pin 201. The drive pin 201 is directly connected to the conductor layer of the adapter 20 to achieve electrical connection with the electrode structure 11 on the chip 10. Exemplarily, the drive pin 201 can be connected to the conductor layer of the adapter via ultrasonic terminal soldering or soldering. Optionally, the semiconductor power device 200 includes the chip 10, the adapter 20, and a connecting bridge 202. The connecting bridge 202 is directly connected to the conductor layer of the adapter 20. The connecting bridge 202 can be connected to the conductor layer of the adapter via ultrasonic terminal soldering or soldering to achieve electrical connection with the electrode structure 11 on the chip 10, eliminating the need for other adapter structures such as molybdenum sheets and simplifying the structure of the semiconductor power device 200. Optionally, the connecting bridge 202 can also be replaced by a connecting pin 203 to achieve connection between the semiconductor power device 200 and other structures.

[0070] Optionally, the semiconductor power device 200 includes the aforementioned chip 10, adapter 20, drive pin 201, and connecting bridge 202. Both drive pin 201 and connecting bridge 202 are directly connected to the conductor layer of the adapter, achieving electrical connection with the electrode structure 11 on the chip 10. Optionally, the conductor layer on the adapter 20 can be made of the same material as the drive pin 201 or connecting bridge 202, thereby reducing damage at the connection point due to differences in thermal expansion between different materials.

[0071] Although the invention has been described with reference to preferred embodiments, various modifications can be made and components can be replaced with equivalents without departing from the scope of the invention. In particular, the technical features mentioned in the various embodiments can be combined in any manner as long as there is no structural conflict. The invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: A chip, including a first surface along its thickness direction, wherein an electrode structure is disposed on one side of the first surface; The adapter includes an insulating layer and a first conductive layer and a second conductive layer disposed on both sides of the insulating layer along the thickness direction, wherein the first conductive layer is electrically connected to the electrode structure. The adapter further includes a via structure, which penetrates the insulating layer along the thickness direction, and the first conductive layer and the second conductive layer are electrically connected through the via structure.

2. The semiconductor structure according to claim 1, characterized in that, The electrode structure includes a first electrode and a second electrode spaced apart on the first surface. The first conductive layer includes a first conductive portion connected to the first electrode and a second conductive portion connected to the second electrode. The second conductive layer includes a third conductive portion and a fourth conductive portion spaced apart. The via structure includes a first via and a second via. The first conductive part and the third conductive part are connected through the first via, and the second conductive part and the fourth conductive part are connected through the second via.

3. The semiconductor structure according to claim 2, characterized in that, The projection of the first electrode in the thickness direction overlaps at least partially with the projection of the first conductive portion in the thickness direction. The projection shape of the first electrode in the thickness direction is consistent with the projection shape of the first conductive part in the thickness direction.

4. The semiconductor structure according to claim 2, characterized in that, The projection of the first conductive part in the thickness direction overlaps at least partially with the projection of the third conductive part in the thickness direction. The projection of the first conductive part in the thickness direction overlaps at least partially with the projection of the fourth conductive part in the thickness direction. The projection of the first via in the thickness direction is located inside the overlapping area of ​​the projections of the first conductive part and the third conductive part.

5. The semiconductor structure according to claim 2, characterized in that, The projection shape of the third conductive part in the thickness direction is different from the projection shape of the first electrode in the thickness direction; And / or, the projection shape of the third conductive portion in the thickness direction is different from the projection shape of the first conductive portion in the thickness direction; And / or, the projection shape of the fourth conductive portion in the thickness direction is different from the projection shape of the second electrode in the thickness direction; And / or, the projection shape of the fourth conductive part in the thickness direction is different from the projection shape of the second conductive part in the thickness direction.

6. The semiconductor structure according to claim 1, characterized in that, The projected outer contour of the first conductive layer in the thickness direction covers the projected outer contour of the electrode structure in the thickness direction. The projected outer contour of the second conductive layer in the thickness direction covers the projected outer contour of the first conductive layer in the thickness direction. The projection of the adapter in the thickness direction is located inside the projection of the chip in the thickness direction.

7. The semiconductor structure according to claim 1, characterized in that, It also includes a connector, which is made of conductive material and is connected between the electrode structure and the first conductive layer. The side of the connector facing away from the electrode structure protrudes from the first surface.

8. The semiconductor structure according to claim 7, characterized in that, It also includes a package, the package comprising a first package portion filled between the insulating layer and the chip, and a second package portion disposed on the side of the insulating layer facing the second conductive layer; The first encapsulation portion is disposed on the periphery of the first conductive layer, the second encapsulation portion is disposed on the periphery of the second conductive layer, and the surface of the second conductive layer away from the insulating layer protrudes from the second encapsulation portion.

9. A method for fabricating a semiconductor structure, characterized in that, include: A chip is provided, the chip including an electrode structure; A connector is formed on one side of the chip along the thickness direction, and the connector is correspondingly connected to the electrode structure; An adapter is provided, the adapter including an insulating layer and a first conductive layer and a second conductive layer disposed on both sides of the insulating layer along the thickness direction, the insulating layer having a through-hole structure through the thickness direction, the first conductive layer and the second conductive layer being electrically connected through the through-hole structure, and the first conductive layer being correspondingly connected to the adapter; A package is formed, wherein a portion of the package structure fills the space between the insulating layer and the chip.

10. A semiconductor power device, characterized in that, Includes the semiconductor structure described in any one of claims 1-8.

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