A bga ssd small size package structure and method based on tmv and vertical wire bonding

Abstract

This invention discloses a small-size BGA SSD packaging structure and method based on TMV and vertical wire bonding. The invention relates to the field of semiconductor packaging technology and includes: a substrate; an RDL layer disposed parallel above the substrate, the distance between the RDL layer and the substrate not exceeding a first predetermined distance; multiple chips stacked alternately on the substrate, with gold wires soldered to the chips perpendicularly upwards to the RDL layer; and a first component with its pads facing upwards on the substrate, the pads connected to the RDL layer via vertically upward-facing copper pillars. This invention ensures that the gold wires are perpendicular to the substrate or chips, avoiding the problems of uneven or interlaced wire bonding caused by safety distances. Furthermore, the use of TMV technology allows multiple components to be stacked, contributing to higher packaging density and further reducing package size.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, particularly to the field of product process development technology, specifically to a small-size BGA SSD packaging structure and method based on TMV and vertical wire bonding. Background Technology

[0002] Currently, with the advent of the information and data explosion era, market demand for memory continues to grow. In the chip manufacturing process, the market's reliance on traditional wire bonding packaging remains high. The market demand for using multi-chip stacking technology to achieve high storage density in devices of the same size is also increasing. This demand presents not only challenges to semiconductor packaging processes in terms of process capabilities but also places higher demands on process control. From the packaging structure, we can see that most are composed of multiple stacked chips, aiming to reduce the space occupied by multi-chip packaging and thus minimize the size of memory devices. The key processes are chip thinning, dicing, and chip bonding. From a market demand perspective, flip-chip (FC) and through-silicon via (TSV), as well as wafer-level packaging, can effectively reduce device size while improving data transmission speed and reducing the possibility of signal interference. However, in the current consumer market, traditional wire bonding packaging still accounts for a large proportion, its advantages lying in cost competitiveness and technological maturity.

[0003] Silicon stacking is an important implementation of 3D stacking. It involves vertically stacking chips together and electrically connecting them via silicon interconnects (TIVs). TSVs are formed by drilling holes in a silicon substrate, using metal wires and insulating layers to enable signal transmission between chips. This technology allows for high-density interconnects and shorter signal transmission paths, contributing to improved performance and reduced power consumption. Package-less stacking is another method where multiple chips are directly stacked without a package layer. The stacked chips are electrically connected via weak metal wires or TSVs. This method achieves higher integration, tighter interconnects, and lower power consumption, and is commonly used in memory stacking and system-level integration. Stacking technology not only brings performance improvements but also design flexibility. By stacking different functions and chips at different levels, more refined chip designs can be achieved to meet the needs of different fields. This flexibility makes stacking technology a promising application in many areas. In the field of artificial intelligence, chip stacking technology can improve processing power and computing speed, enabling more advanced intelligent computing. By stacking multiple layers of chips together, higher data parallel processing capabilities and faster computing speeds can be achieved, accelerating the training and inference processes of artificial intelligence algorithms. This is of great significance for promoting the development of artificial intelligence, because it enables us to have more powerful computing capabilities to handle more complex problems.

[0004] Currently, most stacked packages use horizontal lead connections, requiring signals to be transmitted through long wires. This increases the signal transmission path, leading to increased signal delay. Longer signal transmission distances result in increased power consumption, especially in high-performance applications. The large footprint makes them unsuitable for highly integrated packaging. Reliability is low; gold wires may loosen or detach under external factors such as thermal cycling and vibration. As the demands of electronic products continue to rise, the market is increasingly demanding smaller, thinner, and higher-performance chips. Conventional BGA SSD products typically contain 10 to 50 or more components and are multi-core stacked products. The large number of wire bonding and components limits product size reduction. Therefore, innovations are being made to conventional packaging bonding processes, using TMV through-hole technology and vertical wire bonding technology to achieve new BGA SSD packaging processes. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a small-size BGA SSD packaging structure and method based on TMV and vertical wire bonding. This invention is applicable to innovations based on conventional packaging and bonding processes, using TMV through-hole technology and vertical wire bonding technology to achieve new BGA SSD packaging processes.

[0006] To achieve the above objectives, the first technical solution adopted by the present invention is: a small-size BGA SSD package structure based on TMV and vertical wire bonding, comprising: a substrate; an RDL layer, which is disposed parallel above the substrate, the distance between the RDL layer and the substrate being no greater than a first predetermined distance; a plurality of chips, which are stacked alternately on the substrate, and gold wires soldered on the chips are respectively wired vertically upward to the RDL layer; a first component, which is arranged on the substrate with its pads facing upward, and the pads are connected to the RDL layer through vertically upward metal copper pillars.

[0007] Optionally, the closest distance between the lower surface of the RDL layer and the upper surface of the first component and the upper surfaces of the plurality of chips is no greater than a second predetermined distance.

[0008] Optionally, the horizontal area of ​​the RDL layer is not less than the sum of the horizontal areas of the plurality of chips and the first component, and is not greater than a first preset size.

[0009] Optionally, the minimum horizontal distance between the plurality of chips and the first component is not greater than a third predetermined distance.

[0010] Optionally, the plurality of chips are stacked in a staggered manner, wherein the edge pins of the plurality of chips are connected sequentially by gold wires and then wired upwards perpendicularly to the RDL layer, and the horizontal distance between the gold wires is not greater than the horizontal area of ​​the chip.

[0011] Optionally, it further includes: a dummy silicon wafer, wherein the lower surface of the first component is fixed to the dummy silicon wafer with adhesive, and the lower surface of the dummy silicon wafer is fixed to the substrate with DAF film; wherein the vertical height of the dummy silicon wafer is not greater than the sum of the stacked mounting heights of all the chips, and the cross-sectional area of ​​the dummy silicon wafer is not less than the bottom area of ​​the first component.

[0012] Optionally, it further includes: a second component, the second component being installed at a position corresponding to the connection position of the gold wire and the copper pillar on the RDL layer, and the maximum horizontal distance between the second components not exceeding a fourth predetermined distance.

[0013] Optionally, it further includes: a molding compound that covers the space between the substrate and the RDL layer and the second component on the upper part of the RDL layer.

[0014] The second technical solution adopted in this invention is: a packaging method for a small-size BGA SSD package structure based on TMV and vertical bonding as described in any one of the first technical solutions, comprising: stacking multiple chips on a substrate in a staggered manner by bonding them together with DAF film; bonding the chips upwards to the same height plane by vertical bonding process; fixing a dummy silicon wafer to the substrate with DAF film; fixing a first component on the upper surface of the dummy silicon wafer with adhesive; filling and molding the structure into a molding compound using molding compound; grinding the upper surface of the molding compound to expose the gold wires; using TMV molding via technology to lead out copper pillars to the upper surface of the molding compound at the pad positions of the first component; generating an RDL layer on the upper surface of the molding compound using RDL process; mounting a second component in the corresponding area on the upper part of the RDL layer; and molding and encapsulating the second component.

[0015] Optionally, the step of using TMV through-hole technology to bring out a copper pillar to the upper surface of the molding compound corresponding to the pad position of the first component further includes: using a laser to drill holes in the area corresponding to the pad of the first component on the upper surface of the molding compound, and filling the through holes with an electroplating metal deposition process to generate a copper pillar.

[0016] The beneficial effects of this invention are: This invention avoids the problems of uneven or intersecting wire bonding caused by safety distances between gold wires by making the gold wires perpendicular to the substrate or chip. Furthermore, the use of TMV technology allows multiple components to be stacked, contributing to higher packaging density and further reducing package size. Replacing the substrate with a wafer-level high-density RDL increases interconnect density and enables multi-chip packaging. The vertical wire bonding technique reduces package size and decreases parasitic capacitance and resistance generated during signal transmission, improving signal transmission efficiency.

[0017] Meanwhile, by optimizing the shape of the gold wires, this invention reduces interference between the gold wires, thereby improving the reliability of the packaging, saving costs, increasing production up to 100,000 units (UPH), maximizing the density of chip stacking in three dimensions, and minimizing the overall size. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the small-size BGA SSD package structure based on TMV and vertical wire bonding of the present invention; Figure 2 This is a schematic diagram of the vertical wire bonding structure of a single chip in this invention; Figure 3 This is a schematic diagram of the drilling and filling lead structure of the first component's encapsulation in this invention; Figure 4 This is a schematic diagram of the vertical wire bonding structure of multiple chips in this invention; Figure 5 This is a schematic diagram of the mounting structure of the first component of the present invention; Figure 6 This is a schematic diagram of the first component and multiple chip encapsulation structures of the present invention; Figure 7 This is a schematic diagram of the RDL layer structure constructed according to the present invention; Figure 8 This is a schematic diagram of the plastic encapsulation structure of the second component of the present invention; Figure 9 This is a top view of the structure of the present invention.

[0019] Reference numerals: 1. Substrate; 2. Chip; 21. NAND chip; 22. Controller chip; 3. Gold wire; 4. DAF film; 5. First component; 6. Dummy silicon wafer; 7. Copper pillar; 8. Molded enclosure; 9. RDL layer; 10. Second component. Detailed Implementation

[0020] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0022] This invention provides a small-size BGA SSD package structure based on TMV and vertical wire bonding. This application utilizes chip stacking technology, specifically, vertically stacking multiple chips together to improve integration density, performance, and power efficiency. This technology is no longer limited to the traditional two-dimensional plane but extends to three-dimensional space, enabling the stacking of more components within a limited space. Imagine if we no longer only worked on a single plane but designed circuits with two, three, or even more layers; the number of transistors would increase exponentially, and chip performance would experience a qualitative leap. The core of stacking technology lies in increasing integration density and reducing power consumption. By stacking multiple chips together, the communication distance between chips can be greatly reduced, data transmission speed can be increased, and power consumption can be reduced simultaneously. This hierarchical stacking structure not only helps improve chip stability and reliability but also significantly enhances the performance of the entire system. Stacking technology is mainly divided into 2.5D stacking and 3D stacking. 2.5D stacking involves interconnecting different chips within the same package using silicon interconnect bridges. These interconnect bridges are media that integrate high-density electrical and optical connections, providing high-speed, low-latency signal transmission. 2.5D stacking is commonly used in high-performance computing, servers, and networking devices because it offers higher performance and lower power consumption in these fields. 3D stacking, on the other hand, involves vertically stacking multiple chips together through packaging layers to form a three-dimensional structure. The stacked chips are electrically connected via weak metal wires or silicon interconnect bridges. This stacking method provides higher integration and tighter interconnects, reduces latency between circuits, and saves space. 3D stacking is widely used in mobile devices, the Internet of Things (IoT), and high-performance computing because it enables higher performance and lower power consumption in these areas. The emergence of stacking technology has had a positive impact on the entire technology industry. It has spurred chip manufacturers and chip design companies to compete in developing new technologies and launching new products, enhancing the industry's competitiveness and innovation capabilities. Simultaneously, the application of stacking technology has also driven the development of related industrial chains, promoting technological progress and socio-economic prosperity.

[0023] In one specific embodiment of this application, the packaging structure includes: multiple chips 2, which are stacked parallel to each other on a substrate 1 after being bonded with a DAF film 4, and gold wires 3 on the chips are respectively bonded vertically upwards to a predetermined plane; specifically, this embodiment uses five chips, with DAF films 4 bonded between them. DAF is a high-performance adhesive film widely used in semiconductor packaging for connecting chips and substrate 1, especially excelling in thin-film stacking. Its advantages include: size adaptability: as chip size shrinks, the DAF film 4 can flexibly adapt to various sizes while maintaining excellent coating uniformity. Good interface contact: The DAF film 4 forms a good interface contact with the chip and the packaging structure, ensuring efficient heat transfer. Reliability and durability: Under various temperature, humidity, and mechanical stress conditions, the DAF film 4 maintains stable performance, thereby ensuring the reliability and durability of the chip in long-term use. Semiconductor DAF film 4, with its excellent adhesion, encapsulation performance, and superior heat resistance, significantly improves chip stability, shock resistance, and vibration resistance, providing strong support for the continuous and stable operation of equipment. Using DAF allows for very small and constant thickness adjustments. DAF is not only used for bonding between chips and substrate 1, but also widely used for bonding between chips to form multi-wafer packages. Specifically, the DAF film 4 located at the bottom of the chip supports the chip, while the dicing tape pulls the DAF underneath with weak adhesion. During bonding, after removing the chip and DAF film from the dicing tape, the die is immediately placed on the substrate, eliminating the need for epoxy resin and skipping the dispensing step. This simplifies the process and improves thickness uniformity, thereby reducing defect rates and increasing productivity.

[0024] In one specific embodiment of this application, the DAF film 4 mainly consists of a first adhesive surface, a second adhesive surface, an intermediate layer, and a high thermal conductivity resin layer. The first adhesive surface is bonded to the chip to protect the wafer from external environmental damage; the second adhesive surface is bonded to the substrate 1 to improve the conductivity of the wafer; the intermediate layer is located between the first and second adhesive surfaces and serves to support, fill, and protect the circuitry; the high thermal conductivity resin layer is used to improve the heat dissipation performance of the wafer. The DAF film 4 possesses excellent isolation, thermal conductivity, and corrosion resistance, making it the preferred material for high-requirement semiconductor packaging processes. Currently, the DAF film 4 is mainly used for stacking chips to achieve 3D packaging of flash memory devices. In memory chip packaging, the DAF film 4 has become a commonly used process choice. Compared to adhesives, the DAF film 4 can achieve a consistent thickness and thinner process. It can be used not only for bonding chips to the substrate 1 but also primarily for bonding chips to each other, thereby forming multi-chip packages. For achieving high reliability, high performance, high speed, high device density, and smaller, thinner packages, the DAF film 4 has become a key technology. DAF Adhesive Film 4 exhibits excellent adhesion to various leadframe surfaces and chip sizes without resin seepage. Precise control of the adhesive layer thickness eliminates chip tilting issues, enabling high-volume assembly. DAF Adhesive Film 4 was created to address the challenges posed by epoxy adhesives in multi-chip modules and other applications involving wafer-level and chip-size constraints.

[0025] In one specific embodiment of this application, the wire bonding used in this application involves electrically connecting the pads on the chip to the pins on the packaging substrate 1 using fine gold wires or the like. The general process involves steps such as first-point soldering => wire pulling => second-point soldering => gold wire cutting. Specifically, vertical wire bonding, where the gold wire 3 extends vertically upwards perpendicular to the chip, significantly reduces the space occupied by the gold wire and minimizes interference between them.

[0026] In one specific embodiment of this application, the package structure includes: a first component 5, the bottom of which sits on a dummy silicon wafer 6, with the pads of the first component 5 facing upwards and connected to a predetermined plane via vertically upward-facing copper pillars 7. The first component 5 is an SMT component, i.e., a surface mount component, a packaging technology in the electronics manufacturing industry that directly mounts leadless or short-lead surface-mount components onto the surface of a printed circuit board or other substrate. This technology, by eliminating traditional through-hole channels, allows components to be mounted close to the board surface, reducing lead inductance and parasitic capacitance, and improving high-frequency circuit performance.

[0027] In one specific embodiment of this application, the packaging structure includes: an RDL layer 9, which is disposed on a predetermined plane and parallel to the substrate above it. The distance between the RDL layer 9 and the substrate is not greater than a first predetermined distance. The closest distance between the lower surface of the RDL layer 9 and the upper surface of the first component and the upper surfaces of multiple chips is not greater than a second predetermined distance. The horizontal area of ​​the RDL layer 9 is not less than the sum of the horizontal areas of the multiple chips and the first component, and is not greater than a first preset size. This can limit the size of the entire packaging structure, which can help achieve higher packaging density and further reduce the packaging size. By using a wafer-level high-density RDL to replace the substrate, the interconnection density is improved, and multi-chip packaging is realized. Multiple second components 10 are mounted on the upper surface of the RDL layer 9; the second components 10 are also SMT components. This embodiment uses a wafer-level high-density RDL to replace the substrate, improves the interconnection density, and realizes multi-chip packaging. The vertical wire bonding technology is used to reduce the packaging size and reduce parasitic capacitance and parasitic resistance generated by signal transmission, thereby improving signal transmission efficiency. RDL, or Redistribution Layer Technology, is a key player in this field. It redistributes I / O locations on a chip by adding an additional wiring layer on the chip surface or interposer to adapt to different packaging requirements and improve electrical connectivity flexibility. The core of RDL technology lies in its ability to rearrange the IC's input / output ports to new, more spacious areas, forming a planar array arrangement. This technology significantly increases I / O density, improves electrical performance, and reduces chip area, allowing designers to place chips in a more compact and efficient manner, reducing the overall device footprint. The RDL process involves coating an insulating protective layer on the IC, defining a new wiring pattern through exposure and development, and then using electroplating to create new metal lines that connect the original chip pins to new bumps, achieving a redistribution of the chip pins. The metal lines are primarily made of electroplated copper, but nickel-gold or nickel-palladium-gold materials can also be plated on the copper lines to improve conductivity and reliability. Photoresist, electroplating solution, target material, and etching solution are core materials in the RDL process, directly affecting the performance and reliability of the RDL.

[0028] In one specific embodiment of this application, the packaging structure includes: a molding compound 8, which covers the space between the substrate 1 and the RDL layer 9, as well as the second component 10 on the upper part of the RDL. In this embodiment, the molding compound 8 maximizes the density of chip stacking in three dimensions and minimizes the overall size.

[0029] In one specific embodiment of this application, the plurality of chips 2 includes: a plurality of NAND chips 21, specifically four NAND chips 21, which are bonded together by DAF adhesive film 4, and are staggered in placement to facilitate gold wire bonding. A controller chip 22 is attached to the top of the NAND chips 21. This allows multiple components to be stacked, which helps to achieve higher packaging density and further reduce package size.

[0030] In one specific embodiment of this application, the first component 5 is fixed to the dummy silicon wafer 6 with adhesive, and the dummy silicon wafer 6 is fixed to the substrate 1 with DAF film 4. The semiconductor dummy wafer, also known as a dummy wafer filler, plays a crucial role in semiconductor manufacturing. It is a non-functional wafer specifically designed to fill equipment vacancies, not involved in actual production, and primarily fulfills equipment process requirements. Its core functions include maintaining equipment load balance, protecting production wafers from process risks, and ensuring equipment stability through commissioning.

[0031] In one specific embodiment of this application, the vertical height of the dummy silicon wafer 6 is no greater than the sum of the stacked mounting heights of all chips, and the cross-sectional area of ​​the dummy silicon wafer 6 is no less than the bottom area of ​​the first component 5. This ensures stable mounting of the first component 5 while minimizing package size and increasing package density.

[0032] In one specific embodiment of this application, the nearest horizontal distance between the dummy silicon wafer 6 and the first component and the chip is no greater than a third predetermined distance. This further controls the package size and improves the package density.

[0033] In one specific embodiment of this application, the closest distance between the lower surface of the RDL layer 9 and the upper surface of the first component 5 and the upper surface of the controller chip 22 is no greater than a second predetermined distance. This further controls the package size and improves the package density.

[0034] In one specific embodiment of this application, the mounting position of the second component 10 corresponds to the gold wire 3 and the copper pillar 7 on the RDL layer 9, and the maximum horizontal distance between the second components 10 is not greater than a fourth predetermined distance. This further controls the package size and improves the package density.

[0035] This application also provides a packaging method for a small-size BGA SSD package structure based on TMV and vertical wire bonding, comprising the following steps: multiple chips are bonded together with DAF film 4 and stacked in parallel on a substrate 1 in a staggered manner; then the chips are wire bonded upwards using a vertical wire bonding process; a dummy silicon wafer 6 is fixed to the substrate 1 with DAF film 4, and a first component 5 is fixed to the upper surface of the dummy silicon wafer 6 with adhesive; a molding compound is used for filling and wrapping, and then one side of the gold wire 3 is wrapped with the molding compound until the gold wire is exposed; then, a metal copper pillar on the pad of the first component 5 is brought out using TMV molding via technology at the position of the first component 5 on the molding compound; an RDL layer 9 is generated using RDL process, and a second component 10 is mounted on the corresponding area on the upper part of the RDL layer 9, and then the second component 10 is molded and wrapped. Finally, ball bonding is performed on the back side of the substrate 1.

[0036] In one specific embodiment of this application, multiple chips are stacked parallel to each other on a substrate 1 through a staggered arrangement of DAF film 4, and the chips are wired upwards through a vertical wire bonding process. Specifically, multiple NAND chips 21 and controller chips 22 are wired vertically upwards to the same horizontal plane.

[0037] In one specific embodiment of this application, a molding compound is used for filling and encapsulation, followed by grinding to expose the gold wire 3. A metal copper pillar on the pad of the first component 5 is brought out using TMV molding via technology at the location of the first component 5. Specifically, this includes: first, using a laser to drill holes in the corresponding area of ​​the pad of the first component 5 on the molding compound, and then filling the vias with an electroplated metal deposition process. TMV molding via technology uses laser drilling to create vertical vias in the molding compound, with metal connected to the bottom of the via. Subsequently, conductive material is filled into the vias through sputtering and electroplating processes, assisted by wire bonding and reflow soldering processes to achieve three-dimensional interconnection between logic and memory components. The via depth of the TMV structure can reach 1000 μm, and the via diameter mainly depends on the size of the molding compound filler, generally being greater than or equal to three times the filler diameter.

[0038] The above are merely embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A small-size BGA SSD package structure based on TMV and vertical wire bonding, characterized in that, include: substrate; An RDL layer is disposed parallel to the substrate above the substrate, and the distance between the RDL layer and the substrate is not greater than a first predetermined distance. Multiple chips are stacked sequentially and alternately on the substrate, and gold wires soldered on the chips are respectively wired upwards perpendicularly to the chips to the RDL layer; A first component, with its pads facing upwards, is disposed on the substrate, and the pads are connected to the RDL layer via vertically upward-facing copper pillars.

2. The BGA SSD small-size package structure based on TMV and vertical wire bonding according to claim 1, characterized in that, The closest distance between the lower surface of the RDL layer and the upper surface of the first component and the upper surfaces of the plurality of chips is no greater than a second predetermined distance.

3. The BGA SSD small-size package structure based on TMV and vertical wire bonding according to claim 1, characterized in that, The horizontal area of ​​the RDL layer is not less than the sum of the horizontal areas of the plurality of chips and the first component, and is not greater than the first preset size.

4. The BGA SSD small-size package structure based on TMV and vertical wire bonding according to claim 1, characterized in that, The minimum horizontal distance between the plurality of chips and the first component is no greater than a third predetermined distance.

5. The BGA SSD small-size package structure based on TMV and vertical wire bonding according to claim 1, characterized in that, The multiple chips are stacked in a staggered manner, wherein the edge pins of the multiple chips are connected sequentially by gold wires and then wired upwards perpendicularly to the RDL layer, and the horizontal distance between the gold wires is not greater than the horizontal area of ​​the chip.

6. The BGA SSD small-size package structure based on TMV and vertical wire bonding according to claim 1, characterized in that, Also includes: dummy silicon wafers, The lower surface of the first component is fixed to the dummy silicon wafer with adhesive, and the lower surface of the dummy silicon wafer is fixed to the substrate with DAF film; The vertical height of the dummy silicon wafer is not greater than the sum of the stacked mounting heights of all the chips, and the cross-sectional area of ​​the dummy silicon wafer is not less than the bottom area of ​​the first component.

7. The BGA SSD small-size package structure based on TMV and vertical wire bonding according to claim 1, characterized in that, Also includes: Second component, The installation position of the second component corresponds to the connection position of the gold wire and the copper pillar on the RDL layer, and the maximum horizontal distance between the second components is not greater than the fourth predetermined distance.

8. The BGA SSD small-size package structure based on TMV and vertical wire bonding according to claim 1, characterized in that, Also includes: Molded body, The molding compound covers the space between the substrate and the RDL layer, as well as the second component on the upper part of the RDL layer.

9. A packaging method for a small-size BGA SSD based on TMV and vertical wire bonding according to any one of claims 1-8, characterized in that, include: Multiple chips are bonded together with DAF adhesive film and stacked on a substrate in a staggered manner. The chips are then wired upwards to the same height plane using a vertical wire bonding process. The dummy silicon wafer is fixed to the substrate using DAF adhesive film, and the first component is fixed to the upper surface of the dummy silicon wafer with adhesive. The structure is filled with molding compound and molded into a molding body. The upper surface of the molding body that wraps the gold wire is ground flat until the gold wire is exposed on the upper surface. A metal copper pillar is led out to the upper surface of the molding body using TMV molding through-hole technology at the position corresponding to the first component pad. The RDL process is used to generate an RDL layer on the upper surface of the molded body. A second component is mounted on the corresponding area on the upper part of the RDL layer and then the second component is encapsulated.

10. The BGA SSD small-size packaging method based on TMV and vertical wire bonding according to claim 9, characterized in that, The method of using TMV through-hole technology to bring out metal copper pillars to the upper surface of the molding compound corresponding to the pad position of the first component on the upper surface of the molding compound also includes: A laser is used to drill holes in the area corresponding to the first component pad on the upper surface of the molding compound, and the holes are filled using an electroplating metal deposition process to generate a copper pillar.

Images