Semiconductor structure and method of manufacturing a semiconductor structure

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a manufacturing method of semiconductor structure and the semiconductor structure. The manufacturing method of semiconductor structure comprises the following steps: providing a substrate, forming at least two stack structures and a connecting structure between the at least two stack structures on the substrate; the stack structure comprises a plurality of layers of bit lines, the connecting structure comprises a plurality of layers of connecting layers, and the connecting layers are arranged in the same layer as the bit lines and connected; a plurality of filling holes are formed in the connecting structure, different filling holes expose the top surfaces of different layers of the connecting layers; a contact layer is formed in the filling hole, and the contact layer is connected with the connecting layer. The embodiment of the present disclosure can at least improve the integration of the semiconductor structure, and reduce the parasitic capacitance in the semiconductor structure.

Description

Technical Field

[0001] This disclosure pertains to the field of semiconductors, and specifically relates to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Technology

[0002] Semiconductor structures consist of multiple stacked structures that perform memory functions. These stacked structures are connected to and controlled by peripheral circuits. Higher integration density in a semiconductor structure allows for a greater number of memory cells, resulting in superior performance. However, current semiconductor structures often suffer from significant space wastage; furthermore, as the number of stacked layers increases, parasitic capacitance within the semiconductor structure also grows.

[0003] Therefore, there is an urgent need for a new semiconductor architecture to improve the integration of semiconductor structures and reduce parasitic capacitance within them. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure, which at least helps to improve the integration of the semiconductor structure and reduce the parasitic capacitance within the semiconductor structure.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a semiconductor structure, wherein the semiconductor structure includes: providing a substrate, forming at least two stacked structures and a connection structure located between the at least two stacked structures on the substrate; the stacked structures include multiple bit lines, the connection structure includes multiple connection layers, and the connection layers are disposed on the same layer as the bit lines and connected thereto; forming a plurality of fill holes in the connection structure, with different fill holes exposing the top surfaces of different layers of the connection layers; forming contact layers in the fill holes, and the contact layers being connected to the connection layers.

[0006] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure, the semiconductor structure comprising: a substrate having at least two stacked structures and a connection structure located between the at least two stacked structures; the stacked structures include multiple bit lines, the connection structure includes multiple connection layers, and the connection layers are disposed on the same layer as the bit lines and connected thereto; the connection structure has multiple contact layers, and different contact layers are connected to the top surface of different connection layers.

[0007] The technical solution provided by the embodiments of this disclosure has at least the following advantages: the bit lines of at least two stacked structures are connected to the interconnect layer within the interconnect structure, and the interconnect layer is connected to the contact layer. Therefore, the two stacked structures share the contact layer, thereby improving the integration density of the semiconductor structure. Furthermore, compared to forming a separate step region to support the interconnect layer, the embodiments of this disclosure directly form the contact layer within the interconnect structure, which helps to improve the space utilization of the interconnect structure, thereby reducing the volume of the semiconductor structure and lowering the parasitic capacitance within the semiconductor structure. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0009] Figure 1 A top view of a semiconductor structure is shown;

[0010] Figure 2 It shows Figure 1 A partial cross-sectional view of the semiconductor structure shown;

[0011] Figures 3-23 This invention discloses a schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure.

[0012] Figures 24-28 This invention discloses a schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

[0013] Figures 29-30 A schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to yet another embodiment of the present disclosure is shown. Detailed Implementation

[0014] As the background technology shows, the integration density of semiconductor structures needs to be further improved, and the parasitic capacitance within semiconductor structures needs to be reduced. This will be explained in detail below. Figure 1 This is a top view of a semiconductor structure. Figure 2 for Figure 1 The cross-sectional view of step area 400 shown. (Reference) Figure 1 The semiconductor structure includes a stacked region 300 and a stepped region 400. The stacked region 300 contains a stacked structure that performs memory functions, and the stacked structure includes multiple bit lines. (Reference) Figure 2The step region 400 has multiple steps 40, and contact layers 500 can be disposed on the steps 40. The contact layers 500 are electrically connected to the bit lines through conductive structures within the steps 40, thereby leading out the bit lines so that external circuits can provide signals to or acquire signals from the bit lines. However, as the number of stacked layers increases, the area occupied by the step region 400 becomes larger and larger; that is, the area occupied by the bottommost steps 40 becomes larger, and the distance between the contact layers 500 on the bottommost steps 40 and the stacked structure becomes farther. Therefore, the integration density of the semiconductor structure is poor. In addition, the facing area of ​​the conductive structures in two adjacent steps 40 becomes larger, thereby increasing the parasitic capacitance.

[0015] This disclosure provides a method for manufacturing a semiconductor structure. The method includes: forming at least two stacked structures and interconnect structures on a substrate; interconnect layers within the interconnect structures are disposed on the same layer as and connected to bit lines within the stacked structures; and forming contact layers in the interconnect structures, with different contact layers connected to different interconnect layers. That is, the bit lines of at least two stacked structures are connected to contact layers through interconnect layers. Since the two stacked structures share contact layers, the number of contact layers can be reduced, thereby improving the integration density of the semiconductor structure. Furthermore, the contact layers are formed directly using the spatial location of the interconnect structures, thus eliminating the need to separately form step regions and conductive structures within the step regions. This helps to reduce the volume of the semiconductor structure and avoids parasitic capacitance between adjacent conductive structures.

[0016] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0017] like Figures 3-23 As shown in the figure, one embodiment of this disclosure provides a method for manufacturing a semiconductor structure, and the method for manufacturing a semiconductor structure will be described in detail below.

[0018] First, it should be noted that the semiconductor structure has a first direction X, a second direction Y, and a third direction Z. The first direction X is the extension direction of the bit line 11 or the pseudo bit line 111, the second direction Y is the arrangement direction of the two stacked structures 100 or the two initial stacked structures 10, and the third direction Z is the stacking direction of the interconnect layer 21 or the pseudo interconnect layer 211.

[0019] refer to Figure 3 Provides base 5 (reference) Figure 5On the substrate 5, multiple layers of pseudo-bit lines 111 and stacked, alternately arranged pseudo-connecting layers 211 and first isolation layers 22 are formed. The pseudo-connecting layers 211 are arranged on the same layer as the pseudo-bit lines 111 and connected to each other. That is, the multiple layers of pseudo-bit lines 111 and the multiple layers of pseudo-connecting layers 211 are arranged in a one-to-one correspondence. The multiple layers of pseudo-bit lines 111 and the first isolation layers 22 constitute the initial connection structure 20.

[0020] The pseudo-position line 111 and the pseudo-connection layer 211 can be made of the same material, for example, both can be silicon or both can be silicon germanide, which facilitates the removal of the pseudo-position line 111 and the pseudo-connection layer 211 in the same process step. The pseudo-position line 111 and the pseudo-connection layer 211 can be formed by a deposition process (e.g., epitaxial growth process), and both can be formed in the same deposition process. The first isolation layer 22 can be formed by a chemical vapor deposition process.

[0021] In some embodiments, the pseudo bit line 111 is connected to the memory cell 12. Specifically, the memory cell 12 may include a first source / drain 121, a word line 123, a second source / drain 122, and a capacitor 124 connected in sequence. Multiple memory cells 12 are stacked in the third direction Z to form a memory cell group 120. Multiple memory cell groups 120 are arranged in the first direction X. The word line 123 extends along the third direction Z and serves as the gate of multiple memory cells 12 in the same memory cell group 120. The bit line 11 extends in the first direction X and connects to the first source / drain 121 of the same layer of memory cells 12 in the multiple memory cell groups 120. The pseudo bit line 111 and the memory cells 12 constitute an initial stacked structure 10. Furthermore, the initial stacked structure 10 may also include an insulating layer 13 (see reference) covering the memory cells 12 and the bit line 11. Figure 13 ).

[0022] It should be noted that there are at least two initial stacked structures 10, and the initial connecting structure 20 is located between at least two initial stacked structures 10, that is, at least two stacked structures 100 and a connecting structure 200 located between at least two stacked structures 100 are subsequently formed on the substrate 5.

[0023] For example, the initial connection structure 20 connects two initial stacked structures 10, and the subsequently formed connection structure 200 connects the two stacked structures 100.

[0024] refer to Figures 4-5 , Figure 5 for Figure 4 The diagram shows a cross-sectional view of the semiconductor structure on the plane formed by the first direction X and the third direction Z. Figure 5 The initial interconnect structure 20 is shown. A via 28 is formed through the multilayer dummy interconnect layer 211 to expose the multilayer dummy interconnect layer 211. That is, the etching reagent for subsequent removal of the dummy interconnect layer 211 can enter the interior of the semiconductor structure through the via 28.

[0025] For example, there are multiple vias 28, and the arrangement direction of the multiple vias 28 is parallel to the extension direction of the pseudo-bit line 111, and the extension direction of the vias 28 is parallel to the arrangement direction of the two stacked structures 100. In this way, the two opposite edges of the vias 28 can be brought closer to the pseudo-bit line 111 structure, which can help reduce the residue generated during the subsequent removal of the pseudo-bit line 111.

[0026] For example, all vias 28 have the same depth in the third direction Z and penetrate the pseudo-connection layer 211 through all layers. This simplifies the manufacturing process and allows for a larger subsequent process window.

[0027] In some embodiments, the pseudo bit lines 111 are N layers, where N is a positive integer; and there are N+1 vias 28. It is worth noting that the space between each pair of vias 28 is used to subsequently form contact layers 3 to bring out the N layers of bit lines 11. Therefore, N+1 spaced vias 28 can provide space for N contact layers 3.

[0028] refer to Figures 6-7 , Figure 7 for Figure 6 The diagram shows a cross-sectional view of the semiconductor structure on the plane formed by the first direction X and the third direction Z. The dummy interconnect layer 211 is removed to form the first fill region 241, and the dummy bit line 111 is removed to form the second fill region 242. For example, an etchant with a high selective etching ratio for both the dummy interconnect layer 211 and the first isolation layer 22 can be used to reduce damage to the first isolation layer 22 during the removal of the dummy interconnect layer 211.

[0029] refer to Figures 8-9 A conductive layer 25 is formed within the first filling region 241, the second filling region 242, and the via 28. For example, a metal such as tungsten, molybdenum, cobalt, titanium, or copper is deposited as the conductive layer 25 using chemical vapor deposition or atomic layer deposition. It should be noted that metals have lower resistance than silicon layers, which is beneficial for improving the performance of the semiconductor structure.

[0030] As described above, the via 28 extends in the alignment direction of the two stacked structures 100. Therefore, the edge of the via 28 is closer to the second filling region 242, allowing sufficient reactive gas to enter the second filling region 242. Consequently, the conductive layer 25 of the second filling region 242 has fewer pores and a higher density.

[0031] refer to Figures 10-11 , Figure 11 for Figure 10The diagram shows a cross-sectional view of the semiconductor structure in the first direction X. The conductive layer 25 within the via 28 is removed. The conductive layer 25 in the first filled region serves as the interconnect layer 21, and the conductive layer 25 in the second filled region 242 serves as the bit line 11. That is, the space occupied by the interconnect layer 21 is the same as the original space of the pseudo-interconnect layer 211, and the space occupied by the bit line 11 is the same as the original space of the pseudo-bit line 111. Removing the conductive layer 25 within the via 28 prevents interconnection between the upper and lower interconnect layers 21 and the upper and lower bit lines 11. For example, a dry etching process is used to remove the conductive layer 25 within the via 28.

[0032] In some embodiments, in the arrangement direction of the two stacked structures 100, the width of the via 28 is less than the distance between the two stacked structures 100. If the width of the via 28 is equal to the distance between the two stacked structures 100, the edge of the via 28 contacts the edge of the second filling region 242. Therefore, when removing the conductive layer 25 within the via 28, the conductive layer 25 within the second filling region 242 may be damaged, i.e., a portion of the bit line 11 may be consumed. In other words, when the width of the via 28 is less than the distance between the stacked structures 100, damage to the bit line 11 can be reduced, thereby reducing the resistance of the bit line 11.

[0033] refer to Figure 12 A second isolation layer 26 is formed within the via 28. For example, silicon nitride is deposited within the via 28 as the second isolation layer 26 using a chemical vapor deposition process.

[0034] At this point, based on Figures 3-12 The steps shown allow for the formation of at least two stacked structures 100 and a connecting structure 200 between the at least two stacked structures 100 on the substrate 5. Each stacked structure 100 includes multiple bit lines 11, and the connecting structure 200 includes multiple connecting layers 21, which are disposed on the same layer as and connected to the bit lines 11. Furthermore, a second isolation layer 26 is formed within the stacked structures 100.

[0035] refer to Figures 13-14 , Figure 14 for Figure 13 The diagram shows a top view of the semiconductor structure. A mask layer 4 is formed, and the mask layer 4 is subjected to a first patterning process to form a first opening 41; the first opening 41 exposes a first isolation layer 22 between two adjacent second isolation layers 26. It should be noted that, for a more intuitive understanding, Figure 13 The mask layer 4 located on the connection structure 200 is not fully shown, and only a stacked structure 100 is shown. For example, the mask layer 4 may include a hard mask layer and a photoresist layer stacked together.

[0036] refer to Figure 15 , Figure 15The mask layer 4 located on the connection structure 200 is not fully shown. Along the first opening 41 (reference) Figure 14 The first interconnect layer 211 is exposed by etching. That is, the first isolation layer 22 above the first interconnect layer 21 is removed by etching. It should be noted that the interconnect layer 21 includes the first interconnect layer 211 to the Nth interconnect layer 211, wherein the first interconnect layer 211 is the top interconnect layer 21 and the Nth interconnect layer 21N is the bottom interconnect layer 21.

[0037] Continue to refer to Figures 15-16 , Figure 15 The mask layer 4 located on the stacked structure 100 is not fully shown. The mask layer 4 is subjected to a second patterning process to form a second opening 42. The second opening 42 is located differently from the first opening 41, and the second opening 42 also exposes the first isolation layer 22 between two adjacent second isolation layers 26.

[0038] refer to Figure 17 , Figure 17 The mask layer 4 located on the connection structure 200 is not fully shown. Along the first opening 41 and the second opening 42 (see reference). Figure 16 The etching process is performed to expose the second interconnect layer 212 directly below the first opening 41 and the first interconnect layer 211 directly below the second opening 42. For example, the first interconnect layer 211 can be removed firstly along the first opening using an etching agent for the interconnect layer 21. Then, the first isolation layer 22 on the second interconnect layer 212 is removed along the first opening 41 using an etching agent for the first isolation layer 22, and the first isolation layer 22 on the first interconnect layer 211 is removed along the second opening 42.

[0039] refer to Figure 18 , Figure 18 This is a cross-sectional view of the semiconductor structure on the plane formed by the first direction X and the third direction Z. The aforementioned patterning and etching steps are repeated until the first filling hole 231 to the Nth filling hole 23N are formed, wherein the first filling hole 231 is directly opposite to the Nth opening 4N and exposes the first interconnect layer 211, and the Nth filling hole 23N is directly opposite to the first opening 41 and exposes the Nth interconnect layer 21N.

[0040] At this point, based on Figures 13-18 The steps shown can form multiple filling holes 23 in the connection structure 200, with different filling holes 23 exposing the top surface of different layers of the connection layer 21. The filling holes 23 include the first filling hole 231 to the Nth filling hole 23N, where N is a positive integer.

[0041] Since there are many steps involved in patterning and etching, the thickness of the mask layer 4 can be appropriately increased to avoid excessive consumption of the mask layer 4 and reduced pattern accuracy.

[0042] Continue to refer to Figures 17-18 The filling hole 23 can be located between adjacent vias 28, that is, between adjacent second isolation layers 26. The main reason is that the connecting layer 21 between adjacent vias 28 is not removed. Therefore, during the formation of the filling hole 23, the connecting layer 21 can act as an etching stop layer, thus facilitating control of the etching depth. Furthermore, the filling hole 23 exposes the top surface of the connecting layer 21, allowing the contact layer 3 to contact the top surface of the connecting layer 21. Compared to the contact layer 3 contacting the sidewall of the connecting layer 21, contacting the top surface of the connecting layer 21 increases the contact area, thereby helping to reduce contact resistance.

[0043] Continue to refer to Figures 17-18 In some embodiments, in the arrangement direction of the two stacked structures 100, the width of the filling hole 23 is equal to the width of the through hole 28, that is, the width of the filling hole 23 is equal to the width of the second isolation layer 26. This simplifies the manufacturing process and avoids damage to the alignment line 11 during the formation of the filling hole 23.

[0044] refer to Figures 19-20 , Figure 20 This is a cross-sectional view of the semiconductor structure in the first direction. An initial third isolation layer 271 is formed within the filling hole 23. For example, silicon oxide is filled into the filling hole 23 using a chemical vapor deposition process to serve as the initial third isolation layer 271. The material of the initial third isolation layer 271 can be the same as the material of the first isolation layer 22.

[0045] refer to Figure 21 A portion of the initial third isolation layer 271 is removed to form the contact hole 31, and the remaining initial third isolation layer 271 serves as the third isolation layer 27, which surrounds the contact hole 31. In other words, the sidewalls of the connecting layer 21 are covered by the third isolation layer 27.

[0046] Continue to refer to Figure 21 This forms a contact layer 3 that fills the contact hole 31. For example, the contact hole 31 is filled with a metallic material such as copper, tungsten, titanium, molybdenum or cobalt as the contact layer 3.

[0047] refer to Figures 22-23 , Figure 23 for Figure 22 The semiconductor structure shown is a cross-sectional view in the first direction X. A chemical mechanical polishing process is used for planarization to remove the mask layer 4 and the metal material located in the mask layer 4, thereby exposing the interconnect structure 200 and the stacked structure 100.

[0048] Continue to refer to Figures 22-23There are N contact layers 3 in total, and each of them is connected to N connecting layers 21. That is, the N contact layers 3 are connected to the N connecting layers 21 in a one-to-one correspondence. The heights of the multiple contact layers 3 are different in the stacking direction of the contact layers 3.

[0049] In some embodiments, the distance between the plurality of contact layers 3 can be different, that is, the distance between the plurality of filling holes 23 can be different. For example, the spacing between two adjacent contact layers 3 is proportional to the area of ​​their facing surfaces. This helps to reduce the parasitic capacitance between adjacent contact layers 3, thereby reducing the delay difference.

[0050] In some embodiments, the multiple contact layers 3 can be arranged sequentially according to height in the extension direction of the bit line 11, for example, from high to low. In other embodiments, the multiple contact layers 3 may not be arranged according to height. For example, the contact layer 3 connected to the Nth connection layer 21 can be arranged adjacent to the contact layer 3 connected to the first connection layer 21. This helps to reduce the facing area of ​​the two contact layers 3, thereby reducing parasitic capacitance.

[0051] At this point, based on Figures 19-23 The steps shown allow for the formation of a contact layer 3 within the filling hole 23, which is connected to the connecting layer 21. Specifically, each contact layer 3 is connected to the top surface of a connecting layer 21, and the connecting layer 21 connected to a particular contact layer 3 is called its corresponding connecting layer 21. The contact layer 3 is insulated from other connecting layers 21 besides its corresponding connecting layer 21.

[0052] like Figures 24-28 As shown, another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, which is substantially the same as the method in the foregoing embodiments, with the main difference being that the step of forming the through-hole 28 differs between the two methods. Other process steps can be found in the detailed description of the foregoing embodiments.

[0053] refer to Figure 24 Provides base 5 (reference) Figure 5 On the substrate 5, multiple layers of pseudo-bit lines 111 and stacked and alternately arranged pseudo-connecting layers 211 and a first isolation layer 22 are formed. The pseudo-connecting layers 211 are arranged on the same layer as the pseudo-bit lines 111 and are connected. Through holes 28 are formed through the multiple layers of pseudo-connecting layers 211 to expose the multiple layers of pseudo-connecting layers 211.

[0054] In this design, there is one through-hole 28, and the extension direction of through-hole 28 is parallel to the extension direction of pseudo-bit line 111. This simplifies the manufacturing process. Specifically, through-hole 28 divides the subsequently formed connection structure 200 into a spaced first sub-connection structure 200a and a second sub-connection structure 200b, with through-hole 28 located between the first sub-connection structure 200a and the second sub-connection structure 200b. The first sub-connection structure 200a is connected to one of the two stacked structures 100, and the second sub-connection structure 200b is connected to the other of the two stacked structures 100.

[0055] In some embodiments, the via 28 is equidistant from both stacked structures 100. Thus, during the subsequent removal of the pseudo bit lines 111, the removal rate of the pseudo bit lines 111 in the two stacked structures 100 can remain relatively consistent, thereby avoiding over-etching or incomplete removal. Furthermore, during the subsequent formation of the bit lines 11, the deposition rate of the bit lines 11 in the two stacked structures 100 can remain relatively consistent.

[0056] refer to Figure 25 Remove the pseudo-connection layer 211 to form the first filling region 241, and remove the pseudo bit line 111 to form the second filling region 242.

[0057] refer to Figure 26 A conductive layer 25 is formed in the first filling region 241, the second filling region 242 and the through hole 28.

[0058] refer to Figure 27 The conductive layer 25 located within the via 28 is removed, and a second isolation layer 26 is formed within the via 28. The conductive layer 25 located within the first filling region 241 serves as the connecting layer 21, and the conductive layer 25 located within the second filling region 242 serves as the bit line 11.

[0059] refer to Figure 28 A filling hole 23 is formed, and a contact layer 3 and a third isolation layer 27 surrounding the contact layer 3 are formed within the filling hole 23. Specifically, an initial third isolation layer is formed in the filling hole 23, a portion of the initial third isolation layer is removed to form a contact hole 31, and the remaining initial third isolation layer serves as the third isolation layer 27. The contact layer 3 is formed in the contact hole 31.

[0060] In the arrangement direction of the two stacked structures 100, the width of the contact layer 3 is greater than the width of the second isolation layer 26, and the contact layer 3 spans the second isolation layer 26. That is, the contact layer 3 can be connected to the connection layer 21 in both the first sub-connection structure 200a and the second sub-connection structure 200b, thereby simultaneously leading out the bit lines 11 of the two stacked structures 100.

[0061] like Figures 29-30As shown, another embodiment of this disclosure provides a method for manufacturing a semiconductor structure, which is substantially the same as the method in the foregoing embodiments, except that the step of forming the through-hole 28 is different from that in the foregoing embodiments. Other process steps can be found in the detailed description of the foregoing embodiments.

[0062] In other embodiments, reference is made to Figure 29 The through hole 28 includes a vertical through hole 281 and a plurality of horizontal through holes 282 spaced apart. The extension direction of the horizontal through holes 282 is parallel to the arrangement direction of the two stacked structures 100, and the extension direction of the vertical through holes 281 is parallel to the extension direction of the pseudo-position line 111. The vertical through holes 281 and the horizontal through holes 282 are intersected.

[0063] This increases the process window, making it easier to remove the pseudo-connection layer 211 and pseudo-bit line 111, thereby reducing residue. In addition, the increased process window also facilitates the subsequent deposition of bit line 11 and connection layer 21, thereby reducing defects in bit line 11 and connection layer 21, and thus reducing the resistance of bit line 11 and connection layer 21.

[0064] Continue to refer to Figure 29 This forms a second isolation layer 26 that fills the through-hole 28. The material of the second isolation layer 26 can be the same as that of the first isolation layer 22.

[0065] refer to Figure 30 Multiple filling holes 23 are formed in the connecting structure 200, with different filling holes 23 exposing the top surface of different layers of the connecting layer 21; a contact layer 3 is formed within the filling hole 23, and the contact layer 3 is connected to the connecting layer 21. In addition, a third isolation layer 27 is formed around the contact layer 3 in the filling hole 23.

[0066] In some embodiments, a plurality of filling holes 23 may be located between adjacent transverse through holes 282. Because the connecting layer 21 between adjacent transverse through holes 282 is not completely removed, a contact layer 3 is formed between adjacent transverse through holes 282, which allows the contact layer 3 to be connected to the top surface of the connecting layer 21, thereby increasing the contact area.

[0067] In summary, in this embodiment, the interconnect layer 21 can not only electrically connect the bit lines 11 of the two stacked structures 100, but also electrically connect the contact layers 3. That is, the multiple interconnect layers 21 can also serve as steps to support the contact layers 3. Since the orthographic projection of the contact layers 3 on the substrate 5 lies within the orthographic projection of the interconnect layers 21, the overall projected area of ​​both on the substrate 5 is smaller, which is beneficial for improving the integration density of the semiconductor structure. Furthermore, compared to forming a step region opposite to the stacked structure 100 separately in the first direction X, the interconnect structure 200 and the stacked structure 100 in this embodiment are arranged in the second direction Y, so that the distance between the multiple contact layers 3 and the bit lines 11 can be the same. That is, the distance between the contact layers 3 and the bit lines 11 does not change with the number of stacked layers. Therefore, the facing area between two adjacent interconnect layers 21 is smaller, which is beneficial for reducing parasitic capacitance.

[0068] Furthermore, in this embodiment, a via 28 is formed. The via 28 serves as a process window for removing the pseudo bit line 111 and the pseudo interconnect layer 211, and also as a process window for forming the bit line 11 and the interconnect layer 21. This allows for the formation of low-resistance bit lines 11 and interconnect layers 21, thereby improving the electrical performance of the semiconductor structure.

[0069] like Figures 22-23 , Figure 28 as well as Figure 30 As shown, another embodiment of this disclosure provides a semiconductor structure. This semiconductor structure can be manufactured using the manufacturing method provided in the foregoing embodiments. For a detailed description of this semiconductor structure, please refer to the detailed description of the foregoing embodiments, which will not be repeated here.

[0070] The semiconductor structure includes: a substrate 5, on which at least two stacked structures 100 are provided and a connection structure 200 is located between the at least two stacked structures 100; the stacked structures 100 include multiple bit lines 11, the connection structure 200 includes multiple connection layers 21, and the connection layers 21 are disposed on the same layer as the bit lines 11 and connected thereto; the connection structure 200 has multiple contact layers 3, and different contact layers 3 are connected to the top surface of different connection layers 21.

[0071] The semiconductor structure will be described in detail below with reference to the accompanying drawings.

[0072] refer to Figures 22-23 , Figure 28 as well as Figure 30 In some embodiments, the arrangement direction of the plurality of contact layers 3 is parallel to the extension direction of the bit line 11. In this way, the contact layers 3 can make full use of the space between adjacent stacked structures 100, thereby avoiding space waste.

[0073] For example, multiple contact layers 3 can be arranged in a straight line, which improves the uniformity of the semiconductor structure and simplifies the manufacturing process. Furthermore, in the direction parallel to the extension direction of the bit line 11, adjacent contact layers 3 can be staggered, meaning that adjacent contact layers 3 are not directly opposite each other in the first direction X, which helps to reduce the parasitic capacitance between adjacent contact layers 3.

[0074] The semiconductor structure also includes a second isolation layer 26. The second isolation layer 26 will be described in detail below.

[0075] In some embodiments, reference Figures 22-23 The connection structure 200 connects two stacked structures 100; there are multiple second isolation layers 26, and the arrangement direction of the multiple second isolation layers 26 is parallel to the extension direction of the bit line 11, and the extension direction of the second isolation layers 26 is parallel to the arrangement direction of the two stacked structures 100.

[0076] The contact layer 3 can be located between adjacent second isolation layers 26, that is, the orthographic projections of the contact layer 3 and the second isolation layer 26 on the substrate 5 can be staggered.

[0077] In other embodiments, reference is made to Figure 28 The connection structure 200 includes a first sub-connection structure 200a and a second sub-connection structure 200b spaced apart. The first sub-connection structure 200a is connected to one of the two stacked structures 100, and the second sub-connection structure 200b is connected to the other of the two stacked structures 100. There is one second isolation layer 26, and the extension direction of the second isolation layer 26 is parallel to the extension direction of the bit line 11. The second isolation layer 26 is located between the first sub-connection structure 200a and the second sub-connection structure 200b. In other words, the second isolation layer 26 divides the connection structure 200 into two parts.

[0078] Contact layer 3 can span the second isolation layer 26 and be connected to the connection layer 21 in the first sub-connection structure 200a and the second sub-connection structure 200b, thereby allowing the bit lines 11 of the two stacked structures 100 to be brought out simultaneously.

[0079] In summary, in this embodiment, the contact layer 3 is located within the connection structure 200 between the two stacked structures 100, thus avoiding the formation of a separate step region. This reduces the overall projected area of ​​the contact layer 3 and the connection structure 200, thereby reducing parasitic capacitance. Furthermore, the contact layer 3 is connected to the bit lines 11 of both stacked structures 100, which helps reduce the number of contact layers 3 and the volume of the semiconductor structure. Additionally, the contact layers 3 are arranged in the first direction X, which helps reduce the width of the connection structure 200 in the second direction Y, thereby reducing the volume of the semiconductor structure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided on which at least two stacked structures and a connection structure located between the at least two stacked structures are formed; the stacked structures include multiple bit lines, and the connection structure includes multiple connection layers, wherein the connection layers are disposed on the same layer as the bit lines and are connected to them; Multiple filling holes are formed in the connection structure, with different filling holes exposing the top surface of different layers of the connection layer; A contact layer is formed within the filling hole, and the contact layer is connected to the connecting layer.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Two stacked structures and a connecting structure located between the two stacked structures are formed on the substrate, including: Multiple pseudo-bit lines and stacked and alternately arranged pseudo-connection layers and a first isolation layer are formed on the substrate, wherein the pseudo-connection layers are arranged in the same layer as the pseudo-bit lines and are connected to them. Form through-holes through the multiple layers of the pseudo-connection layers to expose the multiple layers of the pseudo-connection layers; Remove the pseudo-connection layer to form a first fill region, and remove the pseudo bit line to form a second fill region; A connecting layer is formed in the first filling region, and a bit line is formed in the second filling region; A second isolation layer is formed within the through hole.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The connection structure connects the two stacked structures; there are multiple through holes, and the arrangement direction of the multiple through holes is parallel to the extension direction of the pseudo-bit line, and the extension direction of the through holes is parallel to the arrangement direction of the two stacked structures.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, The pseudo bit line has N layers, where N is a positive integer; There are N+1 through holes, and the filling holes are located between adjacent through holes.

5. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, In the arrangement direction of the two stacked structures, the width of the through hole is less than the distance between the two stacked structures; In the arrangement direction of the two stacked structures, the width of the filling hole is equal to the width of the through hole.

6. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The connection structure includes a first sub-connection structure and a second sub-connection structure spaced apart. The first sub-connection structure is connected to one of the two stacked structures, and the second sub-connection structure is connected to the other of the two stacked structures. There is one through-hole, and the extension direction of the through-hole is parallel to the extension direction of the pseudo-bit line. The through-hole is located between the first sub-connection structure and the second sub-connection structure.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, In the arrangement direction of the two stacked structures, the width of the contact layer is greater than the width of the second isolation layer, and the contact layer spans the second isolation layer.

8. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, The through-hole is at the same distance from the two stacked structures.

9. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The through-hole includes a vertical through-hole and a plurality of spaced-apart horizontal through-holes, wherein the extension direction of the horizontal through-holes is parallel to the arrangement direction of the two stacked structures, and the extension direction of the vertical through-holes is parallel to the extension direction of the pseudo-position line; and the vertical through-holes and the horizontal through-holes are intersecting.

10. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The connecting layer includes a first connecting layer to an Nth connecting layer, and the filling hole includes a first filling hole to an Nth filling hole, where N is a positive integer; The steps for forming the filled hole include: A mask layer is formed, and the mask layer is subjected to a first patterning process to form a first opening; Etching is performed along the first opening to expose the first interconnect layer; The mask layer is subjected to a second patterning process to form a second opening; Etching is performed along the first opening and the second opening to expose the second connection layer directly below the first opening and the first connection layer directly below the second opening; Repeat the patterning and etching steps until the first to Nth filling holes are formed, wherein the first filling hole is directly opposite the Nth opening and exposes the first connecting layer, and the Nth filling hole is directly opposite the first opening and exposes the Nth connecting layer.

11. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before forming the contact layer, the method further includes: An initial third isolation layer is formed within the filling hole; A portion of the initial third isolation layer is removed to form a contact hole, and the remaining initial third isolation layer serves as the third isolation layer, which surrounds the contact hole; The contact layer is formed to fill the contact hole.

12. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, A connection layer is formed within the first filling region, and a bit line is formed within the second filling region, including: A conductive layer is formed in the first filling region, the second filling region, and the through-hole; Remove the conductive layer located within the via, and use the conductive layer located in the first filling region as the connection layer, and use the conductive layer located in the second filling region as the bit line.

13. A semiconductor structure, characterized in that, include: A substrate having at least two stacked structures and a connection structure located between the at least two stacked structures; the stacked structures include multiple bit lines, and the connection structure includes multiple connection layers, wherein the connection layers are disposed on the same layer as the bit lines and are connected to them; The connection structure has multiple contact layers, and different contact layers are connected to the top surfaces of different connection layers.

14. The semiconductor structure according to claim 13, characterized in that, The arrangement direction of the plurality of contact layers is parallel to the extension direction of the bit line.

15. The semiconductor structure according to claim 13, characterized in that, In the direction parallel to the extension direction of the bit line, two adjacent contact layers are staggered.

16. The semiconductor structure according to claim 13, characterized in that, The connection structure connects the two stacked structures; The semiconductor structure further includes: a second isolation layer; there are multiple second isolation layers, and the arrangement direction of the multiple second isolation layers is parallel to the extension direction of the bit line, and the extension direction of the second isolation layer is parallel to the arrangement direction of the two stacked structures.

17. The semiconductor structure according to claim 13, characterized in that, The connection structure includes a first sub-connection structure and a second sub-connection structure spaced apart, wherein the first sub-connection structure is connected to one of the two stacked structures and the second sub-connection structure is connected to the other of the two stacked structures. The semiconductor structure further includes a second isolation layer, wherein the extension direction of the second isolation layer is parallel to the extension direction of the bit line; The second isolation layer is located between the first sub-connection structure and the second sub-connection structure.

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