An active bandpass filter Q value calibration circuit
By designing an active bandpass filter Q-value calibration circuit, and utilizing an LDO circuit, a calibration signal filtering circuit, and a Q-value calibration detection circuit, the Q-value of the filter was tuned, solving the problem of unstable performance of the active RC filter and improving the consistency and integration of the chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING RES INST OF ELECTRONICS TECH
- Filing Date
- 2022-10-31
- Publication Date
- 2026-06-26
AI Technical Summary
The Q value of existing active bandpass filter circuits implemented using active RC methods is affected by the resistor R and capacitor C network, resulting in unstable performance. Therefore, it is necessary to design a circuit that can calibrate the Q value of the filter.
Design an active bandpass filter Q-value calibration circuit, including an LDO circuit, a calibration signal filtering circuit, and a Q-value calibration detection circuit. By applying a square wave excitation with known signal amplitude and frequency to the calibration circuit path, the output signal amplitude is detected and compared with a reference signal. The digital circuit control signal is adjusted to tune the RC network inside the bandpass filter until the output signal amplitude is equal to the reference signal.
It achieves effective tuning of the filter Q value, improves chip consistency, has a simple and highly integrated circuit implementation, and can suppress the decrease in detection accuracy caused by common-mode level drift.
Smart Images
Figure CN115694420B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design and manufacturing technology, and in particular to an active bandpass filter Q-value calibration circuit. Background Technology
[0002] With the increasing trend towards miniaturization and integration of RF front-end links, the demand for highly integrated, low-power on-chip bandpass filters is becoming increasingly strong. Intermediate-frequency (IF) active bandpass filters are located in the middle of the signal down-conversion link, serving as an effective means of filtering out out-of-band noise after the RF signal and local oscillator signal are mixed. Their performance directly affects the quality of the signal link. The performance of silicon-based active bandpass filter circuits is often affected by process variations, especially for IF active bandpass filter circuits implemented using active RC methods, where the filter's Q-value is often influenced by the resistor R and capacitor C network. Therefore, a circuit capable of calibrating the filter's Q-value is needed. Summary of the Invention
[0003] To address the existing technical problems, this invention provides an active bandpass filter Q-value calibration circuit that effectively tunes the Q-value of the filter.
[0004] The specific content of this invention is as follows: An active bandpass filter Q-value calibration circuit includes an LDO circuit, a calibration signal filtering circuit, and a Q-value calibration detection circuit; wherein the output terminals V1 and V2 of the LDO circuit power the calibration signal filtering circuit, the output terminal VREF of the LDO circuit provides a reference voltage to the Q-value calibration detection circuit, the output signals VBP and VBN of the calibration signal filtering circuit serve as inputs to the Q-value calibration detection circuit, and the output signal VRZ of the Q-value calibration detection circuit... <n:0>As a control signal for the calibration signal filtering circuit.
[0005] Furthermore, the LDO circuit includes operational amplifiers A1, A2, and A3, and several RC devices; one end of resistor R1 is connected to the power supply VDD, and the other end is connected to resistor R2 and one end of capacitor C1, serving as the positive input terminal of operational amplifier A1; the other end of resistor R2 is connected to the positive input terminal of operational amplifier A2, one end of resistor R3, and one end of capacitor C5; the other end of resistor R3 is connected to one end of resistor R4, one end of capacitor C2, and the positive input terminal of operational amplifier A2; the negative input terminal of operational amplifier A1 is connected to the output terminal V1 and one end of capacitor C3; the negative input terminal of operational amplifier A2 is connected to the output terminal V2 and one end of capacitor C4; the negative input terminal of operational amplifier A3 is connected to the output terminal VREF and one end of capacitor C6; the other ends of capacitors C1 to C6 are all grounded.
[0006] Furthermore, the calibration signal filtering circuit includes inverters INV1 to INV6 and a bandpass filter circuit. CLK is the input terminal of inverter INV1, and the output terminal of inverter INV1 is connected to the input terminals of both inverters INV2 and INV5. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3. The output terminal of inverter INV3 is connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 is connected to the positive input of the bandpass filter. The high-side of inverter INV4 is powered by V1, and the low-side is powered by V2. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6, and the output terminal of inverter INV6 is connected to the inverting input terminal of the bandpass filter. The high-side of inverter INV6 is powered by V1, and the low-side is powered by V2. The bandpass filter and control signal VRZ are also included. <n:0>Connected together, they output differential signals VBP and VBN.
[0007] Furthermore, the Q-value calibration and detection circuit includes a DAC, buffer U1, buffer U2, a hysteresis comparator, a reset circuit, an amplitude detection circuit, operational amplifier A4, digital circuitry, and several RC devices. The output of the DAC is connected to the input of buffer U1. The output of buffer U1 is connected to one end of resistor R5, and the other end is connected to one end of capacitor C7, and simultaneously to the positive input of the hysteresis comparator. One end of resistor R6 is connected to signal VBP, and the other end is connected to the input of buffer U2 and one end of resistor R7. The other end of resistor R7 is connected to signal VBN. The output of buffer U2 is connected to one end of resistor R8. The other end of resistor R8 is connected to one end of resistor R9, and simultaneously to one end of capacitor C8. The other end of resistor R9 is connected to the negative input of operational amplifier A4, and simultaneously to one end of resistor R10. The other end of resistor R10 is connected to the output of operational amplifier A4, and simultaneously to one end of capacitor C9 and the inverting input of the hysteresis comparator. The output L of the hysteresis comparator is connected to the input of the digital circuitry. The digital circuitry outputs a control signal VRZ. <n:0>The output Reset of the reset circuit is connected to the input of the amplitude detection circuit; the other input of the amplitude detection circuit is connected to the signal VBP, and the output of the amplitude detection circuit is connected to one end of resistor R11; the other end of resistor R11 is connected to one end of resistor R12, and also to the positive input of operational amplifier A4; the other end of resistor R12 is connected to the signal VREF; the other ends of capacitors C7 to C9 are all grounded.
[0008] The beneficial effects of this invention are as follows: With this structure, by applying a square wave excitation with known signal amplitude and frequency to the calibration circuit path, the amplitude of the filtered output signal is detected. The obtained amplitude is compared with a predetermined reference signal. Based on the comparison result, the output of the digital circuit control signal is adjusted, thereby tuning the RC network inside the bandpass filter. The adjusted output signal amplitude is then compared with the predetermined reference signal until the amplitude equals the reference signal, thus achieving Q-value calibration. This effectively tunes the Q-value of the filter, improving chip consistency. Compared to traditional active bandpass filter Q-value calibration circuits, it features lower implementation difficulty and higher integration density. Attached Figure Description
[0009] The specific embodiments of the present invention will be further explained below with reference to the accompanying drawings.
[0010] Figure 1 This is a schematic diagram of an LDO circuit;
[0011] Figure 2 A schematic diagram of the calibration signal filtering circuit;
[0012] Figure 3 This is a schematic diagram of the Q-value calibration and detection circuit;
[0013] Figure 4 This is a schematic diagram of the switching on-resistance tuning method for an active RC network. Detailed Implementation
[0014] Combination Figures 1-4 The active bandpass filter Q-value calibration circuit proposed in this invention consists of three parts: an LDO circuit, a calibration signal filtering circuit, and a Q-value calibration detection circuit.
[0015] The outputs V1 and V2 of the LDO circuit power the calibration signal filtering circuit, and the output VREF of the LDO circuit provides a reference voltage to the Q-value calibration detection circuit. The output signals VBP and VBN of the calibration signal filtering circuit serve as the inputs to the Q-value calibration detection circuit, and the output signal VRZ of the Q-value calibration detection circuit... <n:0>As a control signal for the calibration signal filtering circuit.
[0016] The LDO circuit includes operational amplifiers A1, A2, and A3, and several RC components. One end of resistor R1 is connected to the power supply VDD, and the other end is connected to resistor R2 and one end of capacitor C1, serving as the positive input of operational amplifier A1. The other end of resistor R2 is connected to the positive input of operational amplifier A2, one end of resistor R3, and one end of capacitor C5. The other end of resistor R3 is connected to one end of resistor R4, one end of capacitor C2, and the positive input of operational amplifier A2. The negative input of operational amplifier A1 is connected to its output V1 and one end of capacitor C3. The negative input of operational amplifier A2 is connected to its output V2 and one end of capacitor C4. The negative input of operational amplifier A3 is connected to its output VREF and one end of capacitor C6. The other ends of capacitors C1 through C6 are grounded.
[0017] The calibration signal filtering circuit includes inverters INV1 to INV6 and a bandpass filter circuit. CLK is the input terminal of inverter INV1, and the output terminal of inverter INV1 is connected to the input terminals of both inverters INV2 and INV5. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3. The output terminal of inverter INV3 is connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 is connected to the positive input of the bandpass filter. The high-side of inverter INV4 is powered by V1, and the low-side by V2. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6, and the output terminal of inverter INV6 is connected to the inverting input terminal of the bandpass filter. The high-side of inverter INV6 is powered by V1, and the low-side by V2. The bandpass filter and control signal VRZ are also included. <n:0>Connected together, they output differential signals VBP and VBN.
[0018] The Q-value calibration detection circuit includes a DAC, buffers U1 and U2, a hysteresis comparator, a reset circuit, an amplitude detection circuit, operational amplifier A4, digital circuitry, and several RC devices. The output of the DAC is connected to the input of buffer U1. The output of buffer U1 is connected to one end of resistor R5, and the other end is connected to one end of capacitor C7, as well as the positive input of the hysteresis comparator. One end of resistor R6 is connected to signal VBP, and the other end is connected to the input of buffer U2 and one end of resistor R7. The other end of resistor R7 is connected to signal VBN. The output of buffer U2 is connected to one end of resistor R8. The other end of resistor R8 is connected to one end of resistor R9, and also to one end of capacitor C8. The other end of resistor R9 is connected to the negative input of operational amplifier A4, and also to one end of resistor R10. The other end of resistor R10 is connected to the output of operational amplifier A4, and also to one end of capacitor C9 and the inverting input of the hysteresis comparator. The output L of the hysteresis comparator is connected to the input of the digital circuitry. The digital circuitry outputs a control signal VRZ. <n:0>The output Reset of the reset circuit is connected to the input of the amplitude detection circuit; the other input of the amplitude detection circuit is connected to the signal VBP, and the output of the amplitude detection circuit is connected to one end of resistor R11; the other end of resistor R11 is connected to one end of resistor R12, and also to the positive input of operational amplifier A4; the other end of resistor R12 is connected to the signal VREF; the other ends of capacitors C7 to C9 are all grounded.
[0019] Figure 1 In the LDO circuit, R2 = R3, R1 = R4, therefore, the VREF voltage value is VDD / 2. Additionally, 11 * R2 = 4 * R1, therefore V1 = 19VDD / 30, V2 = 11VDD / 30, and δV = V1 - V2 = 4VDD / 15. Capacitors C1, C2, and C5 are used to filter out power supply noise, while capacitors C3, C4, and C6 are used for voltage regulation.
[0020] Figure 2 CLK is a square wave signal with an amplitude of VDD, which has the same center frequency as the main path filter. After being driven by multiple inverters, it generates a differential input signal through INV4 and INV6. The frequency of this differential input signal is the same as the input reference clock frequency, which is also the center frequency of the filter. However, its amplitude is 4VDD / 15, and its common-mode level is VREF. The bandpass filter is a simple second-order active RC filter structure, and its center frequency is the same as the filter being calibrated in the main path. VRZ <n:0>n+1 is a control signal used to control the DAC circuit inside the bandpass filter, generating a DC voltage to change the switch's on-resistance. For example... Figure 4 The active RC network shown is a switching on-resistance tuning method. The voltage generated by the DAC is used as the gate voltage of the NMOS transistor M. Different gate voltages will result in different on-resistances of the NMOS transistor. It and the capacitor C form a zero point to compensate for the Q value of the filter. Figure 2 When the input signal frequency of the bandpass filter is close to the center of the filter, the amplitude of the output signal is 4*δV*Q / π.
[0021] Typically, because active bandpass filters are differential circuits, using one end of the signal for amplitude detection will result in common-mode level deviation. To address this issue... Figure 3 Resistors R6, R7, R8, buffer U2, and capacitor C8 form a common-mode level detection circuit, where R6 = R7, and the common-mode level VR is (VBP + VBN) / 2. R8 and C8 form a first-order low-pass filter to filter out DC noise, and buffer U2 provides driving capability. The amplitude detection circuit detects the amplitude of the VBP signal and relies on the reset signal from the reset circuit as the detection enable. Resistors R9 to R12 form a common-mode level conversion circuit, where the four resistors R9 to R12 have equal values, so the output signal amplitude is VBP + VREF - (VBP + VBN) / 2. This converts the common-mode voltage of the differential filter VBP signal to VREF, and the common-mode voltage of the amplitude detection reference voltage Vrefp output by the DAC is also VREF. Therefore, the two input signals of the hysteresis comparator can be amplitude detected at the same common-mode level.
[0022] Figure 3 In the Q-value calibration detection circuit, the DAC generates an amplitude detection reference voltage signal of 4*δV / π, which serves as an input signal to the hysteresis comparator. Taking a calibration Q-value target of 1 as an example, when... Figure 2 When the Q value of the bandpass filter in the circuit is less than 1, the input signal at the other end of the hysteresis comparator is less than 4*δV / π, and the hysteresis comparator outputs logic 0. The digital circuit then controls the VRZ bit. <n:0>The comparator continues to carry over until the amplitude of the bandpass filter's output signal reaches 4*δV / π. At this point, the comparator starts to toggle, the calibration indicator signal L is 1, calibration is complete, and the control bit VRZ is now active. <n:0>The final control signal for adjusting the Q value serves as the main filter path.
[0023] This invention employs an active bandpass filter Q-value calibration circuit composed of an LDO circuit, a calibration signal filtering circuit, and a Q-value calibration detection circuit to achieve Q-value tuning of the intermediate frequency active bandpass filter circuit. Compared with traditional methods, the circuit implementation is simple, highly integrated, and can be highly integrated with existing active RC circuits. The circuit of this invention is simple, allowing for complete on-chip integration of all calibration circuitry. Furthermore, the proposed calibration circuit includes common-mode level detection and conversion circuitry, which can suppress the decrease in detection accuracy caused by common-mode level drift in the differential filter.
[0024] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.
Claims
1. An active bandpass filter Q-value calibration circuit, characterized in that: It includes an LDO circuit, a calibration signal filtering circuit, and a Q-value calibration detection circuit. The outputs V1 and V2 of the LDO circuit power the calibration signal filtering circuit, and the output VREF of the LDO circuit provides a reference voltage to the Q-value calibration detection circuit. The output signals VBP and VBN of the calibration signal filtering circuit serve as inputs to the Q-value calibration detection circuit, and the output signal VRZ of the Q-value calibration detection circuit... <n:0>As a control signal for the calibration signal filtering circuit;< / n:0> The calibration signal filtering circuit includes inverters INV1~INV6 and a bandpass filter circuit. CLK is the input terminal of inverter INV1, and the output terminal of inverter INV1 is connected to the input terminals of both inverters INV2 and INV5. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3. The output terminal of inverter INV3 is connected to the input terminal of inverter INV4, and the output terminal of inverter INV4 is connected to the positive input of the bandpass filter. The high-side of inverter INV4 is powered by V1, and the low-side by V2. The output terminal of inverter INV5 is connected to the input terminal of inverter INV6, and the output terminal of inverter INV6 is connected to the inverting input terminal of the bandpass filter. The high-side of inverter INV6 is powered by V1, and the low-side by V2. The bandpass filter and control signal VRZ are also included. <n:0> Connected together, they output differential signals VBP and VBN;< / n:0> The Q-value calibration detection circuit includes a DAC, buffers U1 and U2, a hysteresis comparator, a reset circuit, an amplitude detection circuit, operational amplifier A4, digital circuitry, and several RC devices. The output of the DAC is connected to the input of buffer U1. The output of buffer U1 is connected to one end of resistor R5, and the other end is connected to one end of capacitor C7, as well as the positive input of the hysteresis comparator. One end of resistor R6 is connected to signal VBP, and the other end is connected to the input of buffer U2 and one end of resistor R7. The other end of resistor R7 is connected to signal VBN. The output of buffer U2 is connected to one end of resistor R8. The other end of resistor R8 is connected to one end of resistor R9, and also to one end of capacitor C8. The other end of resistor R9 is connected to the negative input of operational amplifier A4, and also to one end of resistor R10. The other end of resistor R10 is connected to the output of operational amplifier A4, and also to one end of capacitor C9 and the inverting input of the hysteresis comparator. The output L of the hysteresis comparator is connected to the input of the digital circuitry. The digital circuitry outputs a control signal VRZ. <n:0> The output Reset of the reset circuit is connected to the input of the amplitude detection circuit; the other input of the amplitude detection circuit is connected to the signal VBP, and the output of the amplitude detection circuit is connected to one end of resistor R11; the other end of resistor R11 is connected to one end of resistor R12, and also to the positive input of operational amplifier A4; the other end of resistor R12 is connected to the signal VREF; the other ends of capacitors C7~C9 are all grounded.< / n:0> 2. The active bandpass filter Q-value calibration circuit according to claim 1, characterized in that: The LDO circuit includes operational amplifiers A1, A2, and A3, and several RC components. One end of resistor R1 is connected to the power supply VDD, and the other end is connected to resistor R2 and one end of capacitor C1, serving as the positive input of operational amplifier A1. The other end of resistor R2 is connected to the positive input of operational amplifier A2, one end of resistor R3, and one end of capacitor C5. The other end of resistor R3 is connected to one end of resistor R4, one end of capacitor C2, and the positive input of operational amplifier A2. The negative input of operational amplifier A1 is connected to its output V1 and one end of capacitor C3. The negative input of operational amplifier A2 is connected to its output V2 and one end of capacitor C4. The negative input of operational amplifier A3 is connected to its output VREF and one end of capacitor C6. The other ends of capacitors C1 through C6 are all grounded.