Manufacturing method of interconnect structure
By introducing air gaps and low dielectric constant materials into the semiconductor interconnect structure, the problem of increased capacitance between conductive layers is solved, thereby reducing resistance-capacitance delay and increasing signal transmission speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- POWERCHIP SEMICON MFG CORP
- Filing Date
- 2021-12-30
- Publication Date
- 2026-05-26
AI Technical Summary
As the integration density of semiconductor devices increases, the spacing between conductive layers decreases, leading to an increase in parasitic capacitance and severe resistance-capacitance delay issues, which affect signal transmission speed.
A dielectric layer containing an air gap is formed between two adjacent sacrificial layers. The opening width is expanded by an etching process to form an interconnect structure. Low dielectric constant material and conductive material are used, combined with barrier layer and spacer wall material to construct the interconnect structure.
By introducing an air gap in the dielectric layer, the parasitic capacitance between conductive layers is reduced, effectively decreasing resistance-capacitance delay and improving signal transmission speed.
Smart Images
Figure CN116259574B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a method for manufacturing a semiconductor structure, and more particularly to a method for manufacturing an interconnect structure. Background Technology
[0002] As the integration density of semiconductor devices continues to increase, the spacing between conductive layers is also becoming smaller. This increases the parasitic capacitance between conductive layers, thus exacerbating the resistance-capacitance (RC) delay problem. Since RC delay reduces signal transmission speed, effectively reducing RC delay is a current ongoing research goal. Summary of the Invention
[0003] This invention provides a method for manufacturing an interconnect structure that can effectively reduce resistor and capacitor delay.
[0004] This invention proposes a method for manufacturing an interconnect structure, comprising the following steps: Providing a substrate. Forming a plurality of sacrificial layers on the substrate. Forming a dielectric layer between two adjacent sacrificial layers. Having an air gap in the dielectric layer. Removing the plurality of sacrificial layers to form a plurality of first openings. Forming a conductive layer in the first openings.
[0005] According to an embodiment of the present invention, in the above-described method for manufacturing the interconnect structure, the method for forming the sacrificial layer may include the following steps: forming a sacrificial material layer on a substrate; forming a hard mask material layer on the sacrificial material layer; patterning the hard mask material layer and the sacrificial material layer to form a plurality of hard mask layers and a plurality of sacrificial layers, and forming a second opening between two adjacent hard mask layers and between two adjacent sacrificial layers.
[0006] According to an embodiment of the present invention, the manufacturing method of the above-described interconnect structure may further include the following step: performing an isotropic etching process on the sacrificial layer to widen the width of the second opening located between two adjacent sacrificial layers.
[0007] According to an embodiment of the present invention, in the manufacturing method of the above-described interconnect structure, the width of the second opening located between two adjacent sacrificial layers may be greater than the width of the second opening located between two adjacent hard mask layers.
[0008] According to an embodiment of the present invention, in the above-described method for manufacturing the interconnect structure, the method for forming the dielectric layer may include the following steps: A dielectric material layer is formed in a second opening. An air gap may be present in the dielectric material layer. The air gap may be located between two adjacent sacrificial layers. Using the sacrificial layer as a terminating layer, a portion of the dielectric material layer and the hard mask layer are removed to form the dielectric layer.
[0009] According to one embodiment of the present invention, in the above-described method for manufacturing the interconnect structure, the conductive layer is formed using, for example, copper.
[0010] According to an embodiment of the present invention, the manufacturing method of the above-described interconnect structure may further include the following steps: A termination layer is formed on a substrate before forming a sacrificial layer. A dielectric layer may be formed on the termination layer. A spacer material layer is conformally formed on the dielectric layer and the termination layer. An etch-back process is performed on the spacer material layer to form a spacer on the sidewall of the dielectric layer. The etch-back process removes a portion of the termination layer exposed by the spacer, thereby exposing a portion of the substrate.
[0011] According to an embodiment of the present invention, the manufacturing method of the above-described interconnect structure may further include the following step: forming a barrier layer in a first opening. The barrier layer is located between the conductive layer and the dielectric layer, and between the conductive layer and the substrate.
[0012] According to an embodiment of the present invention, in the above-described method for manufacturing the interconnect structure, the method for forming the conductive layer and the barrier layer may include the following steps: A barrier material layer is conformally formed in a first opening. A conductive material layer filling the first opening is formed on the barrier material layer. The conductive material layer and the barrier material layer located outside the first opening are removed, thereby forming the conductive layer and the barrier layer.
[0013] According to an embodiment of the present invention, in the manufacturing method of the above-described interconnect structure, the method for removing the conductive material layer and the barrier material layer located outside the first opening is, for example, chemical mechanical polishing.
[0014] Based on the above, in the manufacturing method of the interconnect structure proposed in this invention, since there is an air gap in the dielectric layer and the air gap has a low dielectric constant, the parasitic capacitance between the conductive layers can be reduced, thereby effectively reducing the resistance-capacitance delay.
[0015] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0016] Figures 1A to 1K This is a cross-sectional view of the manufacturing process of an interconnect structure according to an embodiment of the present invention.
[0017] Symbol Explanation
[0018] 100: Base
[0019] 102: Termination Layer
[0020] 104: Sacrificial Material Layer
[0021] 104a: Sacrificial Layer
[0022] 106: Hard mask material layer
[0023] 106a: Hard mask layer
[0024] 108: Dielectric material layer
[0025] 108a: Dielectric layer
[0026] 110: Spacer wall material layer
[0027] 110a: Spacer wall
[0028] 112: Barrier Material Layer
[0029] 112a: Barrier layer
[0030] 114: Conductive material layer
[0031] 114a: Conductive layer
[0032] 116: Internal Wiring Structure
[0033] AG: Air gap
[0034] OP1, OP2: Openings
[0035] TS1, TS2: Top surface
[0036] W1, W2: Width Detailed Implementation
[0037] Figures 1A to 1K This is a cross-sectional view of the manufacturing process of an interconnect structure according to an embodiment of the present invention.
[0038] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. Furthermore, in... Figure 1A Although not shown, the substrate 100 may have the required components such as doped regions and / or isolation structures, and the substrate 100 may have the required components such as semiconductor elements (e.g., active elements such as transistors), dielectric layers and / or interconnect structures, which are omitted here.
[0039] Next, a termination layer 102 can be formed on the substrate 100. The material of the termination layer 102 is, for example, silicon oxide. The method for forming the termination layer 102 is, for example, chemical vapor deposition.
[0040] Then, a sacrificial material layer 104 can be formed on the substrate 100. In this embodiment, the sacrificial material layer 104 can be formed on the termination layer 102. The material of the sacrificial material layer 104 is, for example, silicon nitride. The method for forming the sacrificial material layer 104 is, for example, chemical vapor deposition.
[0041] Next, a hard mask material layer 106 may be formed on the sacrificial material layer 104. The material of the hard mask material layer 106 is, for example, silicon oxide, such as tetraethyl orthosilicate (TEOS) silicon oxide, but the present invention is not limited thereto. The hard mask material layer 106 may be formed by, for example, chemical vapor deposition.
[0042] Please refer to Figure 1B The hard mask material layer 106 and the sacrificial material layer 104 can be patterned to form a plurality of hard mask layers 106a and a plurality of sacrificial layers 104a, and openings OP1 are formed between two adjacent hard mask layers 106a and between two adjacent sacrificial layers 104a. Thus, a plurality of sacrificial layers 104a can be formed on the substrate 100. In this embodiment, the sacrificial layers 104a can be formed on the termination layer 102. Furthermore, the hard mask layers 106a can be formed on the sacrificial layers 104a. For example, the hard mask material layer 106 and the sacrificial material layer 104 can be patterned using photolithography and etching processes (e.g., dry etching).
[0043] Please refer to Figure 1C An isotropic etching process can be performed on the sacrificial layer 104a to widen the opening OP1 between two adjacent sacrificial layers 104a. This isotropic etching process can be, for example, a wet etching process or a dry etching process. In some embodiments, the width W1 of the opening OP1 between two adjacent sacrificial layers 104a can be greater than the width W2 of the opening OP1 between two adjacent hard mask layers 106a.
[0044] Please refer to Figure 1D A dielectric material layer 108 can be formed in the opening OP1. An air gap AG may be present in the dielectric material layer 108. The air gap AG may be located between two adjacent sacrificial layers 104a. The material of the dielectric material layer 108 is, for example, silicon oxide (e.g., TEOS silicon oxide) or a low dielectric constant (low-k) material. The dielectric material layer 108 can be formed by, for example, chemical vapor deposition.
[0045] Please refer to Figure 1EA dielectric layer 108a can be formed by removing a portion of the dielectric material layer 108 and the hard mask layer 106a using a sacrificial layer 104a as a terminating layer. Thus, a dielectric layer 108a can be formed between two adjacent sacrificial layers 104a. In some embodiments, the dielectric layer 108a can be formed on the terminating layer 102. An air gap AG is present in the dielectric layer 108a. In some embodiments, the air gap AG can be located inside the dielectric layer 108a, that is, the air gap AG can be surrounded by the dielectric layer 108a. For example, a chemical mechanical polishing process can be performed on the dielectric material layer 108 and the hard mask layer 106a using the sacrificial layer 104a as a polishing terminating layer to remove a portion of the dielectric material layer 108 and the hard mask layer 106a, thereby forming the dielectric layer 108a.
[0046] Please refer to Figure 1F Multiple sacrificial layers 104a are removed to form multiple openings OP2. The method for removing the sacrificial layers 104a is, for example, wet etching. In addition, in the etching process used to remove the sacrificial layers 104a, a stop layer 102 can be used to protect components (e.g., interconnect structures or electrodes, etc.) located below the stop layer 102 (not shown).
[0047] Please refer to Figure 1G A spacer material layer 110 can be conformally formed on the dielectric layer 108a and the termination layer 102. The material of the spacer material layer 110 can be a material with a high etch selectivity compared to the dielectric layer 108a. For example, the material of the dielectric layer 108a can be TEOS silicon oxide, and the material of the spacer material layer 110 can be silicon nitride. The spacer material layer 110 can be formed, for example, by chemical vapor deposition.
[0048] Please refer to Figure 1H A back-etch process can be performed on the spacer wall material layer 110 to form spacer walls 110a on the sidewalls of the dielectric layer 108a. Furthermore, the back-etch process can remove a portion of the termination layer 102 exposed by the spacer walls 110a, thus exposing a portion of the substrate 100. As a result, the opening OP2 can extend into the termination layer 102 and expose a portion of the substrate 100. The back-etch process can be, for example, a dry etching process.
[0049] Please refer to Figure 1I A barrier material layer 112 can be conformally formed in the opening OP2. The material of the barrier material layer 112 is, for example, tantalum (Ta), tantalum nitride (TaN), or a combination thereof, but the present invention is not limited thereto. The method for forming the barrier material layer 112 is, for example, physical vapor deposition, but the present invention is not limited thereto.
[0050] Please refer to Figure 1JA conductive material layer 114, which fills the opening OP2, can be formed on the barrier material layer 112. The material of the conductive material layer 114 is, for example, copper. The conductive material layer 114 can be formed by electrochemical plating (ECP), physical vapor deposition, chemical vapor deposition, or a combination thereof, but the present invention is not limited thereto.
[0051] Please refer to Figure 1K The conductive material layer 114 and the barrier material layer 112 located outside the opening OP2 can be removed to form a conductive layer 114a and a barrier layer 112a. Thus, a conductive layer 114a and a barrier layer 112a can be formed within the opening OP2. In some embodiments, the cross-sectional shape of the conductive layer 114a may be an inverted trapezoid. The barrier layer 112a is located between the conductive layer 114a and the dielectric layer 108a, and between the conductive layer 114a and the substrate 100. In this embodiment, the barrier layer 112a may be located between the conductive layer 114a and the spacer wall 110a. Furthermore, the method for removing the conductive material layer 114 and the barrier material layer 112 located outside the opening OP2 is, for example, chemical mechanical polishing.
[0052] Using the methods described above (e.g., the damascene method), an interconnect structure 116 can be formed in the opening OP2. The interconnect structure 116 can be a wire, a contact window, or a via. The interconnect structure 116 may include a conductive layer 114a. The conductive layer 114a is formed from a material such as copper. In some embodiments, the interconnect structure 116 may also include a barrier layer 112a. The conductive layer 114a may be located on the barrier layer 112a. The barrier layer 112a is made of materials such as tantalum (Ta), tantalum nitride (TaN), or combinations thereof, but the invention is not limited thereto. In some embodiments, the interconnect structure 116 may be electrically connected to a conductive component (e.g., an interconnect structure or an electrode, etc.) located on or within the substrate 100 (not shown). Furthermore, when the substrate 100 has an open area (not shown), a dummy conductive pattern is simultaneously formed in the open area during the fabrication process of forming the conductive layer 114a. In some embodiments, an open area can be defined as having an area of 100 square micrometers (μm). 2 The region above 114a that does not have a conductive layer 114a.
[0053] Based on the above embodiments, it can be seen that in the manufacturing method of the interconnect structure 116, since the dielectric layer 108a has an air gap AG and the air gap AG has a low dielectric constant, the parasitic capacitance between the conductive layers 114a can be reduced, thereby effectively reducing the resistance-capacitance delay.
[0054] In summary, in the manufacturing method of the interconnect structure in the above embodiments, the resistance and capacitance delay can be effectively reduced because there is an air gap in the dielectric layer.
[0055] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A method for manufacturing an interconnect structure, comprising: Provide a base; Multiple sacrificial layers are formed on the substrate, including: A sacrificial material layer is formed on the substrate; A hard mask material layer is formed on the sacrificial material layer; The hard mask material layer and the sacrificial material layer are patterned to form a plurality of hard mask layers and a plurality of sacrificial layers, and a second opening is formed between two adjacent hard mask layers and between two adjacent sacrificial layers; and An isotropic etching process is performed on the sacrificial layer to widen the width of the second opening located between two adjacent sacrificial layers, wherein the width of the second opening located between two adjacent sacrificial layers is greater than the width of the second opening located between two adjacent hard mask layers. With the hard mask layer remaining on the sacrificial layer, a dielectric layer is formed between two adjacent sacrificial layers, wherein an air gap is present in the dielectric layer; Remove multiple sacrificial layers to form multiple first openings; and A conductive layer is formed in the first opening.
2. The method for manufacturing the interconnect structure as described in claim 1, wherein the method for forming the dielectric layer includes: A dielectric material layer is formed in the second opening, wherein the air gap is present in the dielectric material layer and the air gap is located between two adjacent sacrificial layers; as well as Using the sacrificial layer as a termination layer, a portion of the dielectric material layer and the hard mask layer are removed to form the dielectric layer.
3. The method for manufacturing the interconnect structure as claimed in claim 1, wherein the method for forming the material of the conductive layer includes copper.
4. The method for manufacturing the interconnect structure as described in claim 1, further comprising: Before the sacrificial layer is formed, a terminating layer is formed on the substrate, wherein the dielectric layer is formed on the terminating layer; A spacer material layer is conformally formed on the dielectric layer and the termination layer; as well as An etch-back process is performed on the spacer material layer to form a spacer on the sidewall of the dielectric layer, wherein the etch-back process removes a portion of the termination layer exposed by the spacer and exposes a portion of the substrate.
5. The method for manufacturing the interconnect structure as described in claim 1, further comprising: A barrier layer is formed in the first opening, wherein the barrier layer is located between the conductive layer and the dielectric layer and between the conductive layer and the substrate.
6. The method for manufacturing the interconnect structure as described in claim 5, wherein the method for forming the conductive layer and the barrier layer includes: A barrier material layer is conformally formed in the first opening; A conductive material layer is formed on the barrier material layer to fill the first opening; as well as The conductive material layer and the barrier material layer located outside the first opening are removed to form the conductive layer and the barrier layer.
7. The method for manufacturing the interconnect structure as claimed in claim 6, wherein the method for removing the conductive material layer and the barrier material layer located outside the first opening includes chemical mechanical polishing.