Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate comprising a first region and a second region, and forming an interlayer dielectric layer having a gate opening on the substrate; forming a shielding layer covering the gate opening of the second region and exposing the gate opening of the first region, the shielding layer occupying the gate opening of the second region, so that in the step of forming a first work function material layer in the gate opening of the first region, the first work function material layer is formed on the shielding layer, and in the process of removing the shielding layer and the first work function material layer on the shielding layer, the removal process window of the first work function material layer of the second region is larger, and it is not easy to have residues, and the removal efficiency is higher, which is beneficial to improve the yield; in addition, the removal process window of the shielding layer is larger, and it is not easy to have residues, the second work function layer can better adjust the threshold voltage of the transistor of the second region, reduce the parasitic capacitance in the transistor of the second region, so that the electrical performance of the semiconductor structure is better.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as FinFETs. In FinFETs, the gate structure can control the ultrathin body (fin) from at least two sides. Compared with planar MOSFETs, the gate structure has stronger control over the channel and can effectively suppress short-channel effects. The gate structure has also shifted from the original polysilicon gate structure to a metal gate structure. In the metal gate structure, the work function layer can adjust the threshold voltage of the semiconductor structure.

[0004] In semiconductor structures, the work function layer is used to adjust the threshold voltage of transistors. The quality of the work function layer formation is crucial to the electrical performance of the semiconductor structure. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which improves the formation quality of the work function layer and optimizes the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region, forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer having a gate opening exposing a portion of the substrate; forming a shielding layer covering the gate opening of the second region and exposing the gate opening of the first region; forming a first work function material layer conformally covering the gate opening of the first region and the shielding layer; removing the shielding layer and the first work function material layer located on the shielding layer, the remaining first work function material layer located in the gate opening of the first region serving as a first work function layer; forming a second work function layer conformally covering the gate opening of the second region; after forming the second work function layer, forming a gate layer in the gate opening, and using the first work function layer, the second work function layer, and the gate layer as a gate structure.

[0007] Optionally, the material of the shielding layer includes amorphous silicon, silicon oxide, or silicon nitride.

[0008] Optionally, the step of forming a shielding layer that covers the gate opening in the second region and exposes the gate opening in the first region includes: forming a shielding material layer that covers the gate openings in the first and second regions; removing the shielding material layer in the gate opening in the first region, and using the remaining shielding material layer in the second region as the shielding layer.

[0009] Optionally, the method for forming the semiconductor structure further includes: after forming the shielding material layer, and before removing the shielding material layer from the gate opening in the first region, annealing the shielding material layer.

[0010] Optionally, the shielding material layer may be formed using a chemical vapor deposition process.

[0011] Optionally, a dry etching process is used to remove the shielding material layer in the gate opening of the first region, and the remaining shielding material layer in the second region serves as a shielding layer.

[0012] Optionally, the method for forming the semiconductor structure further includes: after providing the gate opening and before forming the shielding layer, forming a conformal capping layer covering the gate opening; in the step of forming the shielding layer, the shielding layer is formed on the capping layer; in the step of removing the shielding layer and the first work function material layer located on the shielding layer, the etching resistance of the capping layer is greater than the etching resistance of the shielding layer.

[0013] Optionally, the material of the capping layer includes one or more of TiN, TiSiN, and TaN.

[0014] Optionally, the capping layer may be formed using atomic layer deposition or physical vapor deposition.

[0015] Optionally, the step of removing the masking layer and the first work function material layer located on the masking layer includes: forming a mask layer on the first work function material layer that covers the first region and exposes the second region II; removing the masking layer and the first work function material layer located on the masking layer using the mask layer as a mask; the method of forming the semiconductor structure further includes: removing the mask layer after forming the first work function layer.

[0016] Optionally, the mask layer may be made of an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

[0017] Optionally, the mask layer and the first work function material layer located on the mask layer are removed by a dry etching process using the mask layer as a mask.

[0018] Optionally, the method for forming the semiconductor structure includes: after providing the gate opening and before forming the shielding layer, forming a conformally conformal gate dielectric layer covering the gate opening.

[0019] Optionally, the first work function material layer is formed using an atomic layer deposition process.

[0020] Optionally, the second work function layer is formed using an atomic layer deposition process.

[0021] Optionally, the method for forming the semiconductor structure further includes: forming a barrier layer on the second work function layer after forming the second work function layer and before forming the gate layer; in the step of forming the gate layer, the gate layer is formed on the barrier layer.

[0022] Optionally, the substrate includes a substrate, fins discretely disposed on the substrate, and an isolation layer covering a portion of the sidewalls of the fins; the gate opening is surrounded by an interlayer dielectric layer, an isolation layer, and the fins.

[0023] Optionally, the method for forming the semiconductor structure includes: after providing a substrate and before forming the shielding layer, forming an interface layer on the top and sidewalls of the fin that exposes the isolation layer.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0025] In the semiconductor structure formation method provided by this embodiment of the invention, in the step of forming a shielding layer that covers the gate opening of the second region and exposes the gate opening of the first region, and the shielding layer occupies the gate opening of the second region to form a first work function material layer that conformally covers the gate opening of the first region, the first work function material layer is formed on the shielding layer. Compared with the case where the first work function material layer is formed in the gate opening of the second region, in this embodiment, the first work function material layer of the second region is located on the shielding layer. Therefore, in the step of removing the first work function material layer of the second region, the removal process window is larger, the first work function material layer of the second region is less likely to remain, and because the removal process window is larger, the first work function material layer of the second region is more likely to remain. The high layer removal efficiency is beneficial for increasing yield. Furthermore, compared to the case where a first work function material layer is formed on the bottom and sidewalls of the gate opening, and a shielding layer is formed on the first work function material layer, in this embodiment, the bottom and sidewalls of the shielding layer do not form a first work function material layer occupying the gate opening space. During the removal of the shielding layer, the removal process window is larger, and the shielding layer is less likely to remain. Consequently, the second work function layer in the second region is less likely to form on the first work function material layer and the shielding layer, thereby reducing the parasitic capacitance in the transistor of the second region. Because the second work function layer is less likely to form on the first work function material layer and the shielding layer, the second work function layer has better formation quality, enabling better adjustment of the threshold voltage of the transistor in the second region, resulting in better electrical performance of the semiconductor structure.

[0026] In an alternative embodiment, after forming the gate opening and before forming the shielding layer, a conformal capping layer is formed to cover the gate opening. In the step of forming the shielding layer, the shielding layer is formed on the capping layer. Compared with the case where a first work function material layer is formed on the capping layer of the first region and the second region, and then the first work function material layer on the capping layer of the second region is removed, in the step of removing the shielding layer on the capping layer of the second region in this embodiment of the invention, because the etch resistance of the capping layer is greater than that of the shielding layer, the top of the capping layer can be used as the removal stop position, making it less likely that the shielding layer will remain. Attached Figure Description

[0027] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0028] Figures 7 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0029] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0030] refer to Figures 1 to 6 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0031] like Figure 1 As shown, a substrate is provided, the substrate including a first region I for forming a PMOS and a second region II for forming an NMOS, the substrate including a substrate 1, a fin 2 disposed on the substrate 1 and an isolation layer 3 covering part of the sidewalls of the fin 2; an interface layer 12 is formed on the surface of the fin 2 exposing the isolation layer 3; after forming the interface layer 12, a conformal gate dielectric layer 4 is formed on the fin 2 exposing the isolation layer 3.

[0032] like Figure 2 As shown, a first work function material layer 5 is formed to conformally cover the gate dielectric layer 4. The first work function material layer 5 is used to adjust the threshold voltage of the PMOS.

[0033] like Figure 3 As shown, a shielding material layer is formed covering the first region I and the second region II; the shielding material layer in the second region II is removed, and the remaining shielding material layer in the first region I serves as shielding layer 7.

[0034] like Figure 4 As shown, the first work function material layer 5 in the second region II is removed using the shielding layer 7 as a mask, and the remaining first work function material layer 5 in the first region I is used as the first work function layer 6.

[0035] like Figure 5 As shown, after forming the first function layer 6, the occlusion layer 7 is removed.

[0036] like Figure 6 As shown, a second work function layer 8 is formed in the second region II to conformally cover the fin 2, and the second work function layer 8 is also formed on the first work function layer 6; after the second work function layer 8 is formed, a gate layer 9 is formed to cover the second work function layer 8.

[0037] As the integration density of semiconductor structures increases, the pitch between adjacent fins 2 becomes smaller. A first work function material layer 5 is formed on the surface of the fin 2 exposing the isolation layer 3. Correspondingly, the width d of the opening 13 between the first work function material layers 5 of adjacent fin 2 sidewalls (e.g., ...) Figure 2The smaller size of the first work function material layer 5 in the second region II results in a smaller process window for removing the first work function material layer 5. As a result, during the formation of the shielding layer 7, residual shielding layer 10 is likely to exist at the corner of the fin 2 and the isolation layer 3 in the second region II. During the removal of the first work function material layer 5 in the second region II using the shielding layer 7 as a mask, the residual shielding layer 10 will hinder the removal of the first work function material layer 5 in the second region II, resulting in residual first work function layer 11 in the second region II. Correspondingly, during the formation of the second work function layer 8, the second work function layer 8 is formed on the residual shielding layer 10 and residual first work function layer 11 in the second region II. When the semiconductor structure is working, parasitic capacitance is likely to exist in the second region II. The residual shielding layer 10 and residual first work function layer 11 in the second region II will also cause the second work function layer 8 to be unable to accurately adjust the threshold voltage of the second region II, resulting in poor electrical performance of the semiconductor structure.

[0038] In extreme cases, during the process of removing the first work function material layer 5 of the second region II using the shielding layer 7 as a mask, the gate dielectric layer 4 and interface layer 12 on the top of the fin 2 in the second region II are also easily damaged, resulting in the gate dielectric layer 4 and interface layer 12 failing to effectively electrically isolate the fin 2 and the second work function layer 8, leading to poor electrical performance of the semiconductor structure.

[0039] To address the aforementioned technical problem, a substrate is provided, comprising a first region and a second region. An interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer having a gate opening that exposes a portion of the substrate. A shielding layer is formed that covers the gate opening in the second region and exposes the gate opening in the first region. A first work function material layer is formed that conformally covers the gate opening in the first region and the shielding layer. The shielding layer and the first work function material layer located on the shielding layer are removed, leaving the remaining first work function material layer located in the gate opening in the first region as the first work function layer. A second work function layer is formed that conformally covers the gate opening in the second region. After forming the second work function layer, a gate layer is formed in the gate opening, and the first work function layer, the second work function layer, and the gate layer constitute a gate structure.

[0040] The method for forming the semiconductor structure includes forming a shielding layer that covers a gate opening in the second region and exposes a gate opening in the first region, wherein the shielding layer occupies the gate opening in the second region, thereby forming a first work function material layer conformally covering the gate opening in the first region. In this step, the first work function material layer is formed on the shielding layer. Compared to the case where the first work function material layer is formed in the gate opening in the second region, in this embodiment, the first work function material layer in the second region is located on the shielding layer, resulting in a larger removal process window. Therefore, in the step of removing the first work function material layer in the second region, the first work function material layer in the second region is less likely to remain, and because the removal process window is larger, the second... The removal efficiency of the first work function material layer in the region is relatively high, which is beneficial to increasing yield. In addition, compared with the case where the first work function material layer is formed on the bottom surface and sidewalls of the gate opening, and a shielding layer is formed on the first work function material layer, in this embodiment, the bottom and sidewalls of the shielding layer do not form a first work function material layer occupying the gate opening space. In the step of removing the shielding layer, the removal process window of the shielding layer is larger, and the shielding layer is less likely to remain. As a result, the second work function layer in the second region is less likely to be formed on the first work function material layer and the shielding layer. The second work function layer has better formation quality. The second work function layer can better adjust the threshold voltage of the transistor in the second region, reduce the parasitic capacitance in the transistor in the second region, and make the electrical performance of the semiconductor structure better.

[0041] Figures 7 to 20 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0042] refer to Figure 7 and Figure 8 , Figure 8 for Figure 7 In the cross-sectional view at AA, a substrate 100 is provided, the substrate 100 including a first region I and a second region II, an interlayer dielectric layer 101 is formed on the substrate 100, the interlayer dielectric layer 101 having a gate opening 102 exposing a portion of the substrate 100.

[0043] The substrate provides the technological basis for the subsequent formation of semiconductor structures.

[0044] In this embodiment, the step of providing the substrate includes a substrate 103 and fins 104 discretely disposed on the substrate 103. Accordingly, the subsequent formation of a semiconductor structure is exemplified by a FinFET (Fin Field-Effect Transistor). In other embodiments, the substrate may also be a planar substrate, and the corresponding semiconductor structure may be a planar transistor (MOSFET). In some other embodiments, the substrate further includes a plurality of suspended channel layers located on the fins, the channel layers being spaced apart in the normal direction of the substrate surface; correspondingly, the semiconductor structure is a gate-all-around (GAA) transistor.

[0045] In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The first-type transistor and the second-type transistor have different conductivity types. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative Channel Metal Oxide Semiconductor). In other embodiments, the first transistor may also be an NMOS, and the second transistor may also be a PMOS.

[0046] In this embodiment, substrate 103 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0047] In this embodiment, the material of the fin 104 is the same as the material of the substrate 103, and the material of the fin 104 includes silicon.

[0048] The substrate further includes: an isolation layer 105 (such as...) Figure 7 As shown, the substrate 103 is located on the side of the fin 104, and the isolation layer 105 covers part of the sidewall of the fin 104.

[0049] The isolation layer 105 is used to isolate the substrate 103 from the subsequently formed gate structure.

[0050] In this embodiment, the material of the isolation layer 105 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer 105. In addition, silicon oxide has a low dielectric constant, which also helps to improve the function of the subsequent isolation layer 105 in isolating adjacent devices.

[0051] Interlayer dielectric layer 101 is used for electrical isolation of adjacent devices.

[0052] In this embodiment, the material of the interlayer dielectric layer 101 is an insulating material. Specifically, the material of the interlayer dielectric layer 101 includes silicon oxide.

[0053] The gate opening 102 is prepared for the subsequent formation of the gate structure.

[0054] In this embodiment, the gate opening 102 is surrounded by an interlayer dielectric layer 101, an isolation layer 105, and a fin 104. The exposed portion of the substrate in the gate opening 102 refers to the exposed portion of the top wall and sidewall of the fin 104 above the isolation layer 105.

[0055] It should be noted that the substrate 100 further includes a source / drain structure (not shown in the figure) formed in the fins 104 on both sides of the gate opening 102.

[0056] When a semiconductor structure is in operation, the source-drain structure is used to provide stress to the channel, thereby increasing the migration rate of charge carriers in the channel.

[0057] In this embodiment, the first region I is used to form a PMOS. The source and drain structure is made of silicon germanide doped with P-type ions. In this embodiment, the P-type ions include boron, gallium, or indium. The second region II is used to form an NMOS, and the source and drain structure is made of silicon carbide or silicon phosphide doped with N-type ions. In this embodiment, the N-type ions include phosphorus, arsenic, or antimony.

[0058] It should be noted that the sidewall of the gate opening 102 is formed with a sidewall layer (not shown in the figure).

[0059] The sidewall layer is used to electrically isolate the source / drain structure from the gate structure subsequently formed in the gate opening 102.

[0060] The sidewall layer is made of a low-k dielectric material, which helps reduce the capacitive coupling effect between the source / drain structure and the subsequently formed gate structure, thereby improving the electrical performance of the semiconductor structure. The sidewall layer material includes: SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN.

[0061] Specifically, the gate opening 102 is formed by a sidewall layer, an isolation layer 105, and a fin 104.

[0062] It should be noted that the method for forming the semiconductor structure further includes: after providing the substrate 100, forming an interface layer (IL) 106 on the top wall and side wall of the fin 104 that exposes the isolation layer 105.

[0063] The interface layer 106 is used to ensure good interface performance between the fin 104 and the subsequently formed gate dielectric layer, thereby improving the formation quality of the gate dielectric layer.

[0064] In this embodiment, the interface layer 106 is formed by a chemical wetting oxidation process, and the material of the interface layer 106 is silicon oxide.

[0065] Continue to refer to Figure 7 and Figure 8 The method for forming the semiconductor structure includes: after providing the gate opening 102, forming a conformally conformally covering the gate opening 102 with a gate dielectric layer (not shown in the figure).

[0066] The gate dielectric layer is used to electrically isolate the fin 104 from the subsequently formed gate structure. It should be noted that the material of the gate dielectric layer is a high-k dielectric material. Here, a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0067] In this embodiment, the material of the gate dielectric layer is HfO2. In other embodiments, the material of the gate dielectric layer may also be selected from one or more of ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3.

[0068] In this embodiment, the gate dielectric layer is formed using atomic layer deposition (ALD). ALD allows for precise control of the gate dielectric layer thickness and provides excellent gap-filling and step coverage, enabling the gate dielectric layer to conformally cover the bottom and sidewalls of the gate opening 102. In other embodiments, the gate dielectric layer can also be formed using chemical vapor deposition (CVD).

[0069] The method for forming the semiconductor structure further includes: after forming the gate dielectric layer, forming a conformal capping layer 107 covering the gate opening 102.

[0070] The semiconductor formation method further includes: subsequently forming a work function layer on the capping layer 107. The capping layer 107 is formed between the gate dielectric layer and the work function layer. The capping layer 107 protects the gate dielectric layer, making it difficult for metal ions in the work function layer to diffuse into the gate dielectric layer; at the same time, the capping layer 107 also makes it difficult for oxygen ions in the gate dielectric layer to diffuse into the work function layer, thereby preventing the problem of increased oxygen vacancy content in the gate dielectric layer.

[0071] In this embodiment, the capping layer 107 is made of TiN. In other embodiments, the capping layer may also be made of TiSiN or TaN.

[0072] In this embodiment, the capping layer 107 is formed using atomic layer deposition (ALD). In other embodiments, the capping layer may also be formed using physical vapor deposition (PVD).

[0073] refer to Figures 9 to 12 , Figure 10 for Figure 9 Cross-sectional view at point AA Figure 12 for Figure 11 In the cross-sectional view at AA, a shielding layer 108 is formed that covers the gate opening 102 of the second region II and exposes the gate opening 102 of the first region I (e.g., Figure 11 and Figure 12 (As shown).

[0074] In the step of forming a first work function material layer conformally covering the gate opening 102 of the first region I by the shielding layer 108 occupying the gate opening 102 of the second region II, the first work function material layer is formed on the shielding layer 108. Compared with the case where the first work function material layer is formed in the gate opening of the second region, in this embodiment, the first work function material layer of the second region II is located on the shielding layer. Therefore, in the step of removing the first work function material layer of the second region II, the removal process window is larger, the first work function material layer of the second region II is less likely to remain, and because the removal process window is larger, the removal efficiency of the first work function material layer of the second region II is higher, which is beneficial to improving the yield. In addition, the bottom surface and sidewall of the gate opening are also more efficient. Compared to the case where a first work function material layer is formed and a shielding layer is formed on the first work function material layer, in this embodiment, the bottom and sidewalls of the shielding layer 108 do not form a first work function material layer occupying the space of the gate opening 102. In the step of removing the shielding layer 108, the removal process window of the shielding layer 108 is larger, and the shielding layer 108 is less likely to remain. Consequently, the second work function layer subsequently formed in the second region II is less likely to form on the first work function material layer and the shielding layer 108, thereby reducing the parasitic capacitance in the transistor of the second region II. Furthermore, because the second work function layer is less likely to form on the first work function material layer and the shielding layer 108, the second work function layer has better formation quality and can better adjust the threshold voltage of the transistor in the second region II, resulting in better electrical performance of the semiconductor structure.

[0075] In the step of forming the shielding layer 108, the shielding layer 108 is formed on the capping layer 107. Compared with the case where a first work function material layer is formed on the capping layer of the first region and the second region, and then the first work function material layer on the capping layer of the second region is removed, in the step of removing the shielding layer 108 on the capping layer 107 of the second region II in this embodiment of the invention, because the etching resistance of the shielding layer 108 is less than that of the capping layer 107, the capping layer 107 is less likely to be damaged in the step of removing the shielding layer 108. Therefore, the top of the capping layer 107 can be used as the removal stop position, so that the shielding layer 108 is less likely to remain.

[0076] In this embodiment, the material of the shielding layer 108 includes amorphous silicon. Amorphous silicon is an inorganic material, and the capping layer 107 is TiN. TiN is a metallic material, and amorphous silicon is less difficult to etch than metallic materials. In other embodiments, the shielding layer may also include silicon oxide or silicon nitride.

[0077] Specifically, the step of forming a shielding layer 108 that covers the gate opening 102 of the second region II and exposes the gate opening 102 of the first region I includes: as follows Figure 9 and Figure 10 As shown, a shielding material layer 109 is formed to cover the gate opening 102 of the first region I and the second region II; as Figure 11 and Figure 12 As shown, the shielding material layer 109 in the gate opening 102 of the first region I is removed, and the remaining shielding material layer 109 in the second region II serves as the shielding layer 108.

[0078] In this embodiment, the shielding material layer is formed using a chemical vapor deposition (CVD) process. The CVD process allows for control over the deposition thickness of the shielding material layer, resulting in a higher purity film. Consequently, the purity of the subsequently formed shielding layer is also higher, which is beneficial for the subsequent removal of the shielding layer 108.

[0079] The method for forming the semiconductor structure further includes: after forming the shielding material layer 109, and before removing the shielding material layer 109 from the gate opening 102 of the first region I, annealing the shielding material layer 109.

[0080] Specifically, the annealing process includes post cap annealing (PCA).

[0081] In this embodiment, the back cover annealing process is used to repair the interface layer 106, improve the density of the interface layer 106, thereby improving the quality and performance of the interface layer 106, and further improving the electrical performance and reliability of the formed semiconductor structure.

[0082] It should be noted that, in the step of forming the shielding material layer 109, the shielding material layer 109 covers not only the gate openings 102 of the first region I and the second region II, but also the remaining positions of the first region I and the second region II; in the step of removing the shielding material layer 109 from the gate opening 102 of the first region I, the shielding material layer 109 in the remaining areas of the first region I is also removed, and the formed shielding layer 108 covers the entire second region II.

[0083] In this embodiment, a dry etching process is used to remove the shielding material layer 109 in the gate opening 102 of the first region I. The remaining shielding material layer 109 in the second region II serves as the shielding layer 108. The dry etching process has anisotropic etching characteristics, good control over the etching profile, and can achieve fairly accurate pattern transformation. This is beneficial for ensuring that the morphology of the shielding layer 108 meets process requirements. Furthermore, in the step of removing the shielding material layer 109 in the first region I using the dry etching process, the top of the capping layer 107 can be used as the removal stop position, reducing damage to the bottom gate dielectric layer. Subsequently, a second work function layer is formed in the second region II. The gate dielectric layer and the interface layer 106 can better electrically isolate the fin 104 from the second work function layer, which is beneficial for improving the electrical performance of the semiconductor structure.

[0084] In this embodiment, during the step of forming the shielding layer 108, the top of the shielding layer 108 is higher than the top of the interlayer dielectric layer 101. Thus, during the formation of the shielding layer 108, the gate opening 102 of the second region II is completely covered by the shielding layer 108, making the gate opening 102 of the second region II less susceptible to damage and its morphology less prone to change. This results in higher uniformity of the second work function layer subsequently formed in the gate opening 102 of the second region II, which is beneficial for improving the uniformity of semiconductor structure performance.

[0085] refer to Figure 13 and Figure 14 , Figure 14 for Figure 13 In the cross-sectional view at AA, a first work function material layer 110 is formed that conformally covers the gate opening 102 of the first region I and the shielding layer 108.

[0086] The first work function material layer 110 prepares for the subsequent formation of the first work function layer.

[0087] In this embodiment, the first region I is used to form a PMOS, and correspondingly, the material of the first work function material layer 110 includes one or more of titanium nitride, tantalum nitride, titanium carbide, silicon nitride, titanium silicon nitride, and tantalum carbide.

[0088] In this embodiment, the first work function material layer 110 is formed using atomic layer deposition (ALD). ALD has good step coverage capabilities. In other embodiments, the first work function material layer can also be formed using physical vapor deposition (PVD).

[0089] refer to Figures 15 to 18 , Figure 16 for Figure 15 Cross-sectional view at point AA Figure 18 for Figure 17 In the cross-sectional view at AA, the shielding layer 108 and the first work function material layer 110 located on the shielding layer 108 are removed, and the remaining first work function material layer 110 located in the gate opening 102 of the first region I is used as the first work function layer 111.

[0090] Compared to the case where the first work function material layer is formed in the gate opening of the second region, in this embodiment, the removal process window for the first work function material layer 110 in the second region II is larger. Therefore, during the removal of the first work function material layer 110 in the second region II, residues of the first work function material layer 110 in the second region II are less likely to remain. Furthermore, because the removal process window is larger, the removal efficiency of the first work function material layer 110 in the second region II is higher, which is beneficial for increasing yield. In addition, compared to the case where the first work function material layer is formed on the bottom surface and sidewalls of the gate opening, and a shielding layer is formed on the first work function material layer, in this embodiment, the shielding layer 108... In the step of removing the shielding layer 108, since the first work function material layer 110 occupying the space of the gate opening 102 is not formed on the bottom and sidewalls, the removal process window of the shielding layer 108 is relatively large, and the shielding layer 108 is less likely to remain. Consequently, the second work function layer subsequently formed in the second region II is less likely to form on the first work function material layer 110 and the shielding layer 108, thereby reducing the parasitic capacitance in the transistor of the second region II. Furthermore, because the second work function layer is less likely to form on the first work function material layer 110 and the shielding layer 108, the second work function layer has better formation quality and can better adjust the threshold voltage of the transistor in the second region II, resulting in better electrical performance of the semiconductor structure.

[0091] When the semiconductor structure is in operation, the first work function layer 111 is used to adjust the threshold voltage of the first type transistor.

[0092] Specifically, the steps of removing the shielding layer 108 and the first work function material layer 110 located on the shielding layer 108 include:

[0093] like Figure 15 and Figure 16 As shown, a mask layer 112 is formed on the first work function material layer 110, covering the first region I and exposing the second region II.

[0094] In this embodiment, the material of the mask layer 112 includes an organic material layer (not shown in the figure), an anti-reflective coating (not shown in the figure) on the organic material layer, and a photoresist layer (not shown in the figure) on the anti-reflective coating.

[0095] In this embodiment, the organic material layer includes one or more of the following: ODL (organic dielectric layer), DUO (Deep UV Light Absorbing Oxide), and APF (Advanced Patterning Film).

[0096] Materials used for anti-reflective coatings include DARC (dielectric anti-reflective coating) or BARC (bottom anti-reflective coating).

[0097] like Figure 17 and Figure 18 As shown, the masking layer 108 and the first work function material layer 110 located on the masking layer 108 are removed using the masking layer 112 as a mask.

[0098] In this embodiment, the masking layer 108 and the first work function material layer 110 located on the masking layer 108 are removed using a dry etching process with the masking layer 112 as a mask. The dry etching process has anisotropic etching characteristics and good control over the etching profile. While removing the masking layer 108 and the first work function material layer 110 in the second region II, the first work function material layer 110 covered by the masking layer 112 is less likely to be damaged. Furthermore, by using the dry etching process, the masking layer 108 and the first work function material layer 110 can be etched in the same etching equipment by changing the etching gas.

[0099] Furthermore, in the steps of using the dry etching process for the shielding layer 108 and the first work function material layer 110 located on the shielding layer 108, the etching resistance of the capping layer 107 is greater than that of the shielding layer 108, so that the top of the capping layer 107 can be used as the removal stop position, making it less likely that there will be residue in the shielding layer 108.

[0100] It should also be noted that using the mask layer 112 as a mask and employing a dry etching process to remove the mask layer 108 and the first work function material layer 110 located on the mask layer 108 can remove the mask layer 108 and form the first work function layer 111 in one step, which is beneficial to simplifying the semiconductor structure formation process.

[0101] The method for forming the semiconductor structure further includes: after forming the first work function layer 111, removing the mask layer 112.

[0102] Remove the mask layer 112 so that the organic material layer in the mask layer 112 is less likely to contaminate the machine.

[0103] In this embodiment, the mask layer 112 is removed using an ashing process.

[0104] refer to Figure 19 and Figure 20 , Figure 20 for Figure 19 In the cross-sectional view at AA, a second work function layer 113 is formed that conformally covers the gate opening 102 of the second region II.

[0105] The shielding layer 108 and the first work function material layer 110 are less likely to have residues, and thus the second work function layer 113 of the second region II is less likely to be formed on the first work function material layer 110 and the shielding layer 108. The second work function layer 113 has better formation quality. The second work function layer 113 located in the gate opening 102 can better adjust the threshold voltage of the transistor in the second region II, reduce the parasitic capacitance in the transistor in the second region II, and make the electrical performance of the semiconductor structure better.

[0106] The second work function layer 113 is used to adjust the threshold voltage of the second type transistor.

[0107] In this embodiment, the second type transistor is an NMOS, and correspondingly, the material of the second work function layer 113 includes one or more of titanium aluminide, tantalum carbide, aluminum, and titanium carbide.

[0108] In this embodiment, atomic layer deposition (ALD) is used to form the second work function layer 113. ALD has good step coverage capabilities, which helps to improve the formation quality of the second work function layer 113. In other embodiments, physical vapor deposition (PVD) can also be used to form the second work function layer.

[0109] It should be noted that during the process of forming the second work function layer 113 of the gate opening 102 in the second region II, the second work function layer 113 is also formed on the first work function layer 111 of the first region I.

[0110] When the semiconductor structure is working, in the first region I, the second work function layer 113 is far away from the channel. Therefore, the second work function layer 113 is less likely to interfere with the regulation of the threshold voltage of the first type transistor by the first work function layer 111.

[0111] Continue to refer to Figure 19 and Figure 20 After forming the second work function layer 113, a gate layer 114 is formed in the gate opening 102, and the first work function layer 111, the second work function layer 113 and the gate layer 114 are used as the gate structure.

[0112] When a semiconductor structure is in operation, the gate structure is used to control the opening and closing of the channel.

[0113] The steps of forming the gate layer 114 include: forming a conductive material layer (not shown in the figure) on the second work function layer 113; planarizing the conductive material layer, and using the remaining conductive material layer as the gate layer 114.

[0114] In this embodiment, the material of the gate layer 114 includes W.

[0115] In this embodiment, the conductive material layer is formed using an electrochemical plating (ECP) process. Electrochemical plating offers advantages such as simple operation, fast deposition rate, and low cost.

[0116] In this embodiment, the planarization process includes chemical mechanical planarization (CMP). CMP is a global surface planarization technique that gives the top surface of the gate layer 114 a high degree of flatness.

[0117] It should be noted that the method for forming the semiconductor structure further includes: after forming the second work function layer 113 and before forming the gate layer, forming a barrier layer (not shown in the figure) on the second work function layer 113.

[0118] Subsequently, a gate layer is formed on the barrier layer. The barrier layer makes it difficult for ions in the gate layer to diffuse to the source / drain structure below the barrier layer. When the semiconductor structure is working, the source / drain structure can provide greater stress for communication, thereby increasing the migration rate of charge carriers in the channel. The barrier layer also makes it difficult for ions in the gate layer to diffuse to the first work function layer 111 and the second work function layer 113, enabling the first work function layer 111 and the second work function layer 113 to better regulate the threshold voltage.

[0119] In this embodiment, the barrier layer is made of TaN. In other embodiments, the barrier layer can be made of one or more of Ta, Ti, TiN, ZrN, and ZrTiN.

[0120] In this embodiment, atomic layer deposition (ALD) is used to form the barrier layer. In other embodiments, physical vapor deposition (PVD) or chemical vapor deposition (CVD) can also be used to form the barrier layer.

[0121] Accordingly, during the formation of the gate layer 114, the gate layer 114 is formed on the barrier layer.

[0122] It should be noted that, as the pitch between adjacent fins 104 decreases, in this embodiment, the area between adjacent fins 104 in the first region I is filled by the second work function layer 113, and the corresponding barrier layer and gate layer 114 are located above the fins in the first region I. In other embodiments, when the area between adjacent fins is large, a barrier layer may also be formed between adjacent fins, and the gate layer is formed above the fins. In other embodiments, when the area between fins is large enough, a barrier layer and a gate layer may be formed in the area between the fins.

[0123] It should be noted that as the pitch between adjacent fins 104 decreases, the size of the gate opening 102 correspondingly decreases in the extending direction of the fins 104. In this embodiment, a second work function layer 113, a barrier layer, and a gate layer 114 are formed in the gate opening 102. In other embodiments, when the size of the gate opening is small in the extending direction of the fins, only the second work function layer and the barrier layer may be formed in the gate opening. In still other embodiments, when the size of the gate opening is sufficiently small in the extending direction of the fins, only the second work function layer may be formed in the gate opening.

[0124] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region and a second region, an interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer having a gate opening exposing a portion of the substrate; A shielding layer is formed that covers the gate opening in the second region and exposes the gate opening in the first region; A first work function material layer is formed to conformally cover the gate opening in the first region and the shielding layer. Remove the shielding layer and the first work function material layer located on the shielding layer, and the remaining first work function material layer located in the gate opening of the first region is used as the first work function layer; A second work function layer is formed to conformally cover the gate opening of the second region. In the process of forming the second work function layer of the gate opening of the second region, the second work function layer is also formed on the first work function layer of the first region and on the interlayer dielectric layer. After the second work function layer is formed, a gate layer is formed in the gate opening. The gate layer is formed on the interlayer dielectric layer, and the first work function layer, the second work function layer and the gate layer are used as the gate structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the shielding layer includes: amorphous silicon, silicon oxide, or silicon nitride.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming a shielding layer that covers the gate opening in the second region and exposes the gate opening in the first region includes: A shielding material layer is formed to cover the gate openings of the first and second regions; The shielding material layer in the gate opening of the first region is removed, and the remaining shielding material layer in the second region serves as the shielding layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the semiconductor structure further includes: after forming the shielding material layer, and before removing the shielding material layer from the gate opening in the first region, annealing the shielding material layer.

5. The method for forming a semiconductor structure as described in claim 3, characterized in that, The shielding material layer is formed using a chemical vapor deposition process.

6. The method for forming a semiconductor structure as described in claim 3, characterized in that, The shielding material layer in the gate opening of the first region is removed by a dry etching process, and the remaining shielding material layer in the second region serves as a shielding layer.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after providing the gate opening and before forming the shielding layer, forming a conformal capping layer covering the gate opening; In the step of forming the shielding layer, the shielding layer is formed on the capping layer; In the step of removing the shielding layer and the first work function material layer located on the shielding layer, the etching resistance of the capping layer is greater than that of the shielding layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the capping layer includes one or more of TiN, TiSiN, and TaN.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The capping layer is formed using atomic layer deposition or physical vapor deposition.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of removing the shielding layer and the first work function material layer located on the shielding layer include: A mask layer is formed on the first work function material layer, covering the first region and exposing the second region; Using the mask layer as a mask, the shielding layer and the first work function material layer located on the shielding layer are removed; The method for forming the semiconductor structure further includes: after forming the first work function layer, removing the mask layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The mask layer comprises an organic material layer, an anti-reflective coating on the organic material layer, and a photoresist layer on the anti-reflective coating.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, Using the mask layer as a mask, a dry etching process is employed to remove the masking layer and the first work function material layer located on the masking layer.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure includes: after providing the gate opening and before forming the shielding layer, forming a conformally conformal gate dielectric layer covering the gate opening.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first work function material layer is formed using atomic layer deposition (ALD).

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The second work function layer is formed using atomic layer deposition (ALD).

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: forming a barrier layer on the second work function layer after forming the second work function layer and before forming the gate layer; In the step of forming the gate layer, the gate layer is formed on the barrier layer.

17. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate includes a substrate, fins disposed on the substrate, and an isolation layer covering a portion of the sidewalls of the fins; The gate opening is formed by an interlayer dielectric layer, an isolation layer, and a fin.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The method for forming the semiconductor structure includes: after providing a substrate and before forming the shielding layer, forming an interface layer on the top and sidewalls of the fin that exposes the isolation layer.

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