A storage device, a storage control device, and a system on chip

Abstract

The application provides a storage device, a storage control device and a system on chip. The storage device comprises: a first memory configured to store data; a second memory configured to store an error correction code corresponding to the data, the error correction code being used for data protection of the data; and a storage controller configured to write the data to the first memory and read the data from the first memory; wherein the first memory and the second memory belong to different dies. In the application, since the first memory and the second memory belong to different dies, the error correction code is prevented from occupying storage space in the first memory, and the capacity of available data in the first memory is improved.

Description

Technical Field

[0001] This application relates to the field of storage, and in particular to a storage device, a storage control device, and a system-on-a-chip. Background Technology

[0002] With the development of technology, dynamic random access memory (DRAM) chips are becoming larger and operating at higher frequencies. During operation, DRAM chips may experience varying degrees of localized soft failures. To avoid data read / write errors caused by soft failures, DRAM chips employ error checking and correction techniques to protect the data from soft failures.

[0003] Currently, DRAM data protection technology typically involves configuring dedicated error-correcting code (ECC) storage partitions within the DRAM chip, with these partitions generally evenly distributed around the DRAM chip. However, because ECC storage partitions occupy storage space within the DRAM chip, the amount of usable data within the DRAM chip is relatively small. Summary of the Invention

[0004] This application provides a storage device, a storage control device, and a system-on-a-chip to avoid error correction codes occupying storage space in a first memory and to increase the capacity of available data in the first memory.

[0005] In a first aspect, this application provides a storage device, comprising: a first memory configured to store data; a second memory configured to store error correction codes corresponding to the data, the error correction codes being used for data protection; and a storage controller configured to: write data to the first memory; and read data from the first memory; wherein the first memory and the second memory belong to different dies.

[0006] The storage controller and the first memory are coupled via address lines and data lines (including write data lines and read data lines). The storage controller can be configured to write first data to the first memory via address lines and write data lines or to read second data from the first memory via address lines and read data lines.

[0007] For example, the first memory may be DRAM. The first memory may include one or more DRAM dies, such as multiple DRAM dies stacked in 3D. Optionally, the first memory may also be a static random-access memory (SRAM), non-volatile memory (NVM), or other memory based on 3D stacking.

[0008] For example, the second memory may be SRAM. The second memory may include one or more SRAM dies.

[0009] In this application, by integrating the first memory and the second memory onto different dies, the error correction code is stored in the second memory. That is, the storage area for the error correction code is concentrated in the second memory, separate from the first memory. This avoids the error correction code occupying storage space in the first memory, thereby increasing the capacity of available data in the first memory. For example, in a DRAM scenario, the error correction code is stored in the second memory (such as SRAM). Since the second memory and the first memory (such as DRAM) belong to different dies, there is no need to allocate a storage area for the error correction code in the DRAM die, thus avoiding the error correction code occupying storage space in the DRAM die and further increasing the capacity of available data on the DRAM die.

[0010] Furthermore, in existing technologies, the error correction code storage partition and the data storage partition are located in the same die, and the error correction code can only protect data on the same die. However, in this application, since the data storage partition is located in the first memory and the error correction code storage partition is located in the second memory, and the second memory and the first memory belong to different dies, the error correction code in the second memory can protect data in one or more first memories, thereby enabling multiple first memories to share one second memory, which can also be understood as achieving global sharing of error correction codes.

[0011] Furthermore, in existing technologies, since the soft failure of the first memory is related to the actual application scenario, it is impossible to predict which data storage partitions have a high probability of soft failure. Therefore, error correction code storage partitions must be configured for all data storage partitions. However, this is wasteful for data storage partitions that do not experience soft failures, or for application scenarios that are not sensitive to data soft failures (high fault tolerance). In this application, since the data storage partitions are located in the first memory and the error correction code storage partitions are located in the second memory, which belongs to different dies from the first memory, the storage partitions of the second memory can be flexibly allocated to the storage partitions of the first memory that actually require data protection, instead of all data storage partitions being allocated error correction code storage partitions. This saves error correction code storage resources, thereby enabling flexible adjustment of the data protection area according to actual needs and working status, and thus improving the utilization rate of error correction code storage resources.

[0012] In some possible implementations, the data includes first data and second data. The storage device further includes: an error checking and correction (ECC) circuit configured to: generate a first error correction code corresponding to the first data; and correct the second data according to a second error correction code in a second memory; the second error correction code is the error correction code corresponding to the second data; and a storage controller specifically configured to: write the first data to the first memory and read the second data from the first memory.

[0013] In some possible implementations, the ECC circuit is further configured to: generate a first error correction code when it is determined that the first data is data that needs to be protected; and correct the second data according to the second error correction code when it is determined that the second data is data that needs to be protected.

[0014] In some possible implementations, the ECC circuit is also configured to: when it is determined that the first data is data that does not need to be protected, write the first data to the first storage partition according to the first address.

[0015] In some possible implementations, the ECC circuit is also configured to output the second data to the memory controller based on the second address when it is determined that the second data is data that does not need to be protected.

[0016] In this application, when the ECC circuit determines that the first data and the second data are data that need to be protected, it performs ECC operations (such as generating error correction codes) on the first data and the second data. In this way, selective ECC operations are performed on the data, which improves the utilization rate of error correction code storage resources while ensuring effective data protection.

[0017] In some possible implementations, the ECC circuit is configured to determine whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information; and to determine whether the second data is data that needs to be protected based on the second address corresponding to the second data and protection configuration information; wherein the protection configuration information includes a mapping relationship between storage partitions in the first memory and storage partitions in the second memory, and the storage partitions in the second memory correspond to the data that needs to be protected.

[0018] In this application, configurable protection configuration information can be set. By configuring this protection configuration information, the mapping relationship between storage partitions in the first memory and storage partitions in the second memory can be changed. This allows storage partitions in the second memory to be flexibly allocated to storage partitions in the first memory that need protection, rather than being fixed to correspond to all data storage partitions. Thus, for data storage partitions with low access volume, corresponding error correction code storage resources do not need to be configured, saving error correction code storage resources. This allows for adjusting the area used for data protection according to actual needs and operating status, thereby improving the utilization rate of error correction code storage resources.

[0019] In some possible implementations, the memory controller is configured to output a first address and first data to the ECC circuit; the ECC circuit is further configured to: write a first error correction code into a second memory; and write the first data into a first memory partition of the first memory according to the first address.

[0020] In some possible implementations, the ECC circuit is also configured to: when it is determined that the first data is data that does not need to be protected, obtain the third address corresponding to the first address; and write the first error correction code into the second storage partition in the second memory according to the third address, thereby realizing the protection of the first data.

[0021] In some possible implementations, the ECC circuit is also configured to: when it is determined that the second data is data that needs to be protected, obtain the fourth address corresponding to the second address; and read the second error correction code from the fourth storage partition in the second memory according to the fourth address, thereby realizing the protection of the second data.

[0022] In some possible implementations, the memory controller is further configured to output a second address to the ECC circuit; the ECC circuit is further configured to: read second data from a third memory partition of the first memory according to the second address; and output the second data to the memory controller.

[0023] In some possible implementations, the ECC circuit is configured to: check the second data according to the second error correction code; if an error is detected, correct the second data and output the corrected second data to the storage controller; if no error is detected, output the second data to the storage controller.

[0024] In this application, when the ECC circuit determines that the first data and the second data are data that need to be protected, it performs ECC operations (such as error correction according to the error correction code) on the first data and the second data. In this way, selective ECC operations are performed on the data, which improves the utilization rate of error correction code storage resources while ensuring effective data protection.

[0025] In some possible implementations, the ECC circuit is configured to output the second data to the storage controller when it is determined that the second data is data that does not need to be protected.

[0026] In some possible implementations, the ECC circuit and the second memory belong to the same die; or, the ECC circuit and the second memory belong to different dies.

[0027] In some possible implementations, the ECC circuitry and the memory controller are on different dies; or, the ECC circuitry and the memory controller are on the same die.

[0028] In some possible implementations, the low-order addresses of each memory partition in the first memory are the same as the memory addresses of each memory partition in the second memory.

[0029] Secondly, this application provides a storage control device, which may include: a storage controller and an ECC circuit; wherein the storage controller is configured to write first data to a first memory and read second data from the first memory; the ECC circuit is configured to: generate a first error correction code when it is determined that the first data is data that needs to be protected; and correct the second data according to the second error correction code when it is determined that the second data is data that needs to be protected.

[0030] In this application, when the ECC circuit determines that the first data and the second data are data that need to be protected, it performs ECC operations on the first data and the second data (such as generating error correction codes, performing error correction based on the error correction codes, etc.). In this way, selective ECC operations are performed on the data, which improves the utilization rate of error correction code storage resources while ensuring effective data protection.

[0031] In some possible implementations, the ECC circuit is configured to determine whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information; and to determine whether the second data is data that needs to be protected based on the second address corresponding to the second data and protection configuration information; wherein the protection configuration information includes a mapping relationship between the addresses of storage partitions in the first memory and the addresses of storage partitions in the second memory, and the storage partitions of the second memory correspond to the data that needs to be protected.

[0032] In some possible implementations, the memory controller is configured to output a first address and first data to the ECC circuit; the ECC circuit is further configured to: write a first error correction code into a second memory; and write the first data into a first memory partition of the first memory according to the first address.

[0033] In some possible implementations, the ECC circuit is also configured to: when it is determined that the first data is data that needs to be protected, obtain the third address corresponding to the first address; and write the first error correction code into the second storage partition in the second memory according to the third address.

[0034] In some possible implementations, the ECC circuit is also configured to: when it is determined that the first data is data that does not need to be protected, write the first data to the first storage partition according to the first address.

[0035] In some possible implementations, the memory controller is further configured to output a second address to the ECC circuit; the ECC circuit is further configured to: read second data from a third memory partition of the first memory according to the second address; and output the second data to the memory controller.

[0036] In some possible implementations, the ECC circuit is configured to: check the second data according to the second error correction code; if an error is detected, correct the second data and output the corrected second data to the storage controller; if no error is detected, output the second data to the storage controller.

[0037] In some possible implementations, the ECC circuit is also configured to: when it is determined that the second data is data that needs to be protected, obtain the fourth address corresponding to the second address; and read the second error correction code from the fourth storage partition in the second memory according to the fourth address.

[0038] In some possible implementations, the ECC circuit is configured to output the second data to the storage controller when it is determined that the second data is data that does not need to be protected.

[0039] In some possible implementations, the ECC circuit and the second memory belong to the same die; or, the ECC circuit and the second memory belong to different dies.

[0040] In some possible implementations, the ECC circuitry and the memory controller are on different dies; or, the ECC circuitry and the memory controller are on the same die.

[0041] Thirdly, this application provides a system-on-a-chip, including: a processor, a bus, and a storage device according to any one of the first aspects and its possible embodiments;

[0042] The processor is configured to: output a write instruction and first data to a storage device via a bus, or output a read instruction to a storage device via a bus, and receive second data output by the storage device via a bus; the write instruction is used to instruct the writing of first data to a first storage area, and the read instruction is used to instruct the reading of second data from a second storage area.

[0043] Fourthly, this application provides a data storage method that can be applied to the storage device described in any one of the first aspects and its possible embodiments. The method may include: a storage controller writing data to a first memory and reading data from the first memory, wherein the first memory and a second memory are on different dies, and the second memory is used to store error correction codes corresponding to the data, the error correction codes being used for data protection.

[0044] In some possible implementations, the data includes first data and second data; the above-mentioned storage controller writing data to the first memory includes: the storage controller writing the first data to the first memory;

[0045] The memory controller reads data from the first memory, including: the memory controller reads second data from the first memory.

[0046] Accordingly, the above method further includes: the ECC circuit generating a first error correction code corresponding to the first data; or, the ECC circuit correcting the second data according to the second error correction code in the second memory, wherein the second error correction code is the error correction code corresponding to the second data.

[0047] In some possible implementations, the above-mentioned ECC circuit generates a first error correction code corresponding to the first data, including: when it is determined that the first data is data that needs to be protected, the ECC circuit generates a first error correction code;

[0048] The aforementioned ECC circuit corrects the second data according to the second error correction code in the second memory, including: when it is determined that the second data is data that needs to be protected, the ECC circuit corrects the second data according to the second error correction code.

[0049] In some possible implementations, the above method further includes: the ECC circuit determining whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information; or, the ECC circuit determining whether the second data is data that needs to be protected based on the second address corresponding to the second data and protection configuration information; wherein, the protection configuration information includes the mapping relationship between the address of the storage partition in the first memory and the address of the storage partition in the second memory, and the storage partition of the second memory corresponds to the data that needs to be protected.

[0050] In some possible implementations, the above-mentioned storage controller writes first data to the first memory, including: the storage controller outputs a first address and first data to the ECC circuit; the ECC circuit writes the first data to the first storage partition of the first memory according to the first address.

[0051] In some possible implementations, after the ECC circuit generates the first error correction code, the method further includes: the ECC circuit obtaining the third address corresponding to the first address; and writing the first error correction code into the second storage partition in the second memory according to the third address.

[0052] In some possible implementations, the above method further includes: when it is determined that the first data is data that does not need to be protected, the ECC circuit writes the first data into the first memory.

[0053] In some possible implementations, the above-mentioned storage controller reads second data from the first memory, including: the storage controller outputs a second address to the ECC circuit; the ECC circuit reads the second data from a third storage partition of the first memory according to the second address; and the ECC circuit outputs the second data to the storage controller.

[0054] In some possible implementations, the above-mentioned ECC circuit outputs second data to the storage controller, including: the ECC circuit checks the second data according to the second error correction code; if an error is detected, the second data is corrected and the corrected second data is output to the storage controller; if no error is detected, the second data is output to the storage controller.

[0055] In some possible implementations, when the second data is determined to be data that needs to be protected, the above method further includes: the ECC circuit obtaining the fourth address corresponding to the second address; and reading the second error correction code from the fourth storage partition in the second memory according to the fourth address.

[0056] In some possible implementations, the method further includes: when it is determined that the second data is data that does not need to be protected, the ECC circuit outputs the second data to the storage controller.

[0057] Fifthly, this application provides a data storage method that can be applied to the storage control device described in any one of the second aspects and its possible embodiments above. The method may include:

[0058] The storage control device writes first data to the first memory and reads second data from the first memory;

[0059] When the first data is determined to be data requiring protection, the storage control device generates a first error correction code; and

[0060] When the second data is determined to be data that needs to be protected, the storage control device corrects the second data according to the second error correction code.

[0061] In some possible implementations, the above method further includes: the storage control device determining whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information; and,

[0062] The storage control device determines whether the second data is data that needs to be protected based on the second address corresponding to the second data and the protection configuration information.

[0063] The protection configuration information includes the mapping relationship between the addresses of storage partitions in the first memory and the addresses of storage partitions in the second memory, with the storage partitions in the second memory corresponding to the data being protected.

[0064] In some possible implementations, the above-mentioned storage control device writes first data to the first memory, including: the storage control device writes the first data to a first storage partition of the first memory according to a first address.

[0065] In some possible implementations, after the storage control device generates the first error correction code, the method further includes: the storage control device obtaining a third address corresponding to the first address; and writing the first error correction code into a second storage partition in the second memory according to the third address.

[0066] In some possible implementations, the method further includes: when it is determined that the first data is data that does not need to be protected, the storage control device writes the first data into the first memory.

[0067] In some possible implementations, the above-described storage control device reads second data from the first memory, including: the storage controller reads the second data from a third storage partition of the first memory according to a second address.

[0068] In some possible implementations, the storage control device reads the second data from the first memory, including: the storage control device checks the second data according to a second error correction code; if an error is detected, the storage control device corrects the second data and obtains the corrected second data; if no error is detected, the storage control device obtains the second data.

[0069] In some possible implementations, before the storage control device corrects the second data, the method further includes: when it is determined that the second data is data that needs to be protected, the storage control device obtains a fourth address corresponding to the second address; the storage control device reads the second error correction code from the fourth storage partition in the second memory according to the fourth address.

[0070] In some possible implementations, the method further includes: when it is determined that the second data is data that does not need to be protected, the storage control device reads the second data.

[0071] In a sixth aspect, this application provides an electronic device comprising: a processor, a bus, and a storage device as described in the first aspect and any possible embodiments thereof, wherein the processor is coupled to the storage device via the bus.

[0072] In some possible implementations, the processor described above may include a system-on-a-chip as described in the third aspect.

[0073] In some possible implementations, the aforementioned storage device is also used to store program instructions. The aforementioned processor is configured to execute the program instructions stored in the storage device when the electronic device is running, so that the electronic device performs the corresponding functions.

[0074] In some possible implementations, the electronic device further includes an input device and an output device. The input device is used to input commands and information into the electronic device, and is connected to the processor via a bus. The output device is used to output information to the electronic device, and can also be connected to the processor via a bus.

[0075] In some possible implementations, the above-mentioned electronic device further includes an antenna system that, under the control of a processor, transmits and receives wireless communication signals to achieve wireless communication with a mobile communication network.

[0076] It should be understood that the second to sixth aspects of this application are consistent with the technical solutions of the first aspect of this application, and the beneficial effects achieved by each aspect and the corresponding feasible implementation are similar, so they will not be described again. Attached Figure Description

[0077] Figure 1 This is a schematic diagram of the DRAM chip in an embodiment of this application;

[0078] Figure 2 This is a schematic diagram of the protection configuration information in the embodiments of this application;

[0079] Figure 3 This is a schematic diagram of the structure of a storage device according to an embodiment of this application;

[0080] Figure 4 This is a schematic diagram of the data writing process of the storage device in the embodiments of this application;

[0081] Figure 5 This is a schematic diagram of the data reading process of the storage device in the embodiments of this application;

[0082] Figure 6 This is a schematic diagram of the ECC circuit in the embodiments of this application;

[0083] Figure 7 This is a schematic diagram of the ECC circuit in the data writing process in the embodiments of this application;

[0084] Figure 8 This is a schematic diagram of the ECC circuit in the data reading process in the embodiments of this application;

[0085] Figure 9 This is another schematic diagram of the structure of the storage device in the embodiments of this application;

[0086] Figure 10 This is a schematic diagram of a first type of packaging for a storage device in an embodiment of this application;

[0087] Figure 11 This is a schematic diagram of a second type of packaging for the storage device in an embodiment of this application.

[0088] Figure 12 This is a schematic diagram of a third type of packaging for the storage device in the embodiments of this application;

[0089] Figure 13 This is a schematic diagram of a fourth type of packaging for the storage device in the embodiments of this application;

[0090] Figure 14 This is a schematic diagram of the fifth type of packaging for the storage device in the embodiments of this application;

[0091] Figure 15 This is a hardware schematic diagram of the electronic device in the embodiments of this application. Detailed Implementation

[0092] The embodiments of this application will now be described with reference to the accompanying drawings. In this description, reference is made to the accompanying drawings, which form part of this application and illustrate specific aspects of the embodiments of this application or which may be used to illustrate specific aspects of the embodiments of this application.

[0093] Dynamic random access memory (DRAM) is a type of high-capacity, high-density semiconductor memory. As DRAM chips become larger and operate at higher frequencies, during operation, electromagnetic interference within the electronic device can cause individual cells in the DRAM chip to spontaneously reverse their state (a soft data failure). This cell error may be implicit, meaning it doesn't severely affect the data; however, since the various memory banks within a DRAM chip are interconnected, cell errors can lead to data read / write errors, potentially affecting the entire electronic device. Therefore, to avoid data read / write errors caused by cell errors, DRAM chips typically employ error checking and correction (ECC) techniques to correct soft data failures.

[0094] ECC (Error Correction Control) technology is a data protection method whose main function is to detect and correct errors. ECC requires an additional storage partition to store error correction codes, but the number of bits occupied by the error correction code is not linearly related to the data length. Specifically, ECC technology is based on 8 bits of data and 5 bits of error correction code; each additional 8 bits of data requires only one more bit of error correction code. For example, the error correction code generated from 8 bits of data occupies 5 bits of space, while the error correction code for 16 bits of data only requires adding one more bit to the space occupied by the 8-bit error correction code, making it 6 bits; and for 32 bits of data, it only requires adding one more bit to the space occupied by the 16-bit error correction code, making it 7 bits, and so on. The error correction code generated from K = 2n bits of data occupies (n+2) bits of space. When K = 64, n = 6, then n+2 = 8. Therefore, a separate ECC storage partition is typically configured in the DRAM chip, and the address of the ECC storage partition is the same as the address of the DRAM storage partition.

[0095] Figure 1 This is a schematic diagram of an example structure of a DRAM chip in an embodiment of this application. See also... Figure 1 As shown, the DRAM chip 100 may include: a DRAM controller 101, an ECC circuit 102, a DRAM storage partition 103, and an ECC storage partition 104. The DRAM storage partition 103 and the ECC storage partition 104 may be deployed in a ratio such as data:error correction code (which can be understood as the ratio of data length to error correction code bit width) = 8:1.

[0096] Specifically, the DRAM controller 101 is coupled to the DRAM storage partition 103 via address line A, and the DRAM controller 101 is coupled to the ECC circuit 102 via data lines (including write data line W and read data line R). The ECC circuit 102 is coupled to the DRAM storage partition 103 and the ECC storage partition 104 via data lines (including write data line W and read data line R).

[0097] The aforementioned ECC circuit 102 may include an ECC generation module 1021 and an ECC checking module 1022. The ECC generation module 1021 is configured to generate error correction codes corresponding to the data, and the ECC checking module 1022 is configured to check the error correction codes to be corrected, and correct the error correction codes according to the error correction codes when a 1-bit error is detected.

[0098] In actual packaging, the DRAM chip 100 may include: a logic die / basic die 111 and at least one DRAM die 112. The aforementioned DRAM controller 101 and ECC circuitry 102 may be integrated into the logic die 111, and the aforementioned DRAM memory partition 103 and ECC memory partition 104 may be integrated into a single DRAM die 112. The logic die 111 and each DRAM die 112 may be individually packaged, or the logic die 111 and DRAM die 112 may be a combined package of 2.5D (2.5-dimensional) stacked or 3D (3-dimensional) stacked components. Of course, the logic die and DRAM die may also have other implementations, which are not specifically limited in this embodiment.

[0099] Still referencing Figure 1 As shown, the data read / write process of the DRAM chip 100 can be described as follows:

[0100] First, the data writing process may include the following steps:

[0101] Step 1: The DRAM controller 101 receives a write command from the user side and outputs the write operation command and write address to the DRAM die 112 via address line A;

[0102] Step 2: The DRAM controller 101 outputs write data to the ECC circuit 102 via the write data line W;

[0103] Step 3: ECC circuit 102 generates the corresponding error correction code for the written data;

[0104] Step 4: ECC circuit 102 outputs the write data and the corresponding error correction code to DRAM die 112 through the write data line W;

[0105] Specifically, write data is output to DRAM storage partition 103, and error correction code is output to ECC storage partition 104.

[0106] In practical applications, DRAM chips can use 64 bits of data to generate 8 bits of error correction codes.

[0107] Step 5: DRAMdie112 responds to the write operation command, writes the write data to DRAM storage partition 103 according to the write address, and writes the error correction code to ECC storage partition 104 according to the write address.

[0108] Secondly, the data reading process may include the following steps:

[0109] Step 1: The DRAM controller 101 receives a read command from the user side and outputs the read operation command and read address to the DRAM die 112 via address line A;

[0110] Step 2: DRAMdie112 responds to the read operation command and reads the read data and the corresponding error correction code from DRAM storage partition 103 and ECC storage partition 104 respectively according to the read address;

[0111] Step 3: DRAMdie112 outputs the read data and the corresponding error correction code to ECC circuit 102 through the read data line R;

[0112] Step 4: ECC circuit 102 checks the read data;

[0113] Step 5: If the ECC circuit 102 detects a 1-bit error, the ECC circuit 102 corrects the read data according to the error correction code and outputs the corrected read data to the DRAM controller 101 through the read data line R; if the ECC circuit 102 does not detect an error, the ECC circuit 102 outputs the read data to the DRAM controller 101 through the read data line R.

[0114] Step 6: The DRAM controller 101 outputs the read data from the ECC circuit 102 to the user side.

[0115] As can be seen from the above, since the soft failure of DRAM chips is related to the actual application scenario, it is impossible to predict which DRAM partitions have a high probability of soft failure. Therefore, all partitions must be configured with ECC storage partitions. In this case, for partitions that will not experience soft failures, or for application scenarios that are not sensitive to data soft failures (high fault tolerance), configuring ECC storage partitions for all partitions is actually a waste, increasing the overall cost of DRAM chips.

[0116] Additionally, some DRAM chips support using the ECC memory partitions in the aforementioned DRAM die as regular data storage partitions (i.e., using ECC memory partitions to expand the DRAM memory partitions), thereby increasing the usable capacity of the DRAM chip. However, in such application scenarios, the DRAM die may not contain ECC memory partitions. Therefore, given the actual operating conditions of the DRAM chip (such as occasional soft failures caused by high temperatures), the data in the DRAM memory partitions cannot be effectively protected.

[0117] To address the aforementioned issues, this application provides a storage device that may include a first memory, a second memory, and a storage controller; wherein the first memory and the second memory belong to different dies, meaning that the first memory and the second memory are physically independent.

[0118] The first memory can be configured to store data; the second memory can be configured to store error correction codes corresponding to the data in the first memory. The memory controller and the first memory are coupled via address lines and data lines (including write data lines and read data lines). The memory controller can be configured to write first data to the first memory via address lines and write data lines or read second data from the first memory via address lines and read data lines.

[0119] For example, the first memory can be implemented in the form of a DRAM die. The first memory can be one or more DRAM dies.

[0120] In some possible implementations, the first memory may also be a 3D stacked static random-access memory (SRAM), non-volatile memory (NVM), or other types of memory.

[0121] For example, the second memory can be implemented in the form of an SRAM die. The second memory can be one or more SRAM dies.

[0122] Of course, in practical applications, the first memory and the second memory can also be implemented in other forms, and the embodiments of this application do not impose specific limitations.

[0123] In this embodiment, by integrating the first memory and the second memory into different dies, data and error correction codes are stored in different memories. Therefore, there is no need to allocate a storage partition for error correction codes in the first memory, thus avoiding the error correction codes occupying storage space in the first memory and increasing the capacity of available data in the first memory. For example, in a DRAM scenario, with... Figure 1 The difference in the embodiments is that the first memory (such as DRAM) and the second memory (such as SR AM) are integrated in different dies, and the data and the corresponding error correction code are stored in the first memory and the second memory respectively. In this way, there is no need to allocate corresponding storage space for error correction codes in DRAM, thereby reducing the fixed configuration of error correction code storage space in DRAM and thus increasing the available data capacity of DRAM.

[0124] Furthermore, since the data and error correction codes are stored in the first memory and the second memory respectively, and the second memory and the first memory belong to different dies, the error correction codes do not need to be processed like... Figure 1 The embodiments described herein can only protect data in the same die as the error correction code storage partition, but can also protect data in one or more first memories, thereby enabling multiple first memories to share a second memory.

[0125] In addition, such as Figure 1 As described in the embodiments, since DRAM soft failures are related to the actual application scenario, it is impossible to predict which data storage partitions have a high probability of soft failures. Therefore, all data storage partitions are configured with error correction code storage partitions regardless of whether data protection is required. However, this is wasteful for data storage partitions that do not experience soft failures, or for application scenarios that are not sensitive to data soft failures (high fault tolerance). Therefore, in this embodiment, since the data storage partitions are located in the first memory and the error correction code storage partitions are located in the second memory, and the second memory and the first memory belong to different dies, the storage partitions of the second memory can be flexibly allocated to the storage partitions of the first memory that actually require data protection, instead of allocating error correction code storage partitions to all data storage partitions. This saves error correction code storage resources, thereby enabling flexible adjustment of the area used for data protection according to actual needs and working status, and thus improving the utilization rate of error correction code storage resources.

[0126] Optionally, the first memory and the second memory can be deployed in a certain ratio. For example, the first memory and the second memory can be arranged in a data:error correction code ratio (which can be understood as the ratio of data length to error correction code bit width) of 512:1, 256:1, 128:1, 64:1, etc. Of course, the ratio of data to error correction code can also be other ratios, as long as the storage space of the error correction code is much smaller than the storage space of the data. This application embodiment does not make specific limitations.

[0127] In this embodiment, the storage space of the error correction code is much smaller than the storage space of the data. This can be understood as using an error correction code with a smaller address range to protect data with a larger address range. In this way, error correction code storage resources are saved and the utilization rate of error correction code storage resources is improved.

[0128] Furthermore, for example, in Figure 1 In the previous embodiment, all storage areas on an 8Gbit DRAM required a fixed 1Gbit error correction code storage area, regardless of whether ECC was needed. This resulted in additional power consumption and area consumption for data that did not require protection, leading to waste. However, in the embodiment of this application, an 8Gbit first memory only requires the deployment of a 128Mbit second memory, significantly saving error correction code storage resources and increasing the capacity of available data on the DRAM.

[0129] It should be noted that, in the embodiments of this application, the first memory is DRAM and the second memory is SRAM as an example for illustration.

[0130] Furthermore, the first memory can be divided into multiple DRAM partitions, and the second memory can be divided into multiple SRAM partitions. The number of DRAM partitions and SRAM partitions can be configured with reference to the aforementioned data-to-error-correction-code ratio. Additionally, a configurable mapping relationship between the first and second memories can exist, allowing different SRAM partitions to be allocated to different DRAM partitions as storage space for corresponding error-correction codes, thus supporting flexible sharing of the second memory with the first memory. Specifically, if a DRAM partition requires data protection, a corresponding SRAM partition is configured for that DRAM partition; conversely, if a DRAM partition does not require data protection, no corresponding SRAM partition is configured for that DRAM partition.

[0131] In this embodiment, configurable protection configuration information can be set. This protection configuration information can include a mapping relationship between the addresses of storage partitions in the first memory and the addresses of storage partitions in the second memory. By configuring this protection configuration information, the mapping relationship can be changed, allowing storage partitions in the second memory to be flexibly allocated to storage partitions in the first memory that require data protection, rather than being fixed to correspond to all DRAM partitions. This way, for data storage partitions with low access frequency, corresponding error correction code storage resources do not need to be configured, saving error correction code storage resources. This allows for adjusting the area used for data protection according to actual needs and operating status, thereby improving the utilization rate of error correction code storage resources.

[0132] In practical applications, the protection configuration information can include a mapping relationship between the addresses of DRAM partitions requiring data protection and the addresses of SRAM partitions allocated to those DRAM partitions. Therefore, if a DRAM partition has an address mapping relationship in the protection configuration information, it means that the data corresponding to that DRAM partition needs protection; conversely, if a DRAM partition does not have an address mapping relationship in the protection configuration information, it means that the data corresponding to that DRAM partition does not need protection.

[0133] Alternatively, the protection configuration information can also include the mapping relationship between the addresses of all DRAM partitions and the addresses of SRAM partitions. The address of a DRAM partition requiring data protection corresponds to the address of the SRAM partition allocated to that DRAM partition, while the SRAM partition address corresponding to the address of a DRAM partition not requiring data protection can be set to "0", "null", "empty", etc. Therefore, if a DRAM partition has a corresponding SRAM partition address, it means that the data corresponding to that DRAM partition needs protection, while DRAM partitions with mapped addresses of "0", "null", "empty", etc., mean that the data corresponding to that DRAM partition does not need protection.

[0134] For example, suppose the first memory is divided into 512 DRAM partitions and the second memory is divided into 8 partitions. Figure 2 This is a schematic diagram of the protection configuration information in the embodiments of this application. The protection configuration information is implemented in the form of a table. See below. Figure 2 As shown, DRAM partitions requiring data protection (represented by the high-order address of each memory partition), such as channel0+bank1 (i.e., partition 1 in channel 0), channel0+bank63, channel1+bank62, ..., channel7+bank63, are each allocated an SRAM partition (represented by the memory address of each memory partition), such as zone0 to zone7. The mapped address of DRAM partitions that do not require data protection is "0".

[0135] It should be noted that the aforementioned high-order address refers to the first part of the DRAM partition's memory address (which may include the Channel identifier + Bank address). Correspondingly, the latter part of the memory address is the low-order address of the DRAM partition. For example, if the DRAM partition's memory address can be 16 bits, then the first 8 bits are the high-order address of the DRAM partition, and the corresponding last 8 bits are the low-order address. For instance, if the DRAM partition's memory address is channel0 + bank1 + 00010110, the high-order address is channel0 + bank1, and the low-order address is 00010110.

[0136] In some possible implementations, in addition to the DRAM partition and SRAM partition entries, the protection configuration information may also include an "ECC" flag. This flag can be used to indicate whether the DRAM partition needs data protection, or it can be understood as indicating whether the data corresponding to the DRAM partition is data that needs protection, whether the DRAM partition has a corresponding error correction code, and whether the DRAM partition is configured with a corresponding SRAM partition, etc.

[0137] In some possible implementations, the low-order address of each memory partition in the first memory is the same as the memory address of each memory partition in the second memory. For example, the memory address of the DRAM partition requiring data protection is channel0+bank1+00010110, and the address of the SRAM partition corresponding to this DRAM partition can be the low-order address 00010110 of the DRAM partition.

[0138] In some possible implementations, Figure 3 This is a schematic diagram of a storage device according to an embodiment of this application. See also... Figure 3 As shown, the storage device 300 may include: a first memory 301, a second memory 302, a storage controller 303, and an ECC circuit 304; wherein the first memory 301 and the second memory 302 belong to different dies. The storage controller 303 is coupled to the first memory 301 through address line A, and the storage controller 303 is coupled to the ECC circuit 304 through data lines (including write data line W and read data line R) and address line A. The ECC circuit 304 is coupled to the first memory 301 and the second memory 302 through data lines.

[0139] Here, the first memory 301, the second memory 302, and the memory controller 303 are the same as the first memory, the second memory, and the memory controller in the above embodiment.

[0140] In some possible implementations, the ECC circuit is further configured to: when it is determined that the first data is data that needs to be protected, generate a first error correction code corresponding to the first data; and when it is determined that the second data is data that needs to be protected, correct the second data according to the second error correction code corresponding to the second data.

[0141] In the embodiments of this application, when the ECC circuit determines that the first data and the second data are data that need to be protected, it performs ECC operations on the first data and the second data (such as generating error correction codes, performing error correction based on the error correction codes, etc.). In this way, selective ECC operations are performed on the data, which improves the utilization rate of error correction code storage resources while ensuring effective data protection.

[0142] Optionally, the ECC circuit 304 is also configured to listen to the address lines between the memory controller 303 and the first memory 301 to obtain the write address (i.e., the first address) or the read address (the second address) of the data.

[0143] Therefore, the ECC circuit 304 can be configured to: determine whether the first data is data that needs to be protected based on the write address and the above protection configuration information; and determine whether the second data is data that needs to be protected based on the read address and the above protection configuration information.

[0144] For example, if the write address is channel0+bank1+00010110, the ECC circuit will query as follows: Figure 2 The protection configuration information shown indicates that data protection is required for the DRAM partition with the high-order address "channel0+bank1". Therefore, the ECC circuit can generate the first error correction code corresponding to the first data. Similarly, if the read address is channel0+bank63+0100101, the ECC circuit will query... Figure 2The protection configuration information shown indicates that data protection is required for the DRAM partition with the high-order address "channel0+bank63". Therefore, the ECC circuit corrects the second data according to the second error correction code.

[0145] Furthermore, the storage controller is also configured to output first data to the ECC circuit; then, the ECC circuit is also configured to: when it is determined that the first data is data that needs to be protected, generate a first error correction code and write the first error correction code into the second memory; and write the first data into the first storage partition of the first memory according to the write address.

[0146] Furthermore, the ECC circuit is configured to: read second data from the third storage partition of the second memory according to the read address; when it is determined that the second data is data that needs to be protected, read the second error correction code from the second memory and correct the second data according to the second error correction code; and output the corrected second data to the storage controller.

[0147] In some possible embodiments, the ECC circuit may belong to the same die as the second memory; or, the ECC circuit may belong to a different die from the second memory.

[0148] Furthermore, the ECC circuit may belong to a different die than the memory controller; or, the ECC circuit may belong to a different die than the memory controller.

[0149] It is understood that the ECC circuit, the second memory, and the memory controller can be integrated into the same die or into different dies. For example, the ECC circuit and the memory controller can be integrated into one die, and the second memory into another die. Of course, different implementations are also possible, and the embodiments in this application do not impose specific limitations.

[0150] The data read / write process of the storage device will be explained below in conjunction with the structure of the storage device described above.

[0151] Figure 4 This is a schematic diagram of the data writing process of the storage device in the embodiments of this application. See also... Figure 4 As shown, the data writing process may include the following steps:

[0152] S401: The storage controller receives write commands from the user side;

[0153] S402: The memory controller outputs a write operation instruction and a write address (i.e., the first address of the first memory partition) to the first memory via the address lines;

[0154] S403: The memory controller outputs a write address to the ECC circuit;

[0155] S404: The memory controller outputs the first data (i.e., write data) to the ECC circuit via the write data line;

[0156] S405: The ECC circuit determines whether the first data is data that needs to be protected based on the write address; if yes, it obtains the second address of the second storage partition in the second memory and executes S406; if no, it executes S408.

[0157] In some possible embodiments, after obtaining the write address, the ECC circuit can retrieve the high-order address bits (e.g., ChannelID + Bank address) and then use these high-order address bits to query protection configuration information (e.g., ...). Figure 2 (As shown), to determine whether the first data is data that needs protection, that is, to determine whether the first storage partition needs data protection. For example, if the write address is channel0+bank1, the ECC circuit queries... Figure 2 The protection configuration information shown determines that the data corresponding to channel0+bank1 is the data that needs to be protected by the "ECC" flag. In other words, it determines that the first storage partition needs data protection. Then, the ECC circuit can obtain the SRAM partition address (third address) corresponding to channel0+bank1, i.e. zone0, through the protection configuration information.

[0158] S406: The ECC circuit generates the error correction code corresponding to the first data (i.e., the first error correction code);

[0159] S407: The ECC circuit writes the error correction code corresponding to the first data into the second storage partition according to the third address;

[0160] S408: The ECC circuit outputs the first data to the first memory via the write data line;

[0161] In some possible implementations, if the ECC circuit determines that the first data is data that does not need to be protected based on the write address, then in S408, the memory controller can output the first data to the first memory in a transparent manner via the ECC circuit.

[0162] S409: The first memory responds to the write operation instruction and writes the first data to the first memory partition according to the write address.

[0163] In S401 to S409 above, the execution timing of the process of the storage controller writing the first data to the first storage partition and the execution timing of the ECC circuit generating and storing the error correction code corresponding to the first data are not specifically limited.

[0164] In some possible implementations, Figure 5 This is a schematic diagram of the data reading process of the storage device in the embodiments of this application. See also... Figure 5As shown, the data reading process may include the following steps:

[0165] S501: The storage controller receives read commands from the user side;

[0166] S502: The memory controller outputs a read operation instruction and a read address (i.e., the second address of the second memory partition) to the first memory via the address lines;

[0167] S503: The first memory responds to the read operation instruction and reads the second data (i.e., read the data) from the second memory partition according to the read address;

[0168] S504: The first memory outputs the second data to the ECC circuit through the read data line;

[0169] S505: The memory controller outputs the read address to the ECC circuit;

[0170] S506: The ECC circuit determines whether the second data is data that needs to be protected based on the read address; if yes, it obtains the fourth address of the fourth storage partition in the second memory and executes S507; if no, it executes S510.

[0171] In some possible embodiments, after obtaining the write address, the ECC circuit can retrieve the high-order address bits (e.g., ChannelID + Bank address) and then use these high-order address bits to query protection configuration information (e.g., ...). Figure 2 As shown in the diagram, the process by which the ECC circuit determines whether the second data is data that needs protection is similar to the process described above for determining whether the first data is data that needs protection, and will not be repeated here.

[0172] S507: The ECC circuit reads the error correction code (i.e., the second error correction code) corresponding to the second data from the fourth memory partition according to the fourth address;

[0173] S508: The ECC circuit checks the second data according to the error correction code; if the ECC circuit detects an error, then execute S509; if the ECC circuit does not detect an error, then execute S510.

[0174] In practical applications, the first and second data can include multiple bits. When the ECC circuit detects a unit (i.e., 1 bit) error, it executes S509.

[0175] S509: The ECC circuit corrects errors in the second data;

[0176] S510: The ECC circuit outputs the second data to the memory controller via the read data line;

[0177] Here, in S510, the ECC circuit can output the second data or the error-corrected second data to the storage controller.

[0178] In some possible implementations, if the ECC circuit determines that the second data is data that does not need to be protected based on the write address, then in S510, the first memory can output the second data to the memory controller in a transparent manner via the ECC circuit.

[0179] S511: The storage controller outputs the second data from the ECC circuit to the user side.

[0180] As can be seen from the above, since the data storage partition is set in the first memory and the error correction code storage partition is set in the second memory, and the second memory and the first memory belong to different dies, the storage partitions of the second memory can be flexibly allocated to the storage partitions of the first memory that require data protection, instead of all data storage partitions being allocated to error correction code storage partitions. In this way, error correction code storage resources can be saved, thereby realizing the flexible adjustment of the area used for data protection according to actual needs and working status, and thus improving the utilization rate of error correction code storage resources.

[0181] Furthermore, since the data storage partition is located in the first memory and the error correction code storage partition is located in the second memory, and the second memory and the first memory belong to different dies, the ECC circuit can perform ECC operations (such as generating error correction codes and performing error correction based on error correction codes) on the first data and the second data when it determines that the first data and the second data are data that need to be protected, while transparently transmitting the data when it determines that the first data and the second data are data that do not need to be protected. In this way, selective ECC operations are performed on the data, which improves the utilization rate of error correction code storage resources while ensuring effective data protection.

[0182] In some possible implementations, in order to improve the utilization of error correction code storage resources, Figure 6 This is a schematic diagram of the ECC circuit in an embodiment of this application. See also... Figure 6 As shown by the solid line in the figure, the ECC circuit 304 may include: an analysis submodule 3041 and a generation submodule 3042;

[0183] The analysis submodule described above is configured to: obtain the write address from the storage controller; determine the first data as the data to be protected based on the write address and protection configuration information; output a first instruction to the generation submodule to instruct the generation of a first error correction code; the generation submodule is configured to: generate the first error correction code in response to the first instruction.

[0184] In combination with the above Figure 4 The process of writing data to a storage device Figure 7This is a schematic diagram illustrating the workflow of the ECC circuit in the data writing process in the embodiments of this application. See also... Figure 7 As shown, the operation of an ECC circuit may include the following steps:

[0185] S701: The analysis submodule obtains the write address from the storage controller;

[0186] S702: The analysis submodule determines whether the first data is data that needs to be protected based on the write address and protection configuration information; if yes, then execute S703; otherwise, do not respond.

[0187] Specifically, when executing S702, the analysis submodule can query the write address in the preset protection configuration information; when the query result indicates that the write address needs data protection, the first data can be determined as the data that needs to be protected.

[0188] S703: The analysis submodule outputs the first instruction to the generation submodule;

[0189] S704: The generation submodule obtains the first data via the write data line;

[0190] S705: The generation submodule responds to the first instruction and generates the error correction code corresponding to the first data;

[0191] S706: The generation submodule writes the error correction code corresponding to the first data into the second storage module.

[0192] In some possible embodiments, the analysis submodule queries protection configuration information (such as...) via S702. Figure 2 After determining that the first data is the data that needs protection (as shown), the analysis submodule can also obtain the third address corresponding to the write address through the protection configuration information. Then, the analysis submodule outputs the third address to the generation submodule through the first instruction. Next, when the generation submodule executes S706, it writes the error correction code corresponding to the first data into the third storage partition in the second memory according to the third address.

[0193] It should be noted that in the above S701 to S706, the execution order of S701 to S703 and S704 is not specifically limited.

[0194] See also some possible implementations. Figure 6 As shown by the dashed line in the figure, the ECC circuit 304 may also include: a test submodule 3043;

[0195] The analysis submodule described above is also configured to: obtain the read address; determine the second data as the data to be protected based on the read address; output a second instruction to the inspection submodule to instruct the reading of the second error correction code; the inspection submodule is configured to: respond to the second instruction and read the second error correction code from the second memory.

[0196] In combination with the above Figure 5 The process of reading data from a storage device Figure 8 This is a schematic diagram illustrating the workflow of the ECC circuit during the data reading process in an embodiment of this application. See also... Figure 8 As shown, the operation of an ECC circuit may include the following steps:

[0197] S801: The analysis submodule obtains the read address from the storage controller;

[0198] S802: The analysis submodule determines whether the second data is data that needs to be protected based on the read address; if yes, then execute S803; if no, then execute S808.

[0199] Specifically, when executing S802, the analysis submodule can query the read address in the preset protection configuration information; when the query result indicates that data protection is required for the read address, the second data can be determined as the data that needs to be protected.

[0200] S803: The analysis submodule outputs a second instruction to the inspection submodule;

[0201] S804: The inspection submodule obtains the second data via the read data line;

[0202] S805: Check the submodule's response to the second instruction and read the error correction code corresponding to the second data from the second memory;

[0203] S806: The checking submodule checks the second data according to the error correction code; if a 1-bit error is detected, S807 is executed; if no error is detected, S808 is executed.

[0204] S807: The inspection submodule corrects errors in the second data;

[0205] S808: The inspection submodule outputs the corrected second data to the storage controller.

[0206] In some possible embodiments, the analysis submodule queries protection configuration information (such as S802) Figure 2 (As shown) After determining that the second data is the data that needs protection, the analysis submodule can also obtain the fourth address corresponding to the read address through the protection configuration information. Then, the analysis submodule outputs the fourth address to the inspection submodule through the second instruction. Next, when the inspection submodule executes S805, it reads the error correction code corresponding to the second data from the fourth storage partition in the second memory according to the fourth address.

[0207] It should be noted that in the above S801 to S808, the execution order of S801 to S803 and S804 is not specifically limited.

[0208] In this embodiment of the application, the above-mentioned analysis submodule is further configured to: control whether the ECC circuit works when the storage device is in working state, thereby realizing the data protection function of the storage device being turned on or off.

[0209] The following example illustrates the data reading and writing process of the aforementioned storage device.

[0210] Figure 9 This is another structural schematic diagram of the storage device in the embodiments of this application, combined with Figure 9 As shown, the process of reading and writing data on a storage device can be described as follows.

[0211] Writing process:

[0212] Step 1: The storage controller 303 receives a write command from the user side;

[0213] The second step is that the memory controller 303 outputs a write operation instruction and a write address (such as channel0+bank1) to the first memory 301 through the address lines;

[0214] Third step: Storage controller 303 outputs the write address to analysis submodule 2021;

[0215] For example, after receiving the user's write instruction, the DRAM controller (i.e., the storage controller 303) issues the corresponding operation instruction according to the DRAM timing requirements, and at the same time sends the DRAM write instruction address to the ECC address analysis module (i.e., the analysis submodule 2021).

[0216] Step 4: The storage controller 303 outputs the write data to the generation submodule 2022 via the write data line;

[0217] Step 5, Analysis Submodule 2021 Figure 2 The table is queried to find the write address, and it is determined that the storage partition with address channel0+bank1 needs data protection, and the corresponding SRAM partition address, i.e. zone0, is obtained.

[0218] Step 6: The analysis submodule 2021 sends the first instruction and the SRAM partition address zone0 to the generation submodule 2022; here, the first instruction is used to instruct the generation of ECC code.

[0219] For example, when the ECC address analysis module receives a write command from the DRAM controller, it can analyze the access address in the write command. It uses the high-order address bits of this write operation (e.g., 3-bit channel ID + 6-bit Bank address BA5~BA0) to look up an ECC configuration table (i.e., protection configuration information). If the corresponding entry indicates that the address segment requires ECC, then this write operation belongs to a segment requiring ECC protection, and an ECCSRAM partition number can be obtained. If it is identified that this write operation belongs to a segment requiring ECC protection, the ECC address analysis module will issue an ECC instruction and the used ECCSRAM partition number (i.e., SRAM partition address) to the ECC generation module (i.e., the generation submodule).

[0220] Step 7: The generation submodule 2022 responds to the first instruction and generates the error correction code corresponding to the first data;

[0221] Step 8: The generation submodule 2022 writes the error correction code corresponding to the first data into zone0;

[0222] Step 9: The storage controller 303 outputs the first data to the first memory 301 via the write data line;

[0223] For example, for a DRAM write operation, the ECC generation module performs ECC calculations based on the ECC instructions from the ECC address analysis module, generating corresponding ECC check bits (i.e., the first error correction code) in units of certain data bits. The generated ECC check bits are sent to the ECC storage resource pool module (i.e., the second memory) for processing. The write data is then sent to the DRAM die (i.e., the first memory) and stored in the corresponding DRAM storage unit (i.e., the first storage partition).

[0224] Step 10: The first memory 301 responds to the write operation command and writes the first data into channel0+bank1.

[0225] In another embodiment, for example, if the ECC storage resource pool module receives an ECC instruction from the ECC address analysis module, it can write the ECC check bit sent by the ECC generation module into the corresponding SRAM storage address (the SRAM storage address is the same as the low-order address of the DRAM). If the ECC storage resource pool module does not receive an ECC instruction from the ECC address analysis module, it indicates that the address of this write operation does not belong to the segment that needs ECC protection, and no operation is performed.

[0226] Reading process:

[0227] Step 1: The storage controller 303 receives a read command from the user side;

[0228] The second step is that the storage controller 303 outputs a read operation command and a read address (such as channel0+bank63) to the first memory 301 through the address lines;

[0229] Third step: The storage controller 303 outputs the read address to the analysis submodule 2021;

[0230] For example, in a DRAM read operation, the DRAM die receives a read instruction and reads data from the data storage area. Simultaneously, the address of the read operation is sent to the ECC address analysis module.

[0231] Step 4: Analysis of the 2021 submodule Figure 2 The table is queried to find the read address, and it is determined that the DRAM partition with address channel0+bank63 needs data protection, and the corresponding SRAM storage partition address, i.e. zone1, is obtained;

[0232] Step 5: The analysis submodule 2021 sends a second instruction and the SRAM partition address zone1 to the inspection submodule 2023; here, the second instruction is used to instruct the reading of the ECC code.

[0233] For example, when the ECC address analysis module receives a read operation address controlled by DRAM, it analyzes the high-order address bits and uses them (e.g., 3-bit channel ID + 6-bit Bank address BA5~BA0) to look up an ECC configuration table. If the corresponding entry indicates that the address segment requires ECC, then the read operation belongs to a segment requiring ECC protection, and an ECCSRAM partition number can be obtained. The ECC address analysis module then sends an ECC indication requiring ECC verification and the ECCSRAM partition number used to the ECC check module and the ECC storage resource pool module. If the address of the read operation is not identified as belonging to a segment requiring ECC protection, no ECC indication is issued.

[0234] Step 6: Check the response of submodule 2023 to the second instruction and read the error correction code corresponding to the second data from zone1;

[0235] For example, when the ECC storage resource pool module receives a read operation ECC instruction from the ECC address analysis module, it will read the corresponding ECC data from the SRAM storing ECC data and send it to the ECC check module.

[0236] Step 7: The first memory 301 reads the second data from channel 0+bank 63 and outputs it to the inspection submodule 2023;

[0237] For example, the DRAM read data is sent to the ECC check module according to the chip's operating timing.

[0238] Step 8: Submodule 2023 checks the second data according to the error correction code;

[0239] Step 9: If a 1-bit error is detected, check submodule 2023 to correct the error in the second data.

[0240] Step 10: Check that submodule 2023 outputs the corrected second data to storage controller 201;

[0241] For example, if the ECC checking module receives a data bit read from the DRAM and simultaneously receives an ECC check bit from the ECC storage resource pool module and an ECC indication from the ECC address analysis module, it will perform an ECC calculation check. If a single-bit ECC error is detected, the data can be corrected and sent to the DRAM controller. If the ECC checking module receives a data bit read from the DRAM but does not receive an ECC indication from the ECC address analysis module, it does not need to perform an ECC calculation check and directly sends the data to the DRAM controller.

[0242] Step 11: The storage controller 201 outputs the second data to the user side.

[0243] For example, the DRAM controller returns the read data, which has undergone ECC checking / correction, to the user side.

[0244] In the specific implementation process, the above-mentioned storage device can be packaged in, but is not limited to, the following methods.

[0245] The first type, Figure 10 This is a schematic diagram of a first type of packaging for a storage device in an embodiment of this application. See also... Figure 10 As shown, the first memory 301, the second memory 302, the memory controller 303, and the ECC circuit 304 are mounted on the same package substrate 11. The memory controller 303, the ECC circuit 304, and the second memory 302 are integrated on the same die a (such as a logic die or a basic die). The first memory 301 is integrated on another die b (such as a DRAM die) and mounted on the package substrate 12.

[0246] In practical applications, the ECC circuit 304 can communicate with the second memory 302 through the on-chip high-speed bus interface.

[0247] The second type, Figure 11 This is a schematic diagram of a second type of packaging for the storage device in an embodiment of this application. See also... Figure 11As shown, the first memory 301, the second memory 302, the memory controller 303, and the ECC circuit 304 are mounted on the same package substrate 21. The memory controller 303 and the ECC circuit 304 are integrated on a die c (such as a logic die or a basic die), the second memory 302 is integrated on a die d (such as an SRAM die), and the first memory 301 is integrated on another die e (such as a DRAM die).

[0248] In practical applications, ECC circuit 304 can communicate with second memory 302 through a high-speed interconnect interface such as die-to-diephy.

[0249] The third type, Figure 12 This is a schematic diagram of a third type of packaging for the storage device in an embodiment of this application. See also... Figure 12 As shown, the memory controller 303, ECC circuit 304, and second memory 302 are mounted on the package substrate 31. The memory controller 303, ECC circuit 304, and second memory 302 are integrated on the same die f (such as a logic die or a basic die). The first memory 301 is integrated on another die g (such as a DRAM die) and mounted on the package substrate 32.

[0250] In practical applications, the ECC circuit 304 can communicate with the second memory 302 through the on-chip high-speed bus interface.

[0251] The fourth type, Figure 13 This is a schematic diagram of a fourth type of packaging for the storage device in the embodiments of this application. See also... Figure 13 As shown, the memory controller 303 and ECC circuit 304 are integrated on the same die h (such as a logic die or a basic die) and mounted on the package substrate 41. The second memory 302 is integrated on a die i (such as an SRAM die) and mounted on the package substrate 42. The first memory 301 is integrated on a die j (such as a DRAM die) and mounted on the package substrate 43.

[0252] In practical applications, ECC circuit 304 can communicate with second memory 302 through a high-speed interconnect interface such as Serdesphy.

[0253] The fifth type, Figure 14 This is a schematic diagram of the fifth type of packaging for the storage device in the embodiments of this application. See also... Figure 14As shown, the memory controller 303 is integrated into a die k (such as a logic die or a basic die) and mounted on the package substrate 51. The ECC circuit 304 and the second memory 302 are integrated into dies l and m and mounted on the package substrate 52. The first memory 301 is integrated into a die n (such as a DRAM die) and mounted on the package substrate 53.

[0254] In practical applications, ECC circuit 304 can communicate with second memory 302 through a high-speed interconnect interface such as die-to-diephy.

[0255] Of course, the above-mentioned storage device can also have other packaging methods, and this application embodiment does not specifically limit it.

[0256] Based on the same inventive concept, embodiments of this application also provide an error correction device, including: the above-mentioned... Figures 2 to 9 The ECC circuit and the second memory are shown.

[0257] Understandably, in an error correction device, the ECC circuit and the second memory can be configured as follows: Figure 14 The encapsulation method shown is used for encapsulation.

[0258] Based on the same inventive concept, embodiments of this application also provide a storage control device, including: the above-described... Figures 2 to 9 The storage controller and ECC circuit are shown.

[0259] Understandably, in a storage control device, the storage controller and the ECC circuit can adopt the following... Figure 11 Alternatively, it can be packaged using the packaging method shown in Figure 13.

[0260] Based on the same inventive concept, embodiments of this application also provide a system-on-chip (SOC), which may include a processor, a bus, and the aforementioned... Figures 2 to 9 The storage device shown is coupled to a bus.

[0261] The processor is configured to: output write instructions and first data to the storage device via a bus, or output read instructions to the storage device via a bus and receive second data output by the storage device via a bus.

[0262] The processor can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0263] Based on the same inventive concept, embodiments of this application also provide an electronic device, which can be a computing device, such as a server; the electronic device can also be a storage device, such as a storage array; the electronic device can also be a network device, such as a switch.

[0264] Figure 15 This is a hardware schematic diagram of the electronic device in the embodiments of this application. See also: Figure 15 As shown, the electronic device 1500 may include a processor 1501, a storage device 1502, a bus 1503, an input device 1504, an output device 1505, and an antenna system 1506.

[0265] In some possible implementations, the storage device 1502 is consistent with the storage device described in one or more of the above embodiments. Furthermore, the processor 1501 may be consistent with the system-on-a-chip described in the above embodiments.

[0266] Storage device 1502 can store program instructions, such as operating system, application programs, other program modules, executable code, program data, user data, etc.

[0267] Input device 1504 can be used to input commands and information to electronic device 1500. Input device 1504 may be a keyboard or pointing device such as a mouse, trackball, touchpad, microphone, joystick, gamepad, satellite TV antenna, scanner, or similar device. These input devices can be connected to processor 1501 via bus 1503.

[0268] Output device 1505 can be used by electronic device 1500 to output information. In addition to monitor, output device 1505 can also be other peripheral output devices, such as speakers and / or printing devices. These output devices can also be connected to processor 1501 via bus 1503.

[0269] Antenna system 1506, under the control of processor 1501, transmits and receives wireless communication signals to achieve wireless communication with mobile communication networks.

[0270] Of course, electronic devices may also contain other functional components, and this application does not specifically limit them.

[0271] Based on the same inventive concept, this application also provides a data storage method that can be applied to the storage device described in one or more of the above embodiments.

[0272] Therefore, the method may include: the storage controller writing data to the first memory and reading data from the first memory, wherein the first memory and the second memory are different dies, the second memory is used to store the error correction code corresponding to the data, and the error correction code is used to protect the data.

[0273] In some possible implementations, the data includes first data and second data; the above-mentioned storage controller writing data to the first memory includes: the storage controller writing the first data to the first memory;

[0274] The memory controller reads data from the first memory, including: the memory controller reads second data from the first memory.

[0275] Accordingly, the above method further includes: the ECC circuit generating a first error correction code corresponding to the first data; or, the ECC circuit correcting the second data according to the second error correction code in the second memory, wherein the second error correction code is the error correction code corresponding to the second data.

[0276] In some possible implementations, the above-mentioned ECC circuit generates a first error correction code corresponding to the first data, including: when it is determined that the first data is data that needs to be protected, the ECC circuit generates a first error correction code;

[0277] The aforementioned ECC circuit corrects the second data according to the second error correction code in the second memory, including: when it is determined that the second data is data that needs to be protected, the ECC circuit corrects the second data according to the second error correction code.

[0278] In some possible implementations, the above method further includes: the ECC circuit determining whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information; or, the ECC circuit determining whether the second data is data that needs to be protected based on the second address corresponding to the second data and protection configuration information; wherein, the protection configuration information includes the mapping relationship between the address of the storage partition in the first memory and the address of the storage partition in the second memory, and the storage partition of the second memory corresponds to the data that needs to be protected.

[0279] In some possible implementations, the above-mentioned storage controller writes first data to the first memory, including: the storage controller outputs a first address and first data to the ECC circuit; the ECC circuit writes the first data to the first storage partition of the first memory according to the first address.

[0280] In some possible implementations, after the ECC circuit generates the first error correction code, the method further includes: the ECC circuit obtaining the third address corresponding to the first address; and writing the first error correction code into the second storage partition in the second memory according to the third address.

[0281] In some possible implementations, the above method further includes: when it is determined that the first data is data that does not need to be protected, the ECC circuit writes the first data into the first memory.

[0282] In some possible implementations, the above-mentioned storage controller reads second data from the first memory, including: the storage controller outputs a second address to the ECC circuit; the ECC circuit reads the second data from a third storage partition of the first memory according to the second address; and the ECC circuit outputs the second data to the storage controller.

[0283] In some possible implementations, the above-mentioned ECC circuit outputs second data to the storage controller, including: the ECC circuit checks the second data according to the second error correction code; if an error is detected, the second data is corrected and the corrected second data is output to the storage controller; if no error is detected, the second data is output to the storage controller.

[0284] In some possible implementations, when the second data is determined to be data that needs to be protected, the above method further includes: the ECC circuit obtaining the fourth address corresponding to the second address; and reading the second error correction code from the fourth storage partition in the second memory according to the fourth address.

[0285] In some possible implementations, the method further includes: when it is determined that the second data is data that does not need to be protected, the ECC circuit outputs the second data to the storage controller.

[0286] Based on the same inventive concept, this application also provides a data storage method that can be applied to the storage control device described in one or more of the above embodiments.

[0287] Therefore, the method may include:

[0288] The storage control device writes first data to the first memory and reads second data from the first memory; when it is determined that the first data is data that needs to be protected, the storage control device generates a first error correction code; and when it is determined that the second data is data that needs to be protected, the storage control device corrects the second data according to the second error correction code.

[0289] In some possible implementations, the above method further includes: the storage control device determining whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information; and the storage control device determining whether the second data is data that needs to be protected based on the second address corresponding to the second data and protection configuration information; wherein the protection configuration information includes a mapping relationship between the addresses of storage partitions in the first memory and the addresses of storage partitions in the second memory, and the storage partitions of the second memory correspond to the data to be protected.

[0290] In some possible implementations, the above-mentioned storage control device writes first data to the first memory, including: the storage control device writes the first data to a first storage partition of the first memory according to a first address.

[0291] In some possible implementations, after the storage control device generates the first error correction code, the method further includes: the storage control device obtaining a third address corresponding to the first address; and writing the first error correction code into a second storage partition in the second memory according to the third address.

[0292] In some possible implementations, the method further includes: when it is determined that the first data is data that does not need to be protected, the storage control device writes the first data into the first memory.

[0293] In some possible implementations, the above-described storage control device reads second data from the first memory, including: the storage controller reads the second data from a third storage partition of the first memory according to a second address.

[0294] In some possible implementations, the storage control device reads the second data from the first memory, including: the storage control device checks the second data according to a second error correction code; if an error is detected, the storage control device corrects the second data and obtains the corrected second data; if no error is detected, the storage control device obtains the second data.

[0295] In some possible implementations, before the storage control device corrects the second data, the method further includes: when it is determined that the second data is data that needs to be protected, the storage control device obtains a fourth address corresponding to the second address; the storage control device reads the second error correction code from the fourth storage partition in the second memory according to the fourth address.

[0296] In some possible implementations, the method further includes: when it is determined that the second data is data that does not need to be protected, the storage control device reads the second data.

[0297] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more sets of available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. A semiconductor medium can be a solid-state drive (SSD).

[0298] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage device, characterized in that, include: A first memory is configured to store data, the data including first data and second data; The second memory is configured to store the error correction code corresponding to the data, the error correction code being used for data protection of the data; The storage controller is configured to write the first data to the first storage memory; And read the second data from the first memory; The error checking and correction ECC circuit is configured to generate a first error correction code corresponding to the first data; And read the second error correction code from the second memory; the second error correction code is the error correction code corresponding to the second data; The first memory and the second memory belong to different dies.

2. The storage device according to claim 1, characterized in that, The ECC circuit is further configured to: generate the first error correction code when it is determined that the first data is data that needs to be protected; and correct the second data according to the second error correction code when it is determined that the second data is data that needs to be protected.

3. The storage device according to claim 2, characterized in that, The ECC circuit is configured to determine whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information. And based on the second address corresponding to the second data and the protection configuration information, determine whether the second data is data that needs to be protected; The protection configuration information includes a mapping relationship between the addresses of storage partitions in the first memory and the addresses of storage partitions in the second memory, wherein the storage partitions of the second memory correspond to the data that needs to be protected.

4. The storage device according to claim 1, characterized in that, The storage controller is configured to output a first address and first data to the ECC circuit; The ECC circuit is further configured to write the first data into a first storage partition of the first memory according to the first address.

5. The storage device according to claim 3 or 4, characterized in that, The ECC circuit is further configured to: when it is determined that the first data is data that needs to be protected, obtain the third address corresponding to the first address; and write the first error correction code into the second storage partition in the second memory according to the third address.

6. The storage device according to claim 3 or 4, characterized in that, The ECC circuit is further configured to write the first data into the first memory when it is determined that the first data is data that does not need to be protected.

7. The storage device according to any one of claims 2 to 4, characterized in that, The memory controller is also configured to output a second address to the ECC circuit; The ECC circuit is further configured to: read the second data from the third storage partition of the first memory according to the second address; and output the second data to the storage controller.

8. The storage device according to claim 7, characterized in that, The ECC circuit is configured to: check the second data according to the second error correction code; if an error is detected, correct the second data and output the corrected second data to the storage controller; if no error is detected, output the second data to the storage controller.

9. The storage device according to claim 7, characterized in that, The ECC circuit is further configured to: when it is determined that the second data is data that needs to be protected, obtain the fourth address corresponding to the second address; and read the second error correction code from the fourth storage partition in the second memory according to the fourth address.

10. The storage device according to any one of claims 2 to 4, 8 to 9, characterized in that, The ECC circuit is configured to output the second data to the storage controller when it is determined that the second data is data that does not need to be protected.

11. The storage device according to any one of claims 1 to 4, 8 to 9, characterized in that, The ECC circuit and the second memory belong to the same die; or, the ECC circuit and the second memory belong to different dies.

12. The storage device according to any one of claims 1 to 4, 8 to 9, characterized in that, The ECC circuit and the memory controller belong to different dies; or, the ECC circuit and the memory controller belong to the same die.

13. The storage device according to any one of claims 1 to 4, 8 to 9, characterized in that, The low-order addresses of each storage partition in the first memory are the same as the storage addresses of each storage partition in the second memory.

14. The storage device according to any one of claims 1 to 4, 8 to 9, characterized in that, The first memory is dynamic random access memory (DRAM), static random access memory (SRAM), or non-volatile memory (NVM).

15. The storage device according to any one of claims 1 to 4, 8 to 9, characterized in that, The second memory is a static random access memory (SRAM).

16. A storage control device, characterized in that, include: Storage controller and error checking and correction (ECC) circuitry; The storage controller is configured to write first data to the first memory and read second data from the first memory; The ECC circuit is configured to: when it is determined that the first data is data that needs to be protected, generate a first error correction code and write the first error correction code into a second memory; And when it is determined that the second data is data that needs to be protected, the second error correction code is read from the second memory, and the second data is corrected according to the second error correction code; The first memory and the second memory belong to different dies.

17. The storage control device according to claim 16, characterized in that, The ECC circuit is configured to determine whether the first data is data that needs to be protected based on the first address corresponding to the first data and preset protection configuration information. And based on the second address corresponding to the second data and the protection configuration information, determine whether the second data is data that needs to be protected; The protection configuration information includes a mapping relationship between the addresses of storage partitions in the first memory and the addresses of storage partitions in the second memory, wherein the storage partitions in the second memory correspond to the data being protected.

18. The storage control device according to claim 16, characterized in that, The storage controller is configured to output a first address and first data to the ECC circuit; The ECC circuit is further configured to write the first data into the first storage partition of the first memory according to the first address.

19. The storage control device according to claim 18, characterized in that, The ECC circuit is further configured to: when it is determined that the first data is data that needs to be protected, obtain the third address corresponding to the first address; and write the first error correction code into the second storage partition in the second memory according to the third address.

20. The storage control device according to any one of claims 16 to 19, characterized in that, The ECC circuit is further configured to write the first data into the first memory when it is determined that the first data is data that does not need to be protected.

21. The storage control device according to any one of claims 16 to 19, characterized in that, The memory controller is also configured to output a second address to the ECC circuit; The ECC circuit is further configured to: read the second data from the third storage partition of the first memory according to the second address; and output the second data to the storage controller.

22. The storage control device according to claim 21, characterized in that, The ECC circuit is configured to: check the second data according to the second error correction code; if an error is detected, correct the second data and output the corrected second data to the storage controller; if no error is detected, output the second data to the storage controller.

23. The storage control device according to claim 21, characterized in that, The ECC circuit is further configured to: when it is determined that the second data is data that needs to be protected, obtain the fourth address corresponding to the second address; and read the second error correction code from the fourth storage partition in the second memory according to the fourth address.

24. The storage control device according to any one of claims 16 to 19, 22 to 23, characterized in that, The ECC circuit is configured to output the second data to the storage controller when it is determined that the second data is data that does not need to be protected.

25. The storage control device according to claim 21, characterized in that, The ECC circuit and the second memory belong to the same die; or, the ECC circuit and the second memory belong to different dies.

26. The storage control device according to any one of claims 16 to 19, 22 to 23, and 25, characterized in that, The ECC circuit and the memory controller belong to different dies; or, the ECC circuit and the memory controller belong to the same die.

27. A system-on-a-chip, characterized in that, include: Processor, bus, and storage device as described in any one of claims 1 to 15; The processor is configured to: output a write instruction and first data to the storage device via the bus, or output a read instruction to the storage device via the bus and receive second data output by the storage device via the bus; The write instruction is used to instruct the writing of the first data to the first memory, and the read instruction is used to instruct the reading of the second data from the second memory.

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