A novel BIST-based FPGA logic resource testing method and structure thereof

Abstract

The present application relates to the field of integrated circuit technology, in particular to a FPGA logic resource test method and structure based on a new BIST, comprising the following steps: determining the measured module BUT and comparison module BUC of the internal resource of the FPGA to be measured; designing the BIST circuit structure based on the hardware description language, namely: designing the test vector generator TPG, measured module BUT, comparison module BUC and output response analyzer ORA four modules of the BIST circuit based on the hardware description language through the EDA design software of the FPGA; constraining the measured module BUT and comparison module BUC modules, namely: position constraint is conducted on the measured module BUT and comparison module BUC based on the EDA design software of the FPGA; generating and downloading the bit stream file and conducting the real installation board level test verification. The present application is used for solving the problems of low test efficiency, too many test configuration times, complex built-in self-test structure, test sequence generated by TPG not random or random but not covering the full address and weak generalization of the existing FPGA internal resource test.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a method and structure for testing FPGA logic resources based on a novel BIST. Background Technology

[0002] FPGA (Field-Programmable Gate Array) has been developed over many years and has been applied in various fields, greatly facilitating people's lives. However, due to its increasing complexity and integration, the reliability issue of FPGAs has become unavoidable. This issue is even more critical in fields with high reliability requirements, such as medical, defense, and aerospace. While various technologies have been developed to address this increasing complexity and integration, FPGA testing has resulted in a significant increase in testing time and cost. Data shows that testing costs now account for more than 50% of FPGA development costs. To address this, current solutions include considering testability during the design phase, thereby reducing testing difficulty and costs in the final product stage. Based on this idea, FPGA testing technology is booming. Therefore, developing a relatively inexpensive, simple, and reliable testing system is imperative.

[0003] Traditional FPGA testing methods involve designing test circuits based on the FPGA's logic resources and architecture, manufacturing test circuit interface boards and dedicated test sockets, and manually performing tests repeatedly. Specifically, this method involves configuring the FPGA's internal circuitry using hardware description language code and generating a bitstream file. EDA (Electronic Design Automation) software then downloads the bitstream file to the FPGA. Next, peripheral circuits on the interface board or automated test equipment generate the corresponding test stimuli. Finally, the output from a digital display or automated test equipment is used to determine if the test response is correct. This entire process is complex and requires manual intervention. Testing all FPGA logic resources requires repeating this process multiple times, making it both time-consuming and costly. Therefore, this invention designs a novel FPGA logic resource testing method based on BIST (Built-in Self-Test). This method embeds BIST circuitry into the existing FPGA test circuitry to perform the corresponding tests, thus solving the aforementioned problems. Summary of the Invention

[0004] The purpose of this invention is to provide an FPGA logic resource testing method and structure based on a novel BIST, which solves the problems of low efficiency in existing FPGA internal resource testing, excessive number of test configurations, complex built-in self-test structures, non-random or random test sequences generated by TPG that cannot cover all addresses, and poor versatility.

[0005] To address the aforementioned technical problems, this invention provides a novel FPGA logic resource testing method based on BIST, comprising the following steps:

[0006] Step 1: Identify the BUT (Browser Under Test) and BUC (Comparison Module) of the internal resources of the FPGA under test;

[0007] Step 2: Design the BIST circuit structure based on the hardware description language, that is: using the FPGA EDA design software, design the four modules of the BIST circuit based on the hardware description language: Test Vector Generator (TPG), Test Module (BUT), Comparison Module (BUC), and Output Response Analyzer (ORA).

[0008] Step 3: Constrain the BUT and BUC modules, i.e., use FPGA-based EDA design software to perform positional constraints on the BUT and BUC modules.

[0009] Step 4: Generate and download the bitstream file and perform on-board testing and verification. Determine the output result based on the on / off status of the signal indicator lights.

[0010] Preferably, the module under test (BUT) in step one is a programmable logic block (CLB), interconnect resource (IR), input / output block (IOB), or block memory (BRAM), and the comparison module (BUC) is ensured to have the same structure as the module under test (BUT).

[0011] Preferably, when it is determined that the module under test (BUT) is a lookup table (LUT) with 6 inputs and 1 output inside the programmable logic block (CLB), that is: the module under test (BUT) is a lookup table (LUT), and the comparison module (BUC) is another identical lookup table (LUT).

[0012] Preferably, the test vector generator (TPG) designed based on a hardware description language is an improved linear shift register. The improved linear shift register includes shift register one, shift register two, shift register three, shift register four, XOR gate one, XOR gate two, and a NOR gate. The output Q of shift register one and the output of XOR gate two are respectively connected as input signals to the two input ports of XOR gate one. The output of XOR gate one is connected to the input D of shift register two. The output Q of shift register two is connected to the input D of shift register three. The output Q of shift register three is connected to the input D of shift register four. The outputs Q of shift register one, shift register two, and shift register three are respectively connected to the three input ports of the NOR gate. The output Q of shift register four and the output of the NOR gate are respectively connected to the two input ports of XOR gate two. This allows for pseudo-random traversal of all addresses, covering addresses from 000000 to 111111, a total of 64 addresses.

[0013] Preferably, the output response analyzer ORA designed based on the hardware description language is a two-input comparator.

[0014] Preferably, when constraining a certain type of FPGA device containing 10,000 lookup tables (LUTs) in step three, the following steps are included:

[0015] Step a) Divide the 10,000 lookup tables (LUTs) to be tested into two equal parts, with the upper part being the module under test (BUT) and the lower part being the comparison module (BUC).

[0016] Step b) When performing the built-in self-test for the first time, only 8000 lookup table LUTs are covered. Among them, the upper half of all 5000 lookup table LUTs are used when constraining the module under test (BUT), and the lower half of 3000 lookup table LUTs are used when constraining the comparison module (BUC). The remaining resources are used to provide layout and routing space for other circuit modules of BIST.

[0017] Step c) When performing the built-in self-test for the second time, the positions of the tested module BUT and the comparison module BUC are swapped, which can achieve 100% test coverage of 10,000 lookup table LUTs.

[0018] Preferably, the specific process of step four is as follows:

[0019] The bitstream file is automatically generated by the FPGA EDA design software and downloaded to the physical board-level FPGA device via the JTAG interface;

[0020] In all resource testing, only three ports are needed at the implementation board level to complete the coverage test: one input clock port, one reset port, and one output monitoring port. The presence of faults in the tested logic resources is determined by the high or low level of the output monitoring port.

[0021] When in the reset phase, the output monitoring port is at a high level;

[0022] During the testing phase, if both the tested module BUT and the comparator module BUC are fault-free, the output monitoring port will be at a low level, the output result will be 0, and the signal indicator will be on. If either the tested module BUT or the comparator module BUC is faulty, the output monitoring port will be at a high level, the output result will be 1, and the signal indicator will be off.

[0023] This invention also provides the following technical solution: a circuit structure for FPGA logic resource testing based on a novel BIST, wherein the FPGA logic resource testing method based on a novel BIST described above is used for testing, including:

[0024] The Test Vector Generator (TPG) is used to generate pseudo-random test sequences with full addresses inside the FPGA, providing test vectors with full addresses and pseudo-random inputs for the module under test (BUT) and the comparison module (BUC).

[0025] The module under test (BUT) is an internal resource of the FPGA to be tested.

[0026] The comparison module BUC uses other FPGA internal resources with the same structure as the module under test BUT.

[0027] The output response analyzer ORA provides comparison and judgment results for the outputs of the module under test (BUT) and the comparison module (BUC).

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] 1. The method of this invention, through the design of a novel BIST circuit structure, adds a comparison module BUC, reduces the need for ORA circuit design, and effectively realizes self-testing of FPGA internal resource modules. Furthermore, for any resource module, 100% coverage can be achieved through two test traversals. Compared with existing BIST circuit structures, there is no need to design a complex ORA circuit structure; it only requires determining whether the outputs of BUT and BUC are consistent. This method offers advantages such as short test design time, strong versatility, high speed, and low cost.

[0030] 2. The method of this invention designs a novel TPG circuit structure that can output a pseudo-random sequence covering the entire address range. Compared with existing counter-based TPGs, the output has excellent pseudo-randomness, and the testing process is closer to the real results. Compared with existing LFSR (Linear Feedback Shift Register)-based TPGs, the output can traverse all 0 addresses, ensuring the accuracy and comprehensiveness of the test results. Attached Figure Description

[0031] Figure 1 This is a flowchart of the test process based on the novel BIST of the present invention.

[0032] Figure 2 This is a schematic diagram of the novel BIST circuit of the present invention.

[0033] Figure 3 This is a schematic diagram of the LUT test principle based on the novel BIST of the present invention.

[0034] Figure 4 This is a circuit diagram of the improved linear shift register of the present invention.

[0035] In the diagram: 1-Test Vector Generator (TPG), 101-Shift Register 1, 102-Shift Register 2, 103-Shift Register 3, 104-Shift Register 4, 105-XOR Gate 1, 106-XOR Gate 2, 107-NOR Gate, 2-Module Under Test (BUT), 3-Comparison Module (BUC), 4-Output Response Analyzer (ORA). Detailed Implementation

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0037] like Figure 1 As shown, an embodiment of the present invention specifically provides an FPGA logic resource testing method based on a novel BIST, comprising the following four steps: determining the BUT and BUC modules of the internal resources of the FPGA under test, designing the BIST circuit structure based on a hardware description language, constraining the BUT and BUC modules, generating a bitstream file and performing on-board level testing and verification, ultimately achieving FPGA resource coverage testing.

[0038] like Figure 2As shown, the circuit structure for FPGA logic resource testing based on the novel BIST includes four modules: TPG (Test Pattern Generator), BUT (Block Under Test), BUC (Block Under Compare), and ORA (Output Response Analyzer). The test pattern generator TPG1 generates a pseudo-random test sequence with full addresses within the FPGA, providing test vectors with full addresses and pseudo-random inputs for the BUT2 module and the BUC3 comparison module. Both the BUT2 and BUC3 modules are internal resource blocks within the FPGA under test and have identical structures. The output response analyzer ORA4 analyzes and compares the final output results of the BUT2 and BUC3 modules. This method generates pseudo-random test sequences within the FPGA through hardware design, thus avoiding the use of automated test equipment and reducing testing costs. Furthermore, the data processing of the output test responses is also completed within the FPGA by the output response analyzer ORA4 circuit, improving data processing speed. During the test, only one alternation between the module under test (BUT2) and the comparison module (BUC3) is needed to achieve 100% coverage of the FPGA's internal resource modules after two configurations.

[0039] In this embodiment of the invention, the steps for determining the tested module BUT2 and BUC of the internal resources of the FPGA under test are specifically implemented as follows: determine the tested BUT inside the FPGA, which can be CLB (Configurationable Logic Block), IR (Interconnect Resource), IOB (Input Output Block), BRAM (Block RAM), etc., and compare the module BUC3 with the tested BUT.

[0040] The specific implementation of the steps for designing the BIST circuit structure based on a hardware description language in this embodiment of the invention is as follows: Using FPGA EDA design software, four modules of the BIST circuit are designed based on a hardware description language: a test vector generator TPG1, a module under test (BUT2), a comparison module (BUC3), and an output response analyzer ORA4. For example... Figure 3 As shown, for a more detailed description, the following explanation focuses on the LUT (Lookup Table) module with 6 inputs and 1 output within the CLB. The BUT module is the LUT itself; the BUC module is another identical LUT.

[0041] The TPG, designed based on a hardware description language, is an improved linear shift register. Its specific implementation structure is as follows: Figure 4 As shown, the improved linear shift register includes shift register 101, shift register 2 102, shift register 3 103, shift register 4 104, XOR gate 105, XOR gate 2 106, and NOR gate 107. The output terminal Q of shift register 101 and the output terminal of XOR gate 2 106 are respectively connected as input signals to the two input ports of XOR gate 105. The output terminal of XOR gate 105 is connected to the input terminal D of shift register 2 102. The output Q of shift register 102 is connected to the input D of shift register 103. The output Q of shift register 103 is connected to the input D of shift register 104. The outputs Q of shift register 101, shift register 102, and shift register 103 are connected to the three-input port of NOR gate 107. The outputs Q of shift register 104 and NOR gate 107 are connected to the two-input port of XOR gate 106. This configuration enables pseudo-random traversal of all addresses, providing random inputs to both BUT and BUC, covering addresses from 000000 to 111111, a total of 64 addresses, ensuring 100% input coverage. The ORA module, designed using a hardware description language, is a two-input comparator that determines whether the outputs from BUT and BUC are consistent. Testing of other internal FPGA resources is similar to that of the LUT.

[0042] The specific implementation of the steps for constraining the BUT and BUC modules in this embodiment of the invention is as follows: To achieve 100% coverage of the module under test, it is necessary to constrain the BUT and BUC. Taking the LUT under test as an example, for a specific model of FPGA device, which contains 10,000 LUT modules, due to placement and routing limitations, it is not possible to achieve test coverage of 5,000 LUTs each for BUT and BUC at once. To achieve 100% coverage testing, the 10,000 LUTs under test are divided equally vertically, with the upper half being the BUT and the lower half being the BUC. During the first built-in self-test, only 8,000 LUTs are covered, with the constrained BUTs using all 5,000 LUTs in the upper half and the constrained BUCs using 3,000 LUTs in the lower half. The remaining resources are used to provide placement and routing space for other circuit modules in the BIST. During the second built-in self-test, the positions of the BUT and BUC are swapped, achieving 100% test coverage of all 10,000 LUTs. In other words, by reasonably constraining the BUT and BUC, full coverage can be achieved with two traversal tests. Other resource constraints within the FPGA are similar to those of the LUT.

[0043] The specific implementation steps for generating the bitstream file and performing on-board level testing and verification in this embodiment of the invention are as follows: After considering the constraints of the built-in self-test circuit design and placement / routing, the bitstream file is automatically generated by the FPGA's EDA design software and downloaded to the on-board FPGA device via the JTAG interface. In all resource tests, only three ports are needed at the on-board level to complete the coverage test: one input clock port, one reset port, and one output monitoring port. The presence of a fault in the tested logic resource is determined by monitoring the level of the output port. During the reset phase, the output port is high. During the testing phase, if both the BUT and BUC are fault-free, the output port is low; if either the BUT or BUC is faulty, the output port is high.

[0044] The purpose of this invention is to address the problems of low testing efficiency, low test coverage, weak versatility, and complex BIST circuit structure in existing FPGA internal resource testing, which lacks random and full address coverage. Furthermore, it proposes a new BIST circuit structure that can cover all test resources using only three ports, effectively improving FPGA resource testing efficiency and coverage. Compared with existing technologies, this invention proposes a novel TPG circuit structure for self-testing of FPGA internal resources, adding a comparator module BUC3 and simplifying ORA circuit design. It offers advantages such as high testing efficiency, fewer configuration steps, simple BIST structure, and strong versatility for different FPGA internal resources, effectively improving FPGA resource testing efficiency and coverage.

[0045] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for testing FPGA logic resources based on a novel BIST, characterized in that, Includes the following steps: Step 1: Identify the BUT (Browser Under Test) and BUC (Comparison Module) of the internal resources of the FPGA under test; Step 2: Design the BIST circuit structure based on the hardware description language. Using the FPGA's EDA design software, design the four modules of the BIST circuit based on the hardware description language: Test Vector Generator (TPG), Module Under Test (BUT), Comparison Module (BUC), and Output Response Analyzer (ORA). Step 3: Constrain the BUT and BUC modules; use FPGA-based EDA design software to perform positional constraints on the BUT and BUC modules. Step 4: Generate and download the bitstream file and perform on-board testing and verification. Determine the output result based on the on / off status of the signal indicator lights. The test vector generator TPG designed based on the hardware description language is an improved linear shift register. The improved linear shift register includes shift register 1, shift register 2, shift register 3, shift register 4, XOR gate 1, XOR gate 2, and NOR gate. The output terminal Q of shift register 1 and the output terminal of XOR gate 2 are respectively connected to the two input ports of XOR gate 1 as input signals. The output terminal of XOR gate 1 is connected to the input terminal D of shift register 2. The output terminal Q of shift register 2 is connected to the input terminal D of shift register 3. The output terminal Q of shift register 3 is connected to the input terminal D of shift register 4. The output terminals Q of shift register 1, shift register 2, and shift register 3 are respectively connected to the three input ports of NOR gate. The output terminal Q of shift register 4 and the output terminal of NOR gate are respectively connected to the two input ports of XOR gate 2. When constraining a specific type of FPGA device that contains 10,000 lookup tables (LUTs) in step three, the following steps are included: Step a) Divide the 10,000 lookup tables (LUTs) to be tested into two equal parts, with the upper part being the module under test (BUT) and the lower part being the comparison module (BUC). Step b) When performing the built-in self-test for the first time, only 8000 lookup table LUTs are covered. Among them, the upper half of all 5000 lookup table LUTs are used when constraining the module under test (BUT), and the lower half of 3000 lookup table LUTs are used when constraining the comparison module (BUC). The remaining resources are used to provide layout and routing space for other circuit modules of BIST. Step c) When performing the built-in self-test for the second time, the positions of the tested module BUT and the comparison module BUC are swapped, which can achieve 100% test coverage of 10,000 lookup table LUTs.

2. The FPGA logic resource testing method based on a novel BIST as described in claim 1, characterized in that, The module under test (BUT) in step one is a programmable logic block (CLB), interconnect resource (IR), input / output block (IOB), or block memory (BRAM), and the comparison module (BUC) is guaranteed to have the same structure as the module under test (BUT).

3. The FPGA logic resource testing method based on a novel BIST as described in claim 2, characterized in that, When it is determined that the module under test (BUT) is a lookup table (LUT) with 6 inputs and 1 output inside the programmable logic block (CLB), the module under test (BUT) is a lookup table (LUT), and the comparison module (BUC) is another identical lookup table (LUT).

4. The FPGA logic resource testing method based on a novel BIST as described in claim 1, characterized in that, The output response analyzer ORA, designed based on a hardware description language, is a two-input comparator.

5. The FPGA logic resource testing method based on a novel BIST as described in claim 1, characterized in that, The specific process of step four is as follows: The bitstream file is automatically generated by the FPGA EDA design software and downloaded to the physical board-level FPGA device via the JTAG interface; In all resource testing, only three ports are needed at the implementation board level to complete the coverage test: one input clock port, one reset port, and one output monitoring port. The presence of faults in the tested logic resources is determined by the high or low level of the output monitoring port. When in the reset phase, the output monitoring port is at a high level; During the testing phase, if both the tested module BUT and the comparator module BUC are fault-free, the output monitoring port will be at a low level, the output result will be 0, and the signal indicator will be on. If either the tested module BUT or the comparator module BUC is faulty, the output monitoring port will be at a high level, the output result will be 1, and the signal indicator will be off.

6. A circuit structure for FPGA logic resource testing based on a novel BIST, wherein the FPGA logic resource testing method based on a novel BIST as described in any one of claims 1-5 is used for testing, characterized in that, include: The Test Vector Generator (TPG) is used to generate pseudo-random test sequences with full addresses inside the FPGA, providing test vectors with full addresses and pseudo-random inputs for the module under test (BUT) and the comparison module (BUC). The module under test (BUT) is an internal resource of the FPGA to be tested. The comparison module BUC uses other FPGA internal resources with the same structure as the module under test BUT. The output response analyzer ORA provides comparison and judgment results for the outputs of the module under test (BUT) and the comparison module (BUC).

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