Signal line structure, signal line driving method, and signal line circuit

Abstract

The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes: a plurality of parallel signal lines, and each of the signal lines maintains a driving state at any moment. Embodiments of the present disclosure can save components and area of wiring and related circuits while maintaining high-speed and stable signal transmission.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit manufacturing technology, and more particularly, to a signal line structure, a signal line driving method, and a signal line circuit. Background Art

[0002] In a normal data path, due to the random direction of data transitions, crosstalk exists between adjacent parallel different signal lines, affecting data timing. In some cases, grounded traces are inserted for isolation to ensure timing consistency during data transitions. In addition, sometimes a keeper needs to be set to reduce the crosstalk effect between signal lines. The isolation traces and the keeper both occupy additional track and layout area, resulting in a large layout area for signal lines.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a signal line structure, a signal line driving method, and a signal line circuit, which are used to at least to some extent improve the signal quality on the signal line and save the layout area of parallel signal lines.

[0005] According to a first aspect of the present disclosure, there is provided a signal line structure, including: a plurality of parallel signal lines, and each of the signal lines maintains a driving state at any moment.

[0006] In an exemplary embodiment of the present disclosure, each end of each signal line is respectively connected to a first driver and a second driver, and at the same moment, only one of the first driver and the second driver of the same signal line maintains a driving state.

[0007] In an exemplary embodiment of the present disclosure, the first driver maintains a driving state when a first enable signal is at a first level, and maintains a high impedance state when the first enable signal is at a second level; the second driver maintains a driving state when a second enable signal is at the first level, and maintains a high impedance state when the second enable signal is at the second level.

[0008] In an exemplary embodiment of the present disclosure, the first level is a high level, and the second level is a low level.

[0009] In an exemplary embodiment of the present disclosure, the second enable signal is obtained by inverting the first enable signal through an inverter.

[0010] In an exemplary embodiment of the present disclosure, the first driver or the second driver includes at least one gated inverter. An input terminal of the gated inverter is electrically connected to an input signal, an enable terminal is connected to the first enable signal or the second enable signal, and an output terminal is electrically connected to the signal line.

[0011] In an exemplary embodiment of the present disclosure, the multiple parallel signal lines include odd data lines and even data lines arranged in an interleaved manner. The odd data lines are used to transmit odd signals sampled according to an odd clock, and the even data lines are used to transmit even signals sampled according to an even clock. The phase difference between the odd clock and the even clock is 180 degrees; the first enable signals corresponding to the odd data lines and the first enable signals corresponding to the even data lines have different phases, and the second enable signals corresponding to the odd data lines and the second enable signals corresponding to the even data lines have different phases.

[0012] In an exemplary embodiment of the present disclosure, the first enable signals corresponding to the odd data lines and the first enable signals corresponding to the even data lines have a phase difference of 180 degrees, and the second enable signals corresponding to the odd data lines and the second enable signals corresponding to the even data lines have a phase difference of 180 degrees.

[0013] According to a second aspect of the present disclosure, there is provided a signal line driving method, which is applied to the signal line structure as described in any one of the above, and includes: controlling multiple parallel signal lines to maintain a driving state at any moment.

[0014] In an exemplary embodiment of the present disclosure, a first driver and a second driver are respectively arranged at both ends of each signal line. The controlling the multiple parallel signal lines to maintain a driving state at any moment includes: controlling that at the same moment, only one of the first driver and the second driver of the same signal line maintains a driving state.

[0015] In an exemplary embodiment of the present disclosure, the first driver or the second driver includes at least one gated inverter. The input terminal of the gated inverter is electrically connected to an input signal, the enable terminal is connected to a first enable signal or a second enable signal, and the output terminal is electrically connected to the signal line. Only one of the first driver and the second driver that controls the same signal line maintains a driving state at the same time, which includes: inputting a first enable signal with a first level to the enable terminal of the first driver at the same time to make the first driver maintain a driving state, and inputting a second enable signal with a second level to the enable terminal of the second driver to make the second driver maintain a high-impedance state; or, inputting a first enable signal with a second level to the enable terminal of the first driver at the same time to make the first driver maintain a high-impedance state, and inputting a second enable signal with a first level to the enable terminal of the second driver to make the second driver maintain a driving state.

[0016] In an exemplary embodiment of the present disclosure, the input terminal of the first driver is used to receive a first input signal, the enable terminal is connected to a first node, and the output terminal is connected to the signal line. The input terminal of the second driver is used to receive a second input signal, the enable terminal is connected to a second node, and the output terminal is connected to the signal line. The first node is used to receive a driver enable signal, and the second node and the first node are connected by an odd number of inverters. Only one of the first driver and the second driver that controls the first driver and the second driver maintains a driving state at the same time, which includes: in response to a first input signal arrival message, setting the driver enable signal to a first level to make the first driver maintain a driving state and the second driver maintain a high-impedance state; in response to a second input signal arrival message, setting the driver enable signal to a second level to make the second driver maintain a driving state and the first driver maintain a high-impedance state.

[0017] In an exemplary embodiment of the present disclosure, the first level is a high level and the second level is a low level.

[0018] In an exemplary embodiment of the present disclosure, a first driver and a second driver are respectively disposed at both ends of each of the signal lines. The multiple signal lines include odd data lines and even data lines. Maintaining the driving state of the parallel signal lines at any moment includes: inputting a first enable signal with a first level to the first driver of the same odd data line, and inputting a second enable signal with a second level to the second driver to maintain the driving state of the odd data line; or inputting a first enable signal with a second level to the first driver of the same odd data line, and inputting a second enable signal with a first level to the second driver to maintain the driving state of the odd data line; inputting a first enable signal with a first level to the first driver of the same even data line, and inputting a second enable signal with a second level to the second driver to maintain the driving state of the odd data line; or inputting a first enable signal with a second level to the first driver of the same even data line, and inputting a second enable signal with a first level to the second driver to maintain the driving state of the odd data line; the first enable signal corresponding to the odd data line and the first enable signal corresponding to the even data line have different phases, and the second enable signal corresponding to the odd data line and the second enable signal corresponding to the even data line have different phases.

[0019] According to a third aspect of the present disclosure, a signal line circuit is provided, including: a first driver, an input end for receiving a first input signal, an enable end connected to a first node, and an output end connected to the signal line; a second driver, an input end for receiving a second input signal, an enable end connected to a second node, and an output end connected to the signal line; an inverter, an input end connected to the first node, and an output end connected to the second node. The first node is used to receive a driver enable signal, and the driver enable signal includes a first level and a second level. The first level is used to control the first driver to maintain the driving state and the second driver to maintain the high-impedance state, and the second level is used to control the second driver to maintain the driving state and the first driver to maintain the high-impedance state.

[0020] By setting the signal lines to maintain the driving state in the embodiments of the present disclosure, when multiple signal lines are arranged in parallel, crosstalk between the signal lines can be avoided from causing errors in the transmitted data, and there is no need to set isolation traces and state holders, which can greatly save the layout occupation area of the signal lines.

[0021] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic diagram of the signal line structure in an exemplary embodiment of the present disclosure.

[0024] Figure 2 It is a schematic diagram of the driving method of a signal line in an embodiment of the present disclosure.

[0025] Figure 3A It is a schematic diagram of crosstalk between two adjacent signal lines in the related art.

[0026] Figure 3B It is a schematic diagram of crosstalk between two adjacent signal lines in an embodiment of the present disclosure.

[0027] Figure 4 It is a schematic circuit diagram of the first driver and the second driver of a signal line in an embodiment of the present disclosure.

[0028] Figure 5 It is in an embodiment of the present disclosure Figure 4 A schematic diagram of the connection relationship of the shown first enable signal and second enable signal.

[0029] Figure 6 It is a schematic diagram of the setting of a signal line in an embodiment of the present disclosure.

[0030] Figure 7 It is Figure 6 The signal timing diagram corresponding to the shown signal line setting method.

[0031] Figure 8 It is a schematic diagram of a signal line driving method in an embodiment of the present disclosure.

[0032] Figure 9 It is a schematic diagram of a signal line circuit provided by an exemplary embodiment of the present disclosure. Detailed implementation manners

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will recognize that one or more of the specific details may be omitted, or other methods, components, devices, steps, etc. may be used. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring aspects of the present disclosure.

[0034] In addition, the drawings are only schematic illustrations of the present disclosure, and the same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0035] The example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0036] Figure 1 It is a schematic diagram of the signal line structure in an exemplary embodiment of the present disclosure.

[0037] Referring to Figure 1 , the signal line structure 100 may include:

[0038] Multiple parallel signal lines S1 to Sn, and each signal line maintains a driving state at any given time.

[0039] Compared with the related art, there is no need to provide isolation tracks between the multiple parallel signal lines S1 to Sn, nor is it necessary to provide a keeper after transmitting the signal, which can effectively save the wiring area. Since each signal line maintains a driving state at any given time, crosstalk between the parallel signal lines will not cause signal inversion of the signal lines, which can effectively improve the signal stability and avoid the increase in crosstalk, signal inversion on the signal lines, and transmission errors caused by high-density wiring. Therefore, the embodiments of the present disclosure can improve the signal stability while reducing the high-density wiring area.

[0040] There are various ways to control each signal line to maintain a driving state at any given time, and some embodiments will be described below with reference to the drawings.

[0041] Figure 2 It is a schematic diagram of the driving method of a signal line in an embodiment of the present disclosure.

[0042] Referring to Figure 2 , in an exemplary embodiment of the present disclosure, two ends of a signal line S1 are respectively connected to a first driver 11 and a second driver 12, and at the same moment, only one of the first driver 11 and the second driver 12 of the signal line S1 maintains a driving state. The signal line S2 is adjacent to the signal line S1 in parallel, two ends of the signal line S2 are respectively connected to a first driver 21 and a second driver 22, and at the same moment, only one of the first driver 21 and the second driver 22 of the signal line S2 maintains a driving state.

[0043] Continuing to refer to Figure 2 , in an embodiment, the first driver 11 of the signal line S1 maintains a driving state when a first enable signal EN11 is at a first level, and maintains a high-impedance state when the first enable signal EN11 is at a second level; the second driver 12 maintains a driving state when a second enable signal EN12 is at a first level, and maintains a high-impedance state when the second enable signal EN12 is at a second level. When the first enable signal EN11 and the second enable signal EN12 are controlled by two levels, the first level is, for example, a high level, and the second level is, for example, a low level. Alternatively, the first level is, for example, a low level, and the second level is, for example, a high level. The high level is, for example, a state greater than or equal to the power supply voltage, and the low level is, for example, a state less than or equal to the ground voltage. Here, the high level and the low level are relative, and the specific voltage range included needs to be determined according to specific devices. For example, for an N-type field-effect transistor, the high level refers to the gate voltage range that can make it conduct, and the low level refers to the gate voltage range that can make it turn off; for a P-type field-effect transistor, the low level refers to the gate voltage range that can make it conduct, and the high level refers to the gate voltage range that can make it turn off.

[0044] Correspondingly, the first driver 21 of the signal line S2 maintains a driving state when a first enable signal EN21 is at a first level, and maintains a high-impedance state when the first enable signal EN21 is at a second level; the second driver 22 maintains a driving state when a second enable signal EN22 is at a first level, and maintains a high-impedance state when the second enable signal EN22 is at a second level.

[0045] Figure 3A It is a schematic diagram of crosstalk between two adjacent signal lines in the related art.

[0046] Figure 3B It is a schematic diagram of crosstalk between two adjacent signal lines in an embodiment of the present disclosure.

[0047] In Figure 3A and Figure 3BAmong them, signal line S1 and signal line S2 are two adjacent parallel signal lines. The first enable signal corresponding to signal line S1 is EN11, and the second enable signal is EN12; the first enable signal corresponding to signal line S2 is EN21, and the second enable signal is EN22.

[0048] Reference Figure 3A , in the related art, at the first moment T1, a high-level pulse appears in the first enable signal EN11 corresponding to signal line S1, and signal line S1 is driven by the first driver 11 to generate signal A. At the same time, the first driver 21 and the second driver 22 at both ends of signal line S2 adjacent and parallel to signal line S1 are both in a high-impedance state and have no driving ability for signal line S2. Affected by signal A, a crosstalk error EA appears on signal line S2. At the second moment T2, a high-level pulse appears in the first enable signal EN21 corresponding to signal line S2, and signal line S2 is driven by the first driver 21 to generate signal B. At the same time, the first driver 11 and the second driver 12 at both ends of signal line S1 adjacent and parallel to signal line S2 are both in a high-impedance state and have no driving ability for signal line S1. Affected by signal B, a crosstalk error EB appears on signal line S1.

[0049] Similarly, at the third moment T3, when a high-level pulse appears in the second enable signal EN12 corresponding to signal line S1, signal line S1 is driven by the second driver 12 to generate a signal flip (signal C), which affects the state of signal B on signal line S2, and a crosstalk error EC appears on signal line S2. At the fourth moment T4, when a high-level pulse appears in the second enable signal EN22 corresponding to signal line S2, signal line S2 is driven by the second driver 22 to generate a signal flip, which affects the state of signal C on signal line S1, and a crosstalk error also appears.

[0050] Therefore, in the related art, crosstalk is likely to occur between two adjacent parallel signal lines, resulting in data transmission errors.

[0051] Reference Figure 3B , in the embodiment of the present disclosure, only one of the first enable signal EN11 and the second enable signal EN12 of signal line S1 is at a high level at the same time, and only one of the first enable signal EN21 and the second enable signal EN22 of signal line S2 is at a high level at the same time.

[0052] At the second moment T2, the first enable signal EN21 of the signal line S2 becomes high level, the first driver 21 of the signal line S2 becomes the driving state, and data inversion appears on the signal line S2. Since the first enable signal EN11 of the signal line S1 is also high level at this time, the first driver 11 of the signal line S1 is also in the driving state, and the data signal on the signal line S1 is less affected by crosstalk (point D). At the third moment T3, the second enable signal EN12 of the signal line S1 becomes high level, the second driver 12 of the signal line S1 becomes the driving state, and data inversion appears on the signal line S2. Since the first enable signal EN21 of the signal line S2 is also high level at this time, the first driver 21 of the signal line S2 is also in the driving state, and the data signal on the signal line S2 is less affected by crosstalk (point E). By the same token, it can be deduced that at the first moment T1 and the fourth moment T4, the data signals on the signal line S1 and the signal line S2 are also less affected by crosstalk.

[0053] Therefore, by maintaining that only one of the drivers at both ends of the signal line is in the driving state at any moment, the crosstalk influence of the data inversion of the parallel adjacent signal lines on the signal on the signal line can be reduced, and the signal stability can be maintained. That is, by using the method provided by the embodiment of the present disclosure to control the driver of the signal line, the signal stability can be maintained without setting isolation tracks and state maintainers between the signal lines, which can greatly save the wiring area.

[0054] Figure 4 It is a circuit schematic diagram of the first driver and the second driver of the signal line in an embodiment of the present disclosure.

[0055] Reference Figure 4 In an embodiment of the present disclosure, the first driver 11 or the second driver 12 of the signal line S1 includes at least one gated inverter.

[0056] In Figure 4 In the illustrated embodiment, the input end of the first gated inverter 111 in the first driver 11 is electrically connected to the first input signal IN11, the enable end is connected to the first enable signal EN11, and the output end is electrically connected to the signal line S1. The input end of the second gated inverter 121 in the second driver 12 is electrically connected to the second input signal IN12, the enable end is connected to the second enable signal EN12, and the output end is electrically connected to the signal line S1.

[0057] The first gated inverter 111 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4 connected in sequence through connections. Both the first transistor M1 and the second transistor M2 are P-type transistors, and the source of the first transistor M1 is connected to the power supply voltage Vcc. Both the third transistor M3 and the fourth transistor M4 are N-type transistors, and the source of the fourth transistor M4 is grounded. The gates of the first transistor M1 and the fourth transistor M4 are connected to each other and serve as the input terminal of the first gated inverter 111, electrically connected to the first input signal IN1. The gate of the second transistor M2 is connected to the output terminal of the inverter INV1, the input terminal of the inverter INV1 is connected to the gate of the third transistor M3, and the gate of the third transistor M3 serves as the enable terminal of the first gated inverter 111 and is connected to the first enable signal EN11.

[0058] The second gated inverter 121 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8 connected in sequence through connections. Both the fifth transistor M5 and the sixth transistor M6 are P-type transistors, and the source of the fifth transistor M5 is connected to the power supply voltage Vcc. Both the seventh transistor M7 and the eighth transistor M8 are N-type transistors, and the source of the eighth transistor M8 is grounded. The gates of the fifth transistor M5 and the eighth transistor M8 are connected to each other and serve as the input terminal of the second gated inverter 121, electrically connected to the first input signal IN1. The gate of the sixth transistor M6 is connected to the output terminal of the inverter INV2, the input terminal of the inverter INV2 is connected to the gate of the seventh transistor M7, and the gate of the seventh transistor M7 serves as the enable terminal of the second gated inverter 121 and is connected to the second enable signal EN12.

[0059] When the first enable signal EN11 is at a high level, both the second transistor M2 and the third transistor M3 in the first gated inverter 111 are turned on, and the first gated inverter 111 is in a driving state, and the signal on the signal line S1 changes with the first input signal IN11. When the first enable signal EN11 is at a low level, both the second transistor M2 and the third transistor M3 in the first gated inverter 111 are turned off, and the first gated inverter 111 is in a high-impedance state, and the signal on the signal line S1 does not change with the first input signal IN11.

[0060] Similarly, when the second enable signal EN12 is at a high level, both the sixth transistor M6 and the seventh transistor M7 in the second gated inverter 121 are turned on, and the second gated inverter 121 is in a driving state, and the signal on the signal line S1 changes with the second input signal IN12. When the second enable signal EN12 is at a low level, both the sixth transistor M6 and the seventh transistor M7 in the second gated inverter 121 are turned off, and the second gated inverter 121 is in a high-impedance state, and the signal on the signal line S1 does not change with the second input signal IN12.

[0061] When it is set that only one of the first driver 11 and the second driver 12 maintains the driving state at the same time, it can be set that only one of the first enable signal EN11 and the second enable signal EN12 is at a high level at the same time, as Figure 3B shown. In an exemplary embodiment of the present disclosure, the second enable signal EN12 can be obtained by inverting the first enable signal EN11 through an inverter.

[0062] The number of gated inverters in both the first driver 11 and the second driver 12 can be one or more, Figure 4 which is only an example, and the present disclosure does not impose special restrictions on this.

[0063] Figure 5 is a schematic diagram of the connection relationship between the first enable signal and the second enable signal in an embodiment of the present disclosure Figure 4 as shown.

[0064] Referring to Figure 5 , in an exemplary embodiment of the present disclosure, the input end of the first driver 11 is used to receive the first input signal IN11, the enable end is connected to the first node N1, the output end is connected to the signal line S1, the input end of the second driver 12 is used to receive the second input signal IN12, the enable end is connected to the second node N2, the output end is connected to the signal line S1, the first node N1 is used to receive the driver enable signal DRV, and the second node N2 and the first node N1 are connected through an odd number of inverters INV0 ( Figure 5 only one is shown).

[0065] In Figure 5 the shown embodiment, the drive enable signal DRV can control that only one of the first driver 11 and the second driver 12 maintains the driving state at the same time when it is in a high level state or a low level state.

[0066] Figure 6 is a schematic diagram of the setting of the signal line in an embodiment of the present disclosure.

[0067] Referring to Figure 6 , in an exemplary embodiment of the present disclosure, multiple parallel signal lines include odd data lines 61 and even data lines 62 arranged alternately. The odd data lines 61 are used to transmit odd signals sampled according to an odd clock, the even data lines 62 are used to transmit even signals sampled according to an even clock, and the phase difference between the odd clock and the even clock is 180 degrees. The first enable signal EN11 corresponding to the odd data lines 61 and the first enable signal EN21 corresponding to the even data lines 62 have different phases, and the second enable signal EN12 corresponding to the odd data lines 61 and the second enable signal EN22 corresponding to the even data lines 62 have different phases.

[0068] Figure 7 is Figure 6The signal timing diagram corresponding to the shown signal line setting method.

[0069] Reference Figure 7 , in an exemplary embodiment of the present disclosure, the transmission periods of both odd data and even data are T, and the transmission interval between odd data and even data is T / 2, that is, the phases of odd data and even data differ by 180 degrees.

[0070] At the first moment T1, when the rising edge of the first enable signal EN11 corresponding to the odd data line 61 appears, the falling edge of the second enable signal EN12 corresponding to the odd data line 61 appears. The first driver 11 corresponding to the odd data line 61 becomes the driving state, and the second driver 12 becomes the high-impedance state. The signal on the odd data line 61 is controlled by the input signal of the first driver 11; at the third moment T3, when the rising edge of the second enable signal EN12 corresponding to the odd data line 61 appears, the falling edge of the first enable signal EN11 corresponding to the odd data line 61 appears. The second driver 12 corresponding to the odd data line 61 becomes the driving state, and the first driver 11 becomes the high-impedance state. The signal on the odd data line 61 is controlled by the input signal of the second driver 12; at the second moment T2, when the rising edge of the first enable signal EN21 corresponding to the even data line 62 appears, the falling edge of the second enable signal EN22 corresponding to the even data line 62 appears. The first driver 21 corresponding to the even data line 62 becomes the driving state, and the second driver 22 becomes the high-impedance state. The signal on the even data line 62 is controlled by the input signal of the first driver 21; at the fourth moment T4, when the rising edge of the second enable signal EN22 corresponding to the even data line 62 appears, the falling edge of the first enable signal EN21 corresponding to the even data line 62 appears. The second driver 22 corresponding to the even data line 62 becomes the driving state, and the first driver 21 becomes the high-impedance state. The signal on the even data line 62 is controlled by the input signal of the second driver 22.

[0071] The phase difference between the first enable signal EN11 corresponding to the odd data line 61 and the first enable signal EN21 corresponding to the even data line 62 is 180 degrees (T / 2), and the phase difference between the second enable signal EN12 corresponding to the odd data line 61 and the second enable signal EN22 corresponding to the even data line 62 is 180 degrees (T / 2). At the same moment, only one of the first enable signal EN11 and the second enable signal EN12 corresponding to the odd data line 61 maintains a high level; only one of the first enable signal EN21 and the second enable signal EN22 corresponding to the even data line 62 maintains a high level.

[0072] By controlling the odd data line 61 and the even data line 62 to maintain the driving state at any moment, the mutual influence between the alternately transmitted odd data and even data can be avoided, and the data reliability can be improved.

[0073] Figure 8It is a schematic diagram of a signal line driving method in an embodiment of the present disclosure.

[0074] The signal line driving method 800 can be applied to the signal line structure shown in any of the above embodiments.

[0075] Referring Figure 8 , the signal line driving method 800 may include: Step S10, controlling a plurality of parallel signal lines to maintain a driving state at any moment.

[0076] In an exemplary embodiment of the present disclosure, a first driver and a second driver are respectively arranged at both ends of each signal line. Controlling the parallel signal lines to maintain a driving state at any moment includes: controlling that only one of the first driver and the second driver of the same signal line maintains a driving state at the same moment.

[0077] In an exemplary embodiment of the present disclosure, the first driver or the second driver includes at least one gated inverter. The input end of the gated inverter is electrically connected to an input signal, the enable end is connected to a first enable signal or a second enable signal, and the output end is electrically connected to the signal line. Controlling that only one of the first driver and the second driver of the same signal line maintains a driving state at the same moment includes: inputting a first enable signal with a first level to the enable end of the first driver at the same moment to make the first driver maintain a driving state, and inputting a second enable signal with a second level to the enable end of the second driver to make the second driver maintain a high-impedance state; or, inputting a first enable signal with a second level to the enable end of the first driver at the same moment to make the first driver maintain a high-impedance state, and inputting a second enable signal with a first level to the enable end of the second driver to make the second driver maintain a driving state.

[0078] In an exemplary embodiment of the present disclosure, the input end of the first driver is used to receive a first input signal, the enable end is connected to a first node, the output end is connected to the signal line, the input end of the second driver is used to receive a second input signal, the enable end is connected to a second node, the output end is connected to the signal line, the first node is used to receive a driver enable signal, and the second node and the first node are connected by an odd number of inverters. Controlling that only one of the first driver and the second driver maintains a driving state at the same moment includes: in response to the arrival message of the first input signal, setting the driver enable signal to a first level to make the first driver maintain a driving state and the second driver maintain a high-impedance state; in response to the arrival message of the second input signal, setting the driver enable signal to a second level to make the second driver maintain a driving state and the first driver maintain a high-impedance state. In an exemplary embodiment of the present disclosure, the first level is a high level and the second level is a low level.

[0079] In an exemplary embodiment of the present disclosure, a first driver and a second driver are respectively provided at both ends of each signal line. The multiple signal lines include odd data lines and even data lines. Controlling the parallel signal lines to maintain a driving state at any moment includes: inputting a first enable signal of a first level to the first driver of the same odd data line, and inputting a second enable signal of a second level to the second driver to maintain the driving state of the odd data line; or inputting a first enable signal of a second level to the first driver of the same odd data line, and inputting a second enable signal of a first level to the second driver to maintain the driving state of the odd data line; inputting a first enable signal of a first level to the first driver of the same even data line, and inputting a second enable signal of a second level to the second driver to maintain the driving state of the odd data line; or inputting a first enable signal of a second level to the first driver of the same even data line, and inputting a second enable signal of a first level to the second driver to maintain the driving state of the odd data line; the first enable signal corresponding to the odd data line and the first enable signal corresponding to the even data line have different phases, and the second enable signal corresponding to the odd data line and the second enable signal corresponding to the even data line have different phases.

[0080] The relevant principle of the signal driving method 800 has been explained in Figures 1 to 7 the embodiments shown, and the present disclosure will not repeat it here.

[0081] Figure 9 is a schematic diagram of a signal line circuit provided by an exemplary embodiment of the present disclosure.

[0082] Refer to Figure 9 , the signal line circuit 900 includes:

[0083] A first driver 91, whose input end is used to receive a first input signal IN11, the enable end is connected to a first node N1, and the output end is connected to a signal line 90;

[0084] A second driver 92, whose input end is used to receive a second input signal IN12, the enable end is connected to a second node N2, and the output end is connected to the signal line 90;

[0085] An inverter INV, whose input end is connected to the first node N1, and the output end is connected to the second node N2. The first node is used to receive a driver enable signal DRV. The driver enable signal DRV includes a first level and a second level. The first level is used to control the first driver 11 to maintain a driving state and the second driver 12 to maintain a high impedance state, and the second level is used to control the second driver 12 to maintain a driving state and the first driver 11 to maintain a high impedance state.

[0086] Figure 9The signal line circuit 900 shown can ensure that when the driver enable signal DRV is in the high level state or the low level state, only one of the first driver 91 and the second driver 92 can maintain the driving state. Thus, there is no need to provide an isolation track and a state maintainer for the signal line 90, and it is also possible to avoid the influence of the level inversion on the parallel adjacent signal lines on the signal line 90. Therefore, the signal line circuit 900 has a smaller wiring area.

[0087] It should be noted that although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0088] Those skilled in the art will readily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and examples are only considered exemplary, and the true scope and concept of the present disclosure are pointed out by the claims.

Claims

1. A signal line structure, characterized in that, Comprising: Multiple parallel signal lines, each of which maintains a driving state at any given moment; Both ends of each of the signal lines are respectively connected to a first driver and a second driver. At the same moment, only one of the first driver and the second driver of the same signal line maintains a driving state; The first driver maintains a driving state when the first enable signal is at a first level and maintains a high impedance state when the first enable signal is at a second level; the second driver maintains a driving state when the second enable signal is at the first level and maintains a high impedance state when the second enable signal is at the second level; The multiple parallel signal lines include odd data lines and even data lines arranged alternately. The odd data lines are used to transmit odd signals sampled according to an odd clock, and the even data lines are used to transmit even signals sampled according to an even clock. The phase difference between the odd clock and the even clock is 180 degrees; the first enable signals corresponding to the odd data lines and the first enable signals corresponding to the even data lines have different phases, and the second enable signals corresponding to the odd data lines and the second enable signals corresponding to the even data lines have different phases.

2. The signal line structure according to claim 1, wherein The first level is a high level, and the second level is a low level.

3. The signal line structure according to claim 1, wherein The second enable signal is obtained by inverting the first enable signal through an inverter.

4. The signal line structure according to any one of claims 1 to 3, characterized in that, The first driver or the second driver includes at least one gated inverter. The input end of the gated inverter is electrically connected to an input signal, the enable end is connected to the first enable signal or the second enable signal, and the output end is electrically connected to the signal line.

5. The signal line structure according to claim 1, wherein, The first enable signals corresponding to the odd data lines and the first enable signals corresponding to the even data lines have a phase difference of 180 degrees, and the second enable signals corresponding to the odd data lines and the second enable signals corresponding to the even data lines have a phase difference of 180 degrees.

6. A signal line driving method, characterized in that, Applied to the signal line structure according to any one of claims 1 to 5, comprising: Controlling multiple parallel signal lines to maintain a driving state at any given moment; A first driver and a second driver are respectively arranged at both ends of each of the signal lines. The multiple signal lines include odd data lines and even data lines. The controlling the multiple parallel signal lines to maintain a driving state at any given moment includes: Input a first enable signal of a first level to the first driver of the same odd data line, and input a second enable signal of a second level to the second driver to maintain the driving state of the odd data line; or input a first enable signal of the second level to the first driver of the same odd data line, and input a second enable signal of the first level to the second driver to maintain the driving state of the odd data line; input a first enable signal of the first level to the first driver of the same even data line, and input a second enable signal of the second level to the second driver to maintain the driving state of the odd data line; or input a first enable signal of the second level to the first driver of the same even data line, and input a second enable signal of the first level to the second driver to maintain the driving state of the odd data line; the first enable signal corresponding to the odd data line and the first enable signal corresponding to the even data line have different phases, and the second enable signal corresponding to the odd data line and the second enable signal corresponding to the even data line have different phases.

7. The signal line driving method according to claim 6, wherein The input end of the first driver is used to receive a first input signal, the enable end is connected to a first node, and the output end is connected to the signal line. The input end of the second driver is used to receive a second input signal, the enable end is connected to a second node, and the output end is connected to the signal line. The first node is used to receive a driver enable signal. The second node and the first node are connected by an odd number of inverters. Controlling that only one of the first driver and the second driver maintains the driving state at the same time includes: In response to the arrival message of the first input signal, set the driver enable signal to the first level to maintain the driving state of the first driver and the high-impedance state of the second driver; In response to the arrival message of the second input signal, set the driver enable signal to the second level to maintain the driving state of the second driver and the high-impedance state of the first driver.

8. The signal line driving method according to claim 6, characterized in that, The first level is a high level, and the second level is a low level.

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