Semiconductor structure and method of manufacturing the same

Abstract

This disclosure relates to a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a substrate including a first doped region; a first isolation structure located within the first doped region, with a depth greater than the depth of the first doped region; a first gate structure located on the substrate surface of the first doped region, spanning the first isolation structure, with a projected width of the first gate structure on the substrate greater than the projected width of the first isolation structure on the substrate; and a second gate structure located on the substrate surface, situated on both sides of the first gate structure. This disclosure facilitates the reduction of semiconductor device dimensions.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a method for manufacturing the same. Background Technology

[0002] One-time programmable (OTP) memory is a type of non-volatile memory that supports one-time programming and is widely used in analog circuits, digital / SoC chips, SRAM / DRAM memories, and other fields. One-time anti-fuse programmable memory is a type of OTP memory. In its unprogrammed state, anti-fuse memory exhibits a high resistance due to the presence of an insulating dielectric layer. After programming, the insulating dielectric layer breaks down, resulting in a low resistance state, thus completing the write operation.

[0003] However, with the rapid development of integrated circuit technology, the density of devices in integrated circuits is increasing, and the size of semiconductor devices is constantly decreasing to meet the demands. Therefore, miniaturizing the semiconductor device size of one-time antifuse programmable memory has become an urgent problem to be solved. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to reduce the size of the semiconductor structure.

[0005] This disclosure provides a semiconductor structure, including: a substrate including a first doped region; a first isolation structure located within the first doped region, wherein the depth of the first isolation structure is greater than the depth of the first doped region; a first gate structure located on the substrate surface of the first doped region, the first gate structure spanning the first isolation structure, wherein the projected width of the first gate structure on the substrate is greater than the projected width of the first isolation structure on the substrate; and a second gate structure located on the substrate surface, wherein the second gate structure is located on both sides of the first gate structure.

[0006] In some embodiments, the central axis of the first isolation structure coincides with the central axis of the first gate structure.

[0007] In some embodiments, the system further includes a second isolation structure located between the first gate structure and the second gate structure, the second isolation structure being located within the first doped region, and the depth of the second isolation structure being less than the depth of the first doped region.

[0008] In some embodiments, the projected width of the second isolation structure on the substrate is smaller than the spacing between the first gate structure and the second gate structure.

[0009] In some embodiments, the first gate structure includes a first sidewall structure covering the sidewalls of the first gate oxide layer and the first gate layer, and the second gate structure includes a second sidewall structure, wherein the spacing between the first sidewall structure and the second sidewall structure is less than or equal to the width of the second isolation structure.

[0010] In some embodiments, a second doped region is further included, which is located within the substrate and on the side of the second gate structure away from the first doped region.

[0011] In some embodiments, the ion doping type of the first doped region is the same as that of the second doped region, and the ion doping type of the first doped region is opposite to that of the substrate.

[0012] In some embodiments, the second isolation structure is a third doped region, and the ion doping type of the third doped region is opposite to that of the first doped region.

[0013] In some embodiments, the ion doping concentration of the third doped region is greater than that of the first doped region.

[0014] In some embodiments, the first gate structure includes: a first gate oxide layer that spans a first isolation structure and whose orthogonal projection on the substrate is smaller than the orthogonal projection of the first doped region on the substrate; and a first gate layer located on the surface of the first gate oxide layer away from the substrate.

[0015] Accordingly, this disclosure also provides a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate including a first isolation structure; forming a first gate structure on the surface of the substrate, the first gate structure spanning the first isolation structure, and the projected width of the first gate structure on the substrate being greater than the projected width of the first isolation structure on the substrate; forming a second gate structure on the surface of the substrate, the second gate structure being located on both sides of the first gate structure; forming a first doped region in the substrate, the first isolation structure being located in the first doped region, the depth of the first isolation structure being greater than the depth of the first doped region, and the first gate structure being located on the substrate surface of the first doped region.

[0016] In some embodiments, the method further includes forming a second doped region within the substrate, the second doped region being located on the side of the second gate structure away from the first doped region.

[0017] In some embodiments, before forming the first gate structure, the method further includes: forming a second isolation structure within the substrate of the first doped region, the second isolation structure being located between the first gate structure and the second gate structure, and the depth of the second isolation structure being less than the depth of the first doped region.

[0018] In some embodiments, after forming the first doped region, the method further includes: forming a second isolation structure within the substrate of the first doped region, the second isolation structure being located between the first gate structure and the second gate structure, and the depth of the second isolation structure being less than the depth of the first doped region.

[0019] In some embodiments, the second isolation structure is a third doped region, the ion doping concentration of the third doped region is greater than that of the first doped region, and the ion doping type of the third doped region is opposite to that of the first doped region.

[0020] The semiconductor structure provided in this disclosure includes: a substrate, comprising a first doped region; a first isolation structure located within the first doped region, wherein the depth of the first isolation structure is greater than the depth of the first doped region, i.e., the first isolation structure isolates the first doped region into two separate parts; a first gate structure located on the substrate surface of the first doped region, spanning the first isolation structure, wherein the projection width of the first gate structure on the substrate is greater than the projection width of the first isolation structure on the substrate, i.e., the first gate structure is in contact with the first doped regions on both sides of the first isolation structure; and a second gate structure located on the substrate surface, situated on both sides of the first gate structure, forming a selection transistor together with the first gate structure. In this disclosure, by forming the first gate structure on the first doped region, the first doped regions on both sides of the first gate structure can share the first gate structure, thereby forming two memory cells, which reduces the size of the semiconductor device. Simultaneously, since the depth of the first isolation structure is greater than the depth of the first doped region, individual control of these two memory cells is achieved.

[0021] In this embodiment, a second isolation structure is provided between the first gate structure and the second gate structure. The second isolation structure is located within the first doped region. Therefore, when the distance between the first and second gate structures is reduced, the second isolation structure can prevent high voltage from damaging the second gate structure when a voltage is applied to the first gate structure. Furthermore, since the depth of the second isolation structure is less than the depth of the first doped region, it does not obstruct the migration of charge carriers from the second doped region to the first doped region, thereby enabling data writing or reading. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 A cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure;

[0024] Figure 2 A top view schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0025] Figure 3 This is a schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;

[0026] Figure 4 A schematic diagram illustrating the principle of data writing to a semiconductor structure provided in an embodiment of this disclosure;

[0027] Figure 5 A schematic diagram illustrating the principle of data reading from a semiconductor structure provided in an embodiment of this disclosure.

[0028] Figure 6 for Figure 1 The equivalent circuit diagram corresponding to the semiconductor structure in the diagram;

[0029] Figure 7 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0030] Figure 8 A schematic diagram of the structure corresponding to the substrate step in the method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0031] Figure 9 A schematic diagram of the structure corresponding to the step of forming the first gate in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

[0032] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming the first doped region in the method for preparing a semiconductor structure according to an embodiment of the present disclosure. Detailed Implementation

[0033] This disclosure provides a semiconductor structure, including: a substrate including a first doped region; a first isolation structure located within the first doped region, with a depth greater than the depth of the first doped region; a first gate structure located on the substrate surface of the first doped region, spanning the first isolation structure, with a projected width of the first gate structure on the substrate greater than the projected width of the first isolation structure on the substrate; and a second gate structure located on the substrate surface, situated on both sides of the first gate structure. In this disclosure, the first gate structure spans the first isolation structure and contacts the first doped regions on both sides of the first isolation structure, effectively allowing two memory cells to share a single gate. This means that two semiconductor cells are formed within a single semiconductor structure, thereby reducing the size of the semiconductor device.

[0034] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0035] Figure 1 This is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure.

[0036] refer to Figure 1 as well as Figure 2 The semiconductor structure includes: a substrate 100 including a first doped region 110; a first isolation structure 120 located within the first doped region 110, with a depth greater than the depth of the first doped region 110; a first gate structure 130 located on the surface of the substrate 100 of the first doped region 110, spanning the first isolation structure 120, with a projected width of the first gate structure 130 on the substrate 100 greater than the projected width of the first isolation structure 120 on the substrate 100; and a second gate structure 140 located on the surface of the substrate 100, situated on both sides of the first gate structure 130. In some embodiments, the first gate structure 130 is, for example, an antifuse gate structure, and the second gate structure 140 is, for example, a select gate structure. The two second gate structures 140 can share the first gate structure 130, thereby reducing the size of the semiconductor structure.

[0037] refer to Figure 1 as well as Figure 2The first gate structure 130 is in contact with the first doped regions 110 on both sides of the first isolation structure 120, such that both the first gate structure 130 and the first doped regions 110 on both sides of the first isolation structure 120 constitute a memory cell, which is equivalent to two memory cells sharing a single gate. The second gate structure 140 is located on both sides of the first gate structure 130. Thus, the first doped regions 110 can serve as either the source or the drain, forming a selection transistor with the second gate structure 140. Each memory cell and the selection transistor on both sides of the first gate structure 130 constitute a semiconductor cell. In other words, two semiconductor cells can be formed within one semiconductor structure. Compared to one semiconductor cell being formed by one semiconductor structure, this allows for a smaller space allocation for the semiconductor cells, thereby reducing the size of the semiconductor device.

[0038] The semiconductor structure can be a memory, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random-Access Memory), or SDRAM (Synchronous Dynamic Random-Access Memory).

[0039] refer to Figure 1 In some embodiments, the substrate 100 is made of a semiconductor material. Specifically, in some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0040] refer to Figure 1 The depth of the first isolation structure 120 is greater than the depth of the first doped region 110. Thus, the first isolation structure 120 can isolate the first doped region 110 into two discrete parts, allowing the first gate structure 130 to contact the discrete first doped regions 110 respectively, forming two discrete memory cells. When a high voltage is applied to one of the memory cells, the presence of the first isolation structure 120 prevents the other memory cell from being broken down, allowing the two memory cells to share the same gate. This means two semiconductor cells are formed in the same semiconductor structure, thereby reducing the size of the semiconductor device.

[0041] refer to Figure 1In some embodiments, the central axis of the first isolation structure 120 coincides with the central axis of the first gate structure 130. That is, the first isolation structure 120 divides the first gate structure 130 into two parts of equal area, thereby enabling the selection transistor (second gate structure 140) to be turned on, ensuring that the breakdown voltage of the gate oxide layer at both ends of the first isolation structure 120 remains consistent. Simultaneously, since the first isolation structure 120 isolates the first doped region 110 into two equal regions, the lengths of the electron transport paths within the two regions are approximately or substantially the same.

[0042] Thus, when the first gate structure 130 and the first doped regions 110 on both sides of the same semiconductor structure constitute two memory cells, the performance of the two memory cells is similar or even the same. For example, the data write and read rates of the memory cells are similar or the same. When this semiconductor structure is fabricated into a memory, the data write and read rates of each part of the circuit in the memory are more balanced, which is beneficial to improving the performance of the memory.

[0043] refer to Figure 1 In some embodiments, the first gate structure 130 includes: a first gate oxide layer 131, which spans the first isolation structure 120, and the orthogonal projection of the first gate oxide layer 131 onto the substrate 100 is smaller than the orthogonal projection of the first doped region 110 onto the substrate 100; and a first gate layer 132, which is located on the surface of the first gate oxide layer 131 away from the substrate 100. The first gate oxide layer 131 is used to isolate the first gate layer 132 from the first doped region 110 in the substrate 100, and both ends of the first gate oxide layer 131 are in contact with the first doped region 110, thereby allowing the first gate oxide layer 131 located at one end of the first doped region 110 to be broken down individually, thereby enabling individual control of two memory cells. Of course, in some embodiments, the first gate oxide layers 131 located at both ends of the first doped region 110 can also be broken down simultaneously, thereby enabling simultaneous control of two memory cells.

[0044] refer to Figure 1In some embodiments, since the orthographic projection of the first gate oxide layer 131 onto the substrate 110 is smaller than the orthographic projection of the first doped region 110 onto the substrate 110, that is, the width of the first gate oxide layer 131 is smaller than the width of the first doped region 110, the size of the semiconductor structure can be reduced. If the width of the first gate oxide layer 131 is larger than the width of the first doped region 110, a portion of the first gate oxide layer 131 will contact the substrate 100. Since the substrate 100 is grounded, that is, the substrate 100 is in a low-voltage state, when a higher voltage is applied to the first gate structure 130, the first gate oxide layer 131, which is in direct contact with the substrate 100, may be broken down. Therefore, before the second gate structure 140 is turned on, the first gate oxide layer 131 has already been broken down, thereby degrading the performance of the semiconductor structure.

[0045] In some embodiments, the orthographic projection of the first gate oxide layer 131 onto the surface of the substrate 100 can be larger than the orthographic projection of the first gate layer 132 onto the surface of the substrate 100. This allows the first gate oxide layer 131 to protect the surface of the first doped region 110 on the substrate 100, preventing process damage during manufacturing and thus improving the electrical performance of the semiconductor structure. In other embodiments, the orthographic projection of the first gate oxide layer 131 onto the surface of the substrate 100 can be the same as the orthographic projection of the first gate layer 132 onto the surface of the substrate 100. Specifically, in some embodiments, the material of the first gate oxide layer 131 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0046] refer to Figure 1 In some embodiments, the material of the first gate layer 132 can be a semiconductor material or a metal, wherein the semiconductor material can be polycrystalline silicon, and the metal material can be any one of tungsten, copper or aluminum.

[0047] refer to Figure 1 The second gate structure 140 is located on both sides of the first gate structure 130. Thus, the first doped region 110 can serve as either the drain or the source, together with the second gate structure 140, to form a selection transistor. During antifuse programming, a voltage is applied to the second gate structure 140 to turn on the selection transistor. That is, a conductive channel is formed in the substrate 100 below the second gate structure 140. At the same time, a programming voltage is applied to the first gate structure 130, so that the charge carriers in the conductive channel below the second gate structure 140 pass through the first doped region 110 below the first gate structure 130 and break down the first gate oxide layer 131 of the first gate structure 130, thereby completing the data writing.

[0048] refer to Figure 1In some embodiments, the second gate structure 140 may include a second gate oxide layer 141 and a second gate layer 142 stacked sequentially along a direction away from the substrate 100. In some embodiments, the material of the second gate oxide layer 141 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride; the material of the second gate layer 142 may be a semiconductor material or a metal, wherein the semiconductor material may be polycrystalline silicon, and the metal material may be any one of tungsten, copper, or aluminum.

[0049] refer to Figure 1 Compared to the voltage applied to the second gate structure 140 to turn on the selection transistor, the programming voltage applied to the first gate structure 130 is larger. Therefore, if the distance between the first gate structure 130 and the second gate structure 140 is too close, that is, if the distance between the selection transistor and the memory cell is too close, the performance of the selection transistor will degrade during the high-voltage breakdown of the first gate oxide layer 131 of the memory cell, thereby affecting the reliability of the circuit. Therefore, in some embodiments, a second isolation structure 150 may also be included. The second isolation structure 150 is located between the first gate structure 130 and the second gate structure 140, and is located within the first doped region 110. The depth of the second isolation structure 150 is less than the depth of the first doped region 110, so that the first doped region 110 can still serve as either the source or the drain of the selection transistor. Compared to a system where no second isolation structure 150 is provided between the first gate structure 130 and the second gate structure 140, providing the second isolation structure 150 between the first gate structure 130 and the second gate structure 140 effectively increases the spacing between the first gate structure 130 and the second gate structure 140 in a direction perpendicular to the surface of the substrate 100. This increases the distance between the selection transistor and the memory cell, thereby mitigating damage to the selection transistor caused by high-voltage writing to the memory cell when the distance between them is too close. Furthermore, the closer distance between the selection transistor and the memory cell along the direction from the first gate structure 130 to the second gate structure 140 facilitates the reduction of semiconductor device size.

[0050] refer to Figure 1In some embodiments, the projected width of the second isolation structure 150 on the substrate 100 is smaller than the spacing between the first gate structure 130 and the second gate structure 140. That is, the width of the second isolation structure 150 is smaller than the spacing between the first gate structure 130 and the second gate structure 140. Since the second isolation structure 150 is located within the first doped region 110 between the first gate structure 130 and the second gate structure 140, the smaller width of the second isolation structure 150 results in a larger area of ​​the first doped region 110 between the first gate structure 130 and the second gate structure 140. This leads to a higher concentration of doped ions in the first doped region 110, which is beneficial for carrier transport and maintains good performance of the selective transistor. Furthermore, it avoids the problem that a larger width of the second isolation structure 150 might prevent the formation of a conductive channel between the first gate structure 130 and the second gate structure 140.

[0051] refer to Figure 1 In some embodiments, the first gate structure 130 may include a first sidewall structure 133, and the second gate structure 140 may include a second sidewall structure 143. In some embodiments, the first sidewall structure 133 covers the sidewalls of the first gate oxide layer 131 and the first gate layer 132. The spacing between the first sidewall structure 133 and the second sidewall structure 143 may be smaller than the width of the second isolation structure 150. The first sidewall structure 133 and the second sidewall structure 143 are used to protect the first gate structure 130 and the second gate structure 140, respectively. The spacing between the first sidewall structure 133 and the second sidewall structure 143 is smaller than the width of the second isolation structure 150, which is beneficial to further reduce the spacing between the first gate structure 130 and the second gate structure 140 in the horizontal direction, thereby further reducing the size of the semiconductor structure. On the other hand, the width of the second isolation structure 150 is relatively large, which makes the distance between the first gate structure 130 and the second gate structure 140 larger in the direction perpendicular to the surface of the substrate 100, i.e., in the vertical direction. This can improve the damage to the selection transistor caused by the memory cell being written by high voltage due to the close distance between the selection transistor and the memory cell.

[0052] refer to Figure 3 , Figure 3This is a schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present disclosure. In other embodiments, the first gate structure 130 may include a first sidewall structure 133, and the second gate structure 140 may include a second sidewall structure 143. In some embodiments, the first sidewall structure 133 covers the sidewalls of the first gate oxide layer 131 and the first gate layer 132, and the spacing between the first sidewall structure 133 and the second sidewall structure 143 may be equal to the width of the second isolation structure 150. In still other embodiments, the spacing between the first sidewall structure 133 and the second sidewall structure 143 may be greater than the width of the second isolation structure 150. In some embodiments, the materials of the first sidewall structure 133 and the second sidewall structure 143 may be either silicon oxide or silicon nitride.

[0053] Continue to refer to Figure 1 as well as Figure 2 In some embodiments, a second doped region 160 may be included. The second doped region 160 is located within the substrate 100 and on the side of the second gate structure 140 away from the first doped region 110. The second doped region 160 can serve as another source or drain of the selection transistor. When a voltage is applied to the second gate structure 140, a conductive channel can be formed between the second doped region 160 and the first doped region 110 to conduct the first doped region 110 and the second doped region 160, so that charge carriers can be transferred from the second doped region 160 to the first doped region 110.

[0054] refer to Figure 1 as well as Figure 2 In some embodiments, a bit line structure 170 may be included, located on the surface of the substrate 100 of the second doped region 160. In some embodiments, the bit line structure 170 may include a barrier layer 171, a conductive layer 172, and an insulating layer 173 stacked sequentially along a direction away from the substrate 100. The barrier layer 171 is used to prevent mutual diffusion between the conductive layer 172 and the second doped region 160, and the insulating layer 173 is used to isolate the conductive layer 172 from other conductive devices in the semiconductor structure. Specifically, in some embodiments, the second doped regions 160 located on both sides of the first doped region 110 may be connected to different bit line structures 170, so that data from two memory cells can be read separately. Of course, in some embodiments, the second doped regions 160 located on both sides of the first doped region 110 may also be connected to the same bit line structure 170, thereby enabling simultaneous control of two memory cells.

[0055] In some embodiments, the ion doping type of the first doped region 110 is the same as that of the second doped region 160, and the ion doping type of the first doped region 110 is opposite to that of the substrate 100. Thus, the first doped region 110 and the second doped region 160 can form PN junctions with the substrate 100, respectively. Specifically, in some embodiments, the first doped region 110 and the second doped region 160 can be doped with N-type ions, and the substrate 100 can be doped with P-type ions. In other embodiments, the first doped region 110 and the second doped region 160 can also be doped with P-type ions, and the substrate 100 can be doped with N-type ions. In some embodiments, the N-type ion can be at least one of arsenic ions, phosphorus ions, or antimony ions, and the P-type ion can be at least one of boron ions, indium ions, or gallium ions.

[0056] In some embodiments, the second isolation structure 150 can be a third doped region, and the ion doping type of the third doped region is opposite to that of the first doped region 110. That is, the ion type in the third doped region is opposite to that of the second doped region 160. Therefore, when the conductive channel below the second gate structure 140 is turned on, the type of charge carriers transported in the conductive channel is opposite to that of the ions in the third doped region, thus preventing the charge carriers transported below the second gate structure 140 from entering the third doped region, thereby enabling the third doped region to function as an isolation layer. In some embodiments, an example doping type of the third doped region can be P-type, and the ion doping type of the first doped region 110 can be N-type. In other embodiments, an example doping type of the third doped region can be N-type, and the ion doping type of the first doped region 110 can be P-type.

[0057] In some embodiments, the ion doping concentration of the third doped region is greater than that of the first doped region 110, which can better block charge carriers from entering the second isolation structure 150, thereby giving the second isolation structure 150 a better isolation effect.

[0058] In other embodiments, the second isolation structure 150 may also be undoped, for example, both the first isolation structure 120 and the second isolation structure 150 may be shallow trench isolation structures. The materials filling the first isolation structure 120 and the second isolation structure 150 may include at least one of silicon oxide, silicon nitride, silicon carbonitride, or silicon carbonitride oxycarbonate. It is understood that the first isolation structure 120 is configured as an undoped isolation structure because, due to the substrate being grounded, when a voltage is applied to the first gate structure 130, if the first isolation structure 120 is an ion-doped region, a high voltage difference will be formed between the first gate structure 130 and the first isolation structure 120, which may break down the first gate oxide layer 131 at the bottom of the first gate structure 130. This would prevent selective breakdown of the first gate oxide layer 131 of the first gate structure 130, thus preventing separate data access to the two memory cells. Therefore, in this embodiment of the present disclosure, the first isolation structure 120 is an isolation structure without ion doping, and the depth of the first isolation structure 120 is greater than the depth of the first doped region 120, so that the first gate structure 130 and the first doped region respectively constitute two memory cells. Figure 4 This is a schematic diagram illustrating the principle of data writing to a semiconductor structure provided in one embodiment of the present disclosure. Figure 5 This is a schematic diagram illustrating the principle of data reading using a semiconductor structure provided in an embodiment of this disclosure. Figure 6 for Figure 1 The equivalent circuit diagram corresponding to the semiconductor structure in the image. (Reference) Figure 4 as well as Figure 5 The semiconductor structure is defined as follows: the location of one selection transistor is on the left, and the location of the other selection transistor is on the right. During antifuse programming, a voltage is applied to the second gate structure 140 on the left to turn on the left selection transistor. That is, a conductive channel is formed in the substrate 100 below the second gate structure 140 on the left. Simultaneously, a programming voltage is applied to the first gate structure 130, causing charge carriers in the conductive channel below the second gate structure 140 to pass through the first doped region 110 below the first gate structure 130 and break down the first gate oxide layer 131 on the left side of the first isolation structure 120, thereby completing the data writing. At this time, since the right selection transistor is not turned on, the first gate oxide layer 131 on the right side of the first isolation structure 120 will not be broken down, thus enabling data writing to two memory cells in the semiconductor structure separately. Of course, in some embodiments, the first gate oxide layers 131 on both sides of the first isolation structure 120 can also be broken down simultaneously, thereby enabling data writing to two memory cells in the semiconductor structure at the same time.

[0059] refer to Figure 6The storage circuit includes: two storage cells 10, the gates of the two storage cells 10 being electrically connected; and two selection transistors 20, the source or drain of the selection transistor 20 being electrically connected to one end of one of the storage cells 10. The gate of the selection transistor 20 is connected to a word line, one of the source or drain of the selection transistor 20 is connected to a bit line, and the other of the source or drain of the selection transistor 20 is electrically connected to one end of the storage cell 10. In some embodiments, the storage cell 10 may include a first storage cell 11 and a second storage cell 12, and the selection transistor 20 may include a first selection transistor 21 electrically connected to the first storage cell 11 and a second selection transistor 22 electrically connected to the second storage cell 12.

[0060] refer to Figure 4 as well as Figure 6 In some embodiments, the process of writing data to the first memory cell 11 in the memory circuit can be as follows: apply a voltage to the word line of the first selection transistor 21 to turn on the first selection transistor 21, for example, a voltage of 3V can be applied. Apply a high voltage to the first memory cell 11 and a low voltage (e.g., ground) to the bit line 170, thereby creating a high voltage difference between the first memory cell 11 and the bit line. This high voltage difference causes the first gate oxide layer 131 (the first gate oxide layer 131 on the left side of the first isolation structure 120) of the first memory cell 11 to be broken down, forming a low-resistance path between the first memory cell 11 and the drain (the first doped region 110 on the left side of the first isolation structure 120), thereby forming the data writing. In some embodiments, when a lower voltage is applied to the bit line 170 on the right side, the first gate oxide layer 131 located on the right side of the first isolation structure 120 can also be broken down, thereby realizing the data writing to the second memory cell 12. Of course, the first gate oxide layer 131 on both sides of the first isolation structure 120 can be broken through simultaneously, thereby enabling simultaneous data writing to the first storage cell 11 and the second storage cell 12.

[0061] refer to Figure 5 as well as Figure 6The process of reading data from the first memory cell 11 in the memory circuit can be as follows: Since the first gate oxide layer 131 of the first memory cell 11 has been broken down, a low-resistance state is formed. When a voltage is applied to the first memory cell 11, it is equivalent to applying a read voltage to the drain of the first memory cell 11 (the first doped region 110 on the left side of the first isolation structure 120). When a voltage is applied to the first selection transistor 22, a path is formed between the source (the second doped region 160) and the drain. Therefore, a low voltage can be applied to the first memory cell 11, while a relatively large current flows through the path in real time, thereby realizing data reading. In some embodiments, data can also be read from the second memory cell 12, and data can also be read from the first memory cell 11 and the second memory cell 12 simultaneously.

[0062] In the semiconductor structure provided in the above embodiment, a first isolation structure 120 is provided in the first doped region 110 of the substrate 100, and the depth of the first isolation structure 120 is greater than the depth of the first doped region 110. That is, the first isolation structure 120 isolates the first doped region 110 into two separate parts. A first gate structure 130 is located on the surface of the substrate 100 of the first doped region 110. The first gate structure 130 spans the first isolation structure 120, and the projection width of the first gate structure 130 on the substrate 100 is greater than the projection width of the first isolation structure 120 on the substrate 100. That is, the first gate structure 130 is in contact with the first doped regions 110 on both sides of the first isolation structure 120, and both the first gate structure 130 and the first doped regions 110 on both sides of the first isolation structure 120 constitute a memory cell. A second gate structure 140 is located on the surface of the substrate 100, and the second gate structure 140 is located on both sides of the first gate structure 130. Thus, the first doped region 110 can serve as either a source or a drain, and together with the second gate structure 140, they constitute a selection transistor. In this embodiment, the first gate structure 130 spans the first isolation structure 120 and is in contact with the first doped regions 110 on both sides of the first isolation structure 120. This is equivalent to two memory cells sharing one gate, that is, equivalent to forming two semiconductor cells in one semiconductor structure, thereby reducing the size of the semiconductor device.

[0063] Accordingly, another embodiment of this disclosure provides a method for preparing a semiconductor structure, which can form the semiconductor structure provided in the previous embodiment. The method for preparing a semiconductor structure provided in another embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

[0064] Figures 7 to 10 This is a schematic diagram of the structure corresponding to each step in a method for manufacturing a semiconductor structure according to another embodiment of this disclosure.

[0065] Figure 7This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure. Figure 8 This is a schematic diagram of the structure corresponding to the substrate step in the method for fabricating a semiconductor structure according to an embodiment of this disclosure, with reference to... Figure 7 as well as Figure 8 A substrate 100 is provided, which includes a first isolation structure 120. In some embodiments, the substrate 100 is made of a semiconductor material. Specifically, in some embodiments, the substrate 100 is made of silicon. In other embodiments, the substrate 100 may also be a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, or a silicon-on-insulator substrate.

[0066] refer to Figure 8 The first isolation structure 120 can isolate the first doped region 110 subsequently formed in the substrate 100 into two discrete parts, thereby allowing the subsequently formed first gate structure 130 to contact the discrete first doped regions 110 respectively, forming two discrete memory cells. In some embodiments, the first isolation structure 120 can be a shallow trench isolation structure, and the method of forming the first isolation structure 120 can include: patterning the surface of the substrate 100 to define the opening position of the first isolation structure 120; performing an etching process on the patterned surface of the substrate 100 to form a first trench of a predetermined depth in the substrate 100; and depositing an isolation material in the first trench to form the first isolation structure 120. In some embodiments, the isolation material can include at least one of silicon oxide, silicon nitride, silicon carbonitride, or silicon carbonitride oxycarbonate.

[0067] In some embodiments, the second isolation structure 150 can be formed before the first gate structure is formed. That is, the second isolation structure 150 can be formed in the substrate 100 while the first isolation structure 120 is being formed. In this case, since the first gate structure 130 has not yet been formed on the surface of the substrate 100, a larger process operation space is provided for the formation of the second isolation structure 150, and the width of the formed second isolation structure 150 is easier to control, which is beneficial to improving the efficiency of forming the second isolation structure 150. The second isolation structure 150 is located on both sides of the first isolation structure 120. Thus, when the second doped region is subsequently formed in the substrate 100, the second isolation structure 150 is located in the second doped region, which can increase the spacing between the first gate structure 130 and the second gate structure 140 subsequently formed on the surface of the substrate 100 in the vertical direction. This improves the damage to the second gate structure 140 caused by the first gate structure 130 being written with high voltage due to the close distance between the first gate structure 130 and the second gate structure 140.

[0068] In some embodiments, the method of forming the second isolation structure 150 may include: patterning the surface of the substrate 100 to define the opening position of the second isolation structure 150; performing an etching process on the patterned surface of the substrate 100 to form a second trench of a predetermined depth in the substrate 100; and depositing an isolation material in the second trench to form the first isolation structure 120.

[0069] Figure 9 This is a schematic diagram of the structure corresponding to the step of forming the first gate in the method for fabricating a semiconductor structure according to an embodiment of the present disclosure, with reference to... Figure 7 as well as Figure 9 A first gate structure 130 is formed on the surface of the substrate 100. The first gate structure 130 spans the first isolation structure 120, and the projection width of the first gate structure 130 on the substrate 100 is greater than the projection width of the first isolation structure 120 on the substrate 100.

[0070] refer to Figure 9 The first isolation structure 120 divides the first gate structure 130 into a first part and a second part. Thus, when a programming voltage is applied to the first gate structure 130 of the first part to break down the first gate oxide layer 131 of the first gate structure 130 of the first part, the first gate oxide layer 131 in the first gate structure 130 of the second part can be prevented from being broken down, thereby enabling the first part and the second part of the first gate structure 130 to be broken down separately, i.e., data can be written to them separately.

[0071] refer to Figure 9In some embodiments, the formed first gate structure 130 may include a first gate oxide layer 131 and a first gate layer 132 sequentially stacked along a direction away from the substrate 100. The first gate oxide layer 131 is used to isolate the first gate layer 132 from the first doped region 110 in the substrate 100. In some embodiments, the first gate structure 130 may further include a first sidewall structure 133, which covers the sidewalls of the first gate oxide layer 131 and the first gate layer 132 and is used to protect the first gate layer 132 and the first gate oxide layer 131. In some embodiments, the method of forming the first gate structure 130 may include: forming the first gate oxide layer 131 and the first gate layer 132 sequentially stacked on the surface of the substrate 100 using a deposition process; and forming the first sidewall structure 133 on the sidewalls of the first gate oxide layer 131 and the first gate layer 132 using a deposition process. Specifically, in some embodiments, the deposition process may include any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or metal-organic chemical vapor deposition. In some embodiments, the material of the first gate oxide layer 131 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride; the material of the first gate layer 132 may be a semiconductor material or a metal, wherein the semiconductor material may be polysilicon, and the metal material may be any one of tungsten, copper, or aluminum; the material of the first sidewall structure 133 may be any one of silicon oxide or silicon nitride.

[0072] refer to Figure 9 In some embodiments, a second gate structure 140 can be formed on the surface of the substrate 100 simultaneously with the formation of the first gate structure 130. The second gate structure 140 is located on both sides of the first gate structure 130. Thus, the first doped regions 110 subsequently formed on both sides of the first isolation structure 120 can serve as either the gate or the source, together with the second gate structure 140, to form a selection transistor. Both the first gate structure 130 and the first doped regions 110 subsequently formed on both sides of the first isolation structure 120 constitute a memory cell. One selection transistor and one memory cell constitute one semiconductor cell. In this embodiment, it is equivalent to forming two semiconductor cells in one semiconductor structure, thereby reducing the size of the semiconductor device. In some embodiments, the second gate structure 140 can be the same as the first gate structure 130, and the method for forming the second gate structure 140 can also be the same as the method for forming the first gate structure 130. Therefore, the first gate structure 130 and the second gate structure 140 can be formed simultaneously in the same step, which simplifies the process flow.

[0073] Figure 10 This is a schematic diagram of the structure corresponding to the step of forming the first doped region in the method for fabricating a semiconductor structure according to an embodiment of this disclosure, with reference to... Figure 7as well as Figure 10 A first doped region 110 is formed within the substrate 100, a first isolation structure 120 is located within the first doped region 110, the depth of the first isolation structure 120 is greater than the depth of the first doped region 110, and a first gate structure 130 is located on the surface of the substrate 100 of the first doped region 110.

[0074] refer to Figure 10 The depth of the first isolation structure 120 is greater than the depth of the first doped region 110, thus separating the first doped region 110 into two discrete first doped regions 110. In some embodiments, the first doped region 110 is doped with either N-type ions or P-type ions, wherein the N-type ions can be at least one of arsenic ions, phosphorus ions, or antimony ions, and the P-type ions can be at least one of boron ions, indium ions, or gallium ions. In some embodiments, a combination of vertical implantation and tilted implantation can be used to implant ions into the substrate 100 to form the first doped region 110, which results in higher ion implantation efficiency.

[0075] In some embodiments, the formed second isolation structure 150 is located within the first doped region 110, and the depth of the second isolation structure 150 is less than the depth of the first doped region 110. This allows the first doped region 110 to function as either a source or a drain, forming a selection transistor with the second gate structure 140. Simultaneously, the increased spacing between the first gate structure 130 and the second gate structure 140 in a direction perpendicular to the surface of the substrate 100 increases the distance between the selection transistor and the memory cell, thereby mitigating damage to the selection transistor caused by high-voltage writing to the memory cell due to excessively close proximity. Furthermore, the closer distance between the selection transistor and the memory cell in the direction from the first gate structure 130 to the second gate structure 140 facilitates a reduction in the size of the semiconductor device.

[0076] It is worth noting that in some embodiments, the second isolation structure can be formed simultaneously with the formation of the first isolation structure. In other embodiments, the second isolation structure 150 can be formed after the formation of the first doped region 110, that is, after the formation of the first gate structure 130 and the second gate structure 140. In this case, the first gate structure 130 and the second gate structure 140 can be used as masks to form the second isolation structure 150 between the first gate structure 130 and the second gate structure 140.

[0077] refer to Figure 10In some embodiments, the second isolation structure 150 can be a third doped region, with an ion doping concentration greater than that of the first doped region 110, and the ion doping type of the third doped region being opposite to that of the first doped region 110. Thus, when the conductive channel below the second gate structure 140 is turned on, because the type of charge carriers transported in the conductive channel is opposite to the ion type in the third doped region, the charge carriers transported below the second gate structure 140 will not enter the third doped region, thereby enabling the third doped region to perform an isolation function. This allows the third doped region to better block charge carriers from entering the second isolation structure 150, resulting in a better isolation effect for the second isolation structure 150.

[0078] refer to Figure 10 It is understood that in some other embodiments, the second isolation structure 150 may also be undoped with ions. For example, both the first isolation structure 120 and the second isolation structure 150 may be shallow trench isolation structures.

[0079] refer to Figure 10 In some embodiments, the method further includes forming a second doped region 160 within the substrate 100, the second doped region 160 being located on the side of the second gate structure 140 away from the first doped region 110. In some embodiments, the first doped region 110 and the second doped region 160 can serve as the source and drain, respectively, forming a selection transistor with the second gate structure 140. When a voltage is applied to the second gate structure 140, a conductive channel can be formed between the second doped region 160 and the first doped region 110 to conduct the first doped region 110 and the second doped region 160, allowing charge carriers to be transported from the second doped region 160 to the first doped region 110. In some embodiments, the second doped region 160 can be doped with ions of the same type as those in the first doped region 110. Specifically, in some embodiments, the second doped region 160 can be formed using the same process steps as the first doped region 110; therefore, the first doped region 110 and the second doped region 160 can be formed in the same process step, which is beneficial for improving the efficiency of the fabrication process.

[0080] refer to Figure 7 as well as Figure 1In some embodiments, a bit line structure 170 is formed on the surface of the substrate 100 of the second doped region 160. In some embodiments, the bit line structure 170 may include a barrier layer 171, a conductive layer 172, and an insulating layer 173 stacked sequentially in a direction away from the substrate 100. In some embodiments, the conductive layer 172 may be a metallic material, such as any one of tungsten, copper, or aluminum. In other embodiments, the conductive layer 172 may also be a semiconductor material, such as polysilicon. The barrier layer 171 is used to prevent interdiffusion between the conductive layer 172 and the second doped region 160. The material of the barrier layer 171 may be titanium nitride. The insulating layer 173 is used to isolate the conductive layer 172 from other conductive devices in the semiconductor structure. The material of the insulating layer 173 may be any one of silicon oxide or silicon nitride.

[0081] In the semiconductor structure manufacturing method provided in the above embodiments, the substrate 100 includes a first isolation structure 120, a first gate structure 130 is formed on the surface of the substrate 100, the first gate structure 130 spans the first isolation structure 120, and the projection width of the first gate structure 130 on the substrate 100 is greater than the projection width of the first isolation structure 120 on the substrate 100, that is, the first isolation structure 120 divides the first gate structure 130 into a first part and a second part; a second gate structure 140 is formed on the surface of the substrate 100, and the second gate structure 140 is located on the first gate structure 130. On both sides, a first doped region 110 is formed within the substrate 100, and a first isolation structure 120 is located within the first doped region 110. The depth of the first isolation structure 120 is greater than the depth of the first doped region 110, and a first gate structure 130 is located on the surface of the substrate 100 of the first doped region 110. Thus, the first doped region 110 can serve as either a source or a drain, forming a selection transistor with the second gate structure 140. The first and second portions of the first gate structure 130 are respectively in contact with the first doped region 110, forming two memory cells, which is equivalent to two memory cells sharing a single gate. Each memory cell and the selection transistor together form a semiconductor unit, which is equivalent to forming two semiconductor units within a single semiconductor structure, thereby reducing the size of the semiconductor device.

[0082] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, include: Substrate, including a first doped region; A first isolation structure is located within the first doped region, and the depth of the first isolation structure is greater than the depth of the first doped region. A first gate structure is located on the substrate surface of the first doped region, the first gate structure spans the first isolation structure, and the projected width of the first gate structure on the substrate is greater than the projected width of the first isolation structure on the substrate. A second gate structure is located on the surface of the substrate, and the second gate structure is located on both sides of the first gate structure; The second isolation structure is located between the first gate structure and the second gate structure, and the second isolation structure is located within the first doped region, and the depth of the second isolation structure is less than the depth of the first doped region.

2. The semiconductor structure of claim 1, wherein, The central axis of the first isolation structure coincides with the central axis of the first gate structure.

3. The semiconductor structure of claim 1, wherein, The projection width of the second isolation structure on the substrate is smaller than the spacing between the first gate structure and the second gate structure.

4. The semiconductor structure of claim 1, wherein, The first gate structure includes a first sidewall structure, the second gate structure includes a second sidewall structure, and the spacing between the first sidewall structure and the second sidewall structure is less than or equal to the width of the second isolation structure.

5. The semiconductor structure according to claim 1, characterized in that, It also includes a second doped region, which is located within the substrate and on the side of the second gate structure away from the first doped region.

6. The semiconductor structure according to claim 5, characterized in that, The ion doping type of the first doped region is the same as that of the second doped region, and the ion doping type of the first doped region is opposite to that of the substrate.

7. The semiconductor structure according to claim 1, characterized in that, The second isolation structure is a third doped region, and the ion doping type of the third doped region is opposite to that of the first doped region.

8. The semiconductor structure according to claim 7, characterized in that, The ion doping concentration in the third doped region is greater than that in the first doped region.

9. The semiconductor structure according to claim 1, characterized in that: The first gate structure includes: A first gate oxide layer, the first gate oxide layer spanning the first isolation structure, and the orthographic projection of the first gate oxide layer on the substrate being smaller than the orthographic projection of the first doped region on the substrate; A first gate layer is located on the surface of the first gate oxide layer away from the substrate.

10. A method of manufacturing a semiconductor structure, characterized by, include: A substrate is provided, the substrate including a first isolation structure; A first gate structure is formed on the surface of the substrate, the first gate structure spans the first isolation structure, and the projected width of the first gate structure on the substrate is greater than the projected width of the first isolation structure on the substrate; A second gate structure is formed on the surface of the substrate, and the second gate structure is located on both sides of the first gate structure; A first doped region is formed in the substrate, a first isolation structure is located in the first doped region, the depth of the first isolation structure is greater than the depth of the first doped region, and the first gate structure is located on the substrate surface of the first doped region; The method further includes, after forming the first doped region, forming a second isolation structure within the substrate of the first doped region, wherein the second isolation structure is located between the first gate structure and the second gate structure, and the depth of the second isolation structure is less than the depth of the first doped region.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, Also includes: A second doped region is formed within the substrate, the second doped region being located on the side of the second gate structure away from the first doped region.

12. The method for manufacturing a semiconductor structure according to claim 10, characterized in that, The second isolation structure is a third doped region, the ion doping concentration of the third doped region is greater than that of the first doped region, and the ion doping type of the third doped region is opposite to that of the first doped region.

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