Pixel driving circuit with reduced contact number

Abstract

This specification discloses a pixel driving circuit with a reduced number of external contacts. Existing digitally driven pixels require: two power-related contacts (Vcc, GND); contacts for inputting two signals for digital driving (Row signal, Column signal); contacts for inputting the setting values ​​required for pixel driving (Mode selection); and contacts for inputting a reset signal to retain video data within a frame to achieve cycle functionality when driving a pulse width modulator (PWM), and to clear previous video data before inputting new video data. However, the more contacts there are, the lower the efficiency of pick and place during manufacturing. Therefore, the pixel driving circuit proposed in this specification enables digital driving even with a reduced number of contacts through a combination of row and column signals.

Description

[0001] Technology Area

[0002] The present invention relates to a display device, and more specifically, to the operation of a pixel driving circuit having a reduced number of contacts compared to the prior art. Background Technology

[0003] This application claims priority to Korean Patent Application No. 10-2020-0168352, filed on December 4, 2020, the entire contents of which are disclosed in the specification and drawings of which are incorporated herein by reference.

[0004] The description in this section is only to provide background information for the embodiments described in this specification and does not necessarily constitute prior art.

[0005] Various types of display devices, including Liquid Crystal Display Devices (LCDs), Plasma Display Devices (PLDs), and Organic Light Emitting Display Devices (OLEDs), are currently in use. Recently, the display devices used in smartwatches, Virtual Reality (VR), Augmented Reality (AR), and Mixed Reality (MR) devices require small size and high resolution, thus increasing attention is being paid to display devices using micro-light-emitting diodes (μLEDs). Furthermore, large-scale display devices are also commercializing μLEDs.

[0006] On the other hand, driving large display devices using micro-LEDs with a passive matrix requires a large amount of power, making it unsuitable as a driving method for next-generation display devices. Therefore, the active matrix method, with its lower power consumption, is more suitable for next-generation display devices.

[0007] Figure 1 It is a circuit diagram that schematically shows the general structure of a pixel.

[0008] Reference Figure 1It can be confirmed that pixel 10 includes three light-emitting elements R, G, and B, and a pixel driving circuit 11 for driving the light-emitting elements. Digital driving using pulse width modulation (PWM) technology is common for pixels driven in an active matrix manner. Therefore, pixel 10 must have two contacts, Vcc and GND, related to the power supply (for driving the pixel), and contacts for inputting two signals for digital driving. In addition, contacts are needed for inputting the setting values ​​required for pixel driving (mode selection); and contacts are needed for inputting a reset signal to retain video data within a frame to achieve cycle function when driving PWM and to clear previous video data before inputting new video data.

[0009] On the other hand, to manufacture an active matrix display device, existing thin-film transistor backplane (TFT backplane) methods can be used, along with methods that place pixel driving circuits on the semiconductor wafer and attach micro-light-emitting diodes. In particular, when placing pixel driving circuits on the semiconductor wafer, it is necessary to minimize the required number of contacts to improve pick-and-place efficiency. However, as... Figure 1 As shown, the increased number of pins due to multiple contacts increases the difficulty of the pick and place process, leading to an increase in the size of the pixel drive circuit and reducing price competitiveness. Summary of the Invention

[0010] The technical problem to be solved by the present invention

[0011] The purpose of this specification is to provide a pixel driving circuit with a reduced number of external contacts.

[0012] This specification is not limited to the issues mentioned above, and those skilled in the art will clearly understand other issues not mentioned based on the following description.

[0013] Technical solution

[0014] The pixel driving circuit according to this specification for solving the above problems may include: a pixel-embedded memory unit including a plurality of memory cells for storing pixel driving-related settings and video data; a signal detection unit including row signal input terminals and column signal input terminals; a first low-pass filter that outputs a signal having a frequency lower than a preset first cutoff frequency from the signal input from the signal detection unit; and a second low-pass filter that outputs a signal having a frequency lower than a preset second cutoff frequency from the signal input from the signal detection unit to the pixel-embedded memory unit.

[0015] According to one embodiment of this specification, the signal output from the first low-pass filter can be input to the data input terminal of the pixel embedded memory section, the data input terminal being used to store data.

[0016] According to one embodiment of this specification, the signal output from the signal detection unit can be input to the clock terminal of the pixel embedded memory unit, and the clock terminal is used to receive clock signals.

[0017] According to one embodiment of this specification, the signal output from the second low-pass filter can be input to a reset terminal of the pixel embedded memory section, the reset terminal being used to clear the data stored in the memory cell.

[0018] The pixel embedded memory unit according to one embodiment of this specification may include: a flag storage unit for storing mode values; a setting data shift register having a plurality of storage units for storing setting values ​​related to pixel driving; and a video data shift register, the number of which is K corresponding to the number of light-emitting elements, for storing video data.

[0019] According to one embodiment of this specification, the flag storage unit can be configured at the location furthest from the data input terminal of the pixel embedded memory unit.

[0020] According to one embodiment of this specification, the pixel embedded memory unit can be used to output the mode value stored in the flag storage unit to the signal detection unit. In this case, the signal detection unit can be used to output the column signal when the mode value is a first mode, and to output the row signal when the mode value is a second mode.

[0021] According to one embodiment of this specification, the pixel driving circuit may further include: K output switching elements connected to one end of each of the video data shift registers, and outputting the stored data to the light-emitting element corresponding to the video data shift register; and K loop switching elements connected between one end and the other end of each of the shift registers, and inputting the data output from one end back to the other end.

[0022] Each of the video data shift registers according to an embodiment of this specification may further include a plurality of PWM interrupt storage units for interrupting the PWM drive of each light-emitting element.

[0023] According to one embodiment of this specification, each PWM interrupt memory unit may be located adjacent to the least significant bit (LSB) in the video data of each light-emitting element.

[0024] The pixel driving circuit according to this specification may be a component of a pixel circuit that includes a pixel driving circuit and multiple light-emitting elements.

[0025] According to this specification, the pixel circuit can be a component of a display device, the display device including: a display panel having a plurality of pixel circuits arranged thereon; a scan driving circuit that outputs row signals through a plurality of scan lines, the plurality of scan lines being connected to row signal input terminals of the pixel circuits arranged along the row direction; and a data driving circuit that outputs column signals through a plurality of data lines, the plurality of data lines being connected to column signal input terminals of the pixel circuits arranged along the column direction.

[0026] The line signal according to one embodiment of this specification may include: a first scan signal for inputting to the pixel embedded memory unit; a second scan signal for inputting setting value data and video data related to pixel driving; and a clock signal for driving the PWM.

[0027] According to one embodiment of this specification, the first scanning signal may be a signal having a frequency lower than the cutoff frequency of the second low-pass filter.

[0028] According to one embodiment of this specification, the second scanning signal may be a signal having a frequency lower than the cutoff frequency of the first low-pass filter and a frequency higher than the cutoff frequency of the second low-pass filter.

[0029] According to one embodiment of this specification, the clock signal used to drive the PWM may be a signal having a frequency higher than the cutoff frequency of the first low-pass filter.

[0030] According to one embodiment of this specification, the scan drive circuit can output a row signal obtained by repeating M clock signals after a second scan signal according to an M-cycle operation mode.

[0031] The column signal according to one embodiment of this specification may include a mode value data signal, a set value data signal, and a video data signal.

[0032] According to one embodiment of this specification, the most significant bit (MSB) of the data included in the column signal can be a mode value.

[0033] The video data according to one embodiment of this specification may include: L bits of grayscale data corresponding to the grayscale of each light-emitting element; and 1 bit of "0" data as PWM interrupt data.

[0034] Other specific aspects of the invention are included in the detailed description and accompanying drawings.

[0035] Invention Effects

[0036] According to one aspect of this specification, since the number of external contacts of the pixel driving circuit is reduced, the efficiency of the process of arranging and transferring the pixel driving circuit on the semiconductor wafer can be improved.

[0037] According to another aspect of this specification, since the number of external contacts of the pixel driving circuit is reduced, the difficulty of the transfer process is reduced, and the size of the pixel driving circuit is reduced, thereby improving price competitiveness.

[0038] The effects of this invention are not limited to those mentioned above, and those skilled in the art can clearly understand other effects not mentioned from the following description. Attached Figure Description

[0039] Figure 1 It is a circuit diagram that schematically shows the general structure of a pixel.

[0040] Figure 2 This is a block diagram schematically illustrating the structure of the display device described in this specification.

[0041] Figure 3 This is a block diagram schematically illustrating the structure of the pixel driving circuit of this specification.

[0042] Figure 4 This is a block diagram schematically illustrating the structure of the pixel embedded memory section of this specification.

[0043] Figure 5 This is a timing reference diagram for the row and column signals in this manual.

[0044] Figure 6 This is the first operation reference diagram for Mode 1.

[0045] Figure 7 This is the second operation reference diagram for Mode 1.

[0046] Figure 8 This is a reference diagram for operating mode 2.

[0047] Figure 9 This is a reference diagram of the column signal data in this manual.

[0048] Figure 10 This is a reference diagram of the storage unit in this manual that stores data "1" and "0".

[0049] Figure 11 This is a reference diagram showing the operation sequence of Mode 1 and Mode 2 in this manual.

[0050] Figure 12 This is a reference diagram of the PWM interrupt storage unit in this manual.

[0051] Figure 13 This is a reference diagram for cyclic operations. Detailed Implementation

[0052] The advantages and features of the invention disclosed in this specification, as well as the methods for implementing them, will become apparent from the accompanying drawings and the embodiments described in detail below. However, this specification is not limited to the embodiments described below, and can be implemented in various different forms. These embodiments are only intended to ensure that the disclosure of this specification is fully disclosed so that those skilled in the art (hereinafter, "those skilled in the art") can fully understand the scope of this specification. The scope of the claims in this specification is defined by the claims of this invention.

[0053] The terminology used in this specification is for illustrative purposes only and is not intended to limit the scope of the claims. In the following embodiments, unless otherwise stated, the singular form also includes the plural form in the text. The terms "comprises" and / or "comprising" as used in the specification do not exclude the presence or addition of more than one other constituent element besides those mentioned.

[0054] Throughout this specification, the same reference numerals denote the same constituent elements, and "and / or" includes each and all combinations of one or more of the mentioned constituent elements. Although "first," "second," etc., are used to describe various constituent elements, these constituent elements are certainly not limited to these terms. These terms are only used to distinguish one constituent element from another. Therefore, within the scope of the inventive concept, the first constituent element mentioned below can also be a second constituent element.

[0055] This specification uses components of logic circuits and electronic circuits to illustrate embodiments. For ease of understanding, embodiments are described using the case where data "1" corresponds to logic high and data "0" corresponds to logic low. However, the opposite is also possible, and embodiments of the invention will be described in detail with reference to the following drawings.

[0056] Figure 2 This is a block diagram schematically illustrating the structure of the display device described in this specification.

[0057] Reference Figure 2 The display device 100 according to this specification may include a display panel 110, a scanning drive circuit 120, a data drive circuit 130, and a control unit 140.

[0058] The display panel 110 may include a plurality of pixel circuits (PX) according to this specification. The m x n (m and n are natural numbers) plurality of pixel circuits (PX) may be arranged in a matrix. However, the pattern of the plurality of pixel circuits may be arranged in various patterns, such as a "Z" shape, depending on the embodiment.

[0059] The display panel 110 can be one of the following: liquid crystal display (LCD), light emitting diode (LED) display, organic light emitting diode (OLED) display, active-matrix OLED (AMOLED) display, electrochromic display (ECD), digital micromirror device (DMD), actuated mirror device (AMD), grating light valve (GLV), plasma display panel (PDP), electroluminescent display (ELD), or vacuum fluorescent display (VFD), and can also be other types of flat panel displays or flexible displays. In this specification, an LED display panel will be described as an example.

[0060] Each pixel circuit (PX) may include multiple light-emitting elements. These elements can be light-emitting diodes (LEDs). LEDs can be micro LEDs with a size of less than 80 μm. A pixel circuit (PX) can output multiple colors using multiple light-emitting elements of different colors. For example, a pixel circuit (PX) may include light-emitting elements composed of red, green, and blue. As another example, if a white light-emitting element is also included, it can replace any one of the red, green, or blue light-emitting elements. Each light-emitting element included in a pixel circuit (PX) is referred to as a "subpixel."

[0061] Each pixel circuit (PX) may include pixel driving circuitry for driving multiple sub-pixels. The pixel driving circuitry can drive the sub-pixels to turn on or off using row signals output from the scan driving circuitry 120 and / or column signals output from the data driving circuitry 130. The pixel driving circuitry may include at least one thin-film transistor and at least one capacitor, etc. The pixel driving circuitry may be implemented using a stacked structure on a semiconductor wafer.

[0062] The display panel 110 may include scan lines (SL1 to SL2) arranged along the row direction. m) and data lines arranged along the column direction (DL1~DL n The pixel circuit (PX) can be located on the scan lines (SL1 to SL2). m ) and data cable (DL1~DL n The intersection of the two lines. Each pixel circuit (PX) can be connected to any scan line (SL). k ) and any data cable (DL) k The scan lines (SL1~SL) m The data lines (DL1 to DL2) can be connected to the scan drive circuit 120. n It can be connected to the data drive circuit 130.

[0063] The scanning drive circuit 120 can drive multiple scan lines (SL1~SL2). m Output row signal, the multiple scan lines (SL1~SL2) m The scan drive circuit 120 is connected to the row signal input terminals of the pixel circuits arranged along the row direction. Preferably, the scan drive circuit 120 can sequentially connect to the scan lines (SL1~SL2). m The output line signal is as follows. For example, during the first scan drive cycle, a pixel connected to the first scan line (SL1) can be driven, and during the second scan drive cycle, a pixel connected to the second scan line (SL2) can be driven. The operation of the scan drive circuit 120 according to this specification will be described in more detail later.

[0064] The data driving circuit 130 can be driven by multiple data lines (DL1~DL2). n Output column signal (DL1~DL2), the multiple data lines (DL1~DL3) n The data drive circuit 130 is connected to the column signal input terminals of the pixel circuits arranged along the column direction. The column signal includes data related to the grayscale gradation of each pixel circuit. Although one data line is connected to multiple pixel circuits along the vertical direction, the column signal can be input only to the pixel circuits connected to the scan lines selected by the scan drive circuit 120. The operation of the data drive circuit 130 according to this specification will be described in more detail later.

[0065] The control unit 140 can output control signals to execute the operations of the scan drive circuit 120 and the data drive circuit 130. The control unit 140 can output control signals corresponding to image data, which correspond to an image frame, to the scan drive circuit 120 and the data drive circuit 130 respectively.

[0066] Figure 3 This is a block diagram schematically illustrating the structure of the pixel driving circuit of this specification.

[0067] Reference Figure 3 The pixel driving circuit 200 according to this specification may include a signal detection unit 210, a first low-pass filter 220, a second low-pass filter 230, and a pixel embedded memory unit 240.

[0068] The signal detection unit 210 may include: a row signal input terminal for inputting a row signal output from the scan drive circuit 120; and a column signal input terminal for inputting a column signal output from the data drive circuit 130. The row signal or column signal input to the signal detection unit 210 can be output to the first low-pass filter 220, the second low-pass filter 230, and the pixel embedded memory unit 240. Which of the row signal or column signal input to the signal detection unit 210 should be output can be determined according to the operating mode. To control the signal output according to the operating mode, such as... Figure 3 As shown, the signal detection unit 210 can be constructed using logic circuit elements and multiplexers.

[0069] The first low-pass filter 220 is a low-pass filter (LPF) that outputs a signal to the first pixel embedded memory unit 240. The signal is a signal with a frequency lower than a preset first cutoff frequency among the signals input from the signal detection unit 210.

[0070] The second low-pass filter 230 is a low-pass filter (LPF) that outputs a signal to the pixel embedded memory unit 240. The signal is a signal with a frequency lower than a preset second cutoff frequency among the signals input from the signal detection unit 210.

[0071] The first cutoff frequency (Hz) can be higher than the second cutoff frequency. Conversely, the second cutoff frequency (Hz) can be lower than the first cutoff frequency. Therefore, a long logic high signal can pass through the second low-pass filter 230, while a short logic high signal can pass through only the first low-pass filter 220 without passing through the second low-pass filter 230. The first and second cutoff frequencies can be designed to the level of a person skilled in the art based on the desired logic high hold time difference.

[0072] The pixel embedded memory unit 240 may include multiple storage units for storing pixel-driving-related settings and video data. In this specification, a storage unit refers to a circuit element for storing 1 bit of data, and the storage unit according to this specification can be implemented using various storage elements known to those skilled in the art. Although an example of implementing a 1-bit storage unit and a shift register using flip-flops (FF) is presented in this specification, the pixel driving circuit according to this specification is not limited to this example.

[0073] On the other hand, the pixel embedded memory unit 240 may include: a data input terminal for storing data; a clock terminal for receiving a clock signal; and a reset terminal for clearing the data stored in the memory cell. The connection can be formed such that a signal output from the first low-pass filter 220 is input to the data input terminal of the pixel embedded memory unit. The connection can be formed such that a signal output from the signal detection unit 210 is input to the clock terminal of the pixel embedded memory unit. The connection can be formed such that a signal output from the second low-pass filter 230 is input to the reset terminal of the pixel embedded memory unit.

[0074] Figure 4 This is a block diagram schematically illustrating the structure of the pixel embedded memory section of this specification.

[0075] Reference Figure 4 The pixel embedded memory unit 240 according to this specification may include a flag storage unit 241, a setting data shift register 242 and a video data shift register 243.

[0076] The flag storage unit 241 is a storage unit used to store mode values. The flag storage unit 241 may store values ​​corresponding to a first mode or a second mode according to this specification. For example... Figure 4 As shown, the flag storage unit 241 can be configured at the location furthest from the data input terminal data of the pixel embedded memory unit 240.

[0077] According to one embodiment of this specification, the pixel embedded memory unit 240 can output the mode value stored in the flag storage unit 241 to the signal detection unit 210. The signal output from the signal detection unit 210 can be a selection signal (DeMUX Select Signal) for selecting the input terminal of a multiplexer (MUX). In this specification, a mode value of "0" stored in the flag storage unit 241 is referred to as a "first mode," and a mode value of "1" stored in the flag storage unit 241 is referred to as a "second mode." At this time, when the mode value is the first mode, the signal detection unit 210 can output the column signal, and when the mode value is the second mode, the signal detection unit 210 can output the row signal. The characteristics of the column signal and the row signal used for the operations described above will be explained in more detail later.

[0078] The setting data shift register 242 may have multiple storage units for storing setting values ​​related to pixel driving. The size of the setting value data may vary depending on the size of the setting value, for example, 19 bits, 12 bits, etc. Therefore, the number of storage units included in the setting data shift register 242 may also vary.

[0079] The video data shift register 243 may include K shift registers 243 corresponding to the number of light-emitting elements to store video data. Video data refers to grayscale-related data represented by turning the light-emitting elements on / off within a frame. The number of light-emitting elements in a pixel can be varied; in this specification, three light-emitting elements related to RGB are shown as an example. Additionally, 11 bits of grayscale data for each light-emitting element are shown. The number of light-emitting elements and the size of the grayscale data can vary.

[0080] The structure and timing of the row signal and column signal will be described below. The row signal is a signal output from the scan drive circuit 120 according to this specification, and the column signal is a signal output from the data drive circuit 130 according to this specification. The output timing of the row signal and column signal can be controlled by the control unit 140 according to this specification.

[0081] Figure 5 This is a timing reference diagram for the row and column signals in this manual.

[0082] Reference Figure 5 First, the POR signal can be input simultaneously with power supply and remain in a logic high state continuously. Second, the screen frame synchronization signal V_sync can be output periodically according to a preset interval. The row signal and column signal can be input to the pixel driving circuit 200 according to the output timing of the frame synchronization signal V_sync.

[0083] Figure 5 The timing of the signals shown represents the column signal Col.1 and row signal Row 1 input to the pixel driving circuit, which are arranged at a 1×1 position in the multiple pixel circuits of the display panel. Furthermore, the remaining pixel driving circuits differ only in their input timing according to their arrangement, while the structure of each row signal and each column signal is identical.

[0084] The row signal may include: a first scan signal SCAN 1, used to input settings related to pixel driving; a second scan signal SCAN 2, used to input video data; and a clock signal PWM clock, used to drive PWM.

[0085] The first scan signal SCAN 1 can be a signal with a frequency lower than the cutoff frequency of the second low-pass filter 230. Therefore, the first scan signal SCAN 1 can pass through the second low-pass filter 230.

[0086] The second scan signal SCAN 2 can be a signal with a frequency lower than the cutoff frequency of the first low-pass filter 220 and higher than the cutoff frequency of the second low-pass filter 230. Therefore, the second scan signal SCAN 2 can pass through the first low-pass filter 220 but cannot pass through the second low-pass filter 230.

[0087] The clock signal PWM clock used to drive the PWM can be a signal with a frequency higher than the cutoff frequency of the first low-pass filter 220. Therefore, neither the clock signal PWM clock used to drive the PWM can pass through the first low-pass filter 220 nor the second low-pass filter 230.

[0088] The column signal may include mode value data signals, pixel drive-related setting value data signals, and video data signals related to multiple light-emitting elements. In this case, the most significant bit (MSB) of the data included in the column signal may be the mode value.

[0089] The following describes the sequence of operation of the pixel driving circuit 200 according to this specification using the row signal and column signal, i.e., the sequence of operation in mode 1 and mode 2. Referring to... Figures 6 to 8 This describes the path through which the input signal is output in each mode. Because... Figures 6 to 8 The pixel driving circuit 200 shown is Figure 3 The pixel driving circuit 200 shown is the same, so repeated descriptions of each structure are omitted.

[0090] On the other hand, it is assumed that all components included in the pixel driving circuit 200 are in their initial state when the initial drive signal (Power On Reset (POR)) is applied. That is, it is assumed that the input terminal of the multiplexer (MUX) included in the signal detection unit 210 is selected as "0", and the data stored in all memory cells included in the pixel embedded memory unit 240 is "0". The initial drive signal POR may be a signal that is input along with the power supply when the display device is powered on for operation.

[0091] Figure 6 This is the first operation reference diagram for Mode 1.

[0092] Reference Figure 6The first scan signal SCAN 1, output from the scan drive circuit 120, is input to the line signal input terminal. The first scan signal SCAN 1 can be input to the reset terminal of the pixel embedded memory unit 240 via the signal detection unit 210 and the second low-pass filter 230. For this purpose, a flip-flop (DFF) for converting the signal data_l, which has a long logic high, into a pulse signal clear can be connected to the output terminal of the second low-pass filter 230. The first scan signal SCAN 1 can delete data stored in the pixel embedded memory unit 240 in the previous frame.

[0093] Figure 7 This is the second operation reference diagram for Mode 1.

[0094] Reference Figure 7 The second scan signal SCAN 2 output from the scan drive circuit 120 is input to the row signal input terminal, and the column signal 1RRRR...DDDD output from the data drive circuit 130 can be input to the column signal input terminal. The column signal is represented in the most significant bit MSB as mode value "1", setting value "R", and video data "D".

[0095] Figure 9 This is a reference diagram of the column signal data in this manual.

[0096] Reference Figure 9 The video data "H" and "L" represented within the preset time interval T can be confirmed. The length of the time T used to distinguish one bit from the video data signal (data "H", data "L") can be set such that the frequency of the signal included in this time interval has a frequency higher than the second cutoff frequency of the second low-pass filter 230. Therefore, the column signal cannot pass through the second low-pass filter 230.

[0097] Figure 10 This is a reference diagram of the storage unit in this manual that stores data "1" and "0".

[0098] Refer to together Figure 9 and Figure 10 According to this specification, the video data values ​​may include signals having frequencies lower than the cutoff frequency of the first low-pass filter 220 and signals having frequencies higher than the cutoff frequency of the first low-pass filter 220 within the preset reference time T. That is, the logic high hold time A of data "1" can be relatively long, resulting in a signal having a frequency lower than the cutoff frequency of the first low-pass filter 220, and the logic high hold time C of data "0" can be relatively short, resulting in a signal having a frequency higher than the cutoff frequency of the first low-pass filter 220. Figure 10 The waveform of the video data signal having the characteristics described above after passing through the first low-pass filter 220 is shown. Before passing through the first low-pass filter 220, both the video data signal "1" and "0" are logic high, but after passing through the first low-pass filter 220, they are divided into logic low ("0") and logic high ("1") of the video data signal. Therefore, the video data can be stored as "1" and "0" in the storage cells 241, 242, and 243 of the pixel embedded memory unit 240. On the other hand, in the signal detection unit 210, since the pulse is directly input without change, the signal that has not passed through the first low-pass filter 220 can be operated as a clock signal clock_s.

[0099] Refer again Figure 7 The column signal 1RRR...DDDD can be input to the data input terminal of the pixel embedded memory unit 240 through the signal detection unit 210 and the first low-pass filter 220 during the period when the second scan signal SCAN 2 remains logic high. Additionally, the signal output from the signal detection unit 210 is input to the clock terminal of the pixel embedded memory unit 240 and operates as the clock signal clock_s. Therefore, the column signal 1RRR...DDDD can be stored in all memory cells included in the pixel embedded memory unit 240.

[0100] Figure 8 This is a reference diagram for operating mode 2.

[0101] Reference Figure 8 The state is that the mode value "1" is stored in the flag storage unit 241 of the pixel embedded memory unit 240. The mode value "1" is output to the multiplexer (MUX) included in the signal detection unit 210, and the state changes from mode 1 to mode 2.

[0102] The clock signal output from the scan drive circuit 120 for driving the PWM is input to the row signal input terminal. Although the video data signals for other pixel drive circuits arranged along the column direction are input to the column signal input terminal, the multiplexer (MUX) included in the signal detection unit 210 is configured to output only the signals input from the row signal input terminal, so the signals input to the column signal input terminal will not cause any impact in mode 2.

[0103] In the scan drive circuit 120, the clock signal used to drive the PWM can be composed of a pulse signal with relatively high frequency characteristics compared to the video data signal, and can be blocked by the first low-pass filter 220. Therefore, the clock signal used to drive the PWM can be input to the clock terminal of the pixel embedded memory unit 240 via the signal detection unit 210. Then, in the pixel embedded memory unit 240, the video data stored in the shift register 243 can drive the PWM operation of the light-emitting element (LED) according to the timing of the clock signal.

[0104] Figure 11 This is a reference diagram showing the operation sequence of Mode 1 and Mode 2 in this manual.

[0105] Reference Figure 11 After the initial POR is input, Mode 1 (#1, #2) and Mode 2 (#3) are executed sequentially. Then, Mode 1 and Mode 2 are repeated based on the video frames. For example... Figures 6 to 8 As shown, modes 1 and 2 can be repeatedly executed based on the characteristics of row signals and column signals. Through these characteristics, video data and setpoint data can be transmitted together in each frame. In this case, there is an advantage that even if noise occurs in the storage unit storing the setpoints, causing fluctuations in the stored values, the error only occurs within one frame and can be quickly recovered in the next frame.

[0106] On the other hand, depending on the operation settings of the display device, there may be cases where a PWM drive is executed once per frame, or cases where a PWM drive is executed more than twice. In this specification, the operation mode of executing a PWM drive M times repeatedly is referred to as the "M-cycle operation mode". In the case of executing a traditional PWM drive only once, regardless of the value of the least significant bit (LSB) of the grayscale data, the PWM drive can be interrupted by resetting all shift registers. Conversely, in the M-cycle operation mode, after interrupting the PWM drive M times, all shift registers are reset. However, when the value of the least significant bit (LSB) of the grayscale data is "1", the following problem may occur: the light-emitting element (LED) remains on until the most significant bit (MSB) of the grayscale data for the next PWM drive is input. Therefore, each PWM drive needs to be interrupted after the last grayscale data is output.

[0107] According to one embodiment of this specification, the pixel embedded memory unit 240 may further include a plurality of PWM interrupt memory units for interrupting the PWM drive of each light-emitting element.

[0108] Refer again Figure 4The structure of the pixel embedded memory unit 240 according to this specification will be described in more detail. The pixel embedded memory unit 240 according to this specification may include K shift registers corresponding to the number of light-emitting elements (LEDs). Figure 4 The diagram shows three shift registers 243-R, 243-G, and 243-B corresponding to RGB. As described above, each of the shift registers 243 includes L video data storage units for storing video data (i.e., grayscale data) for each light-emitting element. Figure 4 This is an example when the grayscale data of each light-emitting element is 11 bits. Furthermore, each of the shift registers 243 may also include a PWM interrupt memory unit for interrupting the PWM drive of the light-emitting element.

[0109] The PWM interrupt storage unit can be located near the storage unit that stores the least significant bit (LSB) or most significant bit (MSB) of the grayscale data of each light-emitting element.

[0110] Figure 12 This is a reference diagram of the PWM interrupt storage unit in this manual.

[0111] Reference Figure 12 This confirms one PWM interrupt memory unit and four video data storage units. Figure 12 The example shown illustrates a PWM interrupt memory location located after the memory location storing the least significant bit (LSB) of the grayscale data. An example of input data is also shown. When the grayscale data of the light-emitting element (LED) is "0101", one bit "0" can be added to input "0101". 0 Additionally, when the grayscale data of the light-emitting element (LED) is "1010", a "0" can be added to input "1010". 0 ".

[0112] Refer again Figure 4 The remaining structure of the pixel embedded memory unit 240 according to this specification will be described.

[0113] The pixel-embedded memory unit 240 may further include: K output switching elements connected to one end of each shift register 243, outputting stored data to light-emitting elements corresponding to each shift register 243; and K loop switching elements connected between one end and the other end of each shift register 243, inputting data output from one end back to the other end. Figure 4 In the example shown, "K = 3".

[0114] The flag storage unit 241 can output the stored mode value as a selection signal to the K output switching elements and the K loop switching elements. Therefore, when "1" is stored as a mode value in the flag storage unit 241, the loop operation mode can be operated through the output switching elements and the loop switching elements.

[0115] On the other hand, in the cyclic operation mode, the video data signal output from the data driving circuit 130 may include L bits of grayscale data corresponding to the grayscale of each light-emitting element and 1 bit of "0" data as PWM interrupt data. At this time, the PWM interrupt data is located adjacent to the least significant bit (LSB) or most significant bit (MSB) in the grayscale data of each light-emitting element.

[0116] On the other hand, in the cyclic operation mode, the scan drive circuit 120 can output a row signal obtained by repeating M clock signals after a second scan signal according to the M-cyclic operation mode.

[0117] Figure 13 This is a reference diagram for cyclic operations.

[0118] Reference Figure 13 This is an example of using 6-bit PWM to operate with a 50% duty cycle (on-duty).

[0119] The scan drive circuit 120, data drive circuit 130, and control unit 140 described in this specification may include processors, application-specific integrated circuits (ASICs), other chipsets, logic circuits, registers, communication modules, data processing devices, etc., known in the art to which this invention pertains, to perform signal output, calculation, and various control logic. Furthermore, when the aforementioned control logic is implemented as software, the scan drive circuit 120, data drive circuit 130, and control unit 140 may be implemented as a combination of program modules. In this case, the program modules may be stored in a storage device and executed by a processor.

[0120] The computer program may include code, which is encoding in computer languages ​​such as C / C++, C#, JAVA, Python, and machine language that can be read by the computer's processor (CPU) through the computer's device interface, enabling the computer to read the program and execute the method implemented as a program. This code may include functional code related to functions defining the functionality required to perform the method, and may include control code related to the execution process required by the computer's processor to perform the function according to a predetermined procedure. Additionally, this code may include memory reference-related code for determining which location (address) in the computer's internal or external memory should be referenced by the computer's processor to perform the function. Furthermore, when the computer's processor needs to communicate with any other computer or server remotely to perform the function, the code may also include communication-related code regarding how to communicate with any other remote computer or server using the computer's communication module, and what information or media needs to be sent and received during communication.

[0121] In this context, the storage medium refers to a semi-permanent storage medium, rather than a short-term storage medium such as a register, cache, or memory, and is readable by a device. Specifically, examples of the storage medium include, but are not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disk, and optical data storage devices. That is, the program can be stored on various recording media on various servers accessible to the computer or on various recording media on the user's computer. Additionally, code can be stored on the medium, distributed to network-connected computer systems, and accessible in a distributed manner by the computers.

[0122] While embodiments of this specification have been described above with reference to the accompanying drawings, those skilled in the art will understand that the invention can be implemented in other specific forms without altering the technical concept or essential features of the invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

[0123] Explanation of reference numerals in the attached figures

[0124] 100: Display device

[0125] 110: Display panel

[0126] 120: Scan drive circuit

[0127] 130: Data drive circuit

[0128] 140: Control Department

[0129] 200: Pixel driving circuit

[0130] 210: Signal Detection Department

[0131] 220: First low-pass filter

[0132] 230: Second low-pass filter

[0133] 240: Setting Register Section

[0134] 241: Flag storage unit

[0135] 242: Configure the data shift register

[0136] 243: Video data shift register

Claims

1. A pixel driving circuit, wherein, include: The pixel-embedded memory unit includes multiple storage units for storing settings and video data related to pixel driving; The signal detection unit has row signal input terminals and column signal input terminals; The first low-pass filter outputs a signal with a frequency lower than a preset first cutoff frequency from the signal input from the signal detection unit to the pixel embedded memory unit. as well as The second low-pass filter outputs a signal from the signal input from the signal detection unit that has a frequency lower than a preset second cutoff frequency to the pixel embedded memory unit. The pixel embedded memory unit includes: A flag storage unit is used to store the pattern value; A data shift register is configured, comprising multiple storage units storing pixel-driving-related settings; and A video data shift register, wherein the number of video data shift registers is K, corresponding to the number of light-emitting elements, to store video data.

2. The pixel driving circuit according to claim 1, wherein, The signal output from the first low-pass filter is input to the data input terminal of the pixel embedded memory section, and the data input terminal is used to store data.

3. The pixel driving circuit according to claim 1, wherein, The signal output from the signal detection unit is input to the clock terminal of the pixel embedded memory unit, and the clock terminal is used to receive the clock signal.

4. The pixel driving circuit according to claim 1, wherein, The signal output from the second low-pass filter is input to the reset terminal of the pixel embedded memory unit, which is used to clear the data stored in the memory unit.

5. The pixel driving circuit according to claim 1, wherein, The flag storage unit is located at the position furthest from the data input terminal of the pixel embedded memory unit.

6. The pixel driving circuit according to claim 5, wherein, The pixel embedded memory unit is configured as follows: The mode value stored in the flag storage unit is output to the signal detection unit; The signal detection unit is configured as follows: The column signal is output when the mode value is the first mode, and the row signal is output when the mode value is the second mode.

7. The pixel driving circuit according to claim 1, wherein, Also includes: K output switching elements are connected to one end of each of the video data shift registers, and output the stored data to the light-emitting element corresponding to the video data shift register; and K cyclic switching elements are connected between one end and the other end of each of the shift registers, and the data output from one end is input back to the other end.

8. The pixel driving circuit according to claim 7, wherein, Each of the video data shift registers further includes: Multiple pulse width modulator interrupt storage units are used to interrupt the driving of the pulse width modulator for each light-emitting element.

9. The pixel driving circuit according to claim 8, wherein, Each pulse width modulator interrupt memory unit is located adjacent to the least significant bit in the video data of each light-emitting element.

10. A pixel circuit, wherein, include: The pixel driving circuit according to any one of claims 1 to 9; as well as Multiple light-emitting elements.

11. A display device, wherein, include: The display panel is arranged with a plurality of pixel circuits according to claim 10; The scanning drive circuit outputs row signals through multiple scan lines, which are connected to the row signal input terminals of the pixel circuits arranged along the row direction. as well as The data driving circuit outputs column signals through multiple data lines, which are connected to the column signal input terminals of the pixel circuits arranged along the column direction. The column signals include mode value data signals, set value data signals, and video data signals.

12. The display device according to claim 11, wherein, The row signal includes: A first scan signal is input to the pixel embedded memory unit; A second scan signal used to input pixel-driven setpoint data and video data; and The clock signal used to drive the pulse width modulator.

13. The display device according to claim 12, wherein, The first scanning signal is a signal with a frequency lower than the cutoff frequency of the second low-pass filter.

14. The display device according to claim 12, wherein, The second scanning signal is a signal having a frequency lower than the cutoff frequency of the first low-pass filter and a frequency higher than the cutoff frequency of the second low-pass filter.

15. The display device according to claim 12, wherein, The clock signal used to drive the pulse width modulator is a signal with a frequency higher than the cutoff frequency of the first low-pass filter.

16. The display device according to claim 12, wherein, The scan drive circuit outputs a row signal that repeats M clock signals after a second scan signal, according to the M-cycle operation mode.

17. The display device according to claim 11, wherein, The most significant bit of the data included in the column signal is the mode value.

18. The display device according to claim 11, wherein, The video data includes L bits of grayscale data corresponding to the grayscale of each light-emitting element and 1 bit of "0" data as pulse width modulator interrupt data.

Images