Current mirror circuit, multi-channel LED drive circuit and drive system

Abstract

Provided in the present invention are a current mirror circuit, a multi-channel LED drive circuit and a drive system. The current mirror circuit comprises a first mirroring transistor, which generates a first bias voltage on the basis of a reference current; an independent control module, which is connected between a gate of the first mirroring transistor and a gate of a second mirroring transistor and, on the basis of an enable signal, turns on or off the second mirroring transistor, wherein during turning on, after the gate voltage of the second mirroring transistor is pulled to being consistent with the first bias voltage, a path between the gate of the first mirroring transistor and the gate of the second mirroring transistor is turned on, and during turning off, after the path between the gate of the first mirroring transistor and the gate of the second mirroring transistor is cut off, the second mirroring transistor is turned off; and a second mirroring transistor, which is controlled by an output signal of the independent control module and performs mirroring amplification on the reference current, so as to obtain an output current. Without the need to use multiple mirror current sources or provide an operational amplifier circuit as a buffer, the present invention allows for low crosstalk between control operations of multiple LED constant-current drive circuits.

Description

Current mirror circuit, multi-channel LED driving circuit and driving system TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, in particular to a current mirror circuit, a multi-channel LED driving circuit and a driving system. BACKGROUND

[0002] The LED color lamp driving chip circuit usually has three to four LED constant current driving circuits for driving red, green, blue and white LED lamps. The control of the three to four LED constant current driving circuits is independent of each other, but once the independent control actions between the multiple channels produce crosstalk to each other, the mirror amplification of the LED current of each channel will be affected, and finally the LED display will be unstable, and abnormal lamp flashing will occur.

[0003] In order to realize low crosstalk of the control actions between the multiple LED constant current driving circuits, there are two mainstream technical solutions: one is to use multiple mirror currents, and each LED constant current driving circuit uses a mirror current. Since this technical solution uses multiple mirror current sources, the circuit power consumption will be larger. If you want to reduce the circuit power consumption, you need to increase the amplification of the current mirror, but this will increase the mismatch of the current mirror amplification. The second is that the multiple LED constant current driving circuits share a mirror current source, but in order to avoid low crosstalk of the control actions between the multiple LED constant current driving circuits, an operational amplifier circuit is added as a buffer to avoid it. This technical solution requires larger circuit resource consumption.

[0004] How to realize low crosstalk effect between multiple LED constant current driving circuits while not sacrificing the mismatch of current mirror amplification and reducing circuit power consumption has become one of the problems to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only to facilitate the clear and complete description of the technical scheme of the present application, and to facilitate the understanding of those skilled in the art. The above technical solutions cannot be considered as known to those skilled in the art just because they are described in the background section of the present application. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a current mirror circuit, a multi-channel LED driving circuit and a driving system to solve the problem of crosstalk between multiple LED constant current driving circuits in the prior art.

[0007] To achieve the above-mentioned purpose and other related purposes, the present application provides a current mirror circuit, which at least comprises:

[0008] a first mirror tube, a second mirror tube and an independent control module;

[0009] the first mirror tube receives a reference current and generates a first bias voltage based on the reference current;

[0010] the independent control module is connected between the gate of the first mirror tube and the gate of the second mirror tube, and turns on or off the second mirror tube based on an enable signal; when turned on, the gate voltage of the second mirror tube is pulled to be consistent with the first bias voltage, and then a path between the gate of the first mirror tube and the gate of the second mirror tube is turned on; when turned off, the path between the gate of the first mirror tube and the gate of the second mirror tube is cut off, and then the second mirror tube is turned off;

[0011] the second mirror tube is controlled by an output signal of the independent control module, and mirrors and amplifies the reference current to obtain an output current.

[0012] Optionally, the first mirror tube and the second mirror tube are NMOS tubes, or the first mirror tube and the second mirror tube are PMOS tubes;

[0013] when the first mirror tube and the second mirror tube are NMOS tubes, the drain of the first mirror tube receives the reference current, the gate and the drain are connected and output the first bias voltage, and the source is grounded; the gate of the second mirror tube is connected to the output end of the independent control module, the source is grounded, and the drain outputs the output current;

[0014] when the first mirror tube and the second mirror tube are PMOS tubes, the drain of the first mirror tube receives the reference current, the gate and the drain are connected and output the first bias voltage, and the source is connected to a power supply voltage; the gate of the second mirror tube is connected to the output end of the independent control module, the source is connected to the power supply voltage, and the drain outputs the output current.

[0015] More optionally, the independent control module comprises a charging branch, a discharging branch, a transmission unit, a first capacitor, and a charging and discharging control unit;

[0016] one end of the charging branch is connected to a power supply voltage, and the other end is grounded through the discharging branch; the upper plate of the first capacitor is connected to the connection node of the charging branch and the discharging branch, and the lower plate is grounded; the connection node of the charging branch and the discharging branch provides a gate voltage for the second mirror tube;

[0017] the first end of the transmission unit is connected to the first bias voltage, and the second end is connected to the connection node of the charging branch and the discharging branch;

[0018] The charge-discharge control unit receives the enable signal and generates control signals of the charging branch, the discharging branch and the transmission unit based on the enable signal.

[0019] More optionally, when the first mirror tube and the second mirror tube are NMOS tubes, the charge-discharge control unit comprises a first inverter, a delay unit, an AND gate, a second inverter, a third inverter and a NAND gate.

[0020] The charging branch comprises a first PMOS tube and a second PMOS tube, the first PMOS tube provides a charging current, and the second PMOS tube controls on-off of the charging branch; a source of the first PMOS tube is connected to the power supply voltage, a gate receives a second bias voltage, and a drain is connected to a source of the second PMOS tube; a gate of the second PMOS tube receives a charging control signal output by the charge-discharge control unit, and a drain is connected to the discharging branch.

[0021] The discharging branch comprises a first NMOS tube, a drain of the first NMOS tube is connected to the charging branch, a gate receives a discharging control signal output by the charge-discharge control unit, and a source is grounded.

[0022] More optionally, when the first mirror tube and the second mirror tube are NMOS tubes, the charge-discharge control unit comprises a first inverter, a delay unit, an AND gate, a second inverter, a third inverter and a NAND gate.

[0023] An input end of the first inverter receives the enable signal, and an output end is connected to an input end of the delay unit.

[0024] A first input end of the AND gate is connected to an output end of the first inverter, a second input end is connected to an output end of the delay unit, and an output end outputs a control signal of the discharging branch.

[0025] The second inverter and the third inverter are connected in series to an output end of the delay unit, and output a switch control signal of the transmission unit.

[0026] A first input end of the NAND gate receives the enable signal, a second input end is connected to an output end of the delay unit, and an output end outputs a control signal of the charging branch.

[0027] More optionally, the independent control module further comprises a first anti-disturbance unit, the first anti-disturbance unit is connected between the first bias voltage and a first end of the transmission unit; the first bias voltage is connected to the first end of the transmission unit via the first anti-disturbance unit.

[0028] More optionally, the first anti-disturbance unit comprises a first resistor and a second capacitor; a first end of the first resistor is connected to the first bias voltage, and a second end is connected to the first end of the transmission unit; an upper plate of the second capacitor is connected to the first end of the first resistor, and a lower plate is grounded.

[0029] More optionally, the independent control module further comprises a second anti-interference unit, one end of the second anti-interference unit is connected to the connection node of the charging branch and the discharging branch, and the other end is connected to the gate of the second mirror tube; the output voltage of the connection node of the charging branch and the discharging branch controls the second mirror tube through the second anti-interference unit.

[0030] More optionally, the second anti-interference unit is implemented by a second resistor.

[0031] To achieve the above object and other related objects, the application further provides a multi-channel LED driving circuit, which comprises:

[0032] N first current mirrors, N being a natural number greater than or equal to 2; each first current mirror is implemented by the above-mentioned current mirror circuit and shares the same first mirror tube; and each first current mirror outputs a corresponding LED driving current based on a corresponding enable signal.

[0033] Optionally, the multi-channel LED driving circuit further comprises a second current mirror, which receives a reference source and provides a reference current for each first current mirror after mirroring and amplifying the reference source.

[0034] To achieve the above object and other related objects, the application further provides a multi-channel LED driving system, which at least comprises:

[0035] N LED lamps and the above-mentioned multi-channel LED driving circuit, each LED lamp one-to-one corresponds to receive an LED driving current.

[0036] As mentioned above, the current mirror circuit, multi-channel LED driving circuit and driving system of the application have the following beneficial effects:

[0037] The current mirror circuit, multi-channel LED driving circuit and driving system of the application make the multi-channel LED constant current driving circuit share one mirror current source through the independent control module, realize low crosstalk of control action between the multi-channel LED constant current driving circuit without using multiple mirror current sources and without increasing an operational amplifier circuit as a buffer, do not sacrifice the mismatch of current mirror amplification, reduce the power consumption of the circuit, and the circuit structure is novel. BRIEF DESCRIPTION OF DRAWINGS

[0038] Fig. 1 shows a structural schematic diagram of the current mirror circuit of the application.

[0039] Fig. 2 shows a structural schematic diagram of the independent control module of the application.

[0040] Fig. 3 shows a structural schematic diagram of the charging and discharging control unit of the application.

[0041] Fig. 4 shows a schematic diagram of the working principle of the independent control module of the present application.

[0042] Fig. 5 shows a schematic diagram of the structure of the multi-channel LED driving circuit and the multi-channel LED driving system of the present application.

[0043] Element No. Description 1 Multi-channel LED driving circuit 1a Current mirror circuit 11, 11a, 11b, 11c Independent control module 111 Charging branch 112 Discharging branch 113 Transmission unit 114 Charging and discharging control unit 114a First inverter 114b Delay timer 114c AND gate 114d Second inverter 114e Third inverter 114f NAND gate 115 First anti-disturbance unit 116 Second anti-disturbance unit 1b Second current mirror DETAILED DESCRIPTION

[0044] The present application is described in detail below with specific reference being made to certain embodiments. It is to be understood that the present application is not limited to the specific embodiments described and that the specific embodiments are only provided for illustrative purposes. Other advantages and effects of the present application will be readily appreciated by those skilled in the art from the following description and the accompanying drawings. The present application can be implemented or applied in other different embodiments, and the details in the present description can be modified or changed based on different viewpoints and applications without departing from the spirit of the present application.

[0045] Referring to Figs. 1-5, it is to be understood that the drawings provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus the drawings only show the components related to the present application rather than the components number, shape and size in actual implementation. The actual implementation of each component can be arbitrarily changed in shape, number and proportion, and the component layout pattern can be more complicated.

[0046] Embodiment 1

[0047] As shown in FIG. 1, the embodiment provides a current mirror circuit 1a, which comprises:

[0048] a first mirror tube M1, a second mirror tube M2, and an independent control module 11; in the embodiment, the first mirror tube M1 and the second mirror tube M2 are both NMOS tubes.

[0049] As shown in FIG. 1, the first mirror tube M1 receives a reference current Iref1 and generates a first bias voltage Vb1 based on the reference current Iref1. The second mirror tube M2 is controlled by an output signal of the independent control module 11 and mirrors and amplifies the reference current Iref1 to obtain an output current Iout.

[0050] Specifically, the first mirror tube M1 and the second mirror tube M2 constitute a current mirror circuit structure, the first mirror tube M1 serves as a current input tube, the second mirror tube M2 serves as a current output tube, the reference current Iref1 is mirrored and amplified, and the amplification factor can be configured by setting the size or quantity of the first mirror tube M1 and the second mirror tube M2. In the embodiment, the drain of the first mirror tube M1 receives the reference current Iref1, the gate is connected with the drain and outputs the first bias voltage Vb1, and the source is grounded; the gate of the second mirror tube M2 is connected with the output end of the independent control module 11, the source is grounded, and the drain outputs the amplified output current Iout.

[0051] It should be noted that in actual use, the source, drain or gate of the first mirror tube M1 and the second mirror tube M2 can be provided with other devices, which can realize the function of mirroring, and are not limited to the embodiment.

[0052] As shown in FIG. 1, the independent control module 11 is connected between the gate of the first mirror tube M1 and the gate of the second mirror tube M2, and opens or closes the second mirror tube M2 based on an enable signal EN; when opened, the gate voltage of the second mirror tube M2 is pulled to be consistent with the first bias voltage Vb1, and then the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is turned on; when closed, the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is cut off, and then the second mirror tube M2 is turned off. Further, the switching action of the gate of the second mirror tube M2 (or the enable action of the current mirror circuit 1a) does not affect the stability of the first bias voltage Vb1.

[0053] Specifically, in the present embodiment, since the second mirror tube M2 is an NMOS tube, when turned on, first, the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is cut off, then the gate voltage of the second mirror tube M2 is pre-charged to the value of the first bias voltage Vb1, then the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is opened, and the output current Iout is generated based on the first bias voltage Vb1. When turned off, first, the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is cut off, then the gate voltage of the second mirror tube M2 is pulled down, and then the second mirror tube M2 is turned off, and the current mirror circuit 1a stops generating the output current Iout. Since the gate voltage of the second mirror tube M2 is consistent with the first bias voltage Vb1 during the conduction of the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2, the switching action of the gate of the second mirror tube M2 (or the enabling action of the current mirror circuit 1a) does not disturb the first bias voltage Vb1.

[0054] Specifically, as shown in FIG. 2, as an example, the independent control module 11 includes a charging branch 111, a discharging branch 112, a transmission unit 113, a first capacitor C1, and a charging and discharging control unit 114. One end of the charging branch 111 is connected to the power supply voltage vdd, and the other end is connected to the ground gnd through the discharging branch 112; the upper plate of the first capacitor C1 is connected to the connection node of the charging branch 111 and the discharging branch 112, and the lower plate is connected to the ground gnd; the connection node of the charging branch 111 and the discharging branch 112 provides the gate voltage for the second mirror tube M2. The first end of the transmission unit 113 is connected to the first bias voltage vb1, and the second end is connected to the connection node of the charging branch 111 and the discharging branch 112; in the present example, the transmission unit 113 is implemented by a transmission gate, the first end of which is connected to the first bias voltage vb1, and the second end is connected to the connection node of the charging branch 111 and the discharging branch 112, and when the switching control signals EN_dl and ENB_dl of the transmission unit 113 meet the corresponding conditions, the signal transmission between the first bias voltage vb1 and the connection node of the charging branch 111 and the discharging branch 112 is realized. The charging and discharging control unit 114 receives the enable signal EN and generates the control signals (including but not limited to the charging control signal, the discharging control signal, and the switching control signal) of the charging branch 111, the discharging branch 112, and the transmission unit 113 based on the enable signal EN.

[0055] More specifically, as shown in FIG. 2, in the embodiment, the charging branch 111 includes a first PMOS tube P1 and a second PMOS tube P2, wherein the source of the first PMOS tube P1 is connected to the power supply voltage vdd, the gate receives the second bias voltage vb2, and the drain is connected to the source of the second PMOS tube P2; the first PMOS tube P1 provides a charging current Iref2 based on the control of the second bias voltage vb2 to pre-charge the connection node of the charging branch 111 and the discharging branch 112 to the first bias voltage vb1; the gate of the second PMOS tube P2 receives the charging control signal EN_PULSE output by the charge-discharge control unit 114, and the drain is connected to the discharging branch 112; the second PMOS tube P2 controls the on-off of the charging branch 111 based on the charging control signal EN_PULSE. When the charging control signal EN_PULSE is at a low level, the second PMOS tube P2 is turned on, and the charging branch 111 charges the first capacitor C1 with the charging current Iref2; when the charging control signal EN_PULSE is at a high level, the second PMOS tube P2 is turned off, and the charging branch 111 does not realize the charging function. The size of the charging current Iref2 and the first capacitor C1 together determines the charging speed of the connection node of the charging branch 111 and the discharging branch 112, i.e., determines the current opening speed of the second mirror tube M2.

[0056] More specifically, as shown in FIG. 2, in the embodiment, the discharging branch 112 includes a first NMOS tube N1, the drain of the first NMOS tube N1 is connected to the charging branch 111, the gate receives the discharging control signal EN_discharge output by the charge-discharge control unit 114, and the source is grounded gnd; the first NMOS tube N1 controls the on-off of the charging branch 111 based on the control of the discharging control signal EN_discharge. When the discharging control signal EN_discharge is at a high level, the first NMOS tube N1 is turned on, and the discharging branch 112 discharges the first capacitor C1 to turn off the second mirror tube M2; when the discharging control signal EN_discharge is at a low level, the first NMOS tube N1 is turned off, and the discharging branch 112 does not realize the discharging function. The size of the first NMOS tube N1 and the first capacitor C1 together determines the discharging speed of the connection node of the charging branch 111 and the discharging branch 112, i.e., determines the current closing speed of the second mirror tube M2.

[0057] More specifically, as shown in FIG. 3, in the present embodiment, the charge-discharge control unit 114 includes a first inverter 114a, a delay unit 114b, an AND gate 114c, a second inverter 114d, a third inverter 114e, and a NAND gate 114f. The input terminal of the first inverter 114a receives the enable signal EN, and the output terminal is connected to the input terminal of the delay unit 114b. The first input terminal of the AND gate 114c is connected to the output terminal of the first inverter 114a, the second input terminal is connected to the output terminal of the delay unit 114b, and the output terminal outputs the control signal of the discharge branch 112, i.e., the discharge control signal EN_discharge. The second inverter 114d and the third inverter 114e are connected in series to the output terminal of the delay unit 114b, and output the switch control signals EN_dl and ENB_dl (inverted to each other) of the transmission unit 113. The first input terminal of the NAND gate 114f receives the enable signal EN, the second input terminal is connected to the output terminal of the delay unit 114b, and the output terminal outputs the control signal of the charge branch 111, i.e., the charge control signal EN_PULSE. It should be noted that any circuit structure that can realize the following functions is applicable to the present embodiment: when the enable signal EN is valid, control the transmission unit 113 to be turned off, the discharge branch 112 to be turned off, and the charge branch 111 to be turned on, and after a delay, control the transmission unit 113 to be turned on, the charge branch 111 to be turned off; when the enable signal EN is invalid, control the transmission unit 113 to be turned off, the charge branch 111 to remain turned off, and the discharge branch 112 to be turned on and gradually turned off the second mirror tube M2; and the present example is not limited thereto.

[0058] As another implementation manner of the present application, the independent control module 11 further includes a first anti-disturbance unit 115 connected between the first bias voltage vb1 and the first terminal of the transmission unit 113; the first bias voltage vb1 is connected to the first terminal of the transmission unit 113 via the first anti-disturbance unit 115, for reducing the influence of the disturbance at the connection node of the charge branch 111 and the discharge branch 112 on the node where the first bias voltage vb1 is located. As an example, as shown in FIG. 2, the first anti-disturbance unit 115 includes a first resistor R1 and a second capacitor C2, the first terminal of the first resistor R1 is connected to the first bias voltage vb1, and the second terminal is connected to the first terminal of the transmission unit 113; the upper plate of the second capacitor C2 is connected to the first terminal of the first resistor R1, and the lower plate is grounded gnd.

[0059] As another implementation manner of the present application, the independent control module 11 further comprises a second anti-interference unit 116, one end of the second anti-interference unit 116 is connected to the connection node of the charging branch 111 and the discharging branch 112, and the other end is connected to the gate of the second mirror tube M2; the output voltage vcharge of the connection node of the charging branch 111 and the discharging branch 112 controls the second mirror tube M2 through the second anti-interference unit 116, so as to reduce the influence of the disturbance of the connection node of the charging branch 111 and the discharging branch 112 on the gate of the second mirror tube M2. As shown in FIG. 2, as an example, the second anti-interference unit 116 is implemented by a second resistor R2, one end of the second resistor R2 is connected to the connection node of the charging branch 111 and the discharging branch 112, and the other end is connected to the gate of the second mirror tube M2 (and outputs the voltage vo).

[0060] As shown in FIG. 4, the working principle of the current mirror circuit 1a of the present embodiment is as follows (in the present example, the enable signal EN is high level effective):

[0061] When the enable signal EN is valid, the gate voltage vo of the second mirror tube M2 needs to be lifted from 0V voltage value to the voltage value of the gate voltage vb1 (the first bias voltage) of the first mirror tube M1, so that the current mirror circuit la performs current replication amplification. At t0, the enable signal EN is converted from low level to high level, and the discharge control signal EN_discharge is converted from high level to low level, and the discharge branch 112 is turned off; at the same time, the charging control signal EN_PULSE is converted from high level to low level, and the charging branch 111 is turned on, and the charging branch 111 starts to charge the first capacitor C1, and the charging time is t1-t0=Tdelay (Tdelay is determined by the delay timer 114b); during the charging time, the voltage vcharge of the connection node of the charging branch 111 and the discharge branch 112 is lifted from 0V voltage value to the voltage value of vb1 (according to the charge formula Q=I*T=C*V, the charging charge amount Qc1 of the first capacitor C1 during the charging time is Iref2*Tdelay=C1*vb1). At t1, the charging control signal EN_PULSE is converted from low level to high level (high level pulse signal), the charging branch 111 is turned off, and the charging of the first capacitor C1 by the charging branch 111 is stopped, at this time, the switch control signal EN_dl is converted from low level to high level, and ENB_dl is converted from high level to low level, and the transmission unit 113 is turned on, and the connection node of the charging branch 111 and the discharge branch 112 is connected with the first bias voltage vb1 through the first resistor R1. Through the above series of actions, the output signal vo (equal to vcharge) of the independent control module 11 is lifted from 0V voltage value to vb1 voltage value, and then connected with the node where the first bias voltage vb1 is located, which avoids the process that the output signal vo of the independent control module 11 is lifted from 0V voltage value to vb1 voltage value, and the node where the first bias voltage vb1 is located needs to be charged to the output node (the node where vo is located) of the independent control module 11 due to the pressure difference (vb1-vo≠0), and further avoids the interference of the first bias voltage vb1.

[0062] When the enable signal EN is invalid, the gate voltage vo of the second mirror tube M2 needs to be restored to 0V voltage value from the gate voltage vb1 voltage value of the first mirror tube M1, so as to close the output current Iout. At t2, the enable signal EN is converted from high level to low level, the charging control signal EN_PULSE remains high level, and the charging branch 111 remains off. After a time delay of Tdelay, at t3, the switch control signal EN_dl is converted from high level to low level, ENB_dl is converted from low level to high level, the transmission unit 113 is off, and the connection node of the charging branch 111 and the discharging branch 112 is disconnected with the first bias voltage vb1; the discharge control signal EN_discharge is converted from low level to high level, the discharging branch 112 is turned on, and the first capacitor C1 starts to discharge until vo=vcharge=0V. Similarly, through the above series of actions, in the process of reducing the output signal of the independent control module 11 from the vb1 voltage value to the 0V voltage value, due to the off of the transmission unit 113, the output node of the independent control module 11 and the node where the first bias voltage vb1 is located are not connected, which avoids the node where the first bias voltage vb1 is located from being charged to the output node of the independent control module 11 due to the pressure difference (vb1-vo≠0) in the process of reducing the output signal vo of the independent control module 11 from the vb1 voltage value to the 0V voltage value, and further avoids the first bias voltage vb1 from being disturbed.

[0063] It should be noted that the current mirror circuit of the present application can reduce the disturbance of the current mirror enable action on the node where the first bias voltage is located, and avoid the node where the first bias voltage is located from being disturbed to affect the normal work of other circuits connected to the node. The current mirror circuit of the present application is suitable for LED driving, but is not limited to LED driving, and is suitable for any scene requiring to reduce the disturbance of the reference current input node.

[0064] Embodiment Two

[0065] The embodiment provides another current mirror circuit 1a, which is different from the embodiment one in that the first mirror tube M1 and the second mirror tube M2 are both PMOS tubes. Due to the different electrical characteristics of PMOS tubes and NMOS tubes, corresponding adjustments need to be made in circuit connection and control logic (level).

[0066] Specifically, in the embodiment, the drain of the first mirror tube M1 receives the reference current Iref1, the gate is connected with the drain and outputs the first bias voltage Vb1, and the source is connected with the power supply voltage vdd; the gate of the second mirror tube M2 is connected with the output end of the independent control module 11, the source is connected with the power supply voltage vdd, and the drain outputs the amplified output current Iout.

[0067] Specifically, in the embodiment, since the second mirror tube M2 is a PMOS tube, when turned on, first, the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is cut off, then the gate voltage of the second mirror tube M2 is pre-discharged to the value of the first bias voltage Vb1, then the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is opened, and the output current Iout is generated based on the first bias voltage Vb1. When turned off, first, the path between the gate of the first mirror tube M1 and the gate of the second mirror tube M2 is cut off, then the gate voltage of the second mirror tube M2 is pulled up, and then the second mirror tube M2 is turned off, so that the current mirror circuit 1a stops generating the output current Iout.

[0068] Correspondingly, as an example, the charging branch 111 can be configured as a single PMOS tube, when the charging control signal is high, the charging branch 111 is turned off; when the charging control signal is low, the charging branch 111 is turned on, and the connection node of the charging branch 111 and the discharging branch 112 is pulled high to high. The discharging branch 112 can be configured as two NMOS tubes in series, one NMOS tube provides a discharging current, and the other NMOS tube serves as a switching tube; when the discharging control signal is low, the discharging branch 112 is turned off; when the discharging control signal is high, the discharging branch 112 is turned on, and the connection node of the charging branch 111 and the discharging branch 112 is pre-discharged to the first bias voltage vb1 based on the discharging current. The logic relationship between the output signal of the charge-discharge control unit 114 and the enable signal EN is also adaptively adjusted, which is not described here.

[0069] It should be noted that any device type that can realize the mirror function is applicable to the mirror tube of the present application, not limited to the NMOS tube and PMOS tube listed in the embodiment, and the control logic is adaptively adjusted, which is not described here.

[0070] Embodiment three

[0071] As shown in FIG. 5, based on the foregoing introduction of the application of PMOS tubes and NMOS tubes in the current mirror circuit, the present embodiment further provides a multi-channel LED driving circuit 1, comprising:

[0072] N-way first current mirror, N is a natural number greater than or equal to 2; each first current mirror is realized by the current mirror circuit 1a of embodiment one or embodiment two, and each first current mirror shares the same first mirror tube; each first current mirror outputs a corresponding LED driving current based on a corresponding enable signal.

[0073] Further, the multi-channel LED driving circuit 1 of the present application further comprises a second current mirror 1b, which receives a reference source Iref and provides a reference current Iref1 for each first current mirror after mirror amplification of the reference source Iref.

[0074] Specifically, in the present embodiment, N is set to 3, and each first current mirror is implemented by the current mirror circuit 1a of Embodiment 1. As an example, the second current mirror 1b includes a third PMOS tube P3 and a fourth PMOS tube P4, as shown in FIG. 5. The source of the third PMOS tube P3 is connected to the power supply voltage vdd, and the gate and the drain are connected to the reference source Iref; the source of the fourth PMOS tube P4 is connected to the power supply voltage vdd, the gate is connected to the gate of the third PMOS tube P3, and the drain outputs the reference current Iref1; in actual use, any circuit structure that can mirror amplify the reference source Iref to obtain the reference current Iref1 is applicable to the present application. In the present example, the independent control module (denoted as 11a, 11b, 11c, respectively) in each first current mirror uses the gate voltage of the third PMOS tube P3 and the fourth PMOS tube P4 as the second bias voltage vb2, and each independent control module shares the same second bias voltage vb2; in actual use, the second bias voltage of each independent control module can be configured as needed, and the source is not limited to the gate voltage of the third PMOS tube P3 and the fourth PMOS tube P4. As shown in FIG. 5, the three channels share the first mirror tube M1, the reference current Iref1, the first bias voltage vb1, and the second bias voltage vb2; the three channels have independent enable signals (denoted as EN1, EN2, EN3, respectively), independent LED constant current drive independent control modules (11a, 11b, 11c), and independent second mirror tubes (current mirror output tubes M2a, M2b, M2c) and second mirror tube gate voltages (vo1, vo2, vo3), respectively, which output output currents (denoted as Iout1, Iout2, Iout3, respectively) of a predetermined size at each predetermined time period. Due to the presence of each independent control module in the present application, the on-off control action of these channels greatly reduces the influence on the shared first bias voltage vb1, thereby achieving a low crosstalk effect between multiple channels.

[0075] As shown in FIG. 5, the present embodiment also provides a multi-channel LED driving system, which includes N LED lamps and the above-mentioned multi-channel LED driving circuit 1, each LED lamp one-to-one corresponds to receive an LED driving current. In the present example, three LED lamps (denoted as LED1, LED2, LED3, respectively) are respectively connected to the output end of the corresponding second mirror tube, and each independent control module independently enables and controls each LED lamp. As an example, the colors and driving currents of each LED lamp are different.

[0076] The present application achieves low crosstalk between multiple LED constant current driving circuits without using multiple mirror current sources or increasing operational amplifier circuits as buffers, and has low power consumption.

[0077] In summary, the application provides a current mirror circuit, a multi-channel LED driving circuit and a driving system, comprising: a first mirror tube, a second mirror tube and an independent control module; the first mirror tube receives a reference current and generates a first bias voltage based on the reference current; the independent control module is connected between the gate of the first mirror tube and the gate of the second mirror tube, and turns on or off the second mirror tube based on an enable signal; when turned on, the gate voltage of the second mirror tube is pulled to be consistent with the first bias voltage, and then the path between the gate of the first mirror tube and the gate of the second mirror tube is turned on; when turned off, the path between the gate of the first mirror tube and the gate of the second mirror tube is cut off, and then the second mirror tube is turned off; the second mirror tube is controlled by the output signal of the independent control module, and mirrors and amplifies the reference current to obtain an output current. The application uses the independent control module to make the multi-channel LED constant current driving circuit share one mirror current source, realizes low crosstalk of control action between the multi-channel LED constant current driving circuit without using multiple mirror current sources and without increasing an operational amplifier circuit as a buffer, does not sacrifice the mismatch of current mirror amplification, reduces the power consumption of the circuit, and has a novel circuit structure. Therefore, the application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0078] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought of the application should be covered by the claims of the application.

Claims

1. A current mirror circuit, characterized by, The current mirror circuit at least comprises: a first mirror tube, a second mirror tube and an independent control module; the first mirror tube receives a reference current and generates a first bias voltage based on the reference current; the independent control module is connected between the gate of the first mirror tube and the gate of the second mirror tube, and turns on or off the second mirror tube based on an enable signal; when turned on, the gate voltage of the second mirror tube is pulled to be consistent with the first bias voltage, and then the path between the gate of the first mirror tube and the gate of the second mirror tube is turned on; when turned off, the path between the gate of the first mirror tube and the gate of the second mirror tube is cut off, and then the second mirror tube is turned off; the second mirror tube is controlled by the output signal of the independent control module, and mirrors and amplifies the reference current to obtain an output current.

2. The current mirror circuit of claim 1, wherein, The first mirror tube and the second mirror tube are NMOS tubes, or the first mirror tube and the second mirror tube are PMOS tubes; when the first mirror tube and the second mirror tube are NMOS tubes, the drain of the first mirror tube receives the reference current, the gate is connected with the drain and outputs the first bias voltage, and the source is grounded; the gate of the second mirror tube is connected with the output end of the independent control module, the source is grounded, and the drain outputs the output current; when the first mirror tube and the second mirror tube are PMOS tubes, the drain of the first mirror tube receives the reference current, the gate is connected with the drain and outputs the first bias voltage, and the source is connected with a power voltage; the gate of the second mirror tube is connected with the output end of the independent control module, the source is connected with the power voltage, and the drain outputs the output current.

3. The current mirror circuit of claim 1 or 2, characterized in that: The independent control module comprises a charging branch, a discharging branch, a transmission unit, a first capacitor and a charging and discharging control unit; one end of the charging branch is connected with a power voltage, and the other end is grounded through the discharging branch; the upper plate of the first capacitor is connected with the connection node of the charging branch and the discharging branch, and the lower plate is grounded; the connection node of the charging branch and the discharging branch provides a gate voltage for the second mirror tube; the first end of the transmission unit is connected with the first bias voltage, and the second end is connected with the connection node of the charging branch and the discharging branch; the charging and discharging control unit receives the enable signal and generates control signals of the charging branch, the discharging branch and the transmission unit based on the enable signal.

4. The current mirror circuit of claim 3, wherein: when the first mirror tube and the second mirror tube are NMOS tubes: the charging branch comprises a first PMOS tube and a second PMOS tube, the first PMOS tube provides a charging current, and the second PMOS tube controls the on-off of the charging branch; the source of the first PMOS tube is connected with the power voltage, the gate receives a second bias voltage, and the drain is connected with the source of the second PMOS tube; the gate of the second PMOS tube receives a charging control signal output by the charging and discharging control unit, and the drain is connected with the discharging branch; The discharging branch includes a first NMOS tube, a drain of the first NMOS tube is connected to the charging branch, a gate receives a discharging control signal output by the charging and discharging control unit, and a source is grounded.

5. The current mirror circuit of claim 3, wherein: When the first mirror tube and the second mirror tube are NMOS tubes, the charging and discharging control unit includes a first inverter, a delay unit, an AND gate, a second inverter, a third inverter and a NAND gate. An input end of the first inverter receives the enable signal, and an output end is connected to an input end of the delay unit. A first input end of the AND gate is connected to an output end of the first inverter, a second input end is connected to an output end of the delay unit, and an output end outputs a control signal of the discharging branch. The second inverter and the third inverter are connected in series to an output end of the delay unit, and output a switch control signal of the transmission unit. A first input end of the NAND gate receives the enable signal, a second input end is connected to an output end of the delay unit, and an output end outputs a control signal of the charging branch.

6. The current mirror circuit of claim 3, wherein: The independent control module further includes a first anti-interference unit connected between the first bias voltage and a first end of the transmission unit; the first bias voltage is connected to the first end of the transmission unit via the first anti-interference unit.

7. The current mirror circuit of claim 6, wherein: The first anti-interference unit includes a first resistor and a second capacitor; a first end of the first resistor is connected to the first bias voltage, and a second end is connected to the first end of the transmission unit; an upper plate of the second capacitor is connected to the first end of the first resistor, and a lower plate is grounded.

8. The current mirror circuit of claim 3, wherein: The independent control module further includes a second anti-interference unit, one end of the second anti-interference unit is connected to a connection node of the charging branch and the discharging branch, and the other end is connected to a gate of the second mirror tube; an output voltage of the connection node of the charging branch and the discharging branch controls the second mirror tube via the second anti-interference unit.

9. The current mirror circuit of claim 8, wherein: The second anti-interference unit is implemented by a second resistor.

10. The current mirror circuit of claim 3, wherein: When the first mirror tube and the second mirror tube are NMOS tubes, the charging current in the charging branch and the size of the first capacitor jointly determine the current turn-on speed of the second mirror tube.

11. The current mirror circuit of claim 4, wherein: When the first mirror tube and the second mirror tube are NMOS tubes, the first NMOS tube in the discharging branch and the size of the first capacitor jointly determine the current turn-off speed of the second mirror tube.

12. The current mirror circuit of claim 3, wherein: When the first mirror tube and the second mirror tube are PMOS tubes, the discharging branch is configured as two NMOS tubes connected in series, one NMOS tube provides a discharging current, and the other NMOS tube serves as a switch tube; the discharging branch is turned off when the discharging control signal is at a low level, and the discharging branch is turned on when the discharging control signal is at a high level, and the connection node of the charging branch and the discharging branch is pre-discharged to the first bias voltage based on the discharging current.

13. A multi-channel LED driving circuit, characterized by, The multi-channel LED driving circuit includes: N first current mirrors, N is a natural number greater than or equal to 2; each first current mirror is implemented by the current mirror circuit in any one of claims 1-12, and shares the same first mirror tube; and based on a corresponding enable signal, a corresponding LED driving current is output.

14. The multi-channel LED driving circuit of claim 13, wherein: The multi-channel LED driving circuit further comprises a second current mirror receiving a reference source, and providing a reference current for each of the first current mirrors after magnifying the reference source.

15. A multi-channel LED driving system, characterized by, The multi-channel LED driving system at least comprises: N LED lamps and the multi-channel LED driving circuit as claimed in claim 13 or 14, each LED lamp corresponding to one LED driving current.

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