A low-power electrocardiosignal sampling and encoding device

Abstract

The application belongs to the field of electrocardiosignal sampling and pulse coding, and particularly relates to a low-power electrocardiosignal sampling and coding device. The device utilizes the waveform characteristics of each waveband of the electrocardiosignal to realize the classification processing of the electrocardiosignal through the coding mode. Two different conversion modes are adopted through serial-parallel conversion to improve the data processing efficiency. The differential coding of the coding module removes the invalid data in the electrocardiosignal, and solves the problem of serious noise interference. When the R peak interval coding is performed, the R peak interval data is compressed by 5.5 times through the one-hot coding mode. In combination with the processing of 0 data in the differential coding of the amplitude data, the classification processing speed of the entire data is greatly improved, and the operation involved in the entire processing process is extremely small. Compared with the prior art, compared with the traditional analog-digital converter based on the time uniform sampling mechanism, the invalid data caused by the increase of a large number of amplitude data points with 0 after the transmission speed is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to electrocardiosignal sampling and pulse coding, in particular to a low-power electrocardiosignal sampling and coding device. BACKGROUND

[0002] Electrocardiogram (ECG) is a common analysis tool, which has been widely used due to its comprehensive information, simple equipment and low cost. A typical ECG waveform includes a P wave, a QRS complex, a T wave, and a U wave that may be seen in 50% to 75% of ECGs. Electrocardiogram monitors the change of bioelectric signal generated by the heart during the cardiac cycle by placing electrodes on the surface of the skin, and finally generates a waveform that changes with the electric potential. However, cardiovascular diseases are sudden, and long-term monitoring data will have a lot of redundant information, and abnormal heartbeats will be mixed in a large number of normal heartbeats. If we record and present all the ECG data to the doctor, there will be too much data to record continuously, and a large amount of useless data will also bring a sharp increase in the workload of diagnosis. Therefore, we need to process the ECG signal to clearly and intuitively present the most likely problem.

[0003] The traditional ECG signal sampling and processing device is usually formed by combining an analog-to-digital converter and a filter, wherein the analog-to-digital converter is used to collect ECG signals, and the filter is used to classify and process the collected ECG signals. Due to the need of the filter to frequently extract QRS three peak data during the classification process, the traditional ECG signal sampling and processing device has the problems of large amount of calculation and serious noise interference due to the performance limitation of the filter. SUMMARY

[0004] The purpose of the present application is to provide a low-power electrocardiosignal sampling and coding device, which reduces the amount of calculation and solves the problem of noise interference.

[0005] To achieve the above purpose, the present application adopts the following technical scheme:

[0006] A low-power electrocardiosignal sampling and coding device, comprising a UART receiving end, a serial-parallel conversion module, an R peak position storage module RAM, a coding module, a FIFO cache module and a control state machine.

[0007] The UART receiving end is connected to the serial-parallel conversion module and the control state machine respectively, and is used to send the ECG signal transmitted by the external PC end to the serial-parallel conversion module and the control state machine.

[0008] The serial-parallel conversion module is connected with the encoding module, the R-peak position storage module RAM and the control state machine respectively, and is used for generating the original sig signal by adopting 2-to-1 serial-parallel conversion of the amplitude data in the ECG signal; generating the R-peak position signal Sig_R signal by adopting 3-to-1 serial-parallel conversion of the R-peak interval data in the ECG signal; and sending the R-peak data information in the ECG signal to the encoding module;

[0009] The R-peak position storage module RAM is connected with the encoding module, and sends the R-peak data information in the ECG signal to the encoding module;

[0010] The encoding module is connected with the FIFO cache module and the control state machine respectively; includes the voltage amplitude signal difference module and the R-peak interval signal difference module, the voltage amplitude signal difference module is used for completing the amplitude data encoding of the ECG signal according to the received original signal and R-peak data information, and sending the amplitude data encoding to the FIFO cache module; the R-peak interval signal difference module is used for completing the R-peak interval encoding after receiving the R-peak data information, and sending the R-peak interval encoding to the FIFO cache module;

[0011] The FIFO cache module is connected with the control state machine, and is used for combining the received amplitude data encoding, R-peak interval change trend encoding and R-peak interval encoding to obtain the binary encoding of the ECG signal;

[0012] The control state machine is used for receiving the ECG signal sent by the UART receiving end, and controls the time sequence of the serial-parallel conversion module, the encoding module and the FIFO cache module according to the time sequence of the signal.

[0013] Further, in the voltage amplitude signal difference module, the amplitude data encoding of the ECG signal adopts differential encoding, and the differential encoding process is as follows:

[0014] S1, difference is made to two continuous original signals; if the difference result is equal to 0, the two signals are regarded as invalid signals and discarded; if the difference result is not equal to 0, the most significant bit of the difference value is reserved;

[0015] S2, the amplitude data encoding of the ECG signal is generated according to the difference result of step S1.

[0016] Further, the operation of adding a bias to each original signal before differential encoding and excluding the minimum resolution is further included, so as to avoid the problem of great inconsistency between software and hardware.

[0017] Further, in the R-peak interval signal difference module, the R-peak interval encoding of the ECG signal is performed according to the following process:

[0018] S1, distance calculation is performed on three continuous R-peak data, to obtain the interval d1 and d2 of two adjacent R-peaks of a heartbeat;

[0019] S2, quantize d1 and d2 respectively to obtain R peak interval signal ECG signal R peak interval encoding.

[0020] Further, the R peak interval signal difference module is also provided with a one-hot encoding module, and the R peak interval of the ECG signal is sparsely encoded by using one-hot encoding, so as to further reduce hardware power consumption and improve calculation speed, and the specific process is as follows:

[0021] The interval between the current R peak and the previous R peak and the interval between the current R peak and the next R peak are equally divided according to the number of bits required to complete the R peak interval encoding of the ECG signal, and each segment can be represented by one bit after equal division.

[0022] Compared with the prior art, the present application has the following advantages:

[0023] 1. The ECG signal sampling and low-power pulse encoding module device provided by the present application realizes the classification processing of the ECG signal by using the waveform characteristics of each wave band of the ECG signal through encoding. In the entire processing process, the operation amount involved in the encoding of the amplitude data and the encoding of the R peak interval is extremely small, and repeated calculation is not required.

[0024] 2. In the present application, in order to better match the external PC, the serial-parallel conversion module adopts two different conversion modes for the amplitude data and the R peak interval data in the ECG signal according to the required bits of the PC, wherein the 2-to-1 serial-parallel conversion is adopted for the amplitude data in the ECG signal to generate the original sig signal, and the 3-to-1 serial-parallel conversion is adopted for the R peak interval data in the ECG signal to generate the R peak position signal Sig_R signal. While ensuring the integrity of the characteristics of the ECG signal, the data processing efficiency is improved.

[0025] 3. In the encoding module, the differential encoding is adopted for the amplitude data of the ECG signal to remove the invalid data in the collected ECG signal, so as to solve the problem of serious noise interference; and the R peak interval data is compressed by 5.5 times by using the one-hot encoding mode. Combined with the processing of 0 data in the differential encoding of the amplitude data, the classification processing speed of the entire data is greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is a structural schematic diagram of an embodiment;

[0027] Figure 2 is a one-hot encoding module architecture schematic diagram in an example;

[0028] Figure 3 is an embodiment data flow schematic diagram. DETAILED DESCRIPTION

[0029] To better understand the structure and function of the present invention, the ECG signal sampling and low-power pulse coding module of the present invention will be further described below with reference to the accompanying drawings and embodiments. The implementation of the present invention includes, but is not limited to, the following embodiments.

[0030] Example

[0031] like Figure 1 As shown in the figure, this example provides a low-power ECG signal sampling and encoding device, including a UART receiver, a serial-to-parallel conversion module, an R-peak position storage module (RAM), an encoding module, a FIFO buffer module, and a control state machine.

[0032] The UART receiver is connected to the serial-to-parallel conversion module and the control state machine, respectively, and is used to send the ECG signal transmitted from the external PC to the serial-to-parallel conversion module and the control state machine.

[0033] The serial-to-parallel conversion module is connected to the encoding module, the R-peak position storage module (RAM), and the control state machine, respectively. It converts 8-bit UART data into the required fixed-point length and then transmits it to the encoding module for processing. In this embodiment, the serial-to-parallel conversion module performs a 2-to-1 serial-to-parallel conversion on the amplitude data in the ECG signal to generate one original sig signal; it performs a 3-to-1 serial-to-parallel conversion on the R-peak spacing data in the ECG signal to generate one R-peak position signal (Sig_R); and it sends the position information of each R-peak in the ECG signal to the R-peak position storage module.

[0034] The R-peak position storage module (RAM) is connected to the encoding module and sends the data information of each R-peak in the ECG signal to the encoding module.

[0035] The encoding module is connected to both the FIFO buffer module and the control state machine; it includes a voltage amplitude signal differential module and an R-peak interval signal differential module. The voltage amplitude signal differential module encodes the amplitude data of the ECG signal based on the received original SIG signal and the R-peak data information of each heartbeat in the original SIG signal, and sends the encoded amplitude data to the FIFO buffer module. The R-peak interval signal differential module encodes the R-peak interval based on the received R-peak data information, and sends the resulting R-peak interval encoding to the FIFO buffer module.

[0036] The FIFO buffer module is connected to the control state machine and is used to combine the received amplitude data encoding, R-peak spacing change trend encoding, and R-peak spacing encoding to obtain the binary encoding of the ECG signal, and then send it to the control state machine.

[0037] The control state machine is used to control the timing of the serial-to-parallel conversion module, the encoding module, and the FIFO buffer module according to the timing of the ECG signal sent by the UART receiver.

[0038] In this embodiment, the data flow of each module is as follows: Figure 2 , Figure 3 As shown, the UART receives 8 bits of data from the PC and outputs a 96-bit amplitude-encoded signal. This 96-bit amplitude-encoded signal consists of a 74-bit differential Sig signal obtained through differential encoding and a 22-bit R-peak spacing signal. In this embodiment, the UART receiver is a serial interface, therefore the hardware design is primarily serial to save hardware resources. The data flow direction in each module is as follows:

[0039] The UART receiver receives floating-point data from an external PC and then sends it directly to the serial-to-parallel conversion module. The module converts this data into the corresponding encoded data as needed. On the PC, one original Sig signal is quantized to 16 bits, and one R-peak position signal (Sig_R) is quantized to 24 bits. To maintain the integrity of the ECG signal characteristics during conversion and to simplify calculations in the next encoding module, two different serial-to-parallel conversion methods are used based on the characteristics of the ECG signal: a 2-to-1 serial-to-parallel conversion is used for the amplitude data in the ECG signal, where two consecutive 8-bit UART data bits generate one original Sig signal; a 3-to-1 serial-to-parallel conversion is used for the R-peak spacing data in the ECG signal, where three consecutive 8-bit UART data bits generate one R-peak position signal (Sig_R). The original sig signal and the R-peak position signal Sig_R signal obtained after conversion are sent to the encoding module for encoding processing. The corresponding R-peak position information data is sent to the R-peak position storage module RAM for storage, so that it can be called in subsequent encoding.

[0040] In the encoding module, the original SIG signal is encoded by the voltage amplitude signal differential module. During the encoding process, in order to compress the length of the original SIG signal and convert it into 0-1 bit binary code, differential encoding is used to implement binary encoding. The specific processing steps are as follows:

[0041] S1. Take the difference between two consecutive original Sig signals; if the difference is equal to 0, then these two signals are considered invalid and discarded; if the difference is not equal to 0, then retain the most significant bit of the difference.

[0042] S2, generating amplitude data coding of the ECG signal according to the result of step S1. At this point, the original Sig signal is coded into a 74-bit differential signal. The 74-bit Sig differential signal is generated.

[0043] In this process, due to the limited precision word length effect of the fixed point data, the original rounding down operation is cancelled to avoid the problem of great inconsistency between software and hardware. In practical applications, before differential coding, an operation of adding a bias to each original signal and dividing the minimum resolution is also included to avoid the problem of great inconsistency between software and hardware.

[0044] The R peak position signal Sig_R signal is completed by the R peak interval encoding processing of the R peak interval difference module. In the encoding process, considering the overflow protection, the adjacent continuous 3 R peak data are taken out after receiving all the R peak data, and the interval between the adjacent two R peak data is calculated. Then each R peak interval is quantized into 11 bits, and the adjacent two R peak intervals of a heart beat form a 22-bit R peak interval signal.

[0045] After the ECG signal amplitude data coding and R peak interval coding are completed, a 96-bit binary sequence can be obtained, in which the last 22 bits represent the R peak interval. The first 11 bits represent the interval between the current R peak and the previous R peak, and the last 11 bits represent the interval between the current R peak and the next R peak. Since the neural network has a certain fault tolerance, it can be retrained algorithmically to compensate for errors, so a one-hot encoding module is also added in the encoding of the present application to use one-hot encoding for sparse coding of the 22-bit R peak interval, thereby further reducing the hardware power consumption. The specific process of the encoding is as follows:

[0046] The interval between the current R peak and the previous R peak, and the interval between the current R peak and the next R peak are equally divided according to the number of R peak intervals required to complete the R peak interval coding of the ECG signal. Each segment can be represented by one bit after equal division. In this embodiment, the length of the R peak interval ranges from 0 to 2047, which is equally divided into 11 segments; each segment is represented by one bit. For example, if the R peak interval is 10, the encoded data can be represented as "10000000000". The R peak interval using one-hot encoding will only produce one input pulse, greatly reducing the proportion of 0. In order to further quantitatively analyze the speedup ratio, the ratio of the fixed point interval to the one-hot code interval 0 is calculated as follows:

[0047] Bit '1' density:

[0048] According to this ratio, it can be calculated that the R peak interval data is compressed by 5.5 times through one-hot coding. If the hardware processing can obtain gain from 0, then in the calculation of the first layer input of the neural network, we can conservatively estimate that the hardware will obtain a speed gain of 5.5 times.

[0049] The applicant uses the MIT-BIH, an authoritative data set in the field of electrocardio monitoring, to test the classification effects of artificial neural networks and spiking neural networks with the same network structure, and the accuracy rate can reach 99%, which is equivalent to the level of doctor diagnosis, and the power consumption is far less than other known methods.

[0050] The above examples are only one of the preferred embodiments of the present application, and are not a limitation on the scope of protection of the present application. Any changes made by using the design principles of the present application and on this basis without creative labor shall belong to the protection scope of the present application.

Claims

1. A low-power electrocardiogram signal sampling and encoding device, comprising a UART receiving end, a serial-parallel conversion module, an R-peak position storage module RAM, an encoding module, a FIFO buffer module, and a control state machine, characterized in that: the UART receiving end is connected to the serial-parallel conversion module and the control state machine respectively, and is configured to send an ECG signal transmitted by an external PC to the serial-parallel conversion module and the control state machine; the serial-parallel conversion module is connected to the encoding module, the R-peak position storage module RAM, and the control state machine respectively, and is configured to generate an original sig signal by 2-to-1 serial-parallel conversion of amplitude data in the ECG signal, generate an R-peak position signal Sig_R signal by 3-to-1 serial-parallel conversion of R-peak interval data in the ECG signal, and send R-peak data information in the ECG signal to the R-peak position storage module; the R-peak position storage module RAM is connected to the encoding module and configured to send the R-peak data information in the ECG signal to the encoding module; the encoding module is connected to the FIFO buffer module and the control state machine respectively; the encoding module comprises a voltage amplitude signal difference module and an R-peak interval signal difference module, the voltage amplitude signal difference module is configured to complete amplitude data encoding of the ECG signal according to the received original signal and R-peak data information, and send the amplitude data encoding to the FIFO buffer module, and the R-peak interval signal difference module is configured to complete R-peak interval encoding according to the received R-peak data information and send the R-peak interval encoding to the FIFO buffer module; the FIFO buffer module is connected to the control state machine, and is configured to combine the received amplitude data encoding, R-peak interval change trend encoding, and R-peak interval encoding to obtain binary encoding of the ECG signal; and the control state machine is configured to control the timing of the serial-parallel conversion module, the encoding module, and the FIFO buffer module according to the timing of the ECG signal sent by the UART receiving end. In the voltage amplitude signal difference module, differential encoding is used for amplitude data encoding of the ECG signal, and the process of differential encoding is as follows: S1, difference between two continuous original signals is calculated, if the difference result is equal to 0, the two signals are regarded as invalid signals and discarded, if the difference result is not equal to 0, the most significant bit of the difference value is reserved; S2, amplitude data encoding of the ECG signal is generated according to the difference result of step S1. The process of differential encoding is also provided, that is, each original signal is subjected to an operation of adding a bias except for the minimum resolution before differential encoding, so as to avoid a huge inconsistency problem between software and hardware. In the R-peak interval signal difference module, R-peak interval encoding of the ECG signal is performed according to the following process: S1, distance calculation is performed on three continuous R-peak data, to obtain two adjacent R-peak intervals d1 and d2 of a heartbeat; S2, d1 and d2 are quantized respectively to obtain R-peak interval encoding of the ECG signal. In the R-peak interval signal difference module, a one-hot encoding module is further provided, and one-hot encoding is used for sparse encoding of R-peak interval encoding of the ECG signal, and the specific process is as follows: ​ ​ ​ 2. The low power electrocardiosignal sampling and encoding device according to claim 1, characterized in that: ​ ​ ​ 3. The low power electrocardiosignal sampling and encoding device of claim 2, wherein: ​ 4. The low power electrocardiosignal sampling and encoding device of claim 1, wherein: ​ ​ ​ 5. The low power electrocardiograph signal sampling and encoding device of claim 4, wherein: ​ The interval between the current R peak and the previous R peak and the interval between the current R peak and the next R peak are equally divided according to the number of bits required for encoding the intervals between R peaks of the ECG signal, and each of the divided intervals can be represented by one bit.

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