Display panel, driving method thereof, and display device

Abstract

The embodiments of the present application provide a display panel, a driving method thereof, and a display device. The display panel includes multiple rows of pixel circuits; in the pixel circuits, a driving transistor is used to generate a light-emitting driving current; an input end of a data writing module is electrically connected to a data signal line, and an output end is electrically connected to the first electrode of the driving transistor; an input end of a threshold capture module is electrically connected to the second electrode of the driving transistor, and an output end is electrically connected to the gate of the driving transistor; a first plate of a storage capacitor is electrically connected to the gate of the driving transistor, and a second plate is electrically connected to a power supply voltage signal line; a first end of a data stabilization switch is electrically connected to the first electrode of the driving transistor; wherein the second end of the data stabilization switch of the pixel circuit in the nth row is electrically connected to the first plate of the storage capacitor of the pixel circuit in the n+jth row, where n≥1 and j≥2. The present application can improve the charging time of the display panel during high-frequency display and enhance the low grayscale quality of the display panel during high-frequency display.

Description

Technical field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a driving method thereof, and a display device. [Background Technology]

[0002] Organic light-emitting diode (OLED) display panels have advantages such as low power consumption, self-luminescence, wide viewing angles, wide temperature range, and fast response times, making them widely used in the market. The pixel circuits used to control the light-emitting elements are the core technology of OLED display panels and are of great research significance.

[0003] Before the pixel circuit provides the light-emitting driving current to the light-emitting element, it is usually necessary to charge the gate of the driving transistor in the pixel circuit. However, in the existing pixel circuit, when the display panel displays at high frequency, the charging time of the gate of the driving transistor is short, resulting in poor brightness uniformity when the display panel displays low grayscale, affecting the display quality.

[0004] Application Contents

[0005] In view of this, embodiments of the present application provide a display panel and a driving method thereof, as well as a display device to solve the above-mentioned problems.

[0006] In a first aspect, an embodiment of the present application provides a display panel comprising multiple rows of pixel circuits; the pixel circuits comprise a driving transistor, a data writing module, a threshold capture module, a storage capacitor and a data stabilization switch; the driving transistor is used to generate a light-emitting driving current, the input end of the data writing module is electrically connected to the data signal line, and the output end is electrically connected to the first electrode of the driving transistor, the input end of the threshold capture module is electrically connected to the second electrode of the driving transistor, and the output end is electrically connected to the gate of the driving transistor; the storage capacitor comprises a first plate and a second plate, the first plate is electrically connected to the gate of the driving transistor, and the second plate is electrically connected to the power supply voltage signal line; the first end of the data stabilization switch is electrically connected to the first electrode of the driving transistor, and the data stabilization switch is used to stabilize the potential of the first electrode of the driving transistor; wherein the second end of the data stabilization switch of the pixel circuit in the nth row is electrically connected to the first plate of the storage capacitor of the pixel circuit in the n+jth row, n≥1, j≥2.

[0007] In an implementation of the first aspect, a working cycle of the pixel circuit includes a reset phase and a data writing phase performed sequentially; in the reset phase, the data writing module and the data stabilization switch are turned on, and the data writing module transmits a data voltage to the first electrode of the driving transistor; in the data writing phase, the data stabilization switch and the threshold capture module are turned on.

[0008] In an implementation of the first aspect, the pixel circuit further includes a first reset module, an input end of the first reset module is electrically connected to the first reset signal line, an output end is electrically connected to the gate of the driving transistor, and a control end is electrically connected to the first scan line; in the reset stage, the first reset module is turned on.

[0009] In an implementation of the first aspect, a control end of the data writing module is electrically connected to the first scan line, and a signal transmitted by the first scan line controls the switch states of the data writing module and the first reset module to be the same.

[0010] In an implementation of the first aspect, the data write module includes a first transistor, a first electrode of the first transistor is electrically connected to the data signal line, a second electrode is electrically connected to the first electrode of the driving transistor, and a gate is electrically connected to the first scan line; the first reset module includes a second transistor, a first electrode of the second transistor is electrically connected to the first reset signal line, a second electrode is electrically connected to the gate of the driving transistor, and the gate is electrically connected to the first scan line; wherein the channel type of the first transistor and the second transistor is the same.

[0011] In an implementation of the first aspect, the display panel includes a light-emitting element, and the pixel circuit also includes a second reset module, the input end of the second reset module is electrically connected to the second reset signal line, the output end is electrically connected to the first pole of the light-emitting element, and the control end is electrically connected to the second scan line; the control end of the data stabilization switch is electrically connected to the second scan line, and the signal transmitted by the second scan line controls the switching state of the data stabilization switch and the second reset module to be the same.

[0012] In an implementation of the first aspect, the data stabilization switch includes a third transistor, a first electrode of the third transistor is electrically connected to the first end of the data stabilization switch, a second electrode is electrically connected to the second end of the data stabilization switch, and a gate is electrically connected to the control end of the data stabilization switch; the second reset module includes a fourth transistor, a first electrode of the fourth transistor is electrically connected to the input end of the second reset module, a second electrode is electrically connected to the output end of the second reset module, and a gate is electrically connected to the control end of the second reset module; wherein the third transistor and the fourth transistor have the same channel type

[0013] In an implementation of the first aspect, the threshold capture module includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the input end of the threshold capture module, a second electrode is electrically connected to the output end of the threshold capture module, and a gate is electrically connected to the third scan line.

[0014] In an implementation of the first aspect, during the data writing phase, the threshold capture module is turned off no later than the data stabilization switch is turned off.

[0015] In a second aspect, an embodiment of the present application provides a method for driving a display panel, for driving the display panel provided in the first aspect, wherein a working cycle of a pixel circuit in the display panel includes a reset phase and a data writing phase performed sequentially; the driving method includes:

[0016] In the reset phase, the data writing module and the data stabilization switch are turned on, and the data writing module transmits the data voltage to the first electrode of the driving transistor;

[0017] During the data writing phase, the data stabilization switch and the threshold capture module are turned on.

[0018] In an implementation of the second aspect, the pixel circuit further includes a first reset module, wherein an input terminal of the first reset module is electrically connected to the first reset signal line, an output terminal of the first reset module is electrically connected to the gate of the driving transistor, and a control terminal of the first reset module is electrically connected to the first scan line; and the driving method further includes:

[0019] During the reset phase, the first reset module is turned on.

[0020] In a third aspect, an embodiment of the present application provides a display device, comprising the display panel provided in the first aspect.

[0021] In an embodiment of the present application, a data stabilization switch is provided in the pixel circuit and is electrically connected to the first electrode of the driving transistor and the storage capacitor. The voltage stabilizing effect of the storage capacitor can be utilized to stabilize the potential of the first electrode of the driving transistor, thereby first storing the data voltage on the data signal line to the first electrode of the driving transistor, and then turning on the threshold capture module to transmit the data voltage and the threshold voltage of the driving transistor to the gate of the driving transistor.

[0022] After the data voltage is stored in the first electrode of the driving transistor, the threshold capture module does not need to consider reserving the lead time before turning on, and does not need to consider reserving the post time after turning off, which is conducive to increasing the duration of the threshold capture module being turned on, that is, it is conducive to increasing the charging time of the gate of the driving transistor, and further helps to improve the problems of afterimage and poor brightness uniformity that are prone to occur in the display panel when displaying low grayscale, thereby improving the display quality.

[0023] Furthermore, the data stabilization switch of the pixel circuit in the nth row is electrically connected to the storage capacitor Cst of the pixel circuit in the n+jth row, where n ≥ 1 and j ≥ 2. This prevents the pixel circuit in the nth row from interfering with the pixel circuit in the n+jth row, and eliminates the need for additional voltage-stabilizing capacitors in the display panel, thereby reducing the manufacturing cost of the display panel.

Brief Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0025] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application;

[0026] Figure 2 for Figure 1 A schematic diagram of a pixel circuit;

[0027] Figure 3 for Figure 2 A schematic diagram of a pixel circuit shown;

[0028] Figure 4 for Figure 3 A timing diagram of the pixel circuit shown;

[0029] Figure 5 for Figure 3 Another timing diagram of the pixel circuit shown;

[0030] Figure 6 This is a timing diagram of a three-row pixel circuit related to this application;

[0031] Figure 7 A schematic diagram of another pixel circuit provided in an embodiment of the present application;

[0032] Figure 8 for Figure 7 A timing diagram of the pixel circuit shown;

[0033] Figure 9 A flow chart of a method for driving a display panel provided in an embodiment of the present application;

[0034] Figure 10 A schematic diagram of a display device provided in an embodiment of the present application. [Specific implementation method]

[0035] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0036] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0037] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0038] It should be understood that the term "and / or" as used herein is merely a description of the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0039] In the description of this specification, it is necessary to understand that the words "substantially", "approximately", "approximately", "about", "roughly", "generally" and the like described in the claims and embodiments of this application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0040] It should be understood that although the terms "first," "second," and the like may be used in embodiments of the present application to describe directions, transistors, scan lines, and the like, these directions, transistors, scan lines, and the like should not be limited to these terms. These terms are merely used to distinguish directions, transistors, scan lines, and the like from one another. For example, a first direction may also be referred to as a second direction, and similarly, a second direction may also be referred to as a first direction without departing from the scope of the embodiments of the present application.

[0041] The applicant in this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0042] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present application is shown. Figure 2 for Figure 1 A schematic diagram of a pixel circuit in Figure 3 for Figure 2 A schematic diagram of the pixel circuit shown.

[0043] The embodiment of the present application provides a display panel 01, such as Figure 1 As shown, the display panel 01 includes multiple rows of pixel circuits 10 and multiple light-emitting elements 20. The pixel circuits 10 are used to provide light-emitting drive currents for the light-emitting elements 20. The display panel 01 also includes multiple data signal lines DL1 arranged along a first direction X. The data signal lines DL1 extend along a second direction Y. At least some of the pixel circuits 10 arranged along the second direction Y are electrically connected to the same data signal line DL1. The first direction X can be the row direction of the display panel 01, and the second direction Y can be the column direction of the display panel 01.

[0044] like Figure 2 and Figure 3 As shown, the pixel circuit 10 includes a driving transistor Md, a data writing module 101 , a threshold capture module 102 , a storage capacitor Cst and a data stabilization switch 103 .

[0045] The driving transistor Md is used to generate a light-emitting driving current; the input end 1011 of the data writing module 101 is electrically connected to the data signal line DL1, and the output end 1012 is electrically connected to the first electrode of the driving transistor Md. The data writing module 101 can be used to transmit the data voltage Vdata to the first electrode of the driving transistor Md; the input end 1021 of the threshold capture module 102 is electrically connected to the second electrode of the driving transistor Md, and the output end 1022 is electrically connected to the gate of the driving transistor Md. The threshold capture module 102 can be used to capture the threshold voltage Vth of the driving transistor Md. The first electrode of the driving transistor Md can be its source and the second electrode can be its drain; the first end 1031 of the data stabilization switch 103 is electrically connected to the first electrode of the driving transistor Md. The data stabilization switch 103 is used to stabilize the potential of the first electrode of the driving transistor Md.

[0046] The storage capacitor Cst includes a first plate C1 and a second plate C2. The first plate C1 is electrically connected to the gate of the driving transistor Md, and the second plate C2 is electrically connected to the power supply voltage signal line DY1. The storage capacitor Cst can stabilize the gate potential of the driving transistor Md.

[0047] The second end 1032 of the data stabilization switch 103 of the pixel circuit 10 in the nth row is electrically connected to the first plate C1 of the storage capacitor Cst of the pixel circuit 10 in the (n+j)th row, where n≥1 and j≥2.

[0048] That is to say, in addition to stabilizing the gate potential of the driving transistor Md in the pixel circuit 10 in the row (n+j), the storage capacitor Cst of the pixel circuit 10 in the row can also stabilize the first electrode potential of the driving transistor Md in the pixel circuit 10 in the row (n) through the data stabilization switch 103 of the pixel circuit 10 in the row (n).

[0049] In conventional pixel circuits, the data writing module 101 and the threshold capture module 102 are typically enabled for the same period of time, allowing the data voltage Vdata and the threshold voltage Vth to be written to the gate of the driving transistor Md and charging the gate of the driving transistor Md. However, when the display panel operates at high frequencies, the duration during which the data writing module 101 and the threshold capture module 102 are enabled is compressed, resulting in a reduced charging time for the gate of the driving transistor Md. Consequently, the gate potential of the driving transistor Md fails to reach a preset value, which can lead to image sticking and poor brightness uniformity when the display panel displays low grayscale images.

[0050] After research, the inventors of this application discovered that in conventional pixel circuits, during the process of transmitting the data voltage Vdata from the data signal line DL1 to the data write module 101, to ensure that the data write module 101 receives the accurate data voltage Vdata and transmits it to the drive transistor Md, a certain lead time is typically reserved before the data write module 101 is turned on, so that the data voltage Vdata on the data signal line DL1 changes from the voltage value of the previous stage to the voltage value required for the current stage. Furthermore, to ensure that the data write module 101 does not transmit the data voltage Vdata of the next stage to the drive transistor Md during the process of switching from the on state to the off state, a certain post time is typically reserved after the data write module 101 is turned off. Only after the data write module 101 is turned off does the data voltage Vdata on the data signal line DL1 change from the voltage value required for the current stage to the voltage value required for the next stage. Therefore, when the display panel displays at high frequencies, reducing the above lead time or post time to increase the charging time of the gate of the drive transistor Md becomes a solution.

[0051] In an embodiment of the present application, a data stabilization switch 103 is provided in the pixel circuit 10 and is electrically connected to the first electrode of the driving transistor Md and the storage capacitor Cst. The voltage stabilizing effect of the storage capacitor Cst can be utilized to stabilize the potential of the first electrode of the driving transistor Md, so that the data voltage Vdata on the data signal line DL1 can be first stored in the first electrode of the driving transistor Md, and then the threshold capture module 102 is turned on to transmit the data voltage Vdata and the threshold voltage Vth to the gate of the driving transistor Md.

[0052] After the data voltage Vdata is stored in the first electrode of the driving transistor Md, the threshold capture module 102 does not need to consider reserving a lead time before turning on, and does not need to consider reserving a post time after turning off, which is beneficial to increasing the duration of the threshold capture module 102 being turned on, that is, it is beneficial to increasing the charging time of the gate of the driving transistor Md, and further helps to improve the problems of afterimages and poor brightness uniformity that are prone to occur in the display panel 01 when displaying low grayscale, thereby improving the display quality.

[0053] Furthermore, the data stabilization switch 103 of the pixel circuit 10 in the nth row is electrically connected to the storage capacitor Cst of the pixel circuit 10 in the n+jth row, where n ≥ 1 and j ≥ 2. This prevents the pixel circuit 10 in the nth row from interfering with the pixel circuit 10 in the n+jth row, and eliminates the need for additional voltage-stabilizing capacitors in the display panel 01, thereby reducing the manufacturing cost of the display panel 01.

[0054] Figure 4 for Figure 3 A timing diagram of the pixel circuit shown.

[0055] In one embodiment of the present application, Figure 3 and Figure 4 As shown, a working cycle Z of the pixel circuit 10 includes a reset phase E1 and a data writing phase E2 which are performed sequentially, and the data writing phase E2 is performed after the reset phase E1.

[0056] In the reset phase E1, the data writing module 101 and the data stabilization switch 103 are turned on, and the data writing module 101 transmits the data voltage Vdata to the first electrode of the driving transistor Md. At the same time, the first electrode of the driving transistor Md is electrically connected to the storage capacitor Cst via the data stabilization switch 103, and the potential of the first electrode of the driving transistor Md can be maintained at the data voltage Vdata.

[0057] In the data writing phase E2, the data stabilization switch 103 and the threshold capture module 102 are turned on. The data voltage Vdata stored in the first electrode of the driving transistor Md can be transmitted to the gate of the driving transistor Md through the driving transistor Md and the threshold capture module 102, completing the charging of the gate of the driving transistor Md.

[0058] At the same time, the first electrode of the driving transistor Md continues to be electrically connected to the storage capacitor Cst through the data stabilization switch 103, and the potential of the first electrode of the driving transistor Md can be maintained at the data voltage Vdata to ensure the accuracy of the data voltage Vdata transmitted to the gate of the driving transistor Md.

[0059] Further, please continue to combine Figure 3 and Figure 4 The pixel circuit 10 further includes a first reset module 104 having an input terminal 1041 electrically connected to the first reset signal line SL1, an output terminal 1042 electrically connected to the gate of the driving transistor Md, and a control terminal 1043 electrically connected to the first scan line SP1.

[0060] In the reset phase E1 , the first reset module 104 is turned on.

[0061] Specifically, in the reset stage E1, the first scan line SP1 transmits a valid signal to control the first reset module 104 to turn on, and the first reset signal line SL1 transmits the first reset voltage Vref1. The first reset voltage Vref1 is transmitted to the gate of the driving transistor Md through the turned-on first reset module 104, completing the resetting of the gate of the driving transistor Md.

[0062] In the embodiment of the present application, during the reset phase E1, a first reset module 104 is provided to transmit a first reset voltage Vref1 to the gate of the driving transistor Md. Simultaneously, a data writing module 101 is provided to transmit a data voltage Vdata to the first electrode of the driving transistor Md. The first electrode of the driving transistor Md is electrically connected to the storage capacitor Cst via a data stabilization switch 103. The voltage stabilization function of the storage capacitor Cst maintains the potential of the first electrode of the driving transistor Md at the data voltage Vdata. This facilitates reducing the duration of a duty cycle Z of the pixel circuit 10, thereby facilitating high-frequency display of the display panel 01.

[0063] Please refer to Figure 2 and Figure 3 In one embodiment of the present application, the control terminal 1013 of the data writing module 101 is electrically connected to the first scan line SP1, and the signal transmitted by the first scan line SP1 controls the switching state of the data writing module 101 and the first reset module 104 to be the same.

[0064] Alternatively, as Figure 3 As shown, the data writing module 101 includes a first transistor M1, wherein a first electrode of the first transistor M1 is electrically connected to the data signal line DL1, a second electrode is electrically connected to the first electrode of the driving transistor Md, and a gate is electrically connected to the first scan line SP1. The first reset module 104 includes a second transistor M2, wherein a first electrode of the second transistor M2 is electrically connected to the first reset signal line SL1, a second electrode is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the first scan line SP1.

[0065] The first transistor M1 and the second transistor M2 have the same channel type.

[0066] In the embodiment of the present application, the first reset module 104 and the data writing module 101 are both electrically connected to the first scan line SP1, which is beneficial to reducing the number of scan lines electrically connected to the pixel circuit 10, thereby helping to reduce the number of peripheral driving circuits that provide scan signals to the pixel circuit 10, and further helping to reduce the preparation cost of the display panel 01.

[0067] In one embodiment of the present application, Figure 1-Figure 3 As shown, the display panel 01 includes a light-emitting element 20, and the pixel circuit 10 also includes a second reset module 105. The input terminal 1051 of the second reset module 105 is electrically connected to the second reset signal line SL2, the output terminal 1052 is electrically connected to the first pole of the light-emitting element 20, and the control terminal 1053 is electrically connected to the second scan line SP2. The second reset module 105 is used to transmit the second reset voltage Vref2 on the second reset signal line SL2 to the first pole of the light-emitting element 20 to reset the first pole of the light-emitting element 20.

[0068] The control terminal 1033 of the data stabilization switch 103 is electrically connected to the second scan line SP2 , and the signal transmitted by the second scan line SP2 controls the switching states of the data stabilization switch 103 and the second reset module 105 to be the same.

[0069] That is to say, in the reset stage E1 and the data writing stage E2, when the data stabilization switch 103 is turned on, the second reset module 105 is also turned on, and the second reset voltage Vref2 on the second reset signal line SL2 can be transmitted to the first pole of the light-emitting element 20 through the second reset module 105, thereby completing the reset of the first pole of the light-emitting element 20.

[0070] Alternatively, as Figure 3 As shown, the data stabilization switch 103 includes a third transistor M3, a first electrode of the third transistor M3 being electrically connected to the first end 1031 of the data stabilization switch 103, a second electrode being electrically connected to the second end 1032 of the data stabilization switch 103, and a gate being electrically connected to the control end 1033 of the data stabilization switch 103. That is, the first electrode of the third transistor M3 of the pixel circuit 10 in the nth row is electrically connected to the first electrode of the driving transistor Md in the pixel circuit 10, the second electrode is electrically connected to the first plate C1 of the storage capacitor Cst of the pixel circuit 10 in the (n+j)th row, and the gate is electrically connected to the second scan line SP2.

[0071] The second reset module 105 includes a fourth transistor M4. A first electrode of the fourth transistor M4 is electrically connected to an input terminal 1051 of the second reset module 105, a second electrode is electrically connected to an output terminal 1052 of the second reset module 105, and a gate is electrically connected to a control terminal 1053 of the second reset module 105. That is, a first electrode of the fourth transistor M4 is electrically connected to the second reset signal line SL2, a second electrode is electrically connected to the first electrode of the light-emitting element 20, and a gate is electrically connected to the second scan line SP2.

[0072] The third transistor M3 and the fourth transistor M4 have the same channel type.

[0073] In the embodiment of the present application, the data stabilization switch 103 and the second reset module 105 are both electrically connected to the second scan line SP2, which is beneficial to further reduce the number of scan lines electrically connected to the pixel circuit 10, thereby further reducing the number of peripheral driving circuits that provide scan signals to the pixel circuit 10, and further reducing the preparation cost of the display panel 01.

[0074] Please continue to refer to Figure 2 and Figure 3In one embodiment of the present application, the control terminal 1023 of the threshold capture module 102 is electrically connected to the third scan line SP3. In the data writing phase E2, the third scan line SP3 transmits a valid signal to control the threshold capture module 102 to turn on and charge the gate of the driving transistor Md.

[0075] like Figure 3 As shown, the threshold capture module 102 includes a fifth transistor M5, a first electrode of the fifth transistor M5 being electrically connected to the input terminal 1021 of the threshold capture module 102, a second electrode being electrically connected to the output terminal 1022 of the threshold capture module 102, and a gate being electrically connected to the third scan line SP3. That is, the threshold capture module 102 may include only one fifth transistor M5, a first electrode of the fifth transistor M5 being electrically connected to the second electrode of the driving transistor Md, and a second electrode being electrically connected to the gate of the driving transistor Md.

[0076] In addition, combined Figure 2 and Figure 3 As shown, the pixel circuit 10 further includes a power supply voltage writing module 106 and a light emission control module 107. The power supply voltage writing module 106 has an input terminal 1061 electrically connected to the power supply voltage signal line DY1, an output terminal 1062 electrically connected to the first electrode of the driving transistor Md, and a control terminal 1063 electrically connected to the light emission control signal line EM. The light emission control module 107 has an input terminal 1071 electrically connected to the second electrode of the driving transistor Md, an output terminal 1072 electrically connected to the first electrode of the light emitting element 20, and a control terminal 1073 electrically connected to the light emission control signal line EM.

[0077] The power supply voltage writing module 106 may include a sixth transistor M6, wherein a first electrode of the sixth transistor M6 is electrically connected to the power supply voltage signal line DY1, a second electrode is electrically connected to the first electrode of the driving transistor Md, and a gate is electrically connected to the light emission control signal line EM. The light emission control module 107 may include a seventh transistor M7, wherein a first electrode of the seventh transistor M7 is electrically connected to the second electrode of the driving transistor Md, a second electrode is electrically connected to the first electrode of the light emitting element 20, and a gate is electrically connected to the light emission control signal line EM.

[0078] In order to explain the technical solution of this application more clearly, Figure 3 and Figure 4 right Figure 3 The working process of the pixel circuit 10 is described below.

[0079] It should be noted that the following description is based on an example in which the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are P-type transistors. Of course, any one of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may also be an N-type transistor.

[0080] A working cycle Z of the pixel circuit 10 includes a reset phase E1 , a data writing phase E2 and a light emitting phase E3 which are performed in sequence.

[0081] During the reset phase E1, the first scan line SP1 and the second scan line SP2 transmit low-level turn-on signals, turning on the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4. The third scan line SP3 and the light-emission control signal line EM transmit high-level turn-off signals, turning off the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7. Simultaneously, the first reset signal line SL1 transmits a first reset voltage Vref1, which is transmitted to the gate of the drive transistor Md via the turned-on second transistor M2, resetting the gate of the drive transistor Md. The data signal line DL1 transmits a data voltage Vdata, which is transmitted to the first electrode of the drive transistor M1 via the turned-on first transistor M1. The first electrode of the drive transistor Md is then electrically connected to the storage capacitor Cst via the turned-on third transistor M3, allowing the data voltage Vdata to be stored at the first electrode of the drive transistor Md.

[0082] At the same time, the second reset signal line SL2 transmits a second reset voltage Vref2, which is transmitted to the first electrode of the light-emitting element 20 via the turned-on fourth transistor M4, thereby resetting the light-emitting element 20. Optionally, the light-emitting element 20 includes an organic light-emitting diode, and the second reset voltage Vref2 resets the anode of the organic light-emitting diode via the turned-on fourth transistor M4.

[0083] During the data writing phase E2, the first scan line SP1 and the light-emitting control signal line EM transmit high-level off signals, turning off the first transistor M1, the second transistor M2, the sixth transistor M6, and the seventh transistor M7. The second scan line SP2 and the third scan line SP3 transmit low-level on signals, turning on the third transistor M3, the fourth transistor M4, and the fifth transistor M5. At the start of the data writing phase E2, the gate potential of the driving transistor Md is the first reset voltage Vref1, the first electrode potential of the driving transistor Md is the data voltage Vdata, and the potential difference between the first electrode and the gate of the driving transistor Md is (Vdata-Vref1), which is greater than 0. Therefore, the driving transistor Md is turned on, and the data voltage Vdata is transmitted to the gate of the driving transistor Md through the turned-on driving transistor Md and the fifth transistor M5. Simultaneously, the threshold voltage Vth of the driving transistor Md is transmitted to the gate of the driving transistor Md through the turned-on fifth transistor M5, charging the gate of the driving transistor Md. When the gate potential of the driving transistor Md equals (Vdata-|Vth|), the driving transistor Md is turned off.

[0084] Moreover, the first electrode of the driving transistor Md continues to be electrically connected to the storage capacitor Cst through the turned-on third transistor M3 to ensure the stability of the potential of the first electrode of the driving transistor Md.

[0085] At the same time, the second reset voltage Vref2 transmitted by the second reset signal line SL2 can continue to be transmitted to the first electrode of the light emitting element 20 through the turned-on fourth transistor M4 to reset the light emitting element 20 .

[0086] During the light-emitting phase E3, the first, second, and third scan lines SP1, SP2, and SP3 transmit high-level off signals, turning off the first, second, third, fourth, and fifth transistors M1, M2, M3, M4, and M5. The light-emitting control signal line EM transmits a low-level on signal, turning on the sixth and seventh transistors M6 and M7. Simultaneously, the power supply voltage signal line DY1 transmits the power supply voltage VDD, meaning that the first electrode of the driving transistor Md has the power supply voltage VDD. Because the power supply voltage VDD is greater than the data voltage Vdata, the driving transistor Md generates a light-emitting drive current, which is transmitted to the light-emitting element 20 via the seventh transistor M7, controlling the light-emitting element 20 to emit light.

[0087] To ensure the accuracy of the data voltage Vdata received by the pixel circuit 10, a lead time is reserved before the first scan line SP1 transmits a valid signal to control the first transistor M1 to turn on, and a post time is reserved after the first transistor M1 is turned on. However, the lead time and post time do not need to be considered when the fifth transistor M5 is turned on. Therefore, the duration of the fifth transistor M5 turning on can be set to be longer than the duration of the first transistor M1 turning on, thereby increasing the charging time of the gate of the driving transistor Md.

[0088] Figure 5 for Figure 3 Another timing diagram of the pixel circuit shown.

[0089] In one embodiment of the present application, in the data writing phase E2, the threshold capture module 102 is turned off no later than the data stabilization switch 103 is turned off.

[0090] That is, in the data writing phase E2 , the period during which the threshold value capturing module 102 is turned on is within the period during which the data stabilization switch 103 is turned on.

[0091] Optionally, combined Figure 3 and Figure 4 As shown, in the data writing phase E2, the time when the threshold capture module 102 is turned off is the same as the time when the data stabilization switch 103 is turned off.

[0092] Optionally, combined Figure 3 and Figure 5 As shown, in the data writing phase E2, the time when the threshold capture module 102 is turned off is earlier than the time when the data stabilization switch 103 is turned off.

[0093] In the embodiment of the present application, during the period when the threshold capture module 102 is turned on, the first electrode of the driving transistor Md is electrically connected to the storage capacitor Cst through the data stabilization switch 103, which can ensure the stability of the potential of the first electrode of the driving transistor Md at the data voltage Vdata, which is beneficial to ensuring the accuracy of the data voltage Vdata transmitted by the threshold capture module 102 to the gate of the driving transistor Md.

[0094] Figure 6 This is a timing diagram of a circuit of three adjacent rows of pixels related to this application.

[0095] In the embodiment of the present application, the second end 1032 of the data stabilization switch 103 of the pixel circuit 10 in the nth row is electrically connected to the first plate C1 of the storage capacitor Cst of the pixel circuit 10 in the n+jth row, where n ≥ 1 and j ≥ 2. Thus, while the storage capacitor Cst of the pixel circuit 10 in the n+jth row is used to stabilize the potential of the first electrode of the drive transistor Md of the pixel circuit 10 in the nth row, the operation processes of the pixel circuit 10 in the nth row and the pixel circuit 10 in the n+jth row can be prevented from interfering with each other.

[0096] For example, Figure 6 As shown, when j=2, when the pixel circuit 10 in the n+2th row starts to execute the reset phase E1, the pixel circuit 10 in the nth row has completed the reset phase E1 and the data writing phase E2, and the data stabilization switch 103 in the pixel circuit 10 in the nth row has been closed, thereby avoiding the working process of the pixel circuit 10 in the nth row and the working process of the pixel circuit 10 in the n+2th row from affecting each other.

[0097] Figure 7 A schematic diagram of another pixel circuit provided in an embodiment of the present application is shown. Figure 8 for Figure 7 A timing diagram of the pixel circuit shown.

[0098] Figure 7 The pixel circuit 10 shown is Figure 3 The difference of the pixel circuit 10 is that the second transistor M2 and the fifth transistor M5 are N-type transistors including a metal oxide active layer, and the gate of the second transistor M2 is electrically connected to the fourth scan line SP4.

[0099] Compared to Figure 4 The timing shown, Figure 8 The timing changes shown are: the fourth scan line SP4 transmits a high level signal to turn on the second transistor M2 and transmits a low level signal to turn off the second transistor M2. The third scan line SP3 transmits a high level signal to turn on and a low level signal to turn off.

[0100] exist Figure 7 In the illustrated pixel circuit 10, the second transistor M2 and the fifth transistor M5 can both include an indium gallium zinc oxide (IGZO) active layer. Since oxide semiconductor transistors have low off-state leakage current, the effect of leakage current through the second transistor M2 or the fifth transistor M5 on the gate potential of the drive transistor Md can be reduced, which helps maintain the stability of the gate potential of the drive transistor Md, thereby improving the stability of the light-emitting drive current generated by the pixel circuit 10.

[0101] Figure 9A flow chart of a method for driving a display panel provided in an embodiment of the present application.

[0102] The embodiment of the present application also provides a method for driving the display panel 01, which is used to drive the display panel 01 provided in the above embodiment. The structure of the display panel 01 can be as follows: Figure 1 As shown, the structure of the pixel circuit 10 included therein can be as follows Figure 2 、 Figure 3 、 Figure 7 The driving method can be understood in conjunction with the working process of the pixel circuit 10 described above.

[0103] A working cycle Z of the pixel circuit 10 in the display panel 01 includes a reset phase E1 and a data writing phase E2 performed sequentially. Figure 9 As shown, the driving method includes:

[0104] Step B1: In the reset phase E1, the data writing module 101 and the data stabilization switch 103 are turned on, and the data writing module 101 transmits the data voltage Vdata to the first electrode of the driving transistor Md.

[0105] Step B2: In the data writing phase E2, the data stabilization switch 103 and the threshold capture module 102 are turned on.

[0106] In the driving method provided in the embodiment of the present application, the data voltage Vdata on the data signal line DL1 is first stored in the first electrode of the driving transistor Md, and the first electrode of the driving transistor Md is electrically connected to the storage capacitor Cst through the data stabilization switch 103. The voltage stabilization effect of the storage capacitor Cst is utilized to maintain the potential of the first electrode of the driving transistor Md at the data voltage Vdata, and then the threshold capture module 102 is turned on to transmit the data voltage Vdata and the threshold voltage Vth to the gate of the driving transistor Md.

[0107] After the data voltage Vdata is stored in the first electrode of the driving transistor Md, the threshold capture module 102 does not need to consider reserving a lead time before turning on, and does not need to consider reserving a post time after turning off, which is beneficial to increasing the duration of the threshold capture module 102 being turned on, that is, it is beneficial to increasing the charging time of the gate of the driving transistor Md, and further helps to improve the problems of afterimages and poor brightness uniformity that are prone to occur in the display panel 01 when displaying low grayscale, thereby improving the display quality.

[0108] Furthermore, the data stabilization switch 103 of the pixel circuit 10 in the nth row is electrically connected to the storage capacitor Cst of the pixel circuit 10 in the n+jth row, where n ≥ 1 and j ≥ 2. This prevents the pixel circuit 10 in the nth row from interfering with the pixel circuit 10 in the n+jth row, and eliminates the need for additional voltage-stabilizing capacitors in the display panel 01, thereby reducing the manufacturing cost of the display panel 01.

[0109] In one embodiment of the present application, Figure 2 、 Figure 3 、 Figure 7 As shown, the pixel circuit 10 further includes a first reset module 104, an input terminal 1041 of the first reset module 104 is electrically connected to the first reset signal line SL1, an output terminal 1042 is electrically connected to the gate of the driving transistor Md, and a control terminal 1043 is electrically connected to the first scan line SP1. Figure 9 , step B1 of the driving method further includes:

[0110] In the reset phase E1 , the first reset module 104 is turned on.

[0111] Specifically, in the reset stage E1, the first scan line SP1 transmits a valid signal to control the first reset module 104 to turn on, and the first reset signal line SL1 transmits the first reset voltage Vref1. The first reset voltage Vref1 is transmitted to the gate of the driving transistor Md through the turned-on first reset module 104, completing the resetting of the gate of the driving transistor Md.

[0112] In the embodiment of the present application, during the reset phase E1, a first reset module 104 is provided to transmit a first reset voltage Vref1 to the gate of the driving transistor Md. Simultaneously, a data writing module 101 is provided to transmit a data voltage Vdata to the first electrode of the driving transistor Md. The first electrode of the driving transistor Md is electrically connected to the storage capacitor Cst via a data stabilization switch 103. The voltage stabilization function of the storage capacitor Cst maintains the potential of the first electrode of the driving transistor Md at the data voltage Vdata. This facilitates reducing the duration of a duty cycle Z of the pixel circuit 10, thereby facilitating high-frequency display of the display panel 01.

[0113] Figure 10 A schematic diagram of a display device provided in an embodiment of the present application.

[0114] The embodiment of the present application further provides a display device 02, such as Figure 10 As shown, the display device 02 includes the display panel 01 provided in the above embodiment. For example, the display device 02 can be an electronic device such as a mobile phone, a computer, a television, a wearable electronic device, etc., which is not specifically limited in this application.

[0115] In the display device 02, a data stabilization switch 103 is provided in the pixel circuit 10 and is electrically connected to the first electrode of the driving transistor Md and the storage capacitor Cst. The voltage stabilizing effect of the storage capacitor Cst can be utilized to stabilize the potential of the first electrode of the driving transistor Md, so that the data voltage Vdata on the data signal line DL1 can be first stored in the first electrode of the driving transistor Md, and then the threshold capture module 102 is turned on to transmit the data voltage Vdata and the threshold voltage Vth to the gate of the driving transistor Md.

[0116] After the data voltage Vdata is stored in the first electrode of the driving transistor Md, the threshold capture module 102 does not need to consider reserving a lead time before turning on, and does not need to consider reserving a post time after turning off, which is beneficial to increasing the duration of the threshold capture module 102 being turned on, that is, it is beneficial to increasing the charging time of the gate of the driving transistor Md, and further helps to improve the problems of afterimages and poor brightness uniformity that are prone to occur in the display device 02 when displaying low grayscale, thereby improving the display quality.

[0117] Furthermore, the data stabilization switch 103 of the pixel circuit 10 in the nth row is electrically connected to the storage capacitor Cst of the pixel circuit 10 in the n+jth row, where n ≥ 1 and j ≥ 2. This prevents the pixel circuit 10 in the nth row from interfering with the pixel circuit 10 in the n+jth row, and eliminates the need for additional voltage-stabilizing capacitors in the display device 02, thereby reducing the manufacturing cost of the display device 02.

[0118] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: The device comprises a plurality of rows of pixel circuits, wherein the pixel circuits include: A driving transistor for generating a light-emitting driving current; a data writing module, wherein an input end of the data writing module is electrically connected to the data signal line, and an output end of the data writing module is electrically connected to the first electrode of the driving transistor; a threshold capture module, wherein an input end of the threshold capture module is electrically connected to the second electrode of the driving transistor, and an output end of the threshold capture module is electrically connected to the gate of the driving transistor; a storage capacitor comprising a first plate and a second plate, wherein the first plate is electrically connected to the gate of the driving transistor, and the second plate is electrically connected to the power supply voltage signal line; a data stabilization switch, wherein a first end of the data stabilization switch is electrically connected to the first electrode of the driving transistor, and the data stabilization switch is used to stabilize the potential of the first electrode of the driving transistor; The second end of the data stabilization switch of the pixel circuit in the nth row is electrically connected to the first plate of the storage capacitor of the pixel circuit in the (n+j)th row, where n≥1 and j≥2; One working cycle of the pixel circuit includes a reset phase and a data writing phase performed sequentially; In the reset phase, the data writing module and the data stabilization switch are turned on, and the data writing module transmits a data voltage to the first electrode of the driving transistor; During the data writing phase, the data stabilization switch and the threshold capture module are turned on.

2. The display panel according to claim 1, wherein: The pixel circuit further includes a first reset module, wherein an input terminal of the first reset module is electrically connected to the first reset signal line, an output terminal of the first reset module is electrically connected to the gate of the driving transistor, and a control terminal of the first reset module is electrically connected to the first scan line; During the reset phase, the first reset module is turned on.

3. The display panel according to claim 2, wherein: The control end of the data writing module is electrically connected to the first scanning line, and the signal transmitted by the first scanning line controls the switching states of the data writing module and the first reset module to be the same.

4. The display panel according to claim 3, wherein: The data writing module includes a first transistor, wherein a first electrode of the first transistor is electrically connected to the data signal line, a second electrode is electrically connected to the first electrode of the driving transistor, and a gate is electrically connected to the first scanning line; The first reset module includes a second transistor, wherein a first electrode of the second transistor is electrically connected to the first reset signal line, a second electrode is electrically connected to the gate of the driving transistor, and the gate is electrically connected to the first scan line; The first transistor and the second transistor have the same channel type.

5. The display panel according to claim 1, wherein: The display panel includes a light-emitting element, and the pixel circuit further includes a second reset module, wherein the input end of the second reset module is electrically connected to the second reset signal line, the output end is electrically connected to the first electrode of the light-emitting element, and the control end is electrically connected to the second scan line; The control end of the data stabilization switch is electrically connected to the second scan line, and the signal transmitted by the second scan line controls the switch states of the data stabilization switch and the second reset module to be the same.

6. The display panel according to claim 5, wherein: The data stabilization switch includes a third transistor, wherein a first electrode of the third transistor is electrically connected to the first end of the data stabilization switch, a second electrode of the third transistor is electrically connected to the second end of the data stabilization switch, and a gate of the third transistor is electrically connected to the control end of the data stabilization switch; The second reset module includes a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to an input terminal of the second reset module, a second electrode is electrically connected to an output terminal of the second reset module, and a gate is electrically connected to a control terminal of the second reset module; The third transistor and the fourth transistor have the same channel type.

7. The display panel according to claim 1, wherein: The threshold capture module includes a fifth transistor, a first electrode of the fifth transistor is electrically connected to the input end of the threshold capture module, a second electrode is electrically connected to the output end of the threshold capture module, and a gate is electrically connected to the third scan line.

8. The display panel according to claim 1, wherein: During the data writing phase, the threshold capture module is closed no later than the data stabilization switch is closed.

9. A method for driving a display panel, characterized in that: Used to drive the display panel according to any one of claims 1 to 8, wherein a working cycle of a pixel circuit in the display panel includes a reset phase and a data writing phase performed in sequence; the driving method includes: In the reset phase, the data writing module and the data stabilization switch are turned on, and the data writing module transmits a data voltage to the first electrode of the driving transistor; During the data writing phase, the data stabilization switch and the threshold capture module are turned on.

10. The driving method according to claim 9, wherein: The pixel circuit further includes a first reset module, wherein an input terminal of the first reset module is electrically connected to a first reset signal line, an output terminal of the first reset module is electrically connected to a gate of the driving transistor, and a control terminal of the first reset module is electrically connected to a first scan line; the driving method further includes: During the reset phase, the first reset module is turned on.

11. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 8.

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