A sense amplifier circuit and a readout circuit architecture

Abstract

The application provides a readout circuit architecture and a sense amplification circuit, comprising: a readout amplification unit, comprising: a first P-type transistor and a second P-type transistor; a first offset compensation unit, comprising: a first offset compensation tube and a second offset compensation tube; wherein the first P-type transistor is arranged in a first region, and the second P-type transistor is arranged in a second region; when the first region and the second region are arranged at intervals along a first direction, the first offset compensation tube and the second offset compensation tube are both arranged in a third region, and the third region is located between the first region and the second region; when the first region and the second region are arranged adjacent to each other along the first direction, the first offset compensation tube and the second offset compensation tube are arranged in a fourth region and a fifth region respectively. The application can improve the accuracy of the reading result and improve the performance.

Description

Technical Field

[0001] This invention relates to, but is not limited to, a readout circuit architecture and a sensing amplifier circuit. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, consisting of many repeating memory cells. Each memory cell typically includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the transistor to turn on or off, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0003] The sense amplifier is a crucial component of DRAM, playing a key role in data reading and writing. However, PMOS offset exists in the sense amplifier, causing bit line level changes during data read and write operations, interfering with normal data read and write operations. Furthermore, the sense amplifier contains multiple transistors, which may have issues with improper layout. Summary of the Invention

[0004] The present invention aims to provide a readout circuit architecture and a sensing amplifier circuit, which on the one hand can eliminate the PMOS offset in the sensing amplifier and improve the accuracy of the readout results; on the other hand, can optimize the transistor layout of the sensing amplifier, shorten the wiring length, improve the integration, and improve the overall performance.

[0005] The technical solution of this invention is implemented as follows:

[0006] This application provides a readout circuit architecture, including: a sensing amplifier; the sensing amplifier includes:

[0007] The readout amplification unit is configured to amplify the target voltage on the readout bit line and the complementary readout bit line; the readout amplification unit includes: a first P-type transistor and a second P-type transistor;

[0008] A first offset compensation unit is configured to connect the control terminals of the first P-type transistor and the second P-type transistor to a preset voltage in response to an offset cancellation signal; the first offset compensation unit includes: a first offset compensation transistor and a second offset compensation transistor; wherein...

[0009] The first P-type transistor is disposed in the first region, and the second P-type transistor is disposed in the second region;

[0010] When the first region and the second region are arranged at intervals along the first direction, both the first offset compensation tube and the second offset compensation tube are disposed in the third region, which is located between the first region and the second region.

[0011] When the first region and the second region are arranged adjacent to each other along the first direction, the first offset compensation tube is disposed in the fourth region, which is disposed on the side of the first region away from the second region, and the second offset compensation tube is disposed in the fifth region, which is disposed on the side of the second region away from the first region.

[0012] In the above scheme, the readout amplification unit further includes: a first N-type transistor and a second N-type transistor; wherein, the first N-type transistor is disposed in the sixth region, and the second N-type transistor is disposed in the seventh region, the sixth region and the seventh region are arranged along the first direction; the sixth region is adjacent to the first region, the seventh region is adjacent to the second region, and both the sixth region and the seventh region are located between or outside the first region and the second region; when the first region and the second region are arranged at intervals along the first direction: the sixth region, the first region, the third region, the second region and the seventh region are arranged sequentially along the first direction, or the first region, the sixth region, the third region, the seventh region and the second region are arranged sequentially along the first direction; when the first region and the second region are arranged adjacent to each other along the first direction, the sixth region is located between the first region and the fourth region, and the seventh region is located between the second region and the fifth region.

[0013] In the above scheme, the sensing amplifier further includes:

[0014] An isolation unit is configured to, in response to an isolation signal, connect a bit line to the complementary read bit line and connect a complementary bit line to the read bit line, and connect a control terminal of the first P-type transistor to the complementary read bit line and a control terminal of the second P-type transistor to the read bit line; the isolation unit includes: a first isolation transistor, a second isolation transistor, a third isolation transistor, and a fourth isolation transistor;

[0015] A second offset compensation unit is configured to connect the bit line to the readout bit line and the complementary bit line to the complementary readout bit line in response to the offset cancellation signal. The second offset compensation unit includes a third offset compensation tube and a fourth offset compensation tube. The third isolation tube and the third offset compensation tube are both disposed in an eighth region, and the fourth isolation tube and the fourth offset compensation tube are both disposed in a ninth region. The eighth region and the ninth region are arranged along the first direction outside the first region and the second region, and are located on different sides of the first region and the second region. When the first region and the second region are spaced apart along the first direction, the first isolation tube and the second isolation tube are both disposed in the third region. When the first region and the second region are adjacent along the first direction, the first isolation tube is disposed in the fourth region, and the second isolation tube is disposed in the fifth region.

[0016] In the above scheme, the sensing amplifier further includes:

[0017] An equalization unit is configured to equalize the voltages of the readout bit lines and the complementary readout bit lines; the equalization unit includes equalization tubes; wherein the equalization tubes are arranged in one of the third region, the fourth region, the fifth region, the eighth region, and the ninth region.

[0018] In the above scheme, multiple sets of sensing amplifiers are provided, and the multiple sets of sensing amplifiers are arranged separately along a second direction, which is perpendicular to the first direction. The first P-type transistors of two adjacent sets of sensing amplifiers share the same first active region, which is located within the first active region. The first active region also includes two first P-type transistor gates arranged along the second direction above the first active region. The second P-type transistors of two adjacent sets of sensing amplifiers share the same second active region, which is located within the second active region. The second active region also includes two second P-type transistor gates arranged along the second direction above the second active region. The first offset compensation transistors of the multiple sets of sensing amplifiers correspond to multiple first offset compensation transistors. The plurality of third active regions are arranged separately along the second direction and are disposed in the third region or the fourth region. The third region or the fourth region also includes a first offset compensation transistor gate extending along the second direction, and the first offset compensation transistor gate covers the plurality of third active regions. The plurality of second offset compensation transistors of the sensing amplifier correspond to the plurality of fourth active regions. The plurality of fourth active regions are arranged separately along the second direction and are disposed in the third region or the fifth region. The third region or the fifth region also includes a second offset compensation transistor gate extending along the second direction, and the second offset compensation transistor gate covers the plurality of fourth active regions.

[0019] In the above scheme, the multiple third active regions where the source or drain of the first offset compensation transistor of the multiple sets of sensing amplifiers is located are interconnected; the multiple fourth active regions where the source or drain of the second offset compensation transistor of the multiple sets of sensing amplifiers is located are interconnected.

[0020] In the above scheme, the first isolation tube and the second isolation tube are both disposed in the third region, including: the first isolation tube, the first offset compensation tube, the second offset compensation tube and the second isolation tube are arranged sequentially along the first direction, or the first offset compensation tube, the first isolation tube, the second isolation tube and the second offset compensation tube are arranged sequentially along the first direction; the first isolation tube, the first offset compensation tube, the second offset compensation tube and the second isolation tube share the same active region.

[0021] In the above scheme, in the fourth region, the first offset compensation tube and the first isolation tube are arranged sequentially or in reverse order along the first direction; the first offset compensation tube and the first isolation tube share the same active region extending along the first direction; in the fifth region, the second isolation tube and the second offset compensation tube are arranged sequentially or in reverse order along the first direction; the second isolation tube and the second offset compensation tube share the same active region.

[0022] In the above scheme, in the eighth region, the third offset compensation tube and the third isolation tube are arranged sequentially or in reverse order along the first direction, and the third offset compensation tube and the third isolation tube share the same active region; in the ninth region, the fourth isolation tube and the fourth offset compensation tube are arranged sequentially or in reverse order along the first direction, and the fourth isolation tube and the fourth offset compensation tube share the same active region.

[0023] In the above scheme, the fourth region is connected to the eighth region, and the fifth region is connected to the ninth region; in the connected fourth and eighth regions, the first offset compensation tube, the first isolation tube, the third offset compensation tube, and the third isolation tube are arranged sequentially or in reverse order along the first direction; the first offset compensation tube, the first isolation tube, the third offset compensation tube, and the third isolation tube share the same active region; in the connected fifth and ninth regions, the fourth isolation tube, the fourth offset compensation tube, the second isolation tube, and the second offset compensation tube are arranged sequentially or in reverse order along the first direction, and the fourth isolation tube, the fourth offset compensation tube, the second isolation tube, and the second offset compensation tube share the same active region.

[0024] This application embodiment also provides a sensing amplification circuit, including:

[0025] The readout amplification unit is configured to amplify the target voltage on the readout bit line and the complementary readout bit line; the readout amplification unit includes: a P-type transistor and an N-type transistor;

[0026] An isolation unit is configured to connect a bit line to the complementary read bit line and a complementary bit line to the read bit line in response to an isolation signal, and to connect the control terminal of the P-type transistor to the read bit line or the complementary read bit line in response to the isolation signal.

[0027] The first offset compensation unit is configured to connect the control terminal of the P-type transistor to a preset voltage in response to an offset cancellation signal;

[0028] The second offset compensation unit is configured to connect the bit line to the readout bit line and the complementary bit line to the complementary readout bit line in response to the offset cancellation signal.

[0029] In the above scheme, the isolation unit includes: a first isolation subunit and a second isolation subunit; the isolation signal includes: a first isolation signal and a second isolation signal; the first isolation subunit is configured to connect the control terminal of the P-type transistor to the read bit line or the complementary read bit line in response to the first isolation signal; the second isolation subunit is configured to connect the bit line to the complementary read bit line in response to the second isolation signal, and connect the complementary bit line to the read bit line.

[0030] In the above scheme, the P-type transistor includes a first P-type transistor and a second P-type transistor; the N-type transistor includes a first N-type transistor and a second N-type transistor; a first terminal of the first P-type transistor is connected to the read bit line, and a second terminal is connected to a first voltage; a first terminal of the second P-type transistor is connected to the complementary read bit line, and a second terminal is connected to the first voltage; a control terminal of the first N-type transistor is connected to the bit line, a first terminal of the first N-type transistor is connected to the read bit line, and a second terminal is connected to a second voltage; a control terminal of the second N-type transistor is connected to the complementary bit line, a first terminal of the second N-type transistor is connected to the complementary read bit line, and a second terminal is connected to the second voltage.

[0031] In the above scheme, the first isolation sub-unit includes: a first isolation transistor and a second isolation transistor; the control terminals of the first isolation transistor and the second isolation transistor both receive the first isolation signal; the first end of the first isolation transistor is connected to the control terminal of the second P-type transistor, and the second end of the first isolation transistor is connected to the readout bit line; the first end of the second isolation transistor is connected to the control terminal of the first P-type transistor, and the second end of the second isolation transistor is connected to the complementary readout bit line.

[0032] In the above scheme, the second isolation subunit includes: a third isolation tube and a fourth isolation tube; the control terminals of the third isolation tube and the fourth isolation tube both receive the second isolation signal; the first end of the third isolation tube is connected to the bit line, and the second end of the third isolation tube is connected to the complementary readout bit line; the first end of the fourth isolation tube is connected to the complementary bit line, and the second end of the fourth isolation tube is connected to the readout bit line.

[0033] In the above scheme, the first offset compensation unit includes: a first offset compensation transistor and a second offset compensation transistor; the control terminals of the first offset compensation transistor and the second offset compensation transistor both receive the offset cancellation signal; the first ends of the first offset compensation transistor and the first ends of the second offset compensation transistor are both connected to the preset voltage; the second end of the first offset compensation transistor is connected to the control terminal of the second P-type transistor; the second end of the second offset compensation transistor is connected to the control terminal of the first P-type transistor.

[0034] In the above scheme, the second offset compensation unit includes: a third offset compensation tube and a fourth offset compensation tube; the control terminals of the third offset compensation tube and the fourth offset compensation tube both receive the offset cancellation signal; the first end of the third offset compensation tube is connected to the bit line, and the second end of the third offset compensation tube is connected to the readout bit line; the first end of the fourth offset compensation tube is connected to the complementary bit line, and the second end of the fourth offset compensation tube is connected to the complementary readout bit line.

[0035] In the above scheme, the sensing amplification circuit further includes: an equalization unit configured to equalize the voltages of the readout bit line and the complementary readout bit line; the equalization unit includes: an equalization tube; the control terminal of the equalization tube receives an equalization signal, the first terminal of the equalization tube is connected to the readout bit line, and the second terminal of the equalization tube is connected to the complementary readout bit line.

[0036] Therefore, the embodiments of this application provide a readout circuit architecture and a sensing amplification circuit, including: a readout amplification unit configured to amplify the target voltage on the readout bit line and the complementary readout bit line; the readout amplification unit includes: a first P-type transistor and a second P-type transistor; a first offset compensation unit configured to connect the control terminals of the first P-type transistor and the second P-type transistor to a preset voltage in response to an offset cancellation signal; the first offset compensation unit includes: a first offset compensation transistor and a second offset compensation transistor; wherein, the first P-type transistor is disposed in a first region, and the second P-type transistor is disposed in a second region; when the first region and the second region are arranged at intervals along a first direction, both the first offset compensation transistor and the second offset compensation transistor are disposed in a third region, and the third region is located between the first region and the second region; when the first region and the second region are arranged adjacent to each other along the first direction, the first offset compensation transistor is disposed in a fourth region, the fourth region is disposed on the side of the first region away from the second region, and the second offset compensation transistor is disposed in a fifth region, the fifth region is disposed on the side of the second region away from the first region. On the one hand, the readout circuit architecture provided in this application can eliminate the offset of the P-type transistor, avoid the influence of the offset on the readout results, and improve the accuracy of the readout results. On the other hand, this application includes various transistor layout designs, which can adapt to various design needs and help determine the optimal layout design, thereby shortening the wiring length, improving integration, and improving overall performance. Attached Figure Description

[0037] Figure 1 This application provides a schematic diagram of a readout circuit architecture. Figure 1 ;

[0038] Figure 2 This application provides a schematic diagram of a readout circuit architecture. Figure 2 ;

[0039] Figure 3 This application provides a schematic diagram of a readout circuit architecture. Figure 3 ;

[0040] Figure 4 This application provides a schematic diagram of a readout circuit architecture. Figure 4 ;

[0041] Figure 5 This application provides a schematic diagram of a readout circuit architecture. Figure 5 ;

[0042] Figure 6 This application provides a schematic diagram of a readout circuit architecture. Figure 6 ;

[0043] Figure 7This application provides a schematic diagram of a readout circuit architecture. Figure 7 ;

[0044] Figure 8 This application provides a schematic diagram of a readout circuit architecture. Figure 8 ;

[0045] Figure 9 This application provides a schematic diagram of a readout circuit architecture. Figure 9 ;

[0046] Figure 10 This application provides a schematic diagram of the structure of a sensing amplifier circuit;

[0047] Figure 11 A schematic diagram of a sensing amplifier circuit provided in this application embodiment. Figure 1 ;

[0048] Figure 12 A schematic diagram of a sensing amplifier circuit provided in this application embodiment. Figure 2 . Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0051] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0053] In DRAM, the data stored in the main cell needs to be read out by a sense amplifier. However, the sense amplifier will generate an offset during the data reading process, which will affect the accuracy of the reading result.

[0054] Figure 1 , Figure 2 This is a schematic diagram of an optional readout circuit architecture provided in an embodiment of this application.

[0055] like Figure 1 As shown, the readout circuit architecture 10 includes a sense amplifier 20; the sense amplifier 20 includes a readout amplification unit 101 and a first offset compensation unit 102. The readout amplification unit 101 is configured to amplify the target voltage on the readout bit line SABLT and the complementary readout bit line SABLB; the readout amplification unit 101 includes a first P-type transistor and a second P-type transistor. The first offset compensation unit 102 is configured to connect the control terminals of the first P-type transistor and the second P-type transistor to a preset voltage VBIAS in response to an offset cancellation signal OC; the first offset compensation unit 102 includes a first offset compensation transistor and a second offset compensation transistor.

[0056] like Figure 2 As shown, a first P-type transistor 201 is disposed in a first region 301, and a second P-type transistor 201 is disposed in a second region 302. When the first region 301 and the second region 302 are arranged at intervals along the first direction Y, both the first offset compensation transistor 203 and the second offset compensation transistor 204 are disposed in a third region 303, which is located between the first region 301 and the second region 302. When the first region 301 and the second region 302 are arranged adjacent to each other along the first direction Y, the first offset compensation transistor 203 is disposed in a fourth region 304, which is located on the side of the first region 301 away from the second region 302, and the second offset compensation transistor 204 is disposed in a fifth region 305, which is located on the side of the second region 302 away from the first region 301.

[0057] It should be noted that, Figure 2 The diagram shows a transistor layout, consisting of an active region and a gate located on the active region. Transistor placement requires design; a good layout design can shorten wiring length, increase integration density, and thus improve overall performance.

[0058] In this embodiment, the first P-type transistor 201 is disposed in the first region 301, and the second P-type transistor 201 is disposed in the second region 302; the first region 301 and the second region 302 can be arranged alternately or adjacently. When the first region 301 and the second region 302 are arranged alternately along the first direction Y, the first offset compensation transistor 203 and the second offset compensation transistor 204 can both be disposed in the third region 303 between the first region 301 and the second region 302, as shown in the reference. Figure 2 Left figure; When the first region 301 and the second region 302 are arranged adjacently along the first direction Y, the first offset compensation tube 203 can be disposed in the fourth region 304, which is located on the side of the first region 301 away from the second region 302. The second offset compensation tube 204 can be disposed in the fifth region 305, which is located on the side of the second region 302 away from the first region 301. (See reference) Figure 2 The image on the right.

[0059] It is understood that the readout circuit architecture provided in this application includes a variety of transistor layout designs, which can adapt to various design needs and help determine the optimal layout design, thereby shortening the wiring length, improving integration, and improving overall performance.

[0060] In some embodiments of this application, the readout amplification unit 101 further includes: a first N-type transistor and a second N-type transistor.

[0061] like Figure 3 As shown, a first N-type transistor 205 is disposed in a sixth region 306, and a second N-type transistor 206 is disposed in a seventh region 307. The sixth region 306 and the seventh region 307 are arranged along the first direction Y. The sixth region 306 is adjacent to the first region 301, and the seventh region 307 is adjacent to the second region 302. Both the sixth region 306 and the seventh region 307 are located between or outside the first region 301 and the second region 302. When the first region 301 and the second region 302 are arranged at intervals along the first direction Y: the sixth region 306, the first region 301, the third region 303, the second region 302, and the seventh region 307 are arranged sequentially along the first direction Y; or, the first region 301, the sixth region 306, the third region 303, the seventh region 307, and the second region 302 are arranged sequentially along the first direction Y. When the first region 301 and the second region 302 are arranged adjacent to each other along the first direction Y, the sixth region 306 is located between the first region 301 and the fourth region 304, and the seventh region 307 is located between the second region 302 and the fifth region 305.

[0062] In this embodiment, the first N-type transistor 205 is disposed in the sixth region 306, and the second N-type transistor 206 is disposed in the seventh region 307. The sixth region 306 and the seventh region 307 are arranged along the first direction Y, that is, the first region 301, the second region 307, the sixth region 306, and the seventh region 307 are arranged in the same direction. The sixth region 306 is adjacent to the first region 301, and the seventh region 307 is adjacent to the second region 302. The sixth region 306 and the seventh region 307 may both be located between the first region 301 and the second region 302, or they may both be located outside the first region 301 and the second region 302.

[0063] When the first region 301 and the second region 302 are arranged alternately along the first direction Y, they can be arranged sequentially along the first direction Y in the order of the sixth region 306, the first region 301, the third region 303, the second region 302, and the seventh region 307, for reference. Figure 3 The left figure; or, it can be arranged sequentially along the first direction Y in the order of first region 301, sixth region 306, third region 303, seventh region 307, and second region 302, for reference. Figure 3 In the diagram, when the first region 301 and the second region 302 are arranged adjacently along the first direction Y, the sixth region 306 can be located between the first region 301 and the fourth region 304, and the seventh region 307 can be located between the second region 302 and the fifth region 305. (See reference) Figure 3 The image on the right.

[0064] It is understood that the readout circuit architecture provided in the embodiments of this application employs various layout designs for the first N-type transistor, the second N-type transistor, the first P-type transistor, the second P-type transistor, the first offset compensation transistor, and the second offset compensation transistor to shorten the wiring length of the first N-type transistor, the second N-type transistor, the first P-type transistor, and the second P-type transistor.

[0065] In some embodiments of this application, such as Figure 1As shown, the sense amplifier 20 further includes: an isolation unit 103, a second offset compensation unit 104, and an equalization unit 105. The isolation unit 103 is configured to connect the bit line BLT to the complementary read bit line SABLB and the complementary bit line BLB to the read bit line SABLT in response to an isolation signal ISOP or ISON; it also connects the control terminal of a first P-type transistor to the complementary read bit line SABLB and the control terminal of a second P-type transistor to the read bit line SABLT; the isolation unit 103 includes: a first isolation transistor, a second isolation transistor, a third isolation transistor, and a fourth isolation transistor. The second offset compensation unit 104 is configured to connect the bit line BLT to the read bit line SABLT and the complementary bit line BLB to the complementary read bit line SABLB in response to an offset cancellation signal OC; the second offset compensation unit 104 includes: a third offset compensation transistor and a fourth offset compensation transistor. The equalization unit 105 is configured to equalize the voltages of the read bit line SABLT and the complementary read bit line SABLB; the equalization unit 105 includes: an equalization transistor.

[0066] like Figure 4 As shown, the third isolation tube 209 and the third offset compensation tube 211 are both disposed in the eighth region 308, and the fourth isolation tube 210 and the fourth offset compensation tube 212 are both disposed in the ninth region 309. The eighth region 308 and the ninth region 309 are arranged along the first direction Y outside the first region 301 and the second region 302, and are located on different sides of the first region 301 and the second region 302. When the first region 301 and the second region 302 are arranged alternately along the first direction Y, the first isolation tube 207 and the second isolation tube 208 are both disposed in the third region 303. When the first region 301 and the second region 302 are arranged adjacent to each other along the first direction Y, the first isolation tube 207 is disposed in the fourth region 304, and the second isolation tube 208 is disposed in the fifth region 305. In the above layout, the equalization tube can be disposed in one of the third region 303, the fourth region 304, the fifth region 305, the eighth region 308, and the ninth region 309.

[0067] In this embodiment, the third isolation tube 209 and the third offset compensation tube 211 are both disposed in the eighth region 308, and the fourth isolation tube 210 and the fourth offset compensation tube 212 are both disposed in the ninth region 309. The eighth region 308, the ninth region 309, and other regions are arranged along the same direction (i.e., the first direction Y); the eighth region 308 and the ninth region 309 are arranged outside the first region 301 and the second region 302, and are respectively arranged on different sides. When the first region 301 and the second region 302 are arranged alternately along the first direction Y, the first isolation tube 207 and the second isolation tube 208 are both disposed in the third region 303, as shown in the reference. Figure 4Left and middle figures. When the first region 301 and the second region 302 are arranged adjacent to each other along the first direction Y, the first isolation pipe 207 is disposed in the fourth region 304, and the second isolation pipe 208 is disposed in the fifth region 305, as shown in the reference. Figure 4 The right figure shows that the equalization tubes can be arranged in any one of the following regions: third region 303, fourth region 304, fifth region 305, eighth region 308, and ninth region 309. In some embodiments of this application, such as... Figure 5 and Figure 6 As shown, multiple sets of sensing amplifiers 20 are provided, and these sets of sensing amplifiers 20 are arranged discretely along a second direction X, which is perpendicular to the first direction Y. The first P-type transistors 201 of two adjacent sets of sensing amplifiers 20 share the same first active region A1, which is located in a first region 301. The first region 301 also includes two gates of the first P-type transistors 201 arranged along the second direction X above the first active region A1, with the gates of the first P-type transistors 201 covering the width of the first active region A1 in the first direction Y. The second P-type transistors 202 of two adjacent sets of sensing amplifiers 20 share the same second active region A2, which is located in a second region 302. The second region 302 also includes two gates of the second P-type transistors 202 arranged along the second direction X above the second active region A2.

[0068] It should be noted that two transistors sharing the same active region means that the connection terminals of the two transistors corresponding to the same active region are shared or connected to the same node. For example, the two sources or drains share the same active region, or the two sources or drains are connected to the same constant voltage source or ground terminal.

[0069] In this embodiment, the first offset compensation transistors 203 of the multiple sets of sensing amplifiers 20 correspond to multiple third active regions A3. The multiple third active regions A3 are arranged discretely along the second direction and are disposed in a third region 303 or a fourth region 304. If the first offset compensation transistor 203 is disposed in the third region 303, then the multiple third active regions A3 are disposed in the third region 303. (Refer to...) Figure 6 If the first offset compensation tube 203 is located in the fourth region 304, then multiple third active regions A3 are located in the fourth region 304, as shown in the reference. Figure 5 The third region 303 or the fourth region 304 also includes a first offset compensation transistor 203 gate extending along the second direction X, the first offset compensation transistor 203 gate covering the plurality of third active regions A3.

[0070] The second offset compensation transistors 204 of the multiple sets of sensing amplifiers 20 correspond to multiple fourth active regions A4, which are arranged discretely along the second direction X. These multiple fourth active regions A4 are located in either the third region 303 or the fifth region 305. If the second offset compensation transistor 204 is located in the third region 303, then the multiple fourth active regions A4 are located in the third region 303. (Refer to...) Figure 6 If the second offset compensation tube 204 is located in the fifth region 305, then multiple fourth active regions A4 are located in the fifth region 305, as shown in the reference. Figure 5 The third region 303 or the fifth region 305 also includes a second offset compensation transistor 204 gate extending along the second direction X, the second offset compensation transistor 204 gate covering the plurality of fourth active regions A4.

[0071] In this embodiment of the application, if both the first offset compensation tube 203 and the second offset compensation tube 204 are disposed in the third region 303, and the first offset compensation tube 203 and the second offset compensation tube 204 share the same common active region, then the third active region A3 and the fourth active region A4 coincide in the common active region. Figure 6 As shown.

[0072] In some embodiments of this application, such as Figure 7 and Figure 8 As shown, the third active region A3 where the source or drain of the first offset compensation transistor 203 of the multiple sets of sensing amplifiers 20 is located is interconnected; the fourth active region A4 where the source or drain of the second offset compensation transistor 204 of the multiple sets of sensing amplifiers 20 is located is interconnected.

[0073] In this embodiment, the first offset compensation transistor 203 and the second offset compensation transistor 204 are configured to connect the control terminals of the first P-type transistor and the second P-type transistor to a preset voltage in response to an offset cancellation signal. The source or drain of the first offset compensation transistor 203 and the source or drain of the second offset compensation transistor 204 are connected to the preset voltage VBIAS. Therefore, the sources or drains of the multiple first offset compensation transistors 203 and the multiple second offset compensation transistors 204 connected to the preset voltage VBIAS can be interconnected. That is, the regions corresponding to the source or drain of the first offset compensation transistor 203 in the multiple third active regions A3 arranged in the second direction X can be interconnected, and the regions corresponding to the source or drain of the second offset compensation transistor 204 in the multiple fourth active regions A4 can be interconnected.

[0074] It is understandable that transistors of the same type but different functions share the same active area. By setting up shared source and drain terminals, the use of metal wiring for connection is avoided, and the occupied area is reduced. In this way, the use of metal wiring is reduced, thereby reducing contact resistance and improving memory performance.

[0075] In some embodiments of this application, the first isolation tube 207 and the second isolation tube 208 are both disposed in the third region 303, including: the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged sequentially along the first direction Y, as shown in the reference. Figure 6 and Figure 8 Alternatively, the first offset compensation tube 203, the first isolation tube 207, the second isolation tube 208, and the second offset compensation tube 204 are arranged sequentially along the first direction Y. The first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 share the same active region. In some embodiments of this application, such as... Figure 5 and Figure 9 As shown, in the fourth region 304, the first offset compensation tube 203 and the first isolation tube 207 are arranged sequentially or in reverse order along the first direction Y, and the first offset compensation tube 203 and the first isolation tube 207 share the same active region extending along the first direction Y; in the fifth region 305, the second isolation tube 208 and the second offset compensation tube 204 are arranged sequentially or in reverse order along the first direction Y, and the second isolation tube 208 and the second offset compensation tube 204 share the same active region.

[0076] In some embodiments of this application, such as Figure 6 As shown, in the eighth region 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged sequentially or in reverse order along the first direction Y, and the third offset compensation tube 211 and the third isolation tube 209 share the same active region; in the ninth region 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged sequentially or in reverse order along the first direction Y, and the fourth isolation tube 210 and the fourth offset compensation tube 212 share the same active region.

[0077] In some embodiments of this application, such as Figure 5 and Figure 9As shown, the fourth region 304 is connected to the eighth region 308, meaning that the eighth region 308 and the fourth region 304 are merged into one region, sharing the same active area. The eighth region 308 is not marked in the figure. The fifth region 305 is connected to the ninth region 309, meaning that the ninth region 309 and the fifth region 305 are merged into one region. The ninth region 309 is not marked in the figure. In the connected fourth region 304 and eighth region 308, the first offset compensation tube 203, the first isolation tube 207, the third offset compensation tube 211, and the third isolation tube 209 are arranged sequentially or in reverse order along the first direction Y. The first offset compensation tube 203, the first isolation tube 207, the third offset compensation tube 211, and the third isolation tube 209 share the same active area. In the connected fifth region 305 and ninth region 309, the fourth isolation tube 210, the fourth offset compensation tube 212, the second isolation tube 208 and the second offset compensation tube 204 are arranged sequentially or in reverse order along the first direction Y. The fourth isolation tube 210, the fourth offset compensation tube 212, the second isolation tube 208 and the second offset compensation tube 204 share the same active region.

[0078] Combination Figures 5 to 9 Along the first direction Y, the regions are arranged in one of the following orders:

[0079] (1) When the eighth region 308 and the fourth region 304 are one region, and the ninth region 309 and the fifth region 305 are one region, the fourth region 304, the sixth region 306, the first region 301, the second region 302, the seventh region 307, and the fifth region 305 are arranged in sequence.

[0080] In the fourth region 304, the first offset compensation tube 203, the first isolation tube 207, the third offset compensation tube 211, the third isolation tube 209, and the equalization tube 213 are arranged in sequence.

[0081] For the multiple first offset compensation tubes 203 arranged along the second direction X, the active regions where the source or drain of the multiple first offset compensation tubes 203 are located are interconnected.

[0082] In the fifth area 305, the fourth isolation tube 210, the fourth offset compensation tube 212, the second isolation tube 208, and the second offset compensation tube 204 are arranged in sequence.

[0083] For multiple fourth offset compensation transistors 212 arranged along the second direction X, the active regions where the source or drain of the multiple fourth offset compensation transistors 212 are located can be interconnected or not interconnected.

[0084] (2) When the eighth region 308 and the fourth region 304 are one region, and the ninth region 309 and the fifth region 305 are one region, the sixth region 306, the fourth region 304, the first region 301, the second region 302, the fifth region 305 and the seventh region 307 are arranged in sequence.

[0085] In the fourth region 304, the first offset compensation tube 203, the first isolation tube 207, the third offset compensation tube 211, the third isolation tube 209, and the equalization tube 213 are arranged in sequence.

[0086] In the fifth area 305, the fourth isolation tube 210, the fourth offset compensation tube 212, the second isolation tube 208, and the second offset compensation tube 204 are arranged in sequence.

[0087] or,

[0088] In the fourth region 304, the equalization tube 213, the third isolation tube 209, the third offset compensation tube 211, the first isolation tube 207, and the first offset compensation tube 203 are arranged in sequence and share the same active region.

[0089] In the fifth region 305, the second offset compensation tube 204, the second isolation tube 208, the fourth offset compensation tube 212, and the fourth isolation tube 210 are arranged in sequence.

[0090] (3) The eighth region 308, the sixth region 306, the fourth region 304, the first region 301, the second region 302, the fifth region 305, the seventh region 307, and the ninth region 309 are arranged in sequence;

[0091] In the eighth region 308, the third offset compensation tube 211, the third isolation tube 209, and the equalization tube 213 are arranged in sequence.

[0092] In the fourth region 304, the first offset compensation tube 203 and the first isolation tube 207 are arranged in sequence.

[0093] In the fifth area 305, the second isolation tube 208 and the second offset compensation tube 204 are arranged in sequence.

[0094] In the ninth region 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence;

[0095] or,

[0096] In the eighth zone 308, the third isolation tube 209, the third offset compensation tube 211, and the equalization tube 213 are arranged in sequence.

[0097] In the fourth region 304, the first offset compensation tube 203 and the first isolation tube 207 are arranged in sequence.

[0098] In the fifth area 305, the second isolation tube 208 and the second offset compensation tube 204 are arranged in sequence.

[0099] In the ninth region 309, the fourth offset compensation tube 212 and the fourth isolation tube 210 are arranged in sequence;

[0100] or,

[0101] In the eighth zone 308, the third isolation tube 209, the third offset compensation tube 211, and the equalization tube 213 are arranged in sequence.

[0102] In the fourth area 304, the first isolation tube 207 and the first offset compensation tube 203 are arranged in sequence.

[0103] In the fifth area 305, the second offset compensation tube 204 and the second isolation tube 208 are arranged in sequence;

[0104] In the ninth region 309, the fourth offset compensation tube 212 and the fourth isolation tube 210 are arranged in sequence;

[0105] or,

[0106] In the eighth zone 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0107] In the fourth region 304, the equalization tube 213, the first isolation tube 207, and the first offset compensation tube 203 are arranged in sequence;

[0108] In the fifth area 305, the second offset compensation tube 204 and the second isolation tube 208 are arranged in sequence;

[0109] In the ninth region 309, the fourth offset compensation tube 212 and the fourth isolation tube 210 are arranged in sequence;

[0110] or,

[0111] In the eighth zone 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0112] In the fourth area 304, the first isolation tube 207, the first offset compensation tube 203, and the equalization tube 213 are arranged in sequence.

[0113] In the fifth area 305, the second isolation tube 208 and the second offset compensation tube 204 are arranged in sequence.

[0114] In the ninth area 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0115] or,

[0116] In the eighth zone 308, the third isolation pipe 209 and the third offset compensation pipe 211 are arranged in sequence;

[0117] In the fourth region, the first offset compensation tube 203, the first isolation tube 207, and the equalization tube 213 are arranged in sequence.

[0118] In the fifth area 305, the second isolation tube 208 and the second offset compensation tube 204 are arranged in sequence.

[0119] In the ninth region 309, the fourth offset compensation tube 212 and the fourth isolation tube 210 are arranged in sequence;

[0120] (4) The eighth area 308, the sixth area 306, the first area 301, the third area 303, the second area 302, the seventh area 307, and the ninth area 309 are arranged in sequence;

[0121] In the eighth zone 308, the third isolation tube 209, the third offset compensation tube 211, and the equalization tube 213 are arranged in sequence.

[0122] In the third area 303, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0123] In the ninth area 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0124] or,

[0125] In the eighth zone 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0126] In the third region 303, the equalization tube 213, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0127] In the ninth area 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0128] (5) The eighth area 308, the sixth area 306, the first area 301, the third area 303, the second area 302, the seventh area 307, and the ninth area 309 are arranged in sequence;

[0129] In the eighth zone 308, the third offset compensation tube 211, the third isolation tube 209, and the equalization tube 213 are arranged in sequence.

[0130] In the third area 303, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0131] In the ninth area 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0132] or,

[0133] In the eighth zone 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0134] In the third region 303, the equalization tube 213, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0135] In the ninth area 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0136] (6) The ninth region 309, the sixth region 306, the first region 301, the third region 303, the second region 302, the seventh region 307, and the eighth region 308 are arranged in sequence;

[0137] In the ninth area 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0138] In the third region 303, the equalization tube 213, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0139] In the eighth zone 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0140] (7) Ninth region 309, first region 301, sixth region 306, third region 303, seventh region 307, and eighth region 308 are arranged in sequence.

[0141] In the ninth region 309, the fourth isolation tube 210, the fourth offset compensation tube 212, and the equalization tube 213 are arranged in sequence.

[0142] In the third area 303, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0143] In the eighth zone 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0144] or,

[0145] In the ninth area 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0146] In the third region 303, the equalization tube 213, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0147] In the eighth zone 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0148] (8) The eighth region 308, the first region 301, the sixth region 306, the third region 303, the seventh region 307, and the ninth region 309 are arranged in sequence. In the eighth region 308, the third offset compensation tube 211 and the third isolation tube 209 are arranged in sequence;

[0149] In the third region 303, the equalization tube 213, the first isolation tube 207, the first offset compensation tube 203, the second offset compensation tube 204, and the second isolation tube 208 are arranged in sequence.

[0150] In the ninth region 309, the fourth isolation tube 210 and the fourth offset compensation tube 212 are arranged in sequence.

[0151] In the above arrangement, each of the third region 303, the fourth region 304, the fifth region 305, the eighth region 308, and the ninth region 309 contains an active area, and the pipes contained in each region share the same active area.

[0152] For multiple amplifier circuits arranged along the second direction X, the first offset compensation transistor 203 and the second offset compensation transistor 204 are used to connect the active regions of one end (source or drain) of the preset voltage, which can be interconnected, while the active regions of the other end are not interconnected.

[0153] For multiple amplifier circuits arranged along the second direction X, the gates of the third offset compensation transistor 211, the third isolation transistor 209, the equalization transistor 213, the first isolation transistor 207, the first offset compensation transistor 203, the second offset compensation transistor 204, the second isolation transistor 208, the fourth isolation transistor 210, and the fourth offset compensation transistor 212 all extend along the first direction Y, covering multiple active regions and forming the gate of the corresponding transistor in each amplifier circuit.

[0154] It is understood that the readout circuit architecture provided in this application includes a variety of transistor layout designs, which can adapt to various design needs and help determine the optimal layout design, thereby shortening the wiring length, improving integration, and improving overall performance.

[0155] Figure 10 This is a schematic diagram of a sensing amplifier circuit provided in an embodiment of this application, combined with... Figure 1 and Figure 10The sensing amplifier circuit 30 includes: a readout amplification unit 101, a first offset compensation unit 102, an isolation unit 103, and a second offset compensation unit 104. Wherein:

[0156] The readout amplification unit 101 is configured to amplify the target voltage on the readout bit line SABLT and the complementary readout bit line SABLB; the readout amplification unit 101 includes a P-type transistor and an N-type transistor.

[0157] Isolation unit 103 is configured to connect bit line BLT to complementary read bit line SABLB in response to isolation signal ISON, and connect complementary bit line BLB to read bit line SABLT, and connect control terminal of P-type transistor to read bit line SABLT or complementary read bit line SABLB in response to isolation signal ISON.

[0158] The first offset compensation unit 102 is configured to connect the control terminal of the P-type transistor to a preset voltage VBIAS in response to the offset cancellation signal OC.

[0159] The second offset compensation unit 104 is configured to connect the bit line BLT to the read bit line SABLT and the complementary bit line BLB to the complementary read bit line SABLT in response to the offset cancellation signal OC.

[0160] In some embodiments of this application, the isolation unit 103 includes: a first isolation subunit 1031 and a second isolation subunit 1032; the isolation signals include: a first isolation signal ISOP and a second isolation signal ISON. The first isolation subunit 1031 is configured to connect the control terminal of the P-type transistor to the read bit line SABLT or the complementary read bit line SABLB in response to the first isolation signal ISOP; the second isolation subunit 1032 is configured to connect the bit line BLT to the complementary read bit line SABLB in response to the second isolation signal ISON, and connect the complementary bit line BLB to the read bit line SABLT.

[0161] In some embodiments of this application, the P-type transistor includes a first P-type transistor 201 and a second P-type transistor 202; the N-type transistor includes a first N-type transistor 205 and a second N-type transistor 206. The first terminal of the first P-type transistor 201 is connected to the read bit line SABLT, and the second terminal is connected to a first voltage PCS; the first terminal of the second P-type transistor 202 is connected to the complementary read bit line SABLB, and the second terminal is connected to the first voltage PCS; the control terminal of the first N-type transistor 205 is connected to the bit line BLT, the first terminal of the first N-type transistor 205 is connected to the read bit line SABLT, and the second terminal is connected to a second voltage NCS; the control terminal of the second N-type transistor 206 is connected to the complementary bit line BLB, the first terminal of the second N-type transistor 206 is connected to the complementary read bit line SABLB, and the second terminal is connected to the second voltage NCS.

[0162] In some embodiments of this application, the first isolation subunit 1031 includes: a first isolation transistor 207 and a second isolation transistor 208. The control terminals of both the first isolation transistor 207 and the second isolation transistor 208 receive a first isolation signal ISOP; the first terminal of the first isolation transistor 207 is connected to the control terminal of the second P-type transistor 202, and the second terminal of the first isolation transistor 207 is connected to the readout bit line SABLT; the first terminal of the second isolation transistor 208 is connected to the control terminal of the first P-type transistor 201, and the second terminal of the second isolation transistor 208 is connected to the complementary readout bit line SABLB.

[0163] In some embodiments of this application, the second isolation subunit 1032 includes a third isolation transistor 209 and a fourth isolation transistor 210. The control terminals of both the third isolation transistor 209 and the fourth isolation transistor 210 receive a second isolation signal ISON. The first terminal of the third isolation transistor 209 is connected to the bit line BLT, and the second terminal of the third isolation transistor 209 is connected to the complementary readout bit line SABLB. The first terminal of the fourth isolation transistor 210 is connected to the complementary bit line BLB, and the second terminal of the fourth isolation transistor 210 is connected to the readout bit line SABLT.

[0164] In some embodiments of this application, the first offset compensation unit 102 includes a first offset compensation transistor 203 and a second offset compensation transistor 204. The control terminals of both the first offset compensation transistor 203 and the second offset compensation transistor 204 receive an offset cancellation signal OC. The first terminals of both the first offset compensation transistor 203 and the second offset compensation transistor 204 are connected to a preset voltage VBIAS. The second terminal of the first offset compensation transistor 203 is connected to the control terminal of the second P-type transistor 202. The second terminal of the second offset compensation transistor 204 is connected to the control terminal of the first P-type transistor 201.

[0165] In some embodiments of this application, the second offset compensation unit 104 includes a third offset compensation transistor 211 and a fourth offset compensation transistor 212. The control terminals of both the third offset compensation transistor 211 and the fourth offset compensation transistor 212 receive an offset cancellation signal OC. The first terminal of the third offset compensation transistor 211 is connected to the bit line BLT, and the second terminal of the third offset compensation transistor 211 is connected to the readout bit line SABLT. The first terminal of the fourth offset compensation transistor 212 is connected to the complementary bit line BLB, and the second terminal of the fourth offset compensation transistor 212 is connected to the complementary readout bit line SABLB.

[0166] In some embodiments of this application, the sensing amplifier circuit 30 further includes an equalization unit 105 configured to equalize the voltages of the readout bit line SABLT and the complementary readout bit line SABLB in response to an equalization signal EQ. The equalization unit 105 includes an equalization transistor 213; the control terminal of the equalization transistor 213 receives the equalization signal EQ, a first terminal of the equalization transistor 213 is connected to the readout bit line SABLT, and a second terminal of the equalization transistor 213 is connected to the complementary readout bit line SABLB.

[0167] In this embodiment, data is stored in the storage unit 40, and this data is stored in the capacitor 215 in the form of electric charge. The sensing amplifier circuit 30 can read out and write back the data stored in the storage unit 40, combined with... Figure 10 , Figure 11 and Figure 12 It consists of the following processes:

[0168] S1, Pre-charge stage.

[0169] The system provides a first isolation signal ISOP, a second isolation signal ISON, an offset cancellation signal OC, and an equalization signal EQ. The first offset compensation transistor 203, the second offset compensation transistor 204, the first isolation transistor 207, the second isolation transistor 208, the third isolation transistor 209, the fourth isolation transistor 210, the third offset compensation transistor 211, the fourth offset compensation transistor 212, and the equalization transistor 213 are all in the ON state, thereby pre-charging the bit line BLT, the read bit line SABLT, the complementary bit line BLB, and the complementary read bit line SABLB to a preset voltage VBAIS. The first voltage PCS and the second voltage NCS are pre-charged to the preset voltage VBAIS via an external power supply.

[0170] S2, Offset Elimination Stage.

[0171] Maintaining the offset cancellation signal, a first voltage PCS of the first threshold voltage and a second voltage NCS of the second threshold voltage are provided to the two ends of the readout amplification unit 101. The first offset compensation transistor 203, the second offset compensation transistor 204, the third offset compensation transistor 211 and the fourth offset compensation transistor 212 are in the on state. The bit line BLT is connected to the readout bit line SABLT and the complementary bit line BLB is connected to the complementary readout bit line SABLB. The control terminals of the P-type transistors 201 and 202 are connected to the preset voltage VBAIS.

[0172] The first threshold voltage is greater than the preset voltage VBAIS, the preset voltage VBAIS is greater than the second threshold voltage, and the voltage value of the preset voltage VBAIS is usually half of the first threshold voltage.

[0173] For example, the second threshold voltage may be the ground voltage of 0V, and the first threshold voltage may be 1V.

[0174] During the offset elimination process, the first offset compensation transistor 203 and the second offset compensation transistor 204 are turned on, providing a preset voltage VB AIS to the gate of the first P-type transistor 201 and the gate of the second P-type transistor 202. The first P-type transistor 201 and the second P-type transistor 202 are turned on based on the preset voltage VBAIS. The first voltage PCS is transmitted to the complementary read bit line SABLT and the read bit line SABLB. The device difference between the first P-type transistor 201 and the second P-type transistor 202 will cause a voltage difference between the complementary read bit line SABLT and the read bit line SABLB. Then, the voltage difference between the complementary read bit line SABLT and the read bit line SABLB will compensate for the threshold voltage difference between the first P-type transistor 201 and the second P-type transistor 202, thereby realizing the offset elimination of the PMOS transistor.

[0175] The third offset compensation transistor 211 and the fourth offset compensation transistor 212 are turned on. Bit line BLT is electrically connected to and shares voltage with read bit line SABLT. Complementary bit line BLB is electrically connected to and shares voltage with complementary read bit line SABLT. The voltage of bit line BLT serves as the gate voltage of the first N-type transistor 205 to turn on the first N-type transistor 205. The second voltage NCS is electrically connected to the read bit line SABLT and is transmitted to the read bit line SABLT. The voltage of complementary read bit line SABLT serves as the gate voltage of the second N-type transistor 206 to turn on the second N-type transistor 206. The second voltage NCS is electrically connected to the complementary read bit line SABLT and is transmitted to the complementary read bit line SABLT. Bit line SABLB also compensates for the threshold voltage difference between the first N-type transistor 205 and the second N-type transistor 206 through the voltage difference between the complementary read bit line SABLT and the read bit line SABLB, thereby achieving offset elimination of the N-type transistor. Since bit line BLT is electrically connected to the read bit line SABLT and shares the voltage, and complementary bit line BLB is electrically connected to the complementary read bit line SABLB and shares the voltage, there is also a voltage difference between bit line BLT and complementary bit line BLB. The voltage difference between bit line BLT and complementary bit line BLB can also compensate for the threshold voltage difference between the first P-type transistor 201 and the second P-type transistor 202, and between the first N-type transistor 205 and the second N-type transistor 206.

[0176] By turning on the P-type transistor based on a stable preset voltage VBAIS, the threshold voltage difference between the P-type and N-type transistors is eliminated, thus stably eliminating offset noise in the sense amplifier and avoiding signal sensing errors during amplification.

[0177] S3, Charge Sharing Stage.

[0178] The memory cell transistor 214 is turned on by a control command, opening the memory cell 40 and connecting the bit line BLT to the memory cell 40. The memory cell 40 and the bit line BLT share charge to form the target voltage. At the same time, voltage equalization is performed on the read bit line SABLT and the complementary read bit line SABLT, providing an equalization signal EQ to maintain the first signal terminal PCS and the second signal terminal NCS at the preset voltage VBAIS, thus maintaining the read bit line SABLT and the complementary read bit line SABLT at the preset voltage VBAIS.

[0179] After the storage cell 40 shares charge with the bit line BLT, the voltage on the bit line BLT will decrease or increase according to the stored data in the storage cell 40. If the stored data is "0", the voltage on the bit line BLT will decrease, forming a target voltage that is lower than the preset voltage VBAIS. If the stored data is "1", the voltage on the bit line BLT will increase, forming a target voltage that is higher than the preset voltage VBAIS.

[0180] S4, Pre-sensing stage.

[0181] During the pre-sensing phase, the first signal terminal PCS and the second signal terminal NCS are maintained at the preset voltage VBAIS. The first isolation signal ISOP and the second isolation signal ISON are provided. The bit line BLT is connected to the complementary read bit line SABLB, and the complementary bit line BLB is connected to the read bit line SABLT. The target voltage is transmitted to the complementary read bit line SABLB.

[0182] S5, Sensing Amplification Stage.

[0183] During the sensing amplification stage, a first voltage PCS (a first threshold voltage) and a second voltage NCS (a second threshold voltage) are provided to the two ends of the readout amplification unit 101. This pulls down or raises the complementary readout bit line SABLB voltage, further reducing or raising the voltage on the bit line BLT, thus reading out the data from the amplified memory cell. Simultaneously, the change in the bit line BLT potential causes a synchronous change in the voltage of the memory cell 40, enabling a write-back to the open memory cell 40 and restoring the stored charge in the capacitor 215.

[0184] During the sensing amplification stage, if the stored data is "0", the target voltage is low, the voltage of the complementary readout bit line SAB LB decreases, the first P-type transistor 201 is turned on, the first voltage PCS pulls up the voltage of the readout bit line SAB LT and the complementary bit line BLT, the second N-type transistor 206 is turned on, and the second voltage NCS pulls down the voltage of the complementary readout bit line SABLB and the bit line BLB, thereby realizing the pull-down amplification of the target signal.

[0185] During the sensing amplification stage, if the stored data is "1", the target voltage is high, the voltage of the complementary readout bit line SAB LB increases, the first N-type transistor 205 turns on, the second voltage NCS pulls down the voltage of the readout bit line SAB LT and the complementary bit line BLT, the second P-type transistor 202 turns on, and the first voltage PCS pulls up the voltage of the complementary readout bit line SABLB and the bit line BLB, thus achieving the amplification of the target signal. It can be understood that during the offset elimination stage, the first voltage PCS and the second voltage NCS are provided to the two ends of the readout amplification unit 101, and a stable preset voltage VBIAS is provided to the gate of the P-type transistor to eliminate the offset of the P-type transistor, avoiding the influence of the offset on the reading result and improving the accuracy of the reading result.

[0186] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0187] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0188] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A readout circuit architecture, characterized in that, include: Sensing amplifier; The sensing amplifier includes: The readout amplification unit is configured to amplify the target voltage on the readout bit line and the complementary readout bit line; the readout amplification unit includes: a first P-type transistor and a second P-type transistor; A first offset compensation unit is configured to connect the control terminals of the first P-type transistor and the second P-type transistor to a preset voltage in response to an offset cancellation signal; the first offset compensation unit includes: a first offset compensation transistor and a second offset compensation transistor; wherein... The first P-type transistor is disposed in the first region, and the second P-type transistor is disposed in the second region; When the first region and the second region are arranged at intervals along the first direction, both the first offset compensation tube and the second offset compensation tube are disposed in the third region, which is located between the first region and the second region. When the first region and the second region are arranged adjacent to each other along the first direction, the first offset compensation tube is disposed in the fourth region, which is disposed on the side of the first region away from the second region, and the second offset compensation tube is disposed in the fifth region, which is disposed on the side of the second region away from the first region.

2. The readout circuit architecture according to claim 1, characterized in that, The readout amplification unit further includes: a first N-type transistor and a second N-type transistor; wherein... The first N-type transistor is disposed in the sixth region, and the second N-type transistor is disposed in the seventh region, wherein the sixth region and the seventh region are arranged along the first direction; The sixth region is adjacent to the first region, the seventh region is adjacent to the second region, and both the sixth and seventh regions are located between or outside the first and second regions; When the first region and the second region are arranged at intervals along the first direction: the sixth region, the first region, the third region, the second region, and the seventh region are arranged sequentially along the first direction. Alternatively, the first region, the sixth region, the third region, the seventh region, and the second region may be arranged sequentially along the first direction; When the first region and the second region are arranged adjacent to each other along the first direction, the sixth region is located between the first region and the fourth region, and the seventh region is located between the second region and the fifth region.

3. The readout circuit architecture according to claim 1, characterized in that, The sensing amplifier further includes: An isolation unit is configured to, in response to an isolation signal, connect a bit line to the complementary read bit line and connect a complementary bit line to the read bit line, and connect a control terminal of the first P-type transistor to the complementary read bit line and a control terminal of the second P-type transistor to the read bit line; the isolation unit includes: a first isolation transistor, a second isolation transistor, a third isolation transistor, and a fourth isolation transistor; A second offset compensation unit is configured to connect the bit line to the readout bit line and the complementary bit line to the complementary readout bit line in response to the offset cancellation signal; the second offset compensation unit includes a third offset compensation transistor and a fourth offset compensation transistor; wherein... The third isolation tube and the third offset compensation tube are both disposed in the eighth region, and the fourth isolation tube and the fourth offset compensation tube are both disposed in the ninth region. The eighth region and the ninth region are arranged along the first direction outside the first region and the second region, and are located on different sides of the first region and the second region. When the first region and the second region are arranged at intervals along the first direction, both the first isolation pipe and the second isolation pipe are disposed in the third region; When the first region and the second region are arranged adjacent to each other along the first direction, the first isolation tube is disposed in the fourth region and the second isolation tube is disposed in the fifth region.

4. The readout circuit architecture according to claim 3, characterized in that, The sensing amplifier further includes: An equalization unit is configured to equalize the voltages of the readout bit lines and the complementary readout bit lines; the equalization unit includes: an equalization transistor; wherein... The equalization tubes are arranged in one of the third region, the fourth region, the fifth region, the eighth region, and the ninth region.

5. The readout circuit architecture according to any one of claims 1 to 4, characterized in that, The sensing amplifier is provided in multiple sets, and the multiple sets of sensing amplifiers are arranged separately along the second direction, which is perpendicular to the first direction; The first P-type transistors of two adjacent sets of the sensing amplifiers share the same first active region. The first active region is disposed in the first region, and the first region also includes two gates of the first P-type transistors arranged along the second direction above the first active region. The second P-type transistors of two adjacent sets of the sensing amplifiers share the same second active region. The second active region is disposed in the second region, and the second region also includes two gates of the second P-type transistors arranged along the second direction above the second active region. The multiple sets of first offset compensation transistors of the sensing amplifiers correspond to multiple third active regions. The multiple third active regions are arranged separately along the second direction. The multiple third active regions are disposed in the third region or the fourth region. The third region or the fourth region also includes a first offset compensation transistor gate extending along the second direction. The first offset compensation transistor gate covers the multiple third active regions. The multiple sets of second offset compensation transistors of the sensing amplifier correspond to multiple fourth active regions, which are arranged separately along the second direction. The multiple fourth active regions are disposed in the third region or the fifth region. The third region or the fifth region also includes a second offset compensation transistor gate extending along the second direction, which covers the multiple fourth active regions.

6. The readout circuit architecture according to claim 5, characterized in that, The multiple third active regions where the source or drain of the first offset compensation tube of the multiple sets of the sensing amplifiers are located are interconnected; The multiple fourth active regions where the source or drain of the second offset compensation tube of the multiple sets of sensing amplifiers are located are interconnected.

7. The readout circuit architecture according to claim 3, characterized in that, The first isolation tube and the second isolation tube are both disposed in the third region, including: the first isolation tube, the first offset compensation tube, the second offset compensation tube and the second isolation tube are arranged sequentially along the first direction, or the first offset compensation tube, the first isolation tube, the second isolation tube and the second offset compensation tube are arranged sequentially along the first direction; The first isolation tube, the first offset compensation tube, the second offset compensation tube, and the second isolation tube share the same active region.

8. The readout circuit architecture according to claim 3, characterized in that, In the fourth region, the first offset compensation tube and the first isolation tube are arranged sequentially or in reverse order along the first direction; The first offset compensation tube and the first isolation tube share the same active region extending along the first direction; In the fifth region, the second isolation tube and the second offset compensation tube are arranged sequentially or in reverse order along the first direction; The second isolation tube and the second offset compensation tube share the same active region.

9. The readout circuit architecture according to claim 3, characterized in that, In the eighth region, the third offset compensation tube and the third isolation tube are arranged sequentially or in reverse order along the first direction, and the third offset compensation tube and the third isolation tube share the same active region; In the ninth region, the fourth isolation tube and the fourth offset compensation tube are arranged sequentially or in reverse order along the first direction, and the fourth isolation tube and the fourth offset compensation tube share the same active region.

10. The readout circuit architecture according to claim 3, characterized in that, The fourth region is connected to the eighth region, and the fifth region is connected to the ninth region; In the connected fourth and eighth regions, the first offset compensation tube, the first isolation tube, the third offset compensation tube, and the third isolation tube are arranged sequentially or in reverse order along the first direction; the first offset compensation tube, the first isolation tube, the third offset compensation tube, and the third isolation tube share the same active region; In the connected fifth and ninth regions, the fourth isolation tube, the fourth offset compensation tube, the second isolation tube, and the second offset compensation tube are arranged sequentially or in reverse order along the first direction, and the fourth isolation tube, the fourth offset compensation tube, the second isolation tube, and the second offset compensation tube share the same active region.

11. A sensing amplifier circuit, characterized in that, include: The readout amplification unit is configured to amplify the target voltage on the readout bit line and the complementary readout bit line. The readout amplification unit includes: a P-type transistor and an N-type transistor; An isolation unit is configured to connect a bit line to the complementary read bit line and a complementary bit line to the read bit line in response to an isolation signal, and to connect the control terminal of the P-type transistor to the read bit line or the complementary read bit line in response to the isolation signal. The first offset compensation unit is configured to connect the control terminal of the P-type transistor to a preset voltage in response to an offset cancellation signal; The second offset compensation unit is configured to connect the bit line to the readout bit line and the complementary bit line to the complementary readout bit line in response to the offset cancellation signal. The sensing amplification circuit includes the following stages when performing a readout operation: a pre-charge stage, an offset elimination stage, a charge sharing stage, a pre-sensing stage, and a sensing amplification stage. When the sensing amplification circuit is in the pre-charge stage and the offset cancellation stage, the offset cancellation signal is in an active state, and the first offset compensation unit connects the control terminal of the P-type transistor to a preset voltage in response to the active offset cancellation signal. When the sensing amplification circuit is in the charge sharing stage, the pre-sensing stage, and the sensing amplification stage, the offset cancellation signal is in an invalid state.

12. The sensing amplifier circuit according to claim 11, characterized in that, The isolation unit includes: a first isolation subunit and a second isolation subunit; the isolation signal includes: a first isolation signal and a second isolation signal; The first isolation subunit is configured to connect the control terminal of the P-type transistor to the readout bit line or the complementary readout bit line in response to the first isolation signal; The second isolation subunit is configured to connect a bit line to the complementary read bit line and connect a complementary bit line to the read bit line in response to the second isolation signal.

13. The sensing amplifier circuit according to claim 11, characterized in that, The P-type transistor includes: a first P-type transistor and a second P-type transistor; the N-type transistor includes: a first N-type transistor and a second N-type transistor; The first terminal of the first P-type transistor is connected to the read bit line, and the second terminal is connected to a first voltage; the first terminal of the second P-type transistor is connected to the complementary read bit line, and the second terminal is connected to the first voltage; the control terminal of the first N-type transistor is connected to the bit line, the first terminal of the first N-type transistor is connected to the read bit line, and the second terminal is connected to a second voltage; the control terminal of the second N-type transistor is connected to the complementary bit line, the first terminal of the second N-type transistor is connected to the complementary read bit line, and the second terminal is connected to the second voltage.

14. The sensing amplifier circuit according to claim 12, characterized in that, The first isolation subunit includes: a first isolation tube and a second isolation tube; Both the control terminals of the first isolation transistor and the second isolation transistor receive the first isolation signal; the first end of the first isolation transistor is connected to the control terminal of the second P-type transistor, and the second end of the first isolation transistor is connected to the readout bit line; the first end of the second isolation transistor is connected to the control terminal of the first P-type transistor, and the second end of the second isolation transistor is connected to the complementary readout bit line.

15. The sensing amplifier circuit according to claim 12, characterized in that, The second isolation subunit includes: a third isolation tube and a fourth isolation tube; The control terminals of the third isolation tube and the fourth isolation tube both receive the second isolation signal; the first end of the third isolation tube is connected to the bit line, and the second end of the third isolation tube is connected to the complementary readout bit line; the first end of the fourth isolation tube is connected to the complementary bit line, and the second end of the fourth isolation tube is connected to the readout bit line.

16. The sensing amplifier circuit according to claim 13, characterized in that, The first offset compensation unit includes: a first offset compensation tube and a second offset compensation tube; Both the control terminals of the first offset compensation transistor and the second offset compensation transistor receive the offset cancellation signal; both the first terminals of the first offset compensation transistor and the second offset compensation transistor are connected to the preset voltage; the second terminal of the first offset compensation transistor is connected to the control terminal of the second P-type transistor; and the second terminal of the second offset compensation transistor is connected to the control terminal of the first P-type transistor.

17. The sensing amplifier circuit according to claim 11, characterized in that, The second offset compensation unit includes: a third offset compensation tube and a fourth offset compensation tube; The control terminals of the third offset compensation transistor and the fourth offset compensation transistor both receive the offset cancellation signal; the first end of the third offset compensation transistor is connected to the bit line, and the second end of the third offset compensation transistor is connected to the readout bit line; the first end of the fourth offset compensation transistor is connected to the complementary bit line, and the second end of the fourth offset compensation transistor is connected to the complementary readout bit line.

18. The sensing amplifier circuit according to any one of claims 11 to 17, characterized in that, The sensing amplification circuit further includes: An equalization unit is configured to equalize the voltages of the readout bit lines and the complementary readout bit lines; The equalization unit includes: an equalization tube; the control terminal of the equalization tube receives an equalization signal, the first terminal of the equalization tube is connected to the readout bit line, and the second terminal of the equalization tube is connected to the complementary readout bit line.

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