A key generation method and device, electronic equipment and storage medium

Abstract

The application provides a key generation method and device, electronic equipment and storage medium, and relates to the field of encryption. The method comprises the following steps: obtaining an upper round initial key, and generating corresponding digest information of the upper round initial key by using a digest algorithm; dividing the digest information into low-bit information and high-bit information according to the number of bits, and mapping the low-bit information and the high-bit information to a first low-bit matrix and a first high-bit matrix respectively; determining a mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix, and performing logical operation processing on the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix; generating a current round initial key by using the second low-bit matrix and the second high-bit matrix, and performing cyclic shift processing on the current round initial key to obtain a current round output key, so as to perform round key addition processing by using the current round output key; and the security of the round key addition can be improved by reducing the correlation between the keys.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of encryption, in particular to a key generation method and device, electronic equipment and computer readable storage medium. BACKGROUND

[0002] AES encryption algorithm (Advanced Encryption Standard) is a common encryption algorithm. The algorithm generally includes four encryption processes: key addition layer (also known as round key addition), byte substitution layer, row shift layer and column confusion layer, wherein the round key addition link includes multiple rounds of iteration processing, and each round of processing uses a corresponding key. In related technologies, the key used for each round of processing of the round key addition is generated by simply iterating the key of the previous round, and the correlation between the keys is strong, thereby reducing the security of the encryption. SUMMARY

[0003] The purpose of the present application is to provide a key generation method, device, electronic equipment and computer readable storage medium, which can isolate the keys used for each round of round key addition processing in multiple ways, thereby reducing the correlation between the keys and improving the security of the round key addition processing.

[0004] To solve the above technical problems, the present application provides a key generation method, comprising:

[0005] Obtaining the initial key of the previous round, and generating the digest information corresponding to the initial key of the previous round by using a digest algorithm;

[0006] According to the number of bits, the digest information is equally divided into low-bit information and high-bit information, and the low-bit information and high-bit information are respectively mapped to a first low-bit matrix and a first high-bit matrix;

[0007] Determine the mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix, and perform logical operation processing on the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix;

[0008] Generating the initial key of the current round by using the second low-bit matrix and the second high-bit matrix, and performing cyclic shift processing on the initial key of the current round to obtain the output key of the current round, so as to execute the round key addition processing of the current round by using the output key of the current round.

[0009] Optionally, after generating the initial key of the current round by using the second low-bit matrix and the second high-bit matrix, the method further comprises:

[0010] The elements in the prime table matrix are subjected to logical operation processing with the byte sequence in the initial key of the current round to confuse the initial key of the current round, and the initial key of the current round after confusion is used to generate the initial key of the next round and the output key of the next round.

[0011] Optionally, before the elements in the prime table matrix are subjected to logical operation processing with the byte sequence in the initial key of the current round, the method comprises:

[0012] Obtaining a prime table matrix;

[0013] Transforming the prime table matrix according to a preset rule and the round corresponding to the current round to obtain the prime table matrix.

[0014] Optionally, the cyclic shift processing of the initial key of the current round to obtain the output key of the current round comprises:

[0015] Equally dividing the initial key of the current round into a low-bit key and a high-bit key according to the number of bits;

[0016] Determining first byte data and second byte data in the low-bit key and the high-bit key respectively according to the round corresponding to the current round;

[0017] Respectively performing modulo operation on the first byte data and the second byte data;

[0018] Cyclically shifting the first byte data in the low-bit key according to the modulo operation result of the first byte data to obtain a low-bit confusion key, and cyclically shifting the second byte data in the high-bit key according to the modulo operation result of the second byte data to obtain a high-bit confusion key;

[0019] XORing the low-bit confusion key and the high-bit confusion key, and inserting the round corresponding to the current round in the XORing result to obtain the output key of the current round.

[0020] Optionally, the modulo operation on the first byte data and the second byte data respectively comprises:

[0021] Respectively performing modulo 16 operation on the first byte data and the second byte data to obtain first operation result and second operation result;

[0022] Respectively performing modulo 2 operation on the first operation result and the second operation result to obtain third operation result and fourth operation result;

[0023] Correspondingly, the low-bit confusion key is obtained by cyclically shifting the first byte data in the low-bit key according to a modulo operation result of the first byte data, and the high-bit confusion key is obtained by cyclically shifting the second byte data in the high-bit key according to a modulo operation result of the second byte data, including:

[0024] The shift bit number of the first byte data is determined according to the first operation result, the shift direction of the first byte data is determined according to the third operation result, and the first byte data is cyclically shifted in the low-bit key according to the shift direction of the shift bit number of the first byte data, to obtain the low-bit confusion key;

[0025] The shift bit number of the second byte data is determined according to the second operation result, the shift direction of the second byte data is determined according to the fourth operation result, and the second byte data is cyclically shifted in the high-bit key according to the shift direction of the shift bit number of the second byte data, to obtain the high-bit confusion key. Optionally, the generating of the digest information corresponding to the initial key of the upper round by using the digest algorithm includes:

[0026] The initial key of the upper round is segmented and processed, and a modulo operation is performed on each segment of the initial key of the upper round, to obtain a modulo operation result corresponding to the initial key of the upper round;

[0027] The initial key of the upper round is filled to a preset length by using the round corresponding to the current round and the modulo operation result, to obtain an input value of the digest algorithm;

[0028] The digest information corresponding to the input value is generated by using the digest algorithm.

[0029] Optionally, the initial key of the upper round is an initial key of a first round, and the obtaining of the initial key of the upper round includes:

[0030] A random number key is generated by using a linear feedback shift register with a current time as a random seed, and the random number key is set as the initial key of the first round.

[0031] Optionally, after the random number key is generated by using the linear feedback shift register with the current time as the random seed, the method further includes:

[0032] The random number key is saved in an internal memory.

[0033] Optionally, the determining of the mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix includes:

[0034] Mark each of the first elements as a target first element in sequence, perform a modulo operation on the target first element, find a second element corresponding to the target first element in the first high-bit matrix by taking the modulo operation result as a position value, and establish a first mapping relationship between the target first element and the corresponding second element;

[0035] Mark each of the second elements as a target second element in sequence, perform a modulo operation on the target second element, find a first element corresponding to the target second element in the first low-bit matrix by taking the modulo operation result as a position value, and establish a second mapping relationship between the target second element and the corresponding first element.

[0036] Optionally, the logical operation processing of the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix comprises:

[0037] In the first low-bit matrix, each of the first elements and the second element establishing the first mapping relationship therebetween is subjected to an exclusive or operation to obtain the second low-bit matrix;

[0038] In the first high-bit matrix, each of the second elements and the first element establishing the second mapping relationship therebetween is subjected to an exclusive or operation to obtain the second high-bit matrix.

[0039] The application further provides a key generation device, comprising:

[0040] An abstract calculation module is configured to obtain an initial key of a previous round and generate abstract information corresponding to the initial key of the previous round by using an abstract algorithm;

[0041] A matrix conversion module is configured to equally divide the abstract information into low-bit information and high-bit information according to the number of bits, and map the low-bit information and the high-bit information to a first low-bit matrix and a first high-bit matrix, respectively;

[0042] A matrix mapping module is configured to determine a mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix, and perform logical operation processing of the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix;

[0043] An output key generation module is configured to generate an initial key of a current round by using the second low-bit matrix and the second high-bit matrix, and perform cyclic shift processing on the initial key of the current round to obtain an output key of the current round, so as to perform round key addition processing of the current round by using the output key of the current round.

[0044] The application further provides an electronic device, comprising:

[0045] a memory for storing a computer program;

[0046] a processor for implementing the key generation method as described above when executing the computer program.

[0047] The application further provides a computer readable storage medium, wherein computer executable instructions are stored in the computer readable storage medium, and the computer executable instructions are loaded and executed by a processor to implement the key generation method as described above.

[0048] The application provides a key generation method, comprising: obtaining an initial key of a previous round, and generating corresponding digest information of the initial key of the previous round by using a digest algorithm; equally dividing the digest information into low-bit information and high-bit information according to a bit number, and mapping the low-bit information and the high-bit information to a first low-bit matrix and a first high-bit matrix respectively; determining a mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix, and performing logical operation processing on the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix; generating an initial key of a current round by using the second low-bit matrix and the second high-bit matrix, and performing cyclic shift processing on the initial key of the current round to obtain an output key of the current round, so as to perform round key addition processing of the current round by using the output key of the current round.

[0049] It can be seen that when the initial key of the previous round is obtained, the present application can firstly generate the digest information corresponding to the key by using the digest algorithm, wherein the digest algorithm has good irreversibility, which can weaken the correlation between the initial key of the previous round and the current round key and significantly increase the difficulty of key exhaustion; then, the present application can equally divide the digest information into low-bit information and high-bit information according to the bit number, and map the low-bit information and the high-bit information to the first low-bit matrix and the first high-bit matrix respectively; further, the present application can determine the mapping relationship between the elements in the first low-bit matrix and the first high-bit matrix, and perform logical operation processing on the first low-bit matrix and the first high-bit matrix according to the mapping relationship to obtain the second low-bit matrix and the second high-bit matrix, so as to further enhance the randomness between the initial key of the previous round and the current round key and weaken the correlation between the initial key of the previous round and the current round key; finally, the present application can generate the initial key of the current round by using the second low-bit matrix and the second high-bit matrix, and perform cyclic shift processing on the initial key of the current round to obtain the output key of the current round, so as to perform the round key addition processing of the current round by using the output key of the current round, thereby isolating the output key of the current round and the initial key of the current round and further weakening the correlation between the initial key of the previous round and the output key of the current round, the initial key of the current round and the output key of the current round, thereby solving the problem that the correlation of the key used in the round key addition of the existing advanced encryption standard algorithm is too strong, and achieving the result of one round one key. The present application also provides a key generation device, an electronic equipment and a computer readable storage medium, which have the above beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0051] Figure 1 A flow chart of a key generation method provided by an embodiment of the present application;

[0052] Figure 2 A schematic diagram of the relationship between the initial key and the output key provided by an embodiment of the present application;

[0053] Figure 3 A schematic diagram of the low-bit matrix and the high-bit matrix provided by an embodiment of the present application;

[0054] Figure 4 A schematic diagram of a key generation process provided by an embodiment of the present application;

[0055] Figure 5 A schematic diagram of a prime table matrix provided by an embodiment of the present application;

[0056] Figure 6 A schematic diagram of another key generation process provided by an embodiment of the present application;

[0057] Figure 7 A schematic diagram of an input value of a digest algorithm provided by an embodiment of the present application;

[0058] Figure 8 A structural block diagram of a key generation device provided by an embodiment of the present application;

[0059] Figure 9 A structural block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0060] To make the objectives, technical solutions and advantages of embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0061] The AES encryption algorithm generally includes four encryption processes: a key addition layer (also referred to as a round key addition), a byte substitution layer, a row shift layer, and a column confusion layer. The round key addition process includes multiple rounds of iteration processing, and each round of processing uses a corresponding key. In related technologies, the key used in each round of round key addition processing of the AES encryption algorithm is generated by simply iterating the key of the previous round, that is, the correlation between the keys is relatively strong, which reduces the security of the AES encryption. Therefore, the present application provides a key generation method, which can isolate the keys used in each round of round key addition processing in multiple ways, thereby reducing the correlation between the keys and improving the security of the round key addition processing. It should be noted that the present application does not limit the specific type of the device executing the method, for example, it can be a personal computer, a server, etc., or a special device such as an FPGA (Field Programmable Gate Array), which can be set according to actual application requirements.

[0062] Please refer to Figure 1 , Figure 1 A flowchart of a key generation method provided by an embodiment of the present application, which can include:

[0063] S100, obtaining the initial key of the previous round, and generating the digest information corresponding to the initial key of the previous round by using the digest algorithm.

[0064] It should be noted that the embodiments of the present application involve two types of keys, namely initial keys and output keys. Each round of key generation will generate the initial key and the output key of the corresponding round, wherein the output key of the round is used to perform the round key addition processing and is generated by the initial key of the round, and the initial key of the round is generated by the initial key of the previous round. It should be particularly pointed out that the embodiments of the present application particularly isolate the initial keys and also isolate the initial keys and the output keys of the same round, so that only the initial keys have a recursive relationship, and the output keys do not have a recursive relationship. That is, the initial key of the previous round can generate the output key of the previous round and the initial key of the current round, and the initial key of the current round can generate the output key of the current round, but the output key of the previous round cannot generate the output key of the current round. For ease of understanding, the relationship between the initial keys and the output keys is described with reference to Figure 2 , Figure 2 The embodiments of the present application provide a schematic diagram of the relationship between the initial keys and the output keys. As can be seen, after the improvement of the present application, there will be no direct iterative generation relationship between the output keys, thereby significantly reducing the correlation between the output keys and effectively improving the security of the round key addition link in the AES encryption algorithm.

[0065] It should be noted that the embodiments of the present application do not limit the length of the initial keys and the output keys. For example, it can be 128 bits (Bit), 256 bits, etc., which can be set according to actual application requirements. It can be understood that if the length of the output key is the same as the length of the key required by the AES encryption algorithm, the output key can be directly used for round key addition processing; if the length of the output key is less than or greater than the length of the key required by the AES encryption algorithm, the length of the output key can also be adjusted to the length specified by the AES encryption algorithm by key expansion, high-low bit XOR merging, etc. For ease of understanding, the embodiments of the present application will be introduced based on a specific length of 128 bits.

[0066] The isolation manner between the initial key and the output key provided by the embodiment of the present application will be described in detail below. Firstly, the embodiment of the present application can generate the digest information corresponding to the initial key of the previous round by using the digest algorithm, and generate the initial key and the output key of the current round based on the digest information. Considering that the digest algorithm has the characteristic of irreversibility, that is, it is easy to generate the digest A by using the string A through the digest algorithm, but it is very difficult to reversely restore the string A by using the digest A, therefore, the algorithm can greatly increase the difficulty of restoring the initial key of the previous round by using the initial key of the current round, and further can effectively isolate the initial key of the previous round and the initial key of the current round, thereby significantly reducing the correlation between the initial key of the previous round and the initial key of the current round. It should be noted that the embodiment of the present application does not limit the specific digest algorithm, for example, it can be MD5 (Message-Digest Algorithm, information digest algorithm), SHA256 (Secure Hash Algorithm, secure hash algorithm), etc., which can be set according to actual application requirements. Considering that the SHA256 algorithm is widely used and has strong security, the embodiment of the present application can use SHA256 as the required digest algorithm. It should be pointed out that the output value of SHA256 is 256 bits, that is, the length of the digest information can be 256 bits.

[0067] Further, it can be understood that the initial key of the first round should be generated in other ways. The embodiment of the present application does not limit the generation manner of the initial key of the first round, for example, it can be artificially specified or randomly generated. In order to improve security, the initial key of the first round can be randomly generated in the embodiment of the present application. The embodiment of the present application does not limit the specific manner of randomly generating the initial key of the first round, which can refer to related technologies of random number generation. Preferably, the embodiment of the present application can generate a random number key by using a linear feedback shift register (LFSR, linear feedback shift register), and set the random number key as the initial key of the first round. Of course, in order to further improve the randomness of the initial key of the first round, a random seed (seed) can also be input to the linear feedback shift register to generate a random number key, for example, considering that the time information has strong randomness, therefore, the current time can be input to the linear feedback shift register as a random seed to generate a random number key.

[0068] Based on this, the initial key of the previous round is the initial key of the first round, and obtaining the initial key of the previous round can include:

[0069] S110, generating a random number key by using a linear feedback shift register with the current time as a random seed, and setting the random number key as the initial key of the first round.

[0070] It should be noted that the embodiments of the present application do not limit the specific working mode of the linear feedback shift register, which can be formulated as:

[0071] ;

[0072] wherein, represents the output value of the linear feedback shift register, represents the random seed, represents the tap parameter.

[0073] Further, to avoid other devices or personnel reading this random number key, it can also be saved in the internal memory of the device executing the method, thereby enhancing the security of encryption.

[0074] Based on this, after generating the random number key by using the linear feedback shift register with the current time as the random seed, the method can further include:

[0075] S111, saving the random number key into the internal memory.

[0076] S200, dividing the digest information into low-bit information and high-bit information according to the bit number, and mapping the low-bit information and the high-bit information to a first low-bit matrix and a first high-bit matrix, respectively.

[0077] For the convenience of understanding, please refer to Figure 3 , Figure 3 is a schematic diagram of the low-bit matrix and the high-bit matrix provided by the embodiments of the present application. In a possible case, for the digest information generated by the SHA256 algorithm, the embodiments of the present application can divide it into low-bit information and high-bit information according to the bit number, wherein the low-bit information is the 0-127 bits of the digest information, and the high-bit information is the 128-255 bits of the digest information. Then, the embodiments of the present application can map the low-bit information and the high-bit information to a first low-bit matrix (low 128 bits) and a first high-bit matrix (high 128 bits) respectively according to bytes (each byte contains 8 bits). Among them, the first byte in the low-bit information is mapped to the 0th position in the first low-bit matrix, the second byte is mapped to the 1st position in the first low-bit matrix, and so on. The high-bit information is mapped to the first high-bit matrix in the same way as the low-bit information. In this way, each byte in the low-bit information and the high-bit information can be sequentially mapped to the 16 positions of the first low-bit matrix and the first high-bit matrix. Of course, the above description is based on a specific digest information length and a mapping length (8 bits), and when the length of the digest information, the mapping length (such as changing from 8 bits to 4 bits), and other information change, the form (such as size) of the low-bit matrix and the high-bit matrix may also change, which can be set according to actual application requirements.

[0078] S300, determine a mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix, and perform logical operation processing on the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix.

[0079] After converting the low-bit information and the high-bit information into matrix forms, embodiments of the present application determine a mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix, and perform logical operation processing on the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix, so as to confuse the low-bit information and the high-bit information, thereby further reducing the correlation between the previous round initial key and the current round key.

[0080] It is worth noting that the mapping relationship from the first element to the second element can be different from the mapping relationship from the second element to the first element. For example, the first element A is mapped to the second element B, and the second element B is mapped to the first element C. Furthermore, embodiments of the present application can further improve the randomness between the previous round initial key and the current round key by setting the above chaotic mapping relationship, thereby further reducing the correlation between the previous round initial key and the current round key. It should be noted that embodiments of the present application do not limit the setting method of the above mapping relationship, for example, it can be artificially set, or it can be set based on the numerical value of each element. Considering that the above mapping relationship is set based on the numerical value of each element, it is not only beneficial to improve randomness, but also convenient for key forward restoration, therefore embodiments of the present application can set the above mapping relationship based on the numerical value of each element. Specifically, for the first element, each first element can be sequentially marked as a target first element, the target first element is subjected to modulo 16 operation, the modulo operation result is taken as a position value to find the second element corresponding to the target first element in the first high-bit matrix, and a first mapping relationship between the target first element and the corresponding second element is established. Similarly, for the first element, each second element can be sequentially marked as a target second element, the target second element is subjected to modulo operation, the modulo operation result is taken as a position value to find the first element corresponding to the target second element in the first low-bit matrix, and a second mapping relationship between the target second element and the corresponding first element is established. For example, when the 10th position of the first high-bit matrix is 125, the data obtained after modulo 16 operation is 13, then the 10th position of the first high-bit matrix and the 13th position of the first low-bit matrix are established mapping relationship. For another example, when the 13th position of the first low-bit matrix is 123, the data obtained after modulo 16 operation is 11, then the 13th position of the first low-bit matrix and the 11th position of the first high-bit matrix are established mapping relationship. It should be noted that the number of bits of the modulo operation can also be adjusted according to actual application requirements, and is not limited to 16 bits.

[0081] Based on this, the mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix is determined, including:

[0082] S311, each first element is sequentially marked as a target first element, the target first element is subjected to a modulo operation, the modulo operation result is taken as a position value to find a second element corresponding to the target first element in the first high-bit matrix, and a first mapping relationship between the target first element and the corresponding second element is established.

[0083] S312, each second element is sequentially marked as a target second element, the target second element is subjected to a modulo operation, the modulo operation result is taken as a position value to find a first element corresponding to the target second element in the first low-bit matrix, and a second mapping relationship between the target second element and the corresponding first element is established.

[0084] After the mapping relationship is constructed, the first low-bit matrix and the first high-bit matrix can be subjected to logical operation processing based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix, so as to confuse the low-bit information and the high-bit information. It should be noted that the present embodiment does not limit the specific logical operation, which can be set according to actual application requirements, for example, the logical operation can be XOR operation.

[0085] Based on this, the first low-bit matrix and the first high-bit matrix are subjected to logical operation processing based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix, including:

[0086] S321, in the first low-bit matrix, each first element and a second element establishing a first mapping relationship with the first element are subjected to XOR operation to obtain a second low-bit matrix;

[0087] S322, in the first high-bit matrix, each second element and a first element establishing a second mapping relationship with the second element are subjected to XOR operation to obtain a second high-bit matrix.

[0088] For example, when the 10th position of the first high-bit matrix is 125, the data obtained after modulo 16 operation is 13, then the 10th position of the first high-bit matrix is subjected to XOR operation with the 13th position data of the first low-bit matrix, assuming that the 13th position data of the first low-bit matrix is 20, then the 10th byte of the high-bit information obtained from the first high-bit matrix is 105.

[0089] S400, generating the initial key of the current round by using the second low-bit matrix and the second high-bit matrix, and performing cyclic shift processing on the initial key of the current round to obtain an output key of the current round, so as to execute the round key addition processing of the current round by using the output key of the current round.

[0090] After the second low-bit matrix and the second high-bit matrix are generated, the low-bit information and the high-bit information after the confusion can be obtained by reassembling the elements in the positions of the two matrices in the original mapping manner; then, the initial key of the round can be obtained by assembling the low-bit information and the high-bit information after the confusion.

[0091] Further, the initial key of the round and the output key of the round are isolated by the cyclic shift processing in the embodiments of the present application, so that the recursive relationship between the output keys is ensured. It should be noted that the embodiments of the present application do not limit whether the cyclic shift is performed on the whole initial key of the round or on the part of the initial key of the round, which can be performed according to the actual application requirements. In order to improve the randomness between the initial key of the round and the output key of the round, the embodiments of the present application can only perform the cyclic shift on the part of the initial key of the round. Specifically, the initial key of the round can be equally divided into a low-bit key and a high-bit key according to the bit number, wherein the output key of the round is 256 bits, the low-bit key is 0-127 bits of the output key of the round, and the high-bit key is 128-255 bits of the output key of the round. Then, the first byte data and the second byte data in the low-bit key and the high-bit key can be determined according to the round corresponding to the round, and the first byte data and the second byte data are subjected to the modulo operation. Further, the first byte data and the second byte data are subjected to the cyclic shift processing in the low-bit key and the high-bit key according to the modulo operation result of the first byte data and the modulo operation result of the second byte data, to obtain a low-bit confusion key and a high-bit confusion key. Finally, the low-bit confusion key and the high-bit confusion key are subjected to the exclusive-OR operation, and the round corresponding to the round is inserted into the exclusive-OR operation result, to obtain the output key of the round.

[0092] Based on this, the cyclic shift processing on the initial key of the round to obtain the output key of the round can include:

[0093] S411, the initial key of the round is equally divided into a low-bit key and a high-bit key according to the bit number;

[0094] S412, the first byte data and the second byte data in the low-bit key and the high-bit key are determined according to the round corresponding to the round;

[0095] S413, the first byte data and the second byte data are subjected to the modulo operation respectively;

[0096] S414, the first byte data is subjected to the cyclic shift in the low-bit key according to the modulo operation result of the first byte data to obtain a low-bit confusion key, and the second byte data is subjected to the cyclic shift in the high-bit key according to the modulo operation result of the second byte data to obtain a high-bit confusion key;

[0097] S415, XOR operation is performed on the low-bit confusion key and the high-bit confusion key, and the round corresponding to the XOR operation result is inserted to obtain the output key of the round.

[0098] It should be noted that the embodiment of the present application does not limit the specific manner of performing the modulo operation on the first byte data and the second byte data and performing the cyclic shift on the low-bit key and the high-bit key according to the modulo operation result. For example, the modulo 16 operation can be performed on the first byte data and the second byte data, and the modulo operation result is used as the shift bit number of the cyclic shift, and the low-bit key and the high-bit key are cyclically shifted in the specified direction; for another example, the modulo 2 operation can be performed on the first byte data and the second byte data, and the shift direction is determined according to the modulo operation result, and then the low-bit key and the high-bit key are cyclically shifted according to the shift direction and the specified shift bit number. Of course, the above two manners can also be combined. The specific case of combining the above two manners will be introduced based on a specific example. After the first byte data and the second byte data are determined, the modulo 16 calculation MOD16 can be performed on them, and the data of MOD16 will be used as the Byte number of the cyclic shift; the result obtained by MOD16 is subjected to the modulo 2 calculation MOD2, and the data of MOD2 will be used as the direction of the cyclic shift, which is 1 for left shift and 0 for right shift. For example, the result after MOD16 is 13, and the result of MOD2 is 1, so the first byte data is cyclically shifted left by 13 bytes from the current Byte position.

[0099] Based on this, the modulo operation is performed on the first byte data and the second byte data, which can include:

[0100] S4131, the modulo 16 operation is performed on the first byte data and the second byte data respectively to obtain the first operation result and the second operation result;

[0101] S4132, the modulo 2 operation is performed on the first operation result and the second operation result respectively to obtain the third operation result and the fourth operation result;

[0102] Correspondingly, the cyclic shift of the first byte data in the low-bit key according to the modulo operation result of the first byte data to obtain the low-bit confusion key, and the cyclic shift of the second byte data in the high-bit key according to the modulo operation result of the second byte data to obtain the high-bit confusion key, include:

[0103] S4141, the shift bit number of the first byte data is determined according to the first operation result, the shift direction of the first byte data is determined according to the third operation result, and the first byte data is cyclically shifted in the low-bit key according to the shift direction of the shift bit number of the first byte data to obtain the low-bit confusion key;

[0104] S4142, determining the shift bit number of the second byte data according to the second operation result, determining the shift direction of the second byte data according to the fourth operation result, and performing cyclic shift on the second byte data in the high-bit key according to the shift direction of the shift bit number of the second byte data to obtain the high-bit confusion key.

[0105] It can be seen that the bytes to be processed by the cyclic shift in each round are not the same, and the parameters (shift bit number and direction) involved in the cyclic shift are also different, so the randomness and isolation between the initial key of the current round and the output key of the current round can be effectively enhanced.

[0106] Further, it can be understood that the initial key of the current round will also be used to generate the initial key of the next round. Of course, to further enhance the randomness between the initial key of the current round and the initial key of the next round, the initial key of the current round can also be further confused, and the initial key of the next round can be generated by using the initial key of the current round after the confusion.

[0107] Finally, in the embodiment, for the convenience of understanding, please refer to Figure 4 , Figure 4 is a schematic diagram of a key generation process provided by an embodiment of the application, wherein W0-W3 refer to keys. It can be seen that the initial key of the current round can be converted into the key of the current round by using the SHA256 hash algorithm, by performing modulo 16 calculation, mapping calculation, XOR calculation, and random number insertion, so that the effective isolation between the initial key of the current round and the key of the current round can be realized by using the SHA256 hash algorithm, modulo 16 calculation, mapping calculation, XOR calculation, and random number insertion.

[0108] Based on the above embodiment, when the previous round initial key is obtained, the present application can first generate the digest information corresponding to the key by using the digest algorithm, wherein the digest algorithm has good irreversibility, which can weaken the correlation between the previous round initial key and the current round key, and significantly increase the key exhaustion difficulty; then, the present application can equally divide the digest information into low-bit information and high-bit information according to the bit number, and map the low-bit information and the high-bit information to the first low-bit matrix and the first high-bit matrix respectively; further, the present application can determine the mapping relationship between the elements in the first low-bit matrix and the first high-bit matrix, and perform logical operation processing on the first low-bit matrix and the first high-bit matrix according to the mapping relationship, to obtain the second low-bit matrix and the second high-bit matrix, so as to further enhance the randomness between the current round key and the previous round initial key, and weaken the correlation between the current round key and the previous round initial key; finally, the present application can generate the current round initial key by using the second low-bit matrix and the second high-bit matrix, and perform cyclic shift processing on the current round initial key to obtain the current round output key, so as to use the current round output key to perform the round key addition processing of the current round, thereby isolating the current round output key and the current round initial key, and further weakening the correlation between the current round initial key and the current round output key, and the correlation between the previous round initial key and the current round output key, so as to solve the problem of too strong key correlation used in each round of round key addition in the existing advanced encryption standard algorithm, and achieve the result of one round one key.

[0109] Based on the above embodiment, the present application embodiment can further perform further confusion processing on the current round initial key, and generate the next round key by using the confused current round initial key. The specific process of the confusion processing will be introduced below. Based on this, after generating the current round initial key by using the second low-bit matrix and the second high-bit matrix, it can further include:

[0110] S500, performing logical operation processing on each element in the prime number table matrix and each byte sequence in the current round initial key, to confuse the current round initial key, and generate the next round initial key and the next round output key by using the confused current round initial key.

[0111] The present application embodiment will confuse the current round initial key by using the prime number table matrix. For ease of understanding, please refer to Figure 5 , Figure 5A schematic diagram of the prime number table matrix provided by the embodiment of the present application is shown in FIG. 1. In the diagram, the matrix marked with 1 is the marked prime number table matrix, and 16 prime numbers are arranged in the matrix in sequence. The embodiment of the present application can perform logical operation processing on each element in the prime number table matrix and each byte sequence in the initial round key, so as to confuse the initial round key. Of course, for the convenience of processing, the confusion of the initial round key can be performed before the initial round key is exported to the second low-bit matrix and the second high-bit matrix, that is, the second low-bit matrix and the second high-bit matrix are first subjected to logical operation with the prime number table matrix to obtain a third low-bit matrix and a third high-bit matrix, and then the third low-bit matrix and the third high-bit matrix are used to export the confused initial round key. It should be noted that the embodiment of the present application does not limit the specific type of logical operation, which can be set according to actual application requirements, for example, the logical operation can be XOR operation.

[0112] Further, to further reduce the correlation between the round keys, the prime number table matrix used to confuse the initial round key can be different. Specifically, the embodiment of the present application can transform the original prime number table matrix according to a preset rule and the round corresponding to the current round to obtain the prime number table matrix required for the current round, so as to ensure that the prime number table matrices used in adjacent two rounds are different.

[0113] Based on this, before performing logical operation processing on each element in the prime number table matrix and each byte sequence in the initial round key, the following can be included:

[0114] S511, obtaining an original prime number table matrix;

[0115] S512, transforming the original prime number table matrix according to a preset rule and the round corresponding to the current round to obtain a prime number table matrix.

[0116] It should be noted that the embodiment of the present application does not limit the specific preset rule, which can be set according to actual application requirements, for example, the elements can be circularly shifted, or the positions of the elements can be moved. Figure 5 The matrix marked with 2 in FIG. 2 is a new prime number table matrix obtained by transforming the original prime number table matrix marked with 1 in FIG. 1 for two rounds.

[0117] Further, please refer to Figure 6 , Figure 6 A schematic diagram of another key generation process provided by the embodiment of the present application is shown in FIG. 3. After adding the prime number table matrix XOR step, the initial round key generated by the matrix mapping step will be input to two steps, one of which will be input to the prime number table matrix XOR step for confusion to generate the next round key, and the other of which will be input to the round positioning step to generate the output key of the current round.

[0118] Based on the above embodiment, to further reduce the correlation between the upper round initial key and the current round key, the embodiment of the present application can also increase more random information in the upper round initial key to improve the isolation degree between the upper round initial key and the current round key. Based on this, the generation of the digest information corresponding to the upper round initial key by using the digest algorithm can include:

[0119] S121, segmenting the upper round initial key, and performing modulo operation on each segment of the upper round initial key to obtain a modulo operation result corresponding to the upper round initial key.

[0120] It should be noted that the embodiment of the present application does not limit the specific way of segmenting the upper round initial key, for example, the upper round initial key can be segmented by byte, that is, the length of each segment in the upper round initial key is one byte.

[0121] S122, filling the upper round initial key to a preset length by using the round corresponding to the current round and the modulo operation result to obtain an input value of the digest algorithm.

[0122] Please refer to Figure 7 , Figure 7 for the schematic diagram of the input value of the digest algorithm provided by the embodiment of the present application. The embodiment of the present application can fill the upper round initial key by using the round, the modulo operation result obtained by segmenting the upper round initial key and the data total length, so as to increase random information in the key, thereby enhancing the isolation degree between the upper round initial key and the current round key. Of course, to meet the requirement of SHA256 on the length of the input value, the embodiment of the present application can also fill a sufficient amount of 0 and 1 in the upper round initial key to fill its length to 512 bits required by SHA256.

[0123] S123, generating the digest information corresponding to the input value by using the digest algorithm.

[0124] After obtaining the input value, the embodiment of the present application can process it by using the digest algorithm to obtain the corresponding digest information. For the SHA256 algorithm, it will perform grouping expansion and compression processing on the input value, which will be briefly introduced below.

[0125] Grouping expansion: first, divide the data after message padding into 16 32-bit data, and then expand the 16 data to generate 32-bit data from 17 to 64 by using a permutation function; the formula of the permutation function is:

[0126] ;

[0127] Among them

[0128] ;

[0129] ;

[0130] X represents 32bit data, represents X cyclic right shift K bit, represents X right shift K bit, left low bit is filled with 0, represents XOR calculation, and the data range of j is 17 to 64.

[0131] Compression function: the data after the block expansion needs to be iterated for 64 rounds to obtain the final digest value; the iteration formula is:

[0132] ;

[0133] ;

[0134] ;

[0135] ;

[0136] ;

[0137] ;

[0138] ;

[0139] ;

[0140] ;

[0141] ;

[0142] The logical function used in the iteration formula is:

[0143] ;

[0144] ;

[0145] ;

[0146] .

[0147] The key generation device, electronic equipment and computer readable storage medium provided by the embodiments of the application will be introduced below, and the key generation device, electronic equipment and computer readable storage medium described below can be mutually corresponding with the key generation method described above.

[0148] Please refer to Figure 8 , Figure 8 is a structural block diagram of a key generation device provided by the embodiments of the application, and the device can include:

[0149] The abstract calculation module 801 is configured to obtain the previous round initial key and generate corresponding abstract information of the previous round initial key by using an abstract algorithm.

[0150] The matrix conversion module 802 is configured to equally divide the abstract information into low-bit information and high-bit information according to the bit number, and map the low-bit information and the high-bit information to a first low-bit matrix and a first high-bit matrix respectively.

[0151] The matrix mapping module 803 is configured to determine a mapping relationship between each first element in the first low-bit matrix and each second element in the first high-bit matrix, and perform logical operation processing on the first low-bit matrix and the first high-bit matrix based on the mapping relationship to obtain a second low-bit matrix and a second high-bit matrix.

[0152] The output key generation module 804 is configured to generate the current round initial key by using the second low-bit matrix and the second high-bit matrix, and perform cyclic shift processing on the current round initial key to obtain a current round output key, so as to perform the round key addition processing of the current round by using the current round output key.

[0153] Optionally, the device can further include:

[0154] The prime number table matrix processing module is configured to perform logical operation processing on each element in the prime number table matrix and each byte sequence in the current round initial key, so as to confuse the current round initial key, and generate a next round initial key and a next round output key by using the confused current round initial key.

[0155] Optionally, the prime number table matrix processing module can further include:

[0156] The original prime number table matrix acquisition submodule is configured to acquire an original prime number table matrix.

[0157] The original prime number table matrix transformation submodule is configured to transform the original prime number table matrix according to a preset rule and a round corresponding to the current round to obtain the prime number table matrix.

[0158] Optionally, the output key generation module 804 can include:

[0159] The division submodule is configured to equally divide the current round initial key into low-bit keys and high-bit keys according to the bit number.

[0160] The byte positioning submodule is configured to determine first byte data and second byte data in the low-bit keys and the high-bit keys respectively according to a round corresponding to the current round.

[0161] The modulo operation submodule is configured to perform modulo operation on the first byte data and the second byte data respectively.

[0162] a cyclic shift sub-module, configured to cyclically shift the first byte data in the low-bit key according to a modulo operation result of the first byte data to obtain a low-bit confusion key, and cyclically shift the second byte data in the high-bit key according to a modulo operation result of the second byte data to obtain a high-bit confusion key;

[0163] an exclusive OR sub-module, configured to perform exclusive OR operation on the low-bit confusion key and the high-bit confusion key, and insert a round corresponding to the current round in an exclusive OR operation result to obtain an output key of the current round.

[0164] Optionally, the modulo operation sub-module can comprise:

[0165] a modulo 16 operation unit, configured to perform modulo 16 operation on the first byte data and the second byte data respectively to obtain a first operation result and a second operation result;

[0166] a modulo 2 operation unit, configured to perform modulo 2 operation on the first operation result and the second operation result respectively to obtain a third operation result and a fourth operation result;

[0167] Correspondingly, the cyclic shift sub-module comprises:

[0168] a first cyclic shift unit, configured to determine a shift bit number of the first byte data according to the first operation result, determine a shift direction of the first byte data according to the third operation result, and cyclically shift the first byte data in the low-bit key according to the shift direction of the shift bit number of the first byte data to obtain the low-bit confusion key;

[0169] a second cyclic shift unit, configured to determine a shift bit number of the second byte data according to the second operation result, determine a shift direction of the second byte data according to the fourth operation result, and cyclically shift the second byte data in the high-bit key according to the shift direction of the shift bit number of the second byte data to obtain the high-bit confusion key.

[0170] Optionally, the digest calculation module 801 can comprise:

[0171] a segmented modulo operation sub-module, configured to perform segmented processing on the initial key of the previous round, and perform modulo operation on each segment of the initial key of the previous round to obtain a modulo operation result corresponding to the initial key of the previous round;

[0172] a padding sub-module, configured to pad the initial key of the previous round to a preset length by using the round corresponding to the current round and the modulo operation result to obtain an input value of the digest algorithm;

[0173] a digest calculation sub-module, configured to generate digest information corresponding to the input value by using the digest algorithm.

[0174] Optionally, the initial key of the previous round is the initial key of the first round, and the digest calculation module 801 can comprise:

[0175] The random number key generation submodule is configured to generate a random number key by using a linear feedback shift register with the current time as a random seed, and set the random number key as the initial key of the first round.

[0176] Optionally, the digest calculation module 801 can further include:

[0177] The random number key saving submodule is configured to save the random number key into an internal memory.

[0178] Optionally, the matrix mapping module 803 can include:

[0179] The first mapping submodule is configured to mark each first element as a target first element in sequence, perform a modulo operation on the target first element, find a second element corresponding to the target first element in the first high-bit matrix by taking the modulo operation result as a position value, and establish a first mapping relationship between the target first element and the corresponding second element.

[0180] The second mapping submodule is configured to mark each second element as a target second element in sequence, perform a modulo operation on the target second element, find a first element corresponding to the target second element in the first low-bit matrix by taking the modulo operation result as a position value, and establish a second mapping relationship between the target second element and the corresponding first element.

[0181] Optionally, the matrix mapping module 803 can include:

[0182] The first XOR operation submodule is configured to perform an XOR operation on each first element and a second element that has established a first mapping relationship with the first element in the first low-bit matrix, to obtain a second low-bit matrix.

[0183] The second XOR operation submodule is configured to perform an XOR operation on each second element and a first element that has established a second mapping relationship with the second element in the first high-bit matrix, to obtain a second high-bit matrix.

[0184] Please refer to Figure 9 , Figure 9 A structural block diagram of an electronic device provided by an embodiment of the present application is provided, and the embodiment of the present application provides an electronic device 90, which includes a processor 91 and a memory 92; wherein the memory 92 is configured to save a computer program; and the processor 91 is configured to execute the key generation method provided by the foregoing embodiments when executing the computer program.

[0185] The specific process of the key generation method can refer to the corresponding content provided in the foregoing embodiments, and will not be described here in detail.

[0186] And, the memory 92 as a carrier of resource storage can be a read-only memory, a random memory, a magnetic disk or an optical disk, etc., and the storage mode can be temporary storage or permanent storage.

[0187] In addition, the electronic device 90 further includes a power supply 93, a communication interface 94, an input / output interface 95 and a communication bus 96; wherein the power supply 93 is used to provide working voltage for each hardware device on the electronic device 90; the communication interface 94 can create a data transmission channel between the electronic device 90 and external devices, and the communication protocol followed by the communication interface 94 is any communication protocol applicable to the technical solution of the present application, which is not limited here.

[0188] The embodiment of the present application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to realize the steps of the key generation method of any embodiment.

[0189] Since the embodiments of the computer readable storage medium part correspond to the embodiments of the key generation method part, the embodiments of the storage medium part are described with reference to the description of the embodiments of the key generation method part, and will not be described here.

[0190] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts of each embodiment can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the related parts are described in the method part.

[0191] The skilled person can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly show the interchangeability of hardware and software, the components and steps of each example have been described in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0192] The steps of a method or algorithm described in connection with the embodiments disclosed herein can be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0193] The key generation method, device, electronic equipment and computer readable storage medium provided by the present application are introduced in detail above. The principles and implementation modes of the present application are described by applying specific examples in this paper. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary skilled persons in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A key generation method, characterized in that, include: Obtain the initial key from the previous round, and use a digest algorithm to generate a digest of the initial key from the previous round. The summary information is divided into low-order information and high-order information according to the number of bits, and the low-order information and high-order information are mapped to the first low-order matrix and the first high-order matrix respectively; Determine the mapping relationship between each first element in the first low-order matrix and each second element in the first high-order matrix, and perform logical operations on the first low-order matrix and the first high-order matrix based on the mapping relationship to obtain the second low-order matrix and the second high-order matrix; The initial key for this round is generated using the second low-order matrix and the second high-order matrix, and the initial key for this round is cyclically shifted to obtain the output key for this round, so as to perform the round key addition process for this round using the output key for this round; Determining the mapping relationship between each first element in the first low-order matrix and each second element in the first high-order matrix includes: Each of the first elements is sequentially marked as the target first element. A modulo operation is performed on the target first element. The result of the modulo operation is used as the position value to find the second element corresponding to the target first element in the first high-order matrix, and a first mapping relationship is established between the target first element and the corresponding second element. Each of the second elements is sequentially marked as the target second element. A modulo operation is performed on the target second element. The result of the modulo operation is used as the position value to find the first element corresponding to the target second element in the first low-order matrix, and a second mapping relationship between the target second element and the corresponding first element is established. The step of performing logical operations on the first low-order matrix and the first high-order matrix based on the mapping relationship to obtain the second low-order matrix and the second high-order matrix includes: In the first low-order matrix, each of the first elements and the second element with which the first mapping relationship is established are XORed to obtain the second low-order matrix; In the first high-order matrix, each of the second elements and the first element with which the second mapping relationship is established are XORed to obtain the second high-order matrix.

2. The key generation method according to claim 1, characterized in that, After generating the initial key for this round using the second low-order matrix and the second high-order matrix, the following steps are also included: Logical operations are performed between the elements of the prime number table matrix and the bytes of the current round's initial key to confuse the current round's initial key. The confused current round's initial key is then used to generate the next round's initial key and the next round's output key.

3. The key generation method according to claim 2, characterized in that, Before performing logical operations on the elements of the prime number table matrix and the bytes of the initial key for this round, the process includes: Obtain the original prime number table matrix; The original prime number table matrix is ​​transformed according to preset rules and the corresponding round to obtain the prime number table matrix.

4. The key generation method according to claim 1, characterized in that, The step of performing a cyclic shift process on the initial key of this round to obtain the output key of this round includes: The initial key for this round is divided into a low-order key and a high-order key according to the number of bits. The first byte and the second byte of data in the low-key and the high-key are determined according to the round corresponding to this round. Perform modulo operations on the first byte of data and the second byte of data respectively; Based on the modulo operation result of the first byte data, the first byte data is cyclically shifted in the low-order key to obtain the low-order obfuscation key; and based on the modulo operation result of the second byte data, the second byte data is cyclically shifted in the high-order key to obtain the high-order obfuscation key. Perform an XOR operation on the low-order obfuscation key and the high-order obfuscation key, and insert the round number corresponding to this round into the XOR operation result to obtain the output key of this round.

5. The key generation method according to claim 4, characterized in that, The modulo operation on the first byte of data and the second byte of data respectively includes: Perform modulo-16 operations on the first byte of data and the second byte of data respectively to obtain the first operation result and the second operation result; Perform modulo-2 operations on the first and second operation results respectively to obtain the third and fourth operation results; Accordingly, the step of cyclically shifting the first byte of data in the low-order key according to the modulo operation result of the first byte of data to obtain the low-order obfuscation key, and cyclically shifting the second byte of data in the high-order key according to the modulo operation result of the second byte of data to obtain the high-order obfuscation key, includes: The shift number of the first byte data is determined based on the first operation result, the shift direction of the first byte data is determined based on the third operation result, and the first byte data is cyclically shifted in the low-order key according to the shift direction of the shift number of the first byte data to obtain the low-order obfuscation key; The shift number of the second byte data is determined based on the second operation result, the shift direction of the second byte data is determined based on the fourth operation result, and the second byte data is cyclically shifted in the high-order key according to the shift direction of the shift number of the second byte data to obtain the high-order obfuscation key.

6. The key generation method according to claim 1, characterized in that, The step of generating the digest information corresponding to the initial key of the previous round using a digest algorithm includes: The initial key of the previous round is segmented, and a modulo operation is performed on each segment of the initial key of the previous round to obtain the modulo operation result corresponding to the initial key of the previous round. Using the round number corresponding to this round and the result of the modulo operation, the initial key of the previous round is filled to a preset length to obtain the input value of the digest algorithm; The digest algorithm is used to generate a digest of the input value.

7. The key generation method according to claim 1, characterized in that, The initial key for the previous round is the initial key for the first round. Obtaining the initial key for the previous round includes: A random number key is generated using a linear feedback shift register with the current time as the random seed, and the random number key is set as the initial key for the first round.

8. The key generation method according to claim 7, characterized in that, After generating a random number key using a linear feedback shift register with the current time as the random seed, the process also includes: The random number key is saved to the internal memory.

9. A key generation device, characterized in that, include: The digest calculation module is used to obtain the initial key of the previous round and generate digest information corresponding to the initial key of the previous round using a digest algorithm; The matrix transformation module is used to divide the summary information into low-order information and high-order information according to the number of bits, and to map the low-order information and high-order information to a first low-order matrix and a first high-order matrix, respectively; The matrix mapping module is used to determine the mapping relationship between each first element in the first low-order matrix and each second element in the first high-order matrix, and to perform logical operations on the first low-order matrix and the first high-order matrix based on the mapping relationship to obtain the second low-order matrix and the second high-order matrix. The output key generation module is used to generate the initial key for this round using the second low-order matrix and the second high-order matrix, and to perform a cyclic shift process on the initial key for this round to obtain the output key for this round, so as to perform the round key addition process for this round using the output key for this round; The matrix mapping module includes: The first mapping submodule is used to sequentially mark each of the first elements as the target first element, perform a modulo operation on the target first element, use the modulo operation result as the position value to find the second element corresponding to the target first element in the first high-order matrix, and establish a first mapping relationship between the target first element and the corresponding second element. The second mapping submodule is used to sequentially mark each of the second elements as the target second element, perform a modulo operation on the target second element, use the modulo operation result as the position value to find the first element corresponding to the target second element in the first low-order matrix, and establish a second mapping relationship between the target second element and the corresponding first element. The first XOR operation submodule is used to perform an XOR operation on each of the first elements and the second elements with which the first mapping relationship is established in the first low-order matrix to obtain the second low-order matrix. The second XOR operation submodule is used to perform an XOR operation on each of the second elements and the first element with which the second mapping relationship is established in the first high-bit matrix to obtain the second high-bit matrix.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the key generation method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the key generation method as described in any one of claims 1 to 8.

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