System for loading FPGA based on LPC interface

Abstract

The present invention discloses a system for loading FPGAs based on an LPC interface. The system is installed on a processor board with an LPC interface. The system configures the FPGA in SelectMAP mode. The system includes an FT2000 hardware system, BRAM, interface logic LPC_BRAM, and a Microblaze embedded system. The FT2000 hardware system obtains a V7 FPGA configuration data source file from the network and transmits it to the interface logic LPC_BRAM via LPC. The interface logic LPC_BRAM reads the data and writes it to the BRAM cache. The Microblaze embedded system reads the data from the BRAM cache and writes it to an external FLASH memory. Advantageously, the present invention constructs a complete embedded system with a cache, an LPC interface, a SelectMAP interface, and a Flash interface within a single chip, effectively saving board area, reducing hardware costs, and lowering the difficulty of board design, thereby achieving miniaturization, high integration, and high reliability of the embedded system.

Description

Technical Field

[0001] The present invention relates to the technical field of digital hardware and FPGA design, in particular to a system for loading FPGA based on an LPC interface. Background Art

[0002] For digital boards with large-capacity FPGAs, it is often necessary to implement remote version updates and multi-version configuration functions for the FPGA chip. Generally, the processor on the board is used to program the FPGA configuration FLASH and load the FPGA. Programming FLASH and loading FPGA applications usually require a parallel interface. However, with the development of processors and the streamlining of external interfaces, current high-end processors, in addition to high-speed interfaces such as PCIE and DDR, only have the LPC interface to connect to external I / O devices, and no other parallel interfaces can be used. Therefore, using LPC to implement FPGA loading and programming has become an essential application technology for high-speed digital boards.

[0003] LPC (Low Pin Count) is a 33 MHz 4-bit parallel bus protocol based on Intel standards. It replaced the previous ISA bus protocol, but both offer similar performance. Both are used to connect the southbridge and devices such as the Super I / O chip, Flash BIOS, and EC. LPC operates at a 33 MHz clock rate and has a maximum transfer rate of 16 MB / s, but it significantly reduces the number of signal pins by 25 to 30. Super I / O chips and Flash chips designed with LPC interfaces benefit from a reduced pin count and smaller size, simplifying motherboard design. This is why it's called LPC (Low Pin Count). Summary of the Invention

[0004] This invention proposes a system for loading FPGAs based on the LPC interface. The prototype is based on an embedded board with an FT2000 core and a large-capacity V7 series FPGA chip. Multiple versions of the V7 need to be loaded. After power-up, the onboard controller (OBC) reads the program from the external parallel port flash memory and loads the V7 FPGA using the SelectMAP method. The FT2000 obtains the V7 firmware through the network port and then sends it to the OBC via the LPC bus. The OBC then writes the program to the parallel port flash memory, thus implementing remote updates of the V7 FPGA. The technical solution adopted is as follows:

[0005] A system for loading an FPGA based on an LPC interface is provided on a processor board with an LPC interface. The system configures the FPGA in SelectMAP mode and includes an FT2000 hardware system, BRAM, interface logic LPC_BRAM, and a Microblaze embedded system. The FT2000 hardware system obtains a V7 FPGA configuration data source file from the network and transmits it to the interface logic LPC_BRAM via LPC. The interface logic LPC_BRAM reads the data and writes it into the BRAM cache. The Microblaze embedded system reads the data from the BRAM cache and writes it into an external FLASH.

[0006] The technical solution of this invention implements a system design for programming and loading large-capacity FPGA configuration FLASH on a processor board with an LPC interface. The processor board with the LPC interface includes an A7 FPGA chip that implements the on-board control (OBC) function and a FLASH chip for storing the V7 series high-end FPGA configuration program. The A7 FPGA chip implements the LPC interface-based data channel, the FLASH programming interface, and the parallel loading interface logic for the high-end FPGA. Low-end FPGA chips can be used for the A7 FPGA, reducing system implementation costs.

[0007] The technical solution of the present invention is implemented on the A7 FPGA chip, and its functions include realizing a transmission channel for programming data based on the LPC interface, a configuration interface for the large-capacity FPGA on the board based on the SelectMAP mode parallel interface, a programming logic interface for the parallel FLASH chip, and a cache RAM for programming data.

[0008] In a further optimization of the technical solution of the present invention, the interface logic LPC_BRAM includes three subroutines: LPC to FIFO interface, FIFO and data conversion interface. The LPC to FIFO interface subroutine obtains the data sent by the LPC bus and writes it into the FIFO subroutine. The data conversion interface subroutine reads the data from the FIFO subroutine and writes it into BRAM in sequence.

[0009] In a further embodiment of the technical solution of the present invention, the Microblaze embedded soft core of the Microblaze embedded system has an LPC interface.

[0010] In a further preferred embodiment of the technical solution of the present invention, the BRAM is 128KB BRAM.

[0011] In a further preferred embodiment of the technical solution of the present invention, the processor board with the LPC interface is an embedded board with FT2000 as the core. The embedded board with FT2000 as the core includes an A7 FPGA chip for realizing on-board control functions and a FLASH chip for storing a V7 series high-end FPGA configuration program.

[0012] In a further preferred embodiment of the technical solution of the present invention, the data sent by the FT2000 hardware system to the interface logic LPC_BRAM are all transmitted via the LPC bus; the FT2000 hardware system obtains the data and status of the interface logic LPC_BRAM via several GPIOs.

[0013] In a further preferred embodiment of the present invention, programming data from the interface logic LPC_BRAM is written to the BRAM and read by the Microblaze embedded soft core. The interface logic LPC_BRAM sector data is transmitted to the Microblaze embedded soft core via GPIO_in. After writing a sector, the Microblaze embedded soft core is notified via an int interrupt. After the Microblaze embedded soft core completes programming of the sector, it notifies the interface logic LPC_BRAM via GPIO_out. The interface logic LPC_BRAM then transmits data to the FT2000 hardware system via GPIO. This sector-by-sector transmission and programming approach eliminates the need for large-capacity DDR buffer circuits, achieving a low-cost, highly reliable, and highly integrated solution.

[0014] The beneficial effects of the present invention compared with the prior art are:

[0015] 1. The system of the present invention builds a complete embedded system with cache, LPC interface, SelectMAP interface and Flash interface inside a chip, which effectively saves the board area, reduces hardware cost and eases the difficulty of board design, thus realizing the miniaturization, high integration and high reliability of the embedded system.

[0016] 2. The system of the present invention constructs a programmable embedded system with the microblaze soft core as the core processor, eliminating the need for external program FLASH, DDR and other peripheral hardware, enhancing application flexibility, reducing maintenance costs, and improving reliability.

[0017] 3. The system of the present invention is simpler, more reliable, and has lower implementation costs among system solutions that meet such requirements. FPGA chips can load large amounts of data, up to 10MB or more. Implementing this system typically requires a large-capacity DDR cache and a dedicated embedded system. This solution integrates this embedded system within the board's OBC A7 FPGA chip, eliminating the need for external memory and related interface circuit hardware design. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the system architecture of Example 1.

[0019] Figure 2 Implement data transfer system structure diagram for LPC_BRAM.

[0020] Figure 3 for Figure 2 The internal structure diagram of the LPC_BRAM submodule in .

[0021] Figure 4 Schematic diagram of the program flow for transferring V7 configuration data to FT2000.

[0022] Figure 5 This is a system structure diagram of the system of this embodiment implementing configuration data loading on the V7 FPGA after each power-on. DETAILED DESCRIPTION

[0023] The technical solution of the present invention is described in detail below, but the protection scope of the present invention is not limited to the embodiments.

[0024] In order to make the content of the present invention more clear and easy to understand, the following Figure 1-Figure 5 The specific implementation methods are further described.

[0025] The present invention proposes a system for loading FPGAs based on the LPC interface. This system enables a processor with an LPC interface to program and solidify the configuration FLASH of a large-capacity FPGA through the LPC and load the FPGA. The system prototype includes an FT2000 embedded system, an A7 FPGA chip, a FLASH chip, and a V7 FPGA chip. The main functions are implemented within the A7 chip, constructing a complete embedded system with cache, LPC interface, SelectMAP interface, and Flash interface. This effectively saves board area, reduces hardware costs, and eases board design difficulty, achieving miniaturization, high integration, and high reliability of the embedded system. The system's logic includes a transmission channel for programming data based on the LPC interface, a configuration interface for the on-board V7 FPGA based on the SelectMAP parallel interface, a programming logic interface for the parallel FLASH chip, and a RAM cache for programming data. The system's software includes data reception and reading from the LPC, a programming algorithm for the FLASH, and a loader for the high-end FPGA.

[0026] Example 1

[0027] like Figure 1As shown in the figure, this embodiment is a system for loading FPGAs based on the LPC interface. This system consists of four main components: the FT2000 hardware system, a 128KB BRAM, the interface logic LPC_BRAM, and the Microblaze embedded system. The FT2000 hardware system obtains the V7 FPGA configuration data source file from the network and transmits it to the interface logic LPC_BRAM via LPC. The data is then written into a 16-word FIFO in 42-bit word length format (including data and address). The LPC_BRAM reads the data from the FIFO and writes it sequentially into the 128KB Block RAM cache. The Microblaze embedded system reads the data from the cache, programs it into the external FLASH, and then notifies the FT2000 to continue transferring the next 128KB sector of data until the entire configuration data transfer and programming are complete.

[0028] like Figure 2 As shown in the figure, LPC_BRAM implements the data transmission system. The system builds an embedded system with the soft-core processor microblaze as the core. LPC_BRAM is the logical submodule that implements the LPC interface. Its function is to write the program data stream sent by the LPC bus for loading V7 into the BRAM with a capacity of 128KB so that it can be read by the microblaze system and programmed into the FLASH.

[0029] like Figure 3 As shown in the figure, the submodule of the interface logic LPC_BRAM is mainly completed by three subroutines: LPC to FIFO interface, FIFO and data conversion interface. The LPC to FIFO interface obtains the data sent by the LPC bus and writes it into the 16-word FIFO in 42-bit word length format (including data and address). The data conversion interface subroutine reads the data from the FIFO and writes it into the 128KB Block RAM at a time.

[0030] The procedure flow of FT2000 transmitting V7 configuration data is as follows Figure 4 As shown: The whole process is divided into two steps: writing data from FT2000 to dual-port RAM and reading data from Microblaze to program FLASH.

[0031] In order to achieve a complete and accurate data transfer process from FT2000 to 128KB BRAM and read by microblaze, sufficient handshake signals are required between FT2000, LPC_BRAM and microblaze. The system is interconnected as follows: Figure 1As shown in the figure, data sent from the FT2000 to the LPC_BRAM passes through the LPC bus. The FT2000 does not read data or status via the LPC bus, but instead obtains LPC_BRAM status via several GPIOs. LPC_BRAM programming data is written to the 128KB BRAM and read by the microblaze. The sector number is transmitted to the microblaze via GPIO_in. After a sector is written, the microblaze is notified via an int interrupt. When the microblaze completes programming of the sector, it notifies the LPC_BRAM via GPIO_out. The LPC_BRAM then transmits the programming completion signal (prg_cmp) to the FT2000 via GPIO, allowing it to proceed with the next data transfer.

[0032] like Figure 4 As shown, Lpc_rdy: ready signal is connected to the FT gpio and serves as a handshake signal with the FT processor.

[0033] 0 means that the OBC's LPC bus is busy and will not respond to bus commands; 1 means ready and FT can start LPC bus operations.

[0034] Prg_cmp: programming completion signal, connected to 2 gpio of FT;

[0035] 00 means the OBC flash is in blank state and has not been programmed;

[0036] 11 means that one sector programming has been completed and the next programming can be continued;

[0037] 01 means that OBC is currently programming the flash memory and will not respond to programming requests.

[0038] The process steps of LPC_BRAM are as follows:

[0039] 1. If the FIFO is not empty, it starts to read the data sent by the memory write operation of the LPC bus;

[0040] 2. After determining the start flag, the first data read is the sector number, which is written to GPIO_in for Microblaze to read;

[0041] 3. Next, the data is read and written into the dual-port RAM in sequence until the end mark is reached, and the length is determined to be 128K.

[0042] 4. Notify Microblaze to take readings via an interrupt.

[0043] 5. Microblaze reads data from the dual-port RAM and then programs the sector. If successful, it uses GPIO_OUT to send a message indicating that the programming is complete.

[0044] 6. After LPC_BRAM receives the GPIO_out completion information, it sets prg_cmp to notify FT2000 that the sector programming is completed.

[0045] like Figure 5 As shown in the figure, when configuration data is programmed into the Flash, multiple versions can be written separately by address. Each time the module is powered on, the Microblaze system reads the configuration data to be loaded from the Flash according to the command given by the FT2000 system. It then implements SelectMAP parallel loading on the V7 FPGA through the FIFO and logic interface. After successful loading, it sends a Done signal back to the FT2000 system, indicating successful loading.

[0046] The above embodiments are only for illustrating the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. A system for loading FPGA based on LPC interface, characterized by: The system is set on a processor board with an LPC interface. The system configures the FPGA in SelectMAP mode. The system includes an FT2000 hardware system, BRAM, interface logic LPC_BRAM and a Microblaze embedded system. The FT2000 hardware system obtains the configuration data source file of the V7 FPGA from the network and transmits it to the interface logic LPC_BRAM through LPC. The interface logic LPC_BRAM reads the data and writes it into the BRAM cache. The Microblaze embedded system reads the data from the BRAM cache and writes it into the external FLASH.

2. The system for loading FPGA based on LPC interface according to claim 1, characterized in that: The interface logic LPC_BRAM includes three subroutines: LPC to FIFO interface, FIFO and data conversion interface. The LPC to FIFO interface subroutine obtains the data sent by the LPC bus and writes it into the FIFO subroutine. The data conversion interface subroutine reads the data from the FIFO subroutine and writes it into BRAM in sequence.

3. The system for loading FPGA based on LPC interface according to claim 1, characterized in that: The Microblaze embedded soft core of the Microblaze embedded system has an LPC interface.

4. The system for loading FPGA based on LPC interface according to claim 1, characterized in that: The BRAM is 128KB BRAM.

5. The system for loading FPGA based on LPC interface according to claim 1, characterized in that: The processor board with LPC interface is an embedded board with FT2000 as the core. The embedded board with FT2000 as the core includes an A7 FPGA chip for realizing on-board control functions and a FLASH chip for storing V7 series high-end FPGA configuration program.

6. The system for loading FPGA based on LPC interface according to claim 1, characterized in that: The data sent by the FT2000 hardware system to the interface logic LPC_BRAM is transmitted through the LPC bus; the FT2000 hardware system obtains the data and status of the interface logic LPC_BRAM through several GPIOs.

7. The system for loading FPGA based on LPC interface according to claim 6, characterized in that: The programming data of the interface logic LPC_BRAM is written to the BRAM and read by the Microblaze embedded soft core. The interface logic LPC_BRAM sector data is transmitted to the Microblaze embedded soft core through GPIO_in. After writing a sector, the Microblaze embedded soft core is notified through the int interrupt. After the Microblaze embedded soft core completes the programming of the sector, it notifies the interface logic LPC_BRAM through GPIO_out. The interface logic LPC_BRAM is then passed to the FT2000 hardware system through GPIO.

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