A reset device, its driving method, and a display device

Abstract

An embodiment of the present disclosure provides a reset device, a driving method thereof, and a display device. The reset device includes a shift register, a voltage detection module, and a forced reset module. The shift register includes a pull-up module, an output module, and a first reset module. The pull-up module is configured to provide a signal of a first power supply terminal to a pull-up node under the control of an input signal terminal. The output module is configured to provide a signal of a clock signal terminal to an output signal terminal under the control of the pull-up node. The first reset module is configured to provide a signal of a third power supply terminal to the pull-up node under the control of a reset signal terminal. The voltage detection module is configured to output a first voltage signal at an output terminal when a voltage signal of the pull-up node is abnormal, and the first voltage signal is greater than a threshold voltage. The forced reset module is configured to provide a reset signal to the pull-up node when receiving the first voltage signal, so as to reset the pull-up node. The technical solution of the present disclosure can automatically reset when the pull-up node is abnormal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a reset device, a driving method thereof, and a display device. Background Art

[0002] With the development trend of high integration of display panels, the GOA (Gate Driver On Array) technology has emerged. The GOA technology directly integrates the gate driving circuit of the display panel on the array substrate to replace the external driving chip, which has the advantages of low cost, few processes, and high production capacity. The gate driving circuit integrated on the array substrate using the GOA technology is also called a GOA circuit.

[0003] In related technologies, when a display product runs continuously for a long time, abnormal display images may occur. Summary of the Invention

[0004] Embodiments of the present disclosure provide a reset device, a driving method thereof, and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a reset device, including a shift register, a voltage detection module, and a forced reset module. The shift register includes a pull-up module, an output module, and a first reset module. The pull-up module is respectively coupled to an input signal terminal, a first power supply terminal, and a pull-up node, and is configured to provide a signal of the first power supply terminal to the pull-up node under the control of the input signal terminal. The output module is respectively coupled to a clock signal terminal, the pull-up node, and an output signal terminal, and is configured to provide a signal of the clock signal terminal to the output signal terminal under the control of the pull-up node. The first reset module is respectively coupled to a reset signal terminal, a third power supply terminal, and the pull-up node, and is configured to provide a signal of the third power supply terminal to the pull-up node under the control of the reset signal terminal. The voltage detection module includes an input end and an output end. The input end is coupled to the pull-up node and is configured to output a first voltage signal at the output end when the voltage signal of the pull-up node is abnormal. The first voltage signal is greater than a threshold voltage. The forced reset module is coupled to the output end and is configured to provide a reset signal to the pull-up node when receiving the first voltage signal, so that the pull-up node is reset.

[0006] In some possible implementation manners, the voltage detection module includes a diode, a first capacitor, and a first resistor. The positive electrode of the diode is coupled to the input end. The first capacitor and the first resistor are connected in parallel, and both ends of the first capacitor and the first resistor are respectively coupled to the negative electrode of the diode and a fourth power supply terminal. The negative electrode of the diode is coupled to the output end.

[0007] In some possible implementations, the forced reset module includes a control module and a second reset module. The control module is configured to send a trigger signal to the second reset module when receiving a first voltage signal from the voltage detection module. The second reset module is configured to provide a reset signal to the pull-up node when receiving the trigger signal, so as to reset the pull-up node.

[0008] In some possible implementations, the second reset module includes a reset transistor. The gate of the reset transistor is coupled to the control module, and the first and second poles of the reset transistor are respectively coupled to the second power supply terminal and the pull-up node.

[0009] In some possible implementations, the control module includes a timing controller.

[0010] In some possible implementations, it includes at least one of the following:

[0011] The pull-up module includes a first transistor. The gate of the first transistor is coupled to the input signal terminal, and the first and second poles of the first transistor are respectively coupled to the first power supply terminal and the pull-up node.

[0012] The output module includes a third transistor and a storage capacitor. The gate of the third transistor is coupled to the pull-up node, and the first and second poles of the third transistor are respectively coupled to the clock signal terminal and the output signal terminal. The first and second plates of the storage capacitor are respectively coupled to the pull-up node and the output signal terminal.

[0013] The first reset module includes a second transistor. The gate of the second transistor is coupled to the reset signal terminal, and the first and second poles of the second transistor are respectively coupled to the third power supply terminal and the pull-up node.

[0014] In some possible implementations, the shift register further includes:

[0015] A pull-down module, which is respectively coupled to the second power supply terminal, the pull-up node and the control node, and is configured to provide the signal of the second power supply terminal to the pull-down node and the control node under the control of the pull-up node.

[0016] A noise suppression module, which is respectively coupled to the first control power supply terminal, the control node and the pull-down node, and is configured to provide the signal of the first control power supply terminal to the control node under the control of the first control power supply terminal, and provide the signal of the first control power supply terminal to the pull-down node under the control of the control node; a reset control module, which is respectively coupled to the pull-down node, the second power supply terminal and the pull-up node, and is configured to provide the signal of the second power supply terminal to the pull-up node under the control of the pull-down node.

[0017] A third reset module, which is respectively coupled to the pull-down node, the second power supply terminal and the output signal terminal, and is configured to provide the signal of the second power supply terminal to the output signal terminal under the control of the pull-down node.

[0018] A reset control module, which is respectively coupled to a pull - down node, a second power supply terminal, and a pull - up node, and is configured to provide a signal of the second power supply terminal to the pull - up node under the control of the pull - down node;

[0019] A fourth reset module, which is respectively coupled to a second control power supply terminal, a second power supply terminal, and an output signal terminal, and is configured to provide a signal of the second power supply terminal to the output signal terminal under the control of the second control power supply terminal.

[0020] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a driving method for a reset device, which is applied to the reset device of any embodiment of the present disclosure. The method includes:

[0021] A voltage detection module detects the voltage of the pull - up node of the shift register. When the voltage signal of the pull - up node is abnormal, the output terminal outputs a first voltage signal, and the first voltage signal is greater than the threshold voltage;

[0022] When the forced reset module receives the first voltage signal, it provides a reset signal to the pull - up node, so that the pull - up node is reset.

[0023] In some possible implementation manners, when the first reset module of the shift register provides a signal of the third power supply terminal to the pull - up node, the forced reset module provides a reset signal to the pull - up node.

[0024] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, which includes the reset device of any embodiment of the present disclosure.

[0025] The technical solution of the embodiments of the present disclosure can achieve the following beneficial effects: When the pull - up node is abnormal, a reset signal can be automatically provided to the pull - up node to reset it, thereby extending the service life of the shift register.

[0026] The above summary is only for the purpose of the specification and is not intended to be limiting in any way. In addition to the above - described illustrative aspects, embodiments, and features, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In the drawings, unless otherwise specified, the same reference numerals throughout the several views denote the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments of the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0028] Figure 1 It is a schematic structural diagram of a shift register in the related art;

[0029] Figure 2 Schematic diagram for comparing the first transistor characteristic curves of products with good display screens and products with abnormal display screens;

[0030] Figure 3 Schematic diagram of the reset device structure in an embodiment of the present disclosure;

[0031] Figure 4A Voltage signal diagram of the pull-up node under normal conditions;

[0032] Figure 4B Schematic diagram of the abnormal elevation of the pull-up node;

[0033] Figure 5 Schematic diagram of the voltage detection module in an embodiment of the present disclosure;

[0034] Figure 6 Schematic diagram of the reset device structure in another embodiment of the present disclosure;

[0035] Figure 7 Schematic diagram of the reset device structure in yet another embodiment of the present disclosure;

[0036] Figure 8 Timing diagram of one frame time of the reset device of the present disclosure.

[0037] Explanation of reference numerals:

[0038] 10. Shift register; 20. Voltage detection module; 30. Forced reset module; 11. Pull-up module; 12. Output module; 13. First reset module; 14. Pull-down module; 15. Noise reduction module; 16. Third reset module; 17. Reset control module; 18. Fourth reset module; 31. Control module; 32. Second reset module. Detailed implementation manners

[0039] In the following, only some exemplary embodiments are briefly described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and the description are considered to be exemplary in nature rather than restrictive.

[0040] Currently, when LCD display products are applied in static display scenarios such as billboards and digital photo frames, for example, digital photo frame products are more stringent than traditional consumer electronics display products. The display products experience a screen flashing phenomenon after continuously running without power-off for half a year. The 15-inch display products using the 11T1C model have 6.67% and 1% color mosaic defects at the end customers with 7D*24h, and the 21-inch display products have 2 pcs color mosaic defects at the end customers with 7D*24h after continuously running for 3000h.

[0041] Figure 1 It is a schematic structural diagram of a shift register in the related art. As Figure 1 shown, the shift register adopts a 10T1C structure. The inventor found that the main reason for the above problems is that: with the 7D*24h continuous operation of the display product, most of the electrons in the active layer material hydrogenated amorphous silicon (a-Si:H) of the transistor are trapped by the defect states in the forbidden band, and more and more holes are injected from the source electrode into the active layer, resulting in Figure 1 the characteristic drift of the first transistor M1 in the circuit shown, the off-state current Ioff increases, resulting in leakage of the first power supply terminal VDS to the pull-up node PU, and then causing the potential of the pull-up node PU to rise abnormally, resulting in a decrease in the pulling-down ability of the pull-down node PD, causing the pull-up node PU to be repeatedly pulled high, and then causing the first transistor M1 to output repeatedly (Multi), resulting in an abnormal display screen.

[0042] Figure 2 It is a schematic diagram comparing the characteristic curves of the first transistor in products with good display screens and products with abnormal display screens. Figure 2 In it, the abscissa is voltage and the ordinate is current. Products with good display screens can be called OK products, and products with abnormal display screens can be called NG products. Referring to Figure 2 shown, the off-state current Ioff of the NG product increases compared with that of the OK product, resulting in abnormal and unstable operation of the shift register, thus affecting the product stability.

[0043] In order to solve the problem of abnormal display caused by the characteristic drift of the first transistor in the related art, the embodiments of the present disclosure provide a reset device. The technical solution of the present disclosure will be introduced in detail below through embodiments.

[0044] Figure 3 It is a schematic structural diagram of the reset device according to the embodiment of the present disclosure. In one embodiment, as Figure 3 shown, the reset device according to the embodiment of the present disclosure includes a shift register 10, a voltage detection module 20, and a forced reset module 30.

[0045] In one embodiment, as Figure 3As shown, the shift register 10 includes a pull-up module 11, an output module 12, and a first reset module 13. The pull-up module 11 is respectively coupled to an input signal terminal INPUT, a first power supply terminal VDS, and a pull-up node PU. The pull-up module 11 is configured to provide the signal of the first power supply terminal VDS to the pull-up node PU under the control of the input signal terminal INPUT. The output module 12 is respectively coupled to a clock signal terminal CLK, the pull-up node PU, and an output signal terminal OUTPUT. The output module 12 is configured to provide the signal of the clock signal terminal CLK to the output signal terminal OUTPUT under the control of the pull-up node PU. The first reset module 13 is respectively coupled to a reset signal terminal RST, a third power supply terminal VSD, and the pull-up node PU. The first reset module 13 is configured to provide the signal of the third power supply terminal VSD to the pull-up node PU under the control of the reset signal terminal RST.

[0046] In one embodiment, as Figure 3 shown, the voltage detection module 20 includes an input terminal a and an output terminal b. The input terminal a is coupled to the pull-up node PU. The voltage detection module 20 is configured to output a first voltage signal V1 at the output terminal b when the voltage signal of the pull-up node PU is abnormal, and the first voltage signal V1 is greater than the threshold voltage V0. The forced reset module 30 is coupled to the output terminal b. The forced reset module 30 is configured to provide a reset signal to the pull-up node PU when receiving the first voltage signal V1, so that the pull-up node PU is reset.

[0047] It should be noted that in the display panel, the output signal terminal OUTPUT of the shift register 10 can be connected to the gate line to provide a gate driving signal to the gate line. In one frame of the picture, the working state of the shift register 10 can include a driving stage and a reset stage. In the driving stage, the pull-up module 11 provides the signal of the first power supply terminal VDS to the pull-up node PU under the control of the input signal terminal INPUT. At this time, the voltage of the pull-up stage PU is the same as the voltage of the first power supply terminal VDS; the output module 12 provides the signal of the clock signal terminal CLK to the output signal terminal OUTPUT under the control of the pull-up node PU, provides a gate signal to the gate line, and drives the corresponding row of pixels to display. In the reset stage, the first reset module 13 provides the signal of the third power supply terminal VSD to the pull-up node PU under the control of the reset signal terminal RST. At this time, the voltage of the pull-up stage PU is the same as the voltage of the third power supply terminal VSD; the output module 12 is turned off, no gate signal is output from the gate line, and the corresponding row of pixels does not display. Usually, the first power supply terminal VDS is a high-level signal, and the third power supply terminal VSD is a low-level signal. Under normal circumstances, the voltage signal of the pull-up node PU is as Figure 4A shown, Figure 4A is the voltage signal diagram of the pull-up node PU under normal circumstances. From Figure 4AIt can be seen that during the reset phase, the voltage of the pull-up node PU remains the signal of the third power supply terminal VSD.

[0048] Figure 4B FIG. is a schematic diagram of the abnormal elevation of the pull-up node PU. Due to the continuous operation of the input module 11, the characteristics of the devices in the input module 11 drift, resulting in leakage of the first power supply terminal VDS to the pull-up node PU during the reset phase, causing the potential of the pull-up node PU to abnormally rise during the reset phase, as Figure 4B shown, resulting in an abnormal signal of the pull-up node PU and causing abnormal display.

[0049] The voltage detection module 20 of the present disclosure embodiment can detect the voltage signal of the pull-up node PU. When the voltage of the pull-up node PU is normal, the output terminal b of the voltage detection module 20 outputs a second voltage signal V2, and the second voltage signal V2 is less than or equal to the threshold voltage V0, and the forced reset module 30 does not provide a reset signal to the pull-up node PU. When the voltage of the pull-up node PU is abnormal, the output terminal b of the voltage detection module 20 outputs a first voltage signal V1, and the first voltage signal V1 is greater than the threshold voltage V0. After receiving the first voltage signal V1, the forced reset module 30 provides a reset signal to the pull-up node PU, so that the pull-up node PU is reset, avoiding the abnormal elevation of the pull-up node PU during the reset phase, avoiding abnormal display, and extending the service life of the shift register.

[0050] The reset device of the present disclosure embodiment can be applied to display products in a continuous static display scenario. By monitoring the voltage of the pull-up node PU through the voltage detection module 20, when the pull-up node PU is abnormal, a first voltage signal is provided to the forced reset module 30, so that the forced reset module provides a reset signal to the pull-up node PU, preventing abnormal display caused by the abnormal elevation of the pull-up node PU due to leakage of the input module.

[0051] Exemplarily, the display panel may include multiple rows of pixels and multiple gate lines, and each gate line may provide a gate driving signal to a row of pixels. The output signal terminal OUTPUT may be connected to the corresponding gate line, the input signal terminal INPUT may be connected to the upper row of gate lines, and the reset signal terminal RST may be connected to the lower row of gate lines. Referring to Figure 5 FIG., in one implementation, the voltage detection module 20 includes a diode D1, a first capacitor C2, and a first resistor R1. The positive electrode of the diode D1 is coupled to the input terminal a, the first capacitor C2 and the first resistor R1 are connected in parallel, and both ends of the first capacitor C2 and the first resistor R1 are respectively coupled to the negative electrode of the diode D1 and the fourth power supply terminal GND. The negative electrode of the diode D1 is coupled to the output terminal b. Exemplarily, the fourth power supply terminal GND may be a reference voltage terminal. The voltage value of the fourth power supply terminal GND can be set as needed.

[0052] As can be seen from Figure 4, the voltage of the pull-up node PU is a pulsed voltage. During the driving stage, the voltage signal of the pull-up node PU is the third voltage signal V3. During the reset stage, the voltage signal of the pull-up node PU is the fourth voltage signal V4. The third voltage signal V3 is greater than the voltage signal of the fourth power supply terminal GND, and the fourth voltage signal V4 is less than the signal of the fourth power supply terminal GND. It should be noted that as can be seen from Figure 4, the voltage of the pull-up node PU changes during the driving stage. Here, the third voltage signal V3 is not limited to a constant value. The third voltage signal V3 can be a changing value, but the third voltage signal V3 is greater than the signal of the fourth power supply terminal GND.

[0053] During the driving stage, the voltage signal of the pull-up node PU is the third voltage signal V3. The third voltage signal V3 is greater than the voltage signal of the fourth power supply terminal GND. When the diode D1 of the voltage detection module is forward-biased, there is current passing through. The voltage of the pull-up node PU becomes pulsating direct current after passing through the diode D1. During the driving stage, when the voltage of the pull-up node PU increases to the peak value, the first capacitor C2 is charged, and the first capacitor C2 stores electrical energy. During the reset stage, the voltage of the pull-up node PU is less than the voltage of the fourth power supply terminal GND, and the electrical energy of the first capacitor C2 is released. The pulsed voltage of the pull-up node PU is converted into pure direct current through the charging and discharging process of the first capacitor C2, and the voltage drop across the first resistor R1 is the output voltage. Under normal circumstances, the voltage output at the output terminal b is the second voltage signal V2, and the second voltage signal V2 is less than or equal to the threshold voltage V0.

[0054] When the signal of the pull-up node PU is abnormal, an abnormal peak appears during the reset stage of the pull-up node PU, resulting in the first capacitor C2 being charged during the reset stage, causing the voltage drop across the first resistor R1 to increase compared to the normal state of the pull-up node PU, that is, the voltage output at the output terminal b is the first voltage signal V1, and the first voltage signal V1 is greater than the threshold voltage V0.

[0055] Under the normal state of the pull-up node PU, the output terminal b of the voltage detection module 20 can output the second voltage signal V2, and the second voltage signal V2 is less than or equal to the threshold voltage V0. Under the abnormal state of the pull-up node PU, the output terminal b of the voltage detection module 20 outputs the first voltage signal V1, and the first voltage signal V1 is greater than the threshold voltage V0, so that the abnormal state of the pull-up node PU can be detected through the voltage detection module 20.

[0056] It should be noted that the specific value of the threshold voltage V0 is not limited here and can be defined according to actual usage requirements. The structure of the voltage detection module 20 is not limited to the diode D1, the first capacitor C2, and the first resistor R1, and other circuits with voltage detection can also be used. The capacitance value of the first capacitor C2 and the resistance value of the first resistor R1 can both be set according to actual needs and are not specifically limited here.

[0057] Referring to Figure 3 , in one embodiment, the forced reset module 30 includes a control module 31 and a second reset module 32. The control module 31 is configured to send a trigger signal to the second reset module 32 when receiving the first voltage signal V1 from the voltage detection module 20. The second reset module 32 is configured to provide a reset signal to the pull-up node PU when receiving the trigger signal, so as to reset the pull-up node PU.

[0058] Exemplarily, the control module 31 can be a control switch. When the voltage detection module 20 outputs the first voltage signal V1, the control module 31 is started. When the voltage detection module 20 outputs the second voltage signal V2, the control module 31 is not started.

[0059] In one implementation manner, the control module 31 includes a timing controller TCON. The input end of the timing controller TCON is communicatively connected to the voltage detection module 20, and the output end of the timing controller is electrically connected to the forced reset module 30. The timing controller can be used to receive the first voltage signal V1 and the second voltage signal V2 output from the voltage detection module. When the first voltage signal V1 is greater than the threshold voltage V0, the voltage of the pull-up node PU of the shift register is abnormal. When the timing controller determines that the first voltage signal V1 is greater than the threshold voltage V0, a trigger signal is sent to the second reset module 32, otherwise no trigger signal is sent.

[0060] In one embodiment, as Figure 7 shown, the second reset module 32 includes a reset transistor M7. The gate of the reset transistor M7 is coupled to the control module 31, and the first pole and the second pole of the reset transistor M7 are respectively coupled to the second power supply terminal VGL and the pull-up node PU. Thus, when the control module 31 receives the first voltage signal V1, the control module 31 starts to output a valid level signal to control the reset transistor M7 to conduct. Under the control of the control module 31, the reset transistor M7 provides the signal of the second power supply terminal VGL to the pull-up node PU, so as to reset the pull-up node PU. When the control module 31 receives the second voltage signal V2, the control module 31 does not provide a valid level signal to the reset transistor M7.

[0061] Referring to Figure 6, in one embodiment, the shift register 10 further includes a pull-down module 14, a noise suppression module 15, a third reset module 16, a reset control module 17, and a fourth reset module 18.

[0062] In one embodiment, as Figure 6 shown, the pull-down module 14 is respectively coupled to the second power supply terminal VGL, the pull-up node PU, and the control node PD_CN. The pull-down module 14 is configured to provide the signal of the second power supply terminal VGL to the pull-down node PD and the control node PD_CN under the control of the pull-up node PU.

[0063] In one embodiment, as Figure 6 shown, the noise suppression module 15 is respectively coupled to the first control power supply terminal GCH, the control node PD_CN, and the pull-down node PD. The noise suppression module 15 is configured to provide the signal of the first control power supply terminal GCH to the control node PD_CN under the control of the first control power supply terminal GCH, and provide the signal of the first control power supply terminal GCH to the pull-down node PD under the control of the control node PD_CN.

[0064] In one embodiment, as Figure 6 shown, the third reset module 16 is respectively coupled to the pull-down node PD, the second power supply terminal VGL, and the output signal terminal OUTPUT. The third reset module 16 is configured to provide the signal of the second power supply terminal VGL to the output signal terminal OUTPUT under the control of the pull-down node PD.

[0065] In one embodiment, as Figure 6 shown, the fourth reset module 18 is respectively coupled to the second control power supply terminal GCL, the second power supply terminal VGL, and the output signal terminal OUTPUT. The fourth reset module 18 is configured to provide the signal of the second power supply terminal VGL to the output signal terminal OUTPUT under the control of the second control power supply terminal GCL.

[0066] In one embodiment, as Figure 7 shown, the pull-up module 11 includes a first transistor M1. The gate of the first transistor M1 is coupled to the input signal terminal INPUT. The first pole and the second pole of the first transistor M1 are respectively coupled to the first power supply terminal VDS and the pull-up node PU. Thus, when the input signal terminal INPUT is a valid level signal, the first transistor M1 provides the signal of the first power supply terminal VDS to the pull-up node PU under the control of the valid level signal of the input signal terminal INPUT, pulling up the pull-up node PU.

[0067] In one embodiment, as Figure 7As shown, the output module 12 includes a first transistor M3 and a storage capacitor C1. The gate of the first transistor M3 is coupled to the pull-up node PU. The first and second poles of the first transistor M3 are respectively coupled to the clock signal terminal CLK and the output signal terminal OUTPUT. The first and second plates of the storage capacitor C1 are respectively coupled to the pull-up node PU and the output signal terminal OUTPUT. Thus, when the pull-up node PU is at an active level signal, the first transistor M3 provides the signal of the clock signal terminal CLK to the output signal terminal OUTPUT under the control of the active level signal of the pull-up node PU, so that the output signal terminal OUTPUT outputs a gate driving signal.

[0068] In one embodiment, the first power supply terminal VDS is at a high level signal. The second power supply terminal VGL may be at a low level signal. The third power supply terminal VSD may be at a low level signal. The first control power supply terminal GCH may be at a high level signal.

[0069] It should be noted that although the first power supply terminal VDS is at a high level signal and the first control power supply terminal GCH is at a high level signal, it does not mean that the voltage of the first power supply terminal VDS is the same as the voltage of the first control power supply terminal GCH. The voltage of the first power supply terminal VDS and the voltage of the first control power supply terminal GCH may be the same or different, and the specific voltage values of the first power supply terminal VDS and the first control power supply terminal GCH can be set as needed. Similarly, although the second power supply terminal VGL is at a low level signal and the third power supply terminal VSD is at a low level signal, it does not mean that the voltage of the second power supply terminal VGL is the same as the voltage of the third power supply terminal VSD. The voltage of the second power supply terminal VGL and the voltage of the third power supply terminal VSD may be the same or different, and the specific voltage values of the second power supply terminal VGL and the third power supply terminal VSD can be set as needed.

[0070] In one embodiment, as Figure 7 shown, the first reset module 13 includes a first transistor M2. The gate of the first transistor M2 is coupled to the reset signal terminal RST. The first and second poles of the first transistor M2 are respectively coupled to the third power supply terminal VSS and the pull-up node PU. Thus, when the reset signal terminal RST is at an active level signal, the first transistor M2 provides the signal of the third power supply terminal VSS to the pull-up node PU under the control of the active level signal of the reset signal terminal RST, so as to reset the pull-up node PU.

[0071] In one embodiment, as Figure 7As shown, the pull-down module 14 may include a sixth transistor M6 and an eighth transistor M8. The gate of the sixth transistor M6 is coupled to the pull-up node PU, and the first and second poles of the sixth transistor M6 are respectively coupled to the pull-down node PD and the second power supply terminal VGL. The gate of the eighth transistor M8 is coupled to the pull-up node PU, and the first and second poles of the eighth transistor M8 are respectively coupled to the control node PD_CN and the second power supply terminal VGL. Thus, when the pull-up node PU is at an active level signal, the sixth transistor M6 provides the signal of the second power supply terminal VGL to the pull-down node PD under the control of the active level signal of the pull-up node PU, pulling down the pull-down node PD; the eighth transistor M8 provides the signal of the second power supply terminal VGL to the control node PD_CN under the control of the active level signal of the pull-up node PU, pulling down the control node PD_CN.

[0072] Exemplarily, the sixth transistor M6 and the eighth transistor M8 may be of the same type. For example, both the sixth transistor M6 and the eighth transistor M8 may be NMOS.

[0073] In one embodiment, as Figure 7 shown, the noise suppression module 15 may include a fifth transistor M5 and a ninth transistor M9. The gate of the ninth transistor M9 is coupled to the first control power supply terminal GCH, and the first and second poles of the ninth transistor M9 may be respectively coupled to the first control power supply terminal GCH and the control node PD_CN. Thus, when the first control power supply terminal GCH is at an active level, the ninth transistor M9 may provide the signal of the first control power supply terminal GCH to the control node PD_CN under the control of the active level of the first control power supply terminal GCH. The gate of the fifth transistor M5 is coupled to the control node PD_CN, the first pole of the fifth transistor M5 is coupled to the first control power supply terminal GCH, and the second pole of the fifth transistor M5 is coupled to the pull-down node PD. When the signal of the control node PD_CN is at an active level, the fifth transistor M5 may provide the signal of the first control power supply terminal GCH to the pull-down node PD under the control of the active level of the control node PD_CN.

[0074] Exemplarily, the fifth transistor M5 and the ninth transistor M9 may be of the same type. For example, both the fifth transistor M5 and the ninth transistor M9 may be NMOS.

[0075] It should be noted that Figure 7 the circuit structure of the noise suppression module 15 is exemplarily shown in Figure 7 but the noise suppression module 15 is not limited to the

[0076] structure in Figure 7As shown, the third reset module 16 includes an eleventh transistor M11. The gate of the eleventh transistor M11 is coupled to the pull-down node PD, and the first and second poles of the eleventh transistor M11 are respectively coupled to the second power supply terminal VGL and the output signal terminal OUTPUT. Thus, when the pull-down node PD is at an effective level signal, the eleventh transistor M11 provides the signal of the second power supply terminal VGL to the output signal terminal OUTPUT under the control of the effective level signal of the pull-down node PD, resetting the output signal terminal OUTPUT and preventing the output signal terminal OUTPUT from outputting a gate driving signal.

[0077] In one embodiment, as Figure 7 shown, the reset control module 17 includes a tenth transistor M10. The gate of the tenth transistor M10 is coupled to the pull-down node PD, and the first and second poles of the tenth transistor M10 are respectively coupled to the second power supply terminal VGL and the pull-up node PU. Thus, when the pull-down node PD is at an effective level signal, the tenth transistor M10 provides the signal of the second power supply terminal VGL to the pull-up node PU under the control of the effective level signal of the pull-down node PD, causing the pull-up node PU to maintain the reset state.

[0078] In one embodiment, as Figure 7 shown, the fourth reset module 18 includes a fourth transistor M4. The gate of the fourth transistor M4 is coupled to the second control power supply terminal GCL, and the first and second poles of the fourth transistor M4 are respectively coupled to the second power supply terminal VGL and the output signal terminal OUTPUT. When the second control power supply terminal GCL is at an effective level, the fourth transistor M4 conducts, providing the signal of the second power supply terminal VGL to the output signal terminal OUTPUT. During the display stage of a frame of image, the second control power supply terminal GCL provides an ineffective level signal. During the blank stage between two adjacent frames of images, the second control power supply terminal GCL provides an effective level signal. For example, during the display stage of the Nth frame of image, the second control power supply terminal GCL provides an ineffective level signal and the fourth transistor M4 is cut off. After the Nth frame of image and before the (N + 1)th frame of image, the second control power supply terminal GCL provides an effective level signal, the fourth transistor M4 conducts, providing the signal of the second power supply terminal VGL to the output signal terminal OUTPUT, realizing the reset of each shift register in the gate driving circuit, that is, realizing the frame image reset and avoiding affecting the next frame of image.

[0079] Figure 7Exemplarily shown in the figure are the circuit structures of the pull-up module 11, output module 12, first reset module 13, pull-down module 14, noise reduction module 15, third reset module 16, reset control module 17, and fourth reset module 18. It can be understood that the pull-up module 11, output module 12, first reset module 13, pull-down module 14, noise reduction module 15, third reset module 16, reset control module 17, and fourth reset module 18 are not limited to Figure 6 the circuit structures shown in the figure, and other circuit structures can be adopted as long as their functions can be realized.

[0080] Exemplarily, Figure 7 All the transistors in the shown shift register are NMOS transistors. When all the transistors in the shift register are NMOS transistors, the effective level signals of the transistors are high-level signals.

[0081] It should be noted that in the reset device in the embodiments of the present disclosure, in actual use, the types of the transistors are not limited. The transistors can be set as NMOS transistors or PMOS transistors according to needs, and the signals of the input signal terminal INPUT, the first power supply terminal VDS, the second power supply terminal VGL, the third power supply terminal VSD, and the second control power supply terminal GCL are correspondingly set. When the transistors in the reset device are PMOS transistors, the effective level signals of the transistors are low-level signals.

[0082] All the transistors adopted in the embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. According to their functions in the circuit, the transistors adopted in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistors adopted here are symmetrical, their source and drain can be interchanged. In the embodiments of the present disclosure, the source (source electrode) is referred to as the first pole, and the drain (drain electrode) is referred to as the second pole. Alternatively, the drain can be referred to as the first pole, and the source can be referred to as the second pole. According to the form in the drawings, the middle terminal of the transistor is defined as the gate (or gate electrode), the signal input terminal is the source, and the signal output terminal is the drain.

[0083] The switching transistors adopted in the embodiments of the present disclosure can be P-type switching transistors or N-type switching transistors. The P-type switching transistor conducts when the gate is at a low level and cuts off when the gate is at a high level. The N-type switching transistor conducts when the gate is at a high level and cuts off when the gate is at a low level. In addition, in the embodiments of the present disclosure, multiple signals each correspond to a first potential and a second potential. The first potential and the second potential only represent two different potential state quantities of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text. The embodiments of the present disclosure are described by taking the first potential as the effective potential as an example.

[0084] Among them, coupling may include: direct physical contact between two ends or indirect connection between two ends (such as connection through a signal line between two ends). The coupling manner between two ends in the embodiments of the present disclosure is not limited.

[0085] The embodiments of the present disclosure further provide a driving method for a reset device, which is applied to the reset device in any embodiment of the present disclosure. The method includes:

[0086] The voltage detection module 20 detects the voltage of the pull-up node PU of the shift register 10. When the voltage signal of the pull-up node PU is abnormal, the output terminal b outputs a first voltage signal V1, and the first voltage signal V1 is greater than the threshold voltage V0;

[0087] When the forced reset module 30 receives the first voltage signal V1, it provides a reset signal to the pull-up node PU to reset the pull-up node PU.

[0088] In one implementation, when the first reset module 13 of the shift register 10 provides a signal of the third power supply terminal VSD to the pull-up node PU, the forced reset module 30 provides a reset signal to the pull-up node PU.

[0089] Figure 8 is the working timing diagram of the reset device of the present disclosure. The following combines Figure 7 and Figure 8 , and details the working principle of the reset device in the embodiments of the present disclosure. The first power supply terminal VDS is a high-level signal, the second power supply terminal VGL is a low-level signal, the third power supply terminal VSD is a low-level signal, and the first control power supply terminal GCH is a high-level signal.

[0090] In the pull-up stage, the input signal terminal INPUT is an effective level signal (such as a high-level signal), the first transistor M1 is turned on, and a signal of the first power supply terminal VDS is provided to the pull-up node PU to pull up the pull-up node PU. The pull-up stage can be divided into two sub-stages, namely the first sub-stage and the second sub-stage. In the pull-up stage, the first power supply terminal VDS provides a signal to the pull-up node PU, the voltage detection module 20 outputs a second voltage signal V2, and the forced reset module 20 does not provide a reset signal.

[0091] In the first sub - stage, the pull - up node PU is provided with the signal of the first power supply terminal VDS to pull up the pull - up node PU. The first control power supply terminal GCH is at a high - level signal, the ninth transistor M9 is turned on, providing the high - level signal of the first control power supply terminal GCH to the control node PD_CN, the fifth transistor M5 is turned on, providing the high - level signal of the first control power supply terminal GCH to the pull - down node PD. Under the control of the high - level signal of the pull - down node PD, the tenth transistor M10 is turned on, providing the low - level signal of the second power supply terminal VGL to the pull - up node PU. Under the control of the high - level signal of the pull - down node PD, the eleventh transistor M11 is turned on, providing the low - level signal of the second power supply terminal VGL to the output signal terminal OUTPUT. Therefore, no gate signal is output at the output signal terminal in the first sub - stage.

[0092] In the first sub - stage, the pull - up node PU is provided with the high - level signal of the first power supply terminal VDS through the first transistor M1 to charge the pull - up node PU, and the pull - up node is provided with the low - level signal of the second power supply terminal VGL through the tenth transistor M10 to discharge the pull - up node PU. Since the size of the first transistor M1 is larger than that of the tenth transistor M10, the charging speed of the pull - up node PU is greater than the discharging speed of the pull - up node PU, causing the potential of the pull - up node PU to rise slowly. When the pull - up node PU is charged to the valid level signal, the shift register 10 enters the second sub - stage.

[0093] In the second sub - stage, the pull - up node PU is at the valid level signal, the sixth transistor M6 and the eighth transistor M8 are turned on, causing the pull - down node PD and the control node PD_CN to discharge. The first control power supply terminal GCH is at a high - level signal, charging the control node PD_CN through the ninth transistor M9 and charging the pull - down node PD through the fifth transistor M5. Since the size of the sixth transistor M6 is larger than that of the fifth transistor M5 and the size of the eighth transistor M8 is larger than that of the ninth transistor M9, the discharging speed of the pull - down node PD is greater than the charging speed of the pull - down node PD, and the discharging speed of the control node PD_CN is greater than the charging speed of the control node PD_CN. Therefore, both the pull - down node PD and the control node PD_CN are pulled down to the potential of the second power supply terminal VGL. The tenth transistor M10 and the eleventh transistor M11 are cut off, and the pull - up node PU maintains the high - level signal. Under the control of the valid level signal of the pull - up node PU, the first transistor M3 is turned on, providing the signal of the clock signal terminal CLK to the output signal terminal OUTPUT. At this time, the clock signal terminal CLK is at a high - level signal, causing the output signal terminal OUTPUT to output a high - level signal.

[0094] In the reset stage, the reset signal terminal RST is at an effective level signal (for example, a high-level signal), the second transistor M2 is turned on, and a low-level signal of the third power supply terminal VSD is provided to the pull-up node PU, so that the pull-up node PU is reset. Due to the characteristic drift of the first transistor M1, the off-state current of the first transistor M1 increases, and the first transistor M1 cannot be normally turned off, resulting in leakage of the first power supply terminal VDS and abnormal elevation of the pull-up node PU. The voltage detection module 20 detects the voltage of the pull-up node PU and outputs a first potential signal V1. Thus, when the forced reset module 30 receives the first voltage signal V1, the control module controls the reset transistor M7 to start, and provides a signal of the second power supply terminal VGL to the pull-up node PU, so that the pull-up node PU can be maintained at a low-level signal during the reset stage, avoiding abnormal elevation of the pull-up node PU during the reset stage, avoiding display abnormalities, and extending the product life.

[0095] Another embodiment of the present disclosure provides a display device, including the reset device according to any embodiment of the present disclosure. The display device provided by the embodiments of the present disclosure can be, for example, any product or component with display and touch functions such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, an in-vehicle display, an e-book, a biometric device such as a smart skin device, a soft robot, and a biomedical device.

[0096] Other configurations of the reset device and the display device in the above embodiments can adopt various technical solutions known to those of ordinary skill in the art now and in the future, and will not be described in detail here.

[0097] In the description of this specification, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present disclosure.

[0098] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality" means two or more, unless otherwise specifically defined.

[0099] In this disclosure, unless otherwise clearly defined and limited, terms such as "installed", "connected", "joined", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection, an electrical connection, or a communication connection; it may be directly connected, or indirectly connected through an intermediate medium, and it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0100] In this disclosure, unless otherwise clearly defined and limited, the first feature being "on" or "under" the second feature may include the direct contact between the first and second features, or may include the situation where the first and second features are not in direct contact but in contact through other features between them. Moreover, the first feature being "above", "over" and "on top of" the second feature includes that the first feature is directly above and obliquely above the second feature, or merely indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature being "under", "beneath" and "underneath" the second feature includes that the first feature is directly below and obliquely below the second feature, or merely indicates that the horizontal height of the first feature is lower than that of the second feature.

[0101] The above disclosure provides many different embodiments or examples for implementing different structures of this disclosure. To simplify this disclosure, components and settings of specific examples are described above. Of course, they are only examples and are not intended to limit this disclosure. In addition, this disclosure may repeat reference numerals and / or reference letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between various embodiments and / or settings discussed.

[0102] The above are only the specific embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by this disclosure can easily think of various changes or substitutions, and these should all be covered within the protection scope of this disclosure. Therefore, the protection scope of this disclosure shall be subject to the protection scope of the claims.

Claims

1. A reset device, characterized in that, it includes, a shift register, including a pull-up module, an output module, and a first reset module. The pull-up module is respectively coupled to an input signal terminal, a first power supply terminal, and a pull-up node, and is configured to provide the signal of the first power supply terminal to the pull-up node under the control of the input signal terminal; the output module is respectively coupled to a clock signal terminal, the pull-up node, and an output signal terminal, and is configured to provide the signal of the clock signal terminal to the output signal terminal under the control of the pull-up node; The first reset module is respectively coupled to a reset signal terminal, a third power supply terminal, and the pull-up node, and is configured to provide the signal of the third power supply terminal to the pull-up node under the control of the reset signal terminal; a voltage detection module, including an input end and an output end. The input end is coupled to the pull-up node, and is configured to output a first voltage signal at the output end when the voltage signal of the pull-up node is abnormal, and the first voltage signal is greater than a threshold voltage; a forced reset module, coupled to the output end, and is configured to provide a reset signal to the pull-up node to reset the pull-up node when receiving the first voltage signal.

2. The reset device according to claim 1, characterized in that, the voltage detection module includes a diode, a first capacitor, and a first resistor. The positive electrode of the diode is coupled to the input end, the first capacitor and the first resistor are arranged in parallel, and both ends of the first capacitor and the first resistor are respectively coupled to the negative electrode of the diode and a fourth power supply terminal, and the negative electrode of the diode is coupled to the output end.

3. The reset device according to claim 1, characterized in that, the forced reset module includes a control module and a second reset module. The control module is configured to send a trigger signal to the second reset module when receiving the first voltage signal of the voltage detection module, and the second reset module is configured to provide a reset signal to the pull-up node to reset the pull-up node when receiving the trigger signal.

4. The reset device according to claim 3, characterized in that, the second reset module includes a reset transistor. The gate of the reset transistor is coupled to the control module, and the first pole and the second pole of the reset transistor are respectively coupled to a second power supply terminal and the pull-up node.

5. The reset device according to claim 3, characterized in that, the control module includes a timing controller.

6. The reset device according to claim 1, characterized in that, it includes at least one of the following: the pull-up module includes a first transistor. The gate of the first transistor is coupled to the input signal terminal, and the first pole and the second pole of the first transistor are respectively coupled to the first power supply terminal and the pull-up node; The output module includes a third transistor and a storage capacitor. The gate of the third transistor is coupled to the pull-up node. The first and second poles of the third transistor are respectively coupled to the clock signal terminal and the output signal terminal. The first and second plates of the storage capacitor are respectively coupled to the pull-up node and the output signal terminal; The first reset module includes a second transistor. The gate of the second transistor is coupled to the reset signal terminal. The first and second poles of the second transistor are respectively coupled to the third power supply terminal and the pull-up node.

7. The reset device according to claim 1, wherein, the shift register further includes: a pull-down module, respectively coupled to the second power supply terminal, the pull-up node, and a control node, and configured to provide the signal of the second power supply terminal to a pull-down node and the control node under the control of the pull-up node; a noise suppression module, respectively coupled to the first control power supply terminal, the control node, and the pull-down node, and configured to provide the signal of the first control power supply terminal to the control node under the control of the first control power supply terminal, and provide the signal of the first control power supply terminal to the pull-down node under the control of the control node; a third reset module, respectively coupled to the pull-down node, the second power supply terminal, and the output signal terminal, and configured to provide the signal of the second power supply terminal to the output signal terminal under the control of the pull-down node; a reset control module, respectively coupled to the pull-down node, the second power supply terminal, and the pull-up node, and configured to provide the signal of the second power supply terminal to the pull-up node under the control of the pull-down node; a fourth reset module, respectively coupled to the second control power supply terminal, the second power supply terminal, and the output signal terminal, and configured to provide the signal of the second power supply terminal to the output signal terminal under the control of the second control power supply terminal.

8. A driving method for a reset device, applied to the reset device according to any one of claims 1 to 7, wherein, the method includes: the voltage detection module detects the voltage of the pull-up node of the shift register. When the voltage signal of the pull-up node is abnormal, the output terminal outputs a first voltage signal, and the first voltage signal is greater than the threshold voltage; the forced reset module provides a reset signal to the pull-up node when receiving the first voltage signal, so that the pull-up node is reset.

9. The driving method for the reset device according to claim 8, wherein, when the first reset module of the shift register provides the signal of the third power supply terminal to the pull-up node, the forced reset module provides a reset signal to the pull-up node.

10. A display device, wherein, it includes the reset device according to any one of claims 1 to 7.

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