SRAM and System-on-Chip

Abstract

This invention provides an SRAM and a system-on-a-chip (SoC). The SRAM incorporates an additional access transistor connected in parallel with each of the two access transistors in a 6T SRAM memory cell. This increases the read noise margin (SNMR), resulting in a more balanced hold noise margin (SNMH), write noise margin (SNMW), and read noise margin (SNMR) of the SRAM. Therefore, the read and write capabilities of the SRAM are improved without increasing process complexity. The SoC of this invention achieves improved performance due to the use of the SRAM described herein.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to an SRAM and a system-on-a-chip. Background Technology

[0002] SRAM (Static Random-Access Memory) is a storage device that can store data as long as it is powered on. It has the characteristics of small storage capacity, fast operation speed and high operating efficiency, and is a key component of most high-performance System on Chip (SoC).

[0003] The current mainstream SRAM design is the 6T SRAM structure. The basic storage unit of this SRAM is called a bit, which can only store one signal, 0 or 1. One bit consists of 6 transistors. Please refer to [reference needed]. Figure 1 Specifically, it consists of two PMOS transistors, PU1 and PU2, and four NMOS transistors, PD1, PD2, PG1, and PG2. Among them, NMOS transistors PG1 and PG2 are also called pass-gate transistors or access transistors, and their function is to implement…

[0004] The connection of bitlines BL and BL' enables read and write functions. PMOS transistors PU1 and PU2, also known as pull-up transistors or load transistors, function to maintain a high potential (state 1) for their respective nodes. NMOS transistors PD1 and PD2, also known as pull-down transistors or drive transistors, function to maintain a low potential (state 0) for their respective nodes. PU1 and PD1 form one inverter, and PU2 and PD2 form another inverter. These two inverters form an interlock structure to store data. Thus, by swapping the high and low potentials of two nodes (SNL and SNR) in a bit, both 0 and 1 states can be stored.

[0005] However, the existing 6T SRAM read / write capabilities have limitations and cannot meet the demands of higher-performance on-chip systems. Summary of the Invention

[0006] The purpose of this invention is to provide an SRAM and on-chip system with high read and write capabilities.

[0007] To achieve the above objectives, the present invention provides an SRAM having a memory array, wherein the basic memory cell in the memory array comprises:

[0008] The first and second load transistors and the first and second drive transistors, the drain of the first load transistor, the drain of the first drive transistor, the gate of the second load transistor and the gate of the second drive transistor are all coupled to the first node, the gate of the first load transistor, the gate of the first drive transistor, the drain of the second load transistor and the drain of the second drive transistor are all coupled to the second node, the source of the first load transistor and the source of the second load transistor are all coupled to the first power supply, and the source of the first drive transistor and the source of the second drive transistor are all coupled to the second power supply.

[0009] The first to fourth access transistors have their gates coupled to a first word line, the gates of the first and second access transistors are coupled to a second word line, the gates of the third and fourth access transistors are coupled to a second word line, the sources of the first and third access transistors are coupled to a first bit line, the drains of the first and third access transistors are coupled to a first node, the sources of the second and fourth access transistors are coupled to a second bit line, and the drains of the second and fourth access transistors are coupled to a second node.

[0010] Optionally, when the channel length of the third access transistor is the same as the channel length of the first access transistor, the channel width of the third access transistor is 1 / 3 to 1 / 2 of the channel width of the first access transistor.

[0011] Optionally, when the channel length of the fourth access transistor is the same as the channel length of the second access transistor, the channel width of the fourth access transistor is 1 / 3 to 1 / 2 of the channel width of the second access transistor.

[0012] Optionally, when performing a read operation on the smallest storage unit, both the first word line and the second word line are at a high level; when performing a write operation on the smallest storage unit, the first word line is at a high level and the second word line is at a low level.

[0013] Optionally, the first to fourth access transistors, the first driving transistor, and the second driving transistor are all NMOS transistors, and the first load transistor and the second load transistor are both PMOS transistors.

[0014] Optionally, the first power source is the system power supply, and the second power source is ground.

[0015] Optionally, the SRAM further includes control circuitry and row address decoders, column address decoders, and sensitive amplifiers respectively coupled to the memory array and the control circuitry.

[0016] Based on the same inventive concept, the present invention also provides a system-on-a-chip that includes SRAM as described in the present invention.

[0017] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0018] 1. Simply add one set of access transistors to the existing 6T SRAM memory cells, without increasing the process complexity;

[0019] 2. An additional access transistor is connected in parallel with the access transistor of the existing 6T SRAM memory cell, thus making β = I. PD / I PG / / PGa This is equivalent to enhancing the driving capability of the driving transistor PD in the existing 6T SRAM memory cell, increasing the read noise margin SNMR, and making the SRAM's SNMH, SNMW, and SNMR more balanced, thus improving the SRAM's read and write capabilities. Attached Figure Description

[0020] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0021] Figure 1 This is a schematic diagram of the circuit structure of a typical 6T SRAM basic storage cell.

[0022] Figure 2 Yes Figure 1 The diagram shows the static noise margin (SNM) curve for a 6T SRAM basic memory cell.

[0023] Figure 3 This is a schematic diagram of the SRAM system architecture according to an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the circuit structure of a basic SRAM storage cell according to an embodiment of the present invention.

[0025] Figure 5 yes Figure 1 and Figure 4 The diagram shows the voltage levels on the corresponding signal lines when the basic storage cell of SRAM is read or written.

[0026] Figure 6 yes Figure 1 and Figure 4The table shows a comparison of the standby current (Istb), read noise margin (SNMR), and write noise margin (SNMW) of SRAM. Detailed Implementation

[0027] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0028] Please refer to Figure 1 and Figure 2 Key electrical ratio parameters used to evaluate the performance of a typical 6T SRAM memory cell include: α = I PU / I PD ,β=I PD / I PG γ=I PG / I PU Among them, I PU I represents the current of PMOS transistor PU1 or PU2. PD I represents the current of NMOS transistor PD1 or PD2. PGα is the current of NMOS transistor PG1 or PG2, α is a parameter describing the ease of write operation or write stability, β is a parameter describing read stability, and γ is a parameter describing data retention stability. That is, α is related to the write stability margin (also known as write noise margin) SNMW, β is related to the read stability margin (also known as read noise margin) SNMR, and γ is related to the data retention stability margin (also known as retention noise margin) SNMH. Read noise margin SNMR, write noise margin SNMW, and retention noise margin SNMH are the maximum noise that an SRAM memory cell can tolerate before data is lost or corrupted.

[0029] Figure 2 The image shows a graph illustrating static noise margin (SNM) analysis of a typical 6T SRAM memory cell. From... Figure 2 As can be seen, in the existing 6T SRAM read and write process, the read noise margin (SNMR) is the weakest, so it often becomes the bottleneck that limits the improvement of 6T SRAM read and write capabilities.

[0030] Furthermore, due to the mutual influence between the α, β, and γ ratios of the 6T SRAM memory cells and the size of the internal transistors, existing technologies, even by simply adjusting the basic memory cells of the 6T SRAM through methods such as ion implantation (IMP), find it difficult to balance SNMR, SNMW, and SNMH to achieve sufficient read and write capabilities.

[0031] Based on this, the present invention provides an SRAM that, on the basis of the existing typical 6T SRAM basic memory cell structure, adds a set of access transistors PG, which is equivalent to enhancing the driving capability of the driving transistors PD in the 6T SRAM basic memory cell, thereby improving the read and write capability of the 6T SRAM.

[0032] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0033] For details, please refer to Figure 3 and Figure 4An embodiment of the present invention provides an SRAM having a memory array 10, a control circuit 11, and a row address decoder 12, a column address decoder 13, and a sensitive amplifier 14 respectively coupled to the memory array 10 and the control circuit 11. The memory array 10 has a plurality of basic memory cells arranged in rows and columns to form the memory array. Basic memory cells in the same row are connected to the same first word line WL, and basic memory cells in the same column are connected to the same first bit line BL. The row address decoder 12, the column address decoder 13, and the sensitive amplifier 14 are controlled by the timing logic of the control circuit 11 to select corresponding basic memory cells from the memory array 10 for read or write operations. In this system, row address decoder 12 sends corresponding signals to the corresponding first word line WL and second word line RWL to select a row from the memory array 10, and column address decoder 13 sends corresponding signals to the corresponding first bit line BL and second bit line BLB to select a column from the memory array 10. Thus, through the combined action of row address decoder 12 and column decoder 13, the corresponding basic memory cells are selected from the memory array for read or write operations. Sensitive amplifier 14 is used to detect and judge the data content in the selected basic memory cell during a read operation.

[0034] It should be understood that the SRAM system architecture of this embodiment may also include any other suitable circuits in the art, which will not be described in detail here.

[0035] Please refer to this carefully. Figure 4 In this embodiment, the basic memory cell in the SRAM memory array includes 6 NMOS transistors and 2 PMOS transistors. The 6 NMOS transistors are the first access transistor PG1, the second access transistor PG2, the third access transistor PG1a, the fourth access transistor PG2a, the first drive transistor PD1, and the second drive transistor PD2. The 2 PMOS transistors are the first load transistor PU1 and the second load transistor PU2.

[0036] The first access transistor PG1, the second access transistor PG2, the first drive transistor PD1, the second drive transistor PD2, the first load transistor PU1, and the second load transistor PU2 together constitute the basic memory cell structure of a typical 6T SRAM. The third access transistor PG1a is connected in parallel to the first access transistor PG1, and the fourth access transistor PG2a is connected in parallel to the second access transistor PG2.

[0037] Specifically, the drains of the first load transistor PU1, the first drive transistor PD1, the gates of the second load transistor PU2 and the second drive transistor PD2, the drains of the first access transistor PG1, and the drains of the third access transistor PG1a are all coupled to the first node n1. The drains of the second load transistor PU2, the second drive transistor PD2, the gates of the first load transistor PU1 and the first drive transistor PD1, the drains of the second access transistor PG2, and the drains of the fourth access transistor PG2a are all coupled to the second node n2. The first load transistor PU1 and the first drive transistor PD1 form an inverter, and the second load transistor PU2 and the second drive transistor PD2 form another inverter. The input of one inverter is connected to the output of the other inverter, and the output is connected to the input of the other inverter, thus forming an interlocked structure between the two inverters.

[0038] The source of the first load transistor PU1 and the source of the second load transistor PU2 are both coupled to the first power supply Vdd, and the source of the first drive transistor PD1 and the source of the second drive transistor PD2 are both coupled to the second power supply Vss. The first power supply Vdd can be the system power supply for the SRAM, and the second power supply Vss can be ground GND.

[0039] The gates of the first access transistor PG1 and the second access transistor PG2 are both coupled to the first word line WL, which is a typical word line of a 6T SRAM. The gates of the third access transistor PG1a and the fourth access transistor PG2a are coupled to the second word line RWL, which is set to a high level (or a valid signal) during read operations.

[0040] The source of the first access transistor PG1 and the source of the third access transistor PG1a are both coupled to the first bit line BL, and the source of the second access transistor PG2 and the source of the fourth access transistor PG2a are both coupled to the second bit line BLB.

[0041] Please combine Figure 4 and Figure 5 In this embodiment, when a read operation is required on the selected basic memory cell in the SRAM, the first bit line BL, the second bit line BLB, the first word line WL, and the second word line RWL connected to the basic memory cell are all set to "1" (also known as high level or valid signal); when a write operation is required on the selected basic memory cell in the SRAM, the second bit line BLB and the first word line WL connected to the basic memory cell are both set to "1" (also known as high level or valid signal), and the first bit line BL and the second word line RWL are both set to "0" (also known as low level or invalid signal).

[0042] It should be understood that the dimensions of the third access transistor PG1a and the fourth access transistor PG2a can be arbitrarily suitable, as long as they can increase the read noise margin (SNMR) when connected in parallel with the corresponding access transistors. Furthermore, the first access transistor PG1, the second access transistor PG2, the third access transistor PG1a, and the fourth access transistor PG2a can be formed simultaneously during SRAM manufacturing without increasing process complexity.

[0043] Preferably, the first access transistor PG1 and the second access transistor PG2 have the same size, and the third access transistor PG1a and the fourth access transistor PG2a have the same size.

[0044] As an example, when the channel length L of the third access transistor PG1a PGa The channel length L of the first access transistor PG1 PG At the same time, the channel width W of the third access transistor PG1a PGa The channel width W of the first access transistor PG1 PG 1 / 3 to 1 / 2 of it.

[0045] As another example, when the channel length L of the fourth access transistor PG2a PGa The channel length L of the second access transistor PG2 PG At the same time, the channel width W of the fourth access transistor PG2a PGa The channel width W of the second access transistor PG2 PG 1 / 3 to 1 / 2 of it.

[0046] In this embodiment, among the key electrical parameters of the basic SRAM storage cell, parameter α = I PU / I PD ,β=I PD / I( PG / / PGa ), γ=I PG / I PU , among which, I PU I represents the current of either the first load transistor PU1 or the second load transistor PU2. PD I is the current of either the first driving transistor PD1 or the second driving transistor PD2. PG For the current of the first access transistor PG1 or the second access transistor PG2, I( PG / / PGa) represents the current after the first access transistor PG1 and the third access transistor PG1a are connected in parallel, or the current after the second access transistor PG2 and the fourth access transistor PG2a are connected in parallel. α is related to the write stability margin (also known as write noise margin) SNMW, β is related to the read stability margin (also known as read noise margin) SNMR, and γ is related to the data retention stability margin (also known as retention noise margin) SNMH.

[0047] Because I( PG / / PGa ) represents the current after PG1 and PG1a are connected in parallel, or the current after PG2 and PG2a are connected in parallel, I( PG / / PGa )>I PG This is equivalent to enhancing the drive current (i.e., drive capability) of the first driving transistor PD1 or the second driving transistor PD2. Therefore, the SRAM parameter β = I in this embodiment... PD / I( PG / / PGa )relatively Figure 1 The SRAM parameter β = I PD / I PG Smaller, read noise margin relative to SNMR Figure 1 The SRAM's SNMR increases. In addition, SNMH remains relatively unchanged, while SNMW decreases slightly. SNMH, SNMW, and SNMR are more balanced, ultimately improving the SRAM's read and write capabilities.

[0048] Please refer to Figure 6 As an example, when L PGa =L PG W PGa =W PG / 2 o'clock, Figure 4 The SRAM of this embodiment shown is relative to Figure 1 The improvement in SRAM read / write capabilities is shown below:

[0049] (1) Reading current I Read (not in) Figure 6 (As shown in the table) Relatively unchanged, with a slight increase in standby current Istb (7.8% < 10%);

[0050] (2) SNMH remains relatively unchanged (not in) Figure 6 As shown in the table, SNMR increased significantly (15.3% > 10%), while SNMW decreased slightly (8.6% < 10%).

[0051] Clearly, the SNMH, SNMW, and SNMR in this embodiment are more balanced, enabling the SRAM to achieve sufficient read and write capabilities to meet the needs of higher-performance on-chip systems.

[0052] This embodiment also provides a system-on-a-chip, which includes SRAM as described in this embodiment.

[0053] In summary, the SRAM of this invention improves the read and write capabilities of SRAM by simply adding a set of access transistors to the basic storage cell structure of an existing 6T SRAM, without increasing process complexity or cost. The on-chip system of this invention achieves improved performance due to the use of the SRAM of this invention.

[0054] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. An SRAM, characterized in that, The SRAM has a storage array, and the smallest storage cell in the storage array includes: The first and second load transistors and the first and second drive transistors, the drain of the first load transistor, the drain of the first drive transistor, the gate of the second load transistor and the gate of the second drive transistor are all coupled to the first node, the gate of the first load transistor, the gate of the first drive transistor, the drain of the second load transistor and the drain of the second drive transistor are all coupled to the second node, the source of the first load transistor and the source of the second load transistor are all coupled to the first power supply, and the source of the first drive transistor and the source of the second drive transistor are all coupled to the second power supply. The first to fourth access transistors have their gates coupled to a first word line, the gates of the first and second access transistors are coupled to a second word line, the gates of the third and fourth access transistors are coupled to a second word line, the sources of the first and third access transistors are coupled to a first bit line, the drains of the first and third access transistors are coupled to a first node, the sources of the second and fourth access transistors are coupled to a second bit line, and the drains of the second and fourth access transistors are coupled to a second node.

2. The SRAM as described in claim 1, characterized in that, When the channel length of the third access transistor is the same as the channel length of the first access transistor, the channel width of the third access transistor is 1 / 3 to 1 / 2 of the channel width of the first access transistor.

3. The SRAM as described in claim 1, characterized in that, When the channel length of the fourth access transistor is the same as the channel length of the second access transistor, the channel width of the fourth access transistor is 1 / 3 to 1 / 2 of the channel width of the second access transistor.

4. The SRAM as claimed in claim 1, characterized in that, When performing a read operation on the smallest storage unit, both the first word line and the second word line are at a high level; when performing a write operation on the smallest storage unit, the first word line is at a high level and the second word line is at a low level.

5. The SRAM as described in any one of claims 1-4, characterized in that, The first to fourth access transistors, the first driving transistor, and the second driving transistor are all NMOS transistors, while the first load transistor and the second load transistor are both PMOS transistors.

6. The SRAM as claimed in claim 5, characterized in that, The first power source is the system power supply, and the second power source is ground.

7. The SRAM as claimed in claim 5, characterized in that, The SRAM also includes control circuitry and row address decoders, column address decoders, and sensitive amplifiers respectively coupled to the memory array and the control circuitry.

8. A system-on-a-chip, characterized in that, Includes SRAM as described in any one of claims 1-7.

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