High voltage protection circuit and circuit system thereof

Abstract

This application provides a high-voltage protection circuit, including a non-parasitic voltage-resistant transistor formed of a semiconductor structure and a trigger voltage reduction circuit. One end of the trigger voltage reduction circuit is electrically connected to the P-type doped region and the first N-type doped region of the semiconductor structure, and the other end of the trigger voltage reduction circuit is electrically connected to the polysilicon electrode of the semiconductor structure, used to reduce the reverse conduction voltage of the voltage-resistant transistor to a specific voltage value. When the voltage value of the high-voltage signal on the drain of the voltage-resistant transistor is greater than the specific voltage value, the voltage-resistant transistor will reverse conduct, providing a discharge path for the high-voltage signal to flow to the source of the voltage-resistant transistor.

Description

Technical Field

[0001] This invention relates to a high-voltage protection circuit and its circuit system, and more particularly to a high-voltage protection circuit and its circuit system that uses a semiconductor structure to form a withstand voltage transistor and uses a trigger voltage reduction circuit to reduce the reverse conduction voltage of the withstand voltage transistor. Background Technology

[0002] In high-voltage integrated circuit driver circuit applications, the circuit is divided into two blocks: a low-side circuit and a high-voltage side circuit. The design of the isolation structure for the high-voltage termination terminal (HJVT) is crucial in these two blocks. Besides meeting voltage withstand requirements, the isolation structure must also ensure that it does not interfere with the normal operation of the circuit. Signal transmission from the high-voltage gate driver can be achieved through a level shifting circuit implemented with high-voltage laterally diffused metal-oxide-semiconductor (LDMOS). LDMOS primarily boosts the signal output from the low-voltage side circuit and transmits it to the high-voltage circuit. However, to reduce chip area, these high-voltage integrated circuits typically prioritize self-protection and do not include additional electrostatic discharge (ESD) protection circuits. Generally, LDMOS has a very small width and cannot withstand large currents. When high-voltage ESD occurs, if the LDMOS itself is used as the discharge path, it may damage the LDMOS or its connected resistors.

[0003] Please refer to Figure 1 , Figure 1 It is a circuit diagram of a traditional circuit system. For example... Figure 1 As shown, circuit system 1 is a high-voltage integrated circuit. Circuit system 1 includes a low-voltage side circuit block 11 and a high-voltage side circuit block 12, which are connected by a high-voltage laterally diffused metal-oxide-semiconductor LN1 serving as a level shifting circuit. Low-voltage side circuit block 11 includes an electrostatic discharge (ESD) clamping circuit 111 and low-voltage side circuit 112, and uses voltage VCC as the supply voltage. High-voltage side circuit block 12 includes a driving circuit composed of a PMOS transistor P1 and an NMOS transistor N1 (i.e., the high-voltage side circuit here is a driving circuit) and a self-protection circuit composed of a resistor R1, a diode D1, and the ESD clamping circuit 121. High-voltage side circuit block 122 is electrically connected between voltage VB and voltage VS, and uses voltage VB as the supply voltage, where voltage VB is greater than voltage VCC. Circuit system 1 uses an isolation ring to isolate the low-voltage side circuit block 11 from the high-voltage side circuit block 12. The semiconductor structure of the isolation ring forms a parasitic reverse-biased diode HVJT_D. However, the reverse-biased diode HVJT_D has poor electrostatic discharge tolerance and usually cannot meet the 2000-volt requirement.

[0004] While another approach in the prior art is to modify the semiconductor structure with the parasitic reverse bias diode HVJT_D into a parasitic bipolar transistor to improve electrostatic discharge (ESD) tolerance, the width of the high-voltage laterally diffused metal-oxide-semiconductor (LN1) is too small, and the isolation ring needs to ensure sufficient withstand voltage. This results in the reverse conduction voltage of the parasitic bipolar transistor being greater than the original reverse conduction voltage of the high-voltage LN1. Consequently, the ESD discharge path still passes through the high-voltage LN1, potentially damaging the LN1 itself or / and its connected components. To ensure the ESD discharge path leads to the high-voltage termination, the reverse conduction voltage of the parasitic bipolar transistor at the high-voltage termination can be designed to be smaller than that of the high-voltage LN1. However, this approach results in insufficient withstand voltage of the parasitic bipolar transistor, affecting normal circuit operation, or leads to excessively large component area waste. Summary of the Invention

[0005] This invention provides a high-voltage protection circuit, comprising a voltage-resistant transistor and a trigger voltage reduction circuit. When the voltage value of the high-voltage signal at the drain of the voltage-resistant transistor exceeds a specific voltage value, a discharge path is provided for the high-voltage signal to flow from the drain of the voltage-resistant transistor to the source. The trigger voltage reduction circuit is electrically connected between the gate of the voltage-resistant transistor and ground voltage, and is used to reduce the reverse conduction voltage value of the voltage-resistant transistor to a specific voltage value. The voltage-resistant transistor is formed of a semiconductor structure, and the semiconductor structure includes a high-voltage N-well structure, a first epitaxial structure, a deep N-well structure, and a second epitaxial structure in the horizontal direction. The high-voltage N-type well structure includes a horizontally isolated and exposed P-type doped region and a first N-type doped region. One end of the trigger voltage reduction circuit is electrically connected to the P-type doped region and the first N-type doped region. The high-voltage N-type well structure and the first epitaxial structure together include an exposed polysilicon electrode. The deep N-type well structure includes an exposed second N-type doped region. The polysilicon electrode is horizontally isolated from the first N-type doped region and the second N-type doped region and is electrically connected to the other end of the trigger voltage reduction circuit. The second N-type doped region is horizontally isolated from the second epitaxial structure. The first N-type doped region is the source of the voltage-resistant transistor, the second N-type doped region is the drain of the voltage-resistant transistor, and the polysilicon electrode is the gate of the voltage-resistant transistor.

[0006] This invention provides a high-voltage protection circuit, comprising a semiconductor structure and a trigger voltage reduction circuit. The semiconductor structure has, in a horizontal direction, an exposed P-type doped region, a first N-type doped region, a polysilicon electrode, and a second N-type doped region sequentially formed. The P-type doped region and the first N-type doped region are horizontally isolated from each other, the first N-type doped region and the polysilicon electrode are horizontally isolated from each other, and the polysilicon electrode and the second N-type doped region are horizontally isolated from each other, thereby forming a non-parasitic voltage-degrading transistor. The first N-type doped region, the second N-type doped region, and the polysilicon electrode are respectively the source, drain, and gate of the voltage-degrading transistor. One end of the trigger voltage reduction circuit is electrically connected to the P-type doped region and the first N-type doped region, and the other end is electrically connected to the polysilicon electrode, used to reduce the reverse conduction voltage of the voltage-degrading transistor to a specific voltage value. When the voltage of the high-voltage signal on the drain of the voltage-resistant transistor is greater than a certain voltage value, the voltage-resistant transistor will conduct in reverse to provide a discharge path for the high-voltage signal to flow to the source of the voltage-resistant transistor.

[0007] This invention provides a circuit system comprising the aforementioned high-voltage protection circuit and a circuit to be protected, wherein the circuit is connected in parallel to the high-voltage protection circuit.

[0008] In summary, the high-voltage protection circuit provided by the present invention forms a voltage-resistant transistor through a semiconductor structure and reduces the reverse conduction voltage value of the voltage-resistant transistor through a trigger voltage reduction circuit. Therefore, it can solve the technical problem that the circuit to be protected may conduct in reverse before the voltage-resistant transistor HVJT_T.

[0009] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0010] The accompanying drawings are provided to enable those skilled in the art to further understand the invention and are incorporated in and constitute a part of the specification of the invention. The drawings illustrate exemplary embodiments of the invention and are used together with the specification to explain the principles of the invention.

[0011] Figure 1 It is a circuit diagram of a traditional circuit system.

[0012] Figure 2 This is a circuit diagram of the high-voltage protection circuit according to an embodiment of the present invention.

[0013] Figure 3A This is a circuit diagram of the circuit system according to an embodiment of the present invention.

[0014] Figure 3B yes Figure 3A A schematic diagram of the semiconductor structure of the withstand transistor in the high-voltage protection circuit.

[0015] Figure 4A This is a circuit diagram of a circuit system according to another embodiment of the present invention.

[0016] Figure 4B yes Figure 4A A schematic diagram of the semiconductor structure of the withstand transistor in the high-voltage protection circuit.

[0017] Figure 5A This is a circuit diagram of a circuit system according to another embodiment of the present invention.

[0018] Figure 5B yes Figure 5A A schematic diagram of the semiconductor structure of the withstand transistor in the high-voltage protection circuit.

[0019] The symbols indicated in the diagram are explained as follows: 1, 3-5 circuit system; 11 low-voltage side circuit block; 111, 121 electrostatic discharge clamping circuit; 112 low-voltage side circuit; 12 high-voltage side circuit block; 2 high-voltage protection circuit; 21 trigger voltage reduction circuit; HVJT_T withstand voltage transistor; HVJT_D reverse bias diode; P1, N1, N2 transistors; R1-R3 resistors; LN1 high-voltage lateral diffused metal-oxide semiconductor; VCC, VS, VB voltages; GND ground voltage; D1 diode; PS P-type substrate; HVPW high-voltage P-type well; NW1 first N-type well; NW2 second N-type well; FE1 first isolator; FE2 second isolator; FE3 third isolator; FE4 fourth isolator; FE5 fifth isolator; PP1 P-type doped region; NP1 first N-type doped region; NP2 second N-type doped region; PLY polycrystalline silicon electrode; NEPI1 first N-type epitaxial layer; NEPI2 second N-type epitaxial layer; DNW deep N-type well; NBL N-type buried layer. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same component reference numerals are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the following examples are not intended to limit the invention.

[0021] This invention provides a high-voltage protection circuit that primarily utilizes a semiconductor structure to form a high-voltage transistor capable of withstanding high voltages without parasitic behavior. This high-voltage transistor is an NMOS transistor, with its gate, source, and drain being a polysilicon electrode, a first N-type doped region, and a second N-type doped region, respectively. The semiconductor structure also includes a P-type doped region in the direction away from the polysilicon electrode from the first N-type doped region. To ensure sufficient electrostatic discharge tolerance of the high-voltage transistor, but without allowing other components (e.g., a high-voltage laterally diffused metal-oxide-semiconductor used as a level shifting circuit) to be reverse-biased before the high-voltage transistor is reverse-biased, this invention also includes a trigger voltage reduction circuit in the high-voltage protection circuit. One end of the trigger voltage reduction circuit is electrically connected to the first N-type doped region and the P-type doped region, and the other end is electrically connected to the polysilicon electrode. The trigger voltage reduction circuit is used to reduce the reverse conduction voltage of the high-voltage transistor to a specific voltage value.

[0022] Through the above approach, when the voltage value of the high-voltage signal exceeds a specific voltage value, the voltage-resistant transistor can be reverse-conducted before other components are reverse-conducted, thus making the voltage-resistant transistor a discharge path for the high-voltage signal and effectively protecting the components in the circuit system. Furthermore, since it eliminates the need to design a semiconductor structure for a voltage-resistant transistor with a lower withstand voltage (i.e., a lower reverse conduction voltage value) as in previous technologies, another beneficial effect of this invention is that it avoids the area waste caused by excessively large semiconductor structures.

[0023] First, please refer to Figure 2 , Figure 2 This is a circuit diagram of a high-voltage protection circuit according to an embodiment of the present invention. The high-voltage protection circuit 2 includes a voltage-resistant transistor HVJT_T formed through a semiconductor structure, capable of withstanding high voltage and non-parasitic behavior, and a trigger voltage reduction circuit 21, wherein the voltage-resistant transistor HVJT_T is an NMOS transistor. The drain of the voltage-resistant transistor HVJT_T is electrically connected to voltage VB, and the source of the voltage-resistant transistor HVJT_T is electrically connected to ground voltage GND. The two ends of the trigger voltage reduction circuit 21 are respectively electrically connected to the gate of the voltage-resistant transistor HVJT_T and ground voltage GND. The trigger voltage reduction circuit 21 can be implemented with a single resistor, or with a transistor and a resistor, and the present invention is not limited thereto.

[0024] In use, the high-voltage protection circuit 2 is connected in parallel with the circuit to be protected. The trigger voltage reduction circuit 21 causes the withstand voltage transistor HVJT_T to reduce its original reverse conduction voltage value to a specific voltage value, so that the withstand voltage transistor HVJT_T can be reverse-conducted before the circuit to be protected is reverse-conducted, thereby achieving the protection effect. In addition, in one embodiment, in the operating mode, the trigger voltage reduction circuit 21 is designed to make the withstand voltage transistor HVJT_T maintain its original reverse conduction voltage value, that is, maintain its original electrostatic discharge tolerance.

[0025] Please refer to Figure 3A , Figure 3A This is a circuit diagram of the circuit system according to an embodiment of the present invention. In this embodiment, the high-voltage protection circuit 2 is used to protect the high-voltage integrated circuit. Therefore, the circuit system 3 includes a low-voltage side circuit block 11, a high-voltage side circuit block 12, a high-voltage laterally diffused metal-oxide-semiconductor LN1 as a level shifting circuit, and the high-voltage protection circuit 2. The high-voltage protection circuit 2 is electrically connected between voltage VB and ground voltage GND, and is connected in parallel to the high-voltage integrated circuit. The low-voltage side circuit block 11 includes an electrostatic discharge clamping circuit 111 and a low-voltage side circuit 112 connected in parallel. The electrostatic discharge clamping circuit 111 and the low-voltage side circuit 112 are electrically connected between voltage VCC and ground voltage GND, and operate using voltage VCC as the supply voltage. In addition, the electrostatic discharge clamping circuit 111 is used to clamp the voltage, so that voltage VCC is clamped to achieve self-protection.

[0026] The gate of the high-voltage laterally diffused metal-oxide-semiconductor (LN1) is electrically connected to the low-voltage side circuit 112 to receive and boost the signal output from the low-voltage side circuit 112. The source of the high-voltage laterally diffused metal-oxide-semiconductor (LN1) is electrically connected to the ground voltage GND, and the drain of the high-voltage laterally diffused metal-oxide-semiconductor (LN1) is electrically connected to the high-voltage side circuit block 12 to send the boosted signal to the high-voltage side circuit block 12.

[0027] The high-voltage side circuit block 12 includes a driving circuit composed of a PMOS transistor P1 and an NMOS transistor N1 (i.e., the high-voltage side circuit here is a driving circuit) and a self-protection circuit composed of a resistor R1, a diode D1, and an electrostatic discharge clamping circuit 121. The source of the PMOS transistor P1 is electrically connected to the voltage VB, the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are electrically connected to each other and output a driving voltage, the source of the NMOS transistor N1 is electrically connected to a voltage VS less than the voltage VB, and the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are electrically connected to the drain of the high-voltage laterally diffused metal-oxide-semiconductor LN1 to receive the boost signal and determine the output voltage according to the boost signal. It should be noted that the above implementation of the high-voltage side circuit is only one embodiment of the present invention and is not intended to limit the present invention.

[0028] The two ends of resistor R1 are electrically connected to voltage VB (greater than voltage VCC) and the drain of high-voltage laterally diffused metal-oxide-semiconductor LN1, respectively. The cathode and anode of diode D1 are electrically connected to voltage VB and the drain of high-voltage laterally diffused metal-oxide-semiconductor LN1, respectively. Electrostatic discharge clamping circuit 121 is electrically connected between voltage VB and voltage VS. By clamping the voltage difference between voltage VB and voltage VS through electrostatic discharge clamping circuit 121, and through the action of resistor R1 and diode D1, self-protection can be achieved. Please note that the above-described self-protection circuit configuration and implementation is only one embodiment of the present invention and is not intended to limit the present invention.

[0029] The drain and source of the voltage-resistant transistor HVJT_T are electrically connected to voltage VB and ground voltage GND, respectively. When the voltage value of the high-voltage signal at the drain of the voltage-resistant transistor HVJT_T exceeds a certain voltage value, the voltage-resistant transistor HVJT_T will conduct in reverse, and the high-voltage signal used to provide a discharge path to the drain of the voltage-resistant transistor HVJT_T will flow to the source of the voltage-resistant transistor HVJT_T. The trigger voltage buck circuit 21 is electrically connected between the gate of the voltage-resistant transistor HVJT_T and the ground voltage GND, and is used to reduce the reverse conduction voltage value of the voltage-resistant transistor HVJT_T to a certain voltage value.

[0030] Please refer to Figure 3B , Figure 3B yes Figure 3AA schematic diagram of the semiconductor structure of the withstand transistor in the high-voltage protection circuit is shown. The withstand transistor HVJT_T is formed by a semiconductor structure, which, from left to right in the horizontal direction, includes a high-voltage N-type well structure, a first epitaxial structure, a deep N-type well structure, and a second epitaxial structure. The high-voltage N-type well structure includes a horizontally isolated and exposed P-type doped region PP1 and a first N-type doped region NP1, and one end of the trigger voltage reduction circuit 21 is electrically connected to the P-type doped region PP1 and the first N-type doped region NP1. The high-voltage N-type well structure and the first epitaxial structure together include an exposed polysilicon electrode PLY. The deep N-type well structure includes an exposed second N-type doped region NP2. The polysilicon electrode PLY is horizontally isolated from the first N-type doped region NP1 and the second N-type doped region NP2, and is electrically connected to the other end of the trigger voltage reduction circuit 21. The second N-type doped region NP2 is horizontally isolated from the second epitaxial structure. The first N-type doped region NP1 is the source of the voltage-depleting transistor HVJT_T, the second N-type doped region NP2 is the drain of the voltage-depleting transistor HVJT_T, and the polysilicon electrode PLY is the gate of the voltage-depleting transistor HVJT_T. Furthermore, the semiconductor structure further includes a P-type substrate PS, wherein the high-voltage N-type well structure, the first epitaxial structure, the deep N-type well structure, and the second epitaxial structure are formed on the P-type substrate PS.

[0031] The detailed structure of the high-voltage N-type well is described below. The high-voltage N-type well structure includes a high-voltage P-type well (HVPW), a first N-type well (NW1), a first isolation element (FE1), a second isolation element (FE2), a third isolation element (FE3), a P-type doped region (PP1), a first N-type doped region (NP1), and a portion of a polycrystalline silicon electrode (PLY). The high-voltage P-type well (HVPW) is formed on a P-type substrate (PS). The first N-type well (NW1) is formed within the high-voltage P-type well (HVPW), and the P-type doped region (PP1) and the first N-type doped region (NP1) are formed within and exposed in the first N-type well (NW1). A portion of the polycrystalline silicon electrode (PLY) is formed on and exposed in the high-voltage P-type well (HVPW). The first isolation element (FE1) is formed on top of the first N-type well (NW1) and located to the left of the P-type doped region (PP1) in the horizontal direction. The second isolation element (FE2) is formed on top of the first N-type well (NW1) and located between the right side of the P-type doped region (PP1) in the horizontal direction and the left side of the first N-type doped region (NP1) in the horizontal direction. The third separator FE3 is formed on the first N-type well NW1 and is located between the right side of the first N-type doped region NP1 in the horizontal direction and the left side of the polycrystalline silicon electrode PLY in the horizontal direction.

[0032] The first epitaxial structure is described in detail below. The first epitaxial structure includes another portion of a polysilicon electrode PLY, a first N-type epitaxial layer NEPI1, and a portion of a fourth isolation member FE4. The first N-type epitaxial layer NEPI1 is horizontally adjacent to the high-voltage P-type well HVPW and located on a P-type substrate PS. The other portion of the polysilicon electrode PLY is located above the first N-type epitaxial layer NEPI1. The polysilicon electrode PLY is horizontally located between the right side of the third isolation member FE3 and the left side of the fourth isolation member FE4, and a portion of the fourth isolation member FE4 is formed on the first N-type epitaxial layer NEPI1.

[0033] The deep N-type well structure is described in detail below. The deep N-type well structure includes a second N-type doped region PP2, a deep N-type well DNW, a second N-type well NW2, a portion of a fourth spacer FE4, a portion of a fifth spacer FE5, and a portion of an N-type buried layer NBL. The deep N-type well DNW is located on a P-type substrate PS and is horizontally adjacent to the first N-type epitaxial layer NEPI1. The second N-type well NW2 is formed within the deep N-type well DNW. The second N-type doped region NP2 is formed within and exposed in the second N-type well NW2. A portion of the fourth spacer FE4 is formed above the deep N-type well DNW and the second N-type well NW2. A portion of the fifth spacer FE5 is formed above the deep N-type well DNW and the second N-type well NW2. The second N-type doped region NP2 is horizontally located between the right side of the fourth spacer FE4 and the left side of the fifth spacer FE5. Part of the N-type buried layer NBL is located above the P-type substrate PS and below the deep N-type well DNW, and is adjacent to the right side of the deep N-type well DNW in the horizontal direction.

[0034] The second epitaxial structure is described in detail below. The second epitaxial structure includes another portion of the fifth spacer FE5, the second epitaxial layer NEPI2, and another portion of the N-type buried layer NBL. The other portion of the N-type buried layer NBL is located above the P-type substrate PS and below the second epitaxial layer NEPI2. The other portion of the fifth spacer FE5 is located above the second epitaxial layer NEPI2, and the second epitaxial layer NEPI2 is horizontally adjacent to the right side of the deep N-type well DNW.

[0035] The semiconductor structure implementation of the aforementioned withstand voltage transistor HVJT_T is only one embodiment of the present invention, and other types of semiconductor structures may also be used to implement the present invention. As long as the semiconductor structure can sequentially form exposed P-type doped region PP1, first N-type doped region NP1, polysilicon electrode PLY, and second N-type doped region NP2 in the horizontal direction, and through appropriate design, the P-type doped region PP1 and the first N-type doped region NP1 are horizontally isolated from each other, the first N-type doped region NP1 and the polysilicon electrode PLY are horizontally isolated from each other, and the polysilicon electrode PLY and the second N-type doped region NP2 are horizontally isolated from each other, the non-parasitic withstand voltage transistor HVJT_T of the present invention can be realized.

[0036] In the electrostatic discharge (ESD) test mode, the trigger voltage reduction circuit 21 can reduce the reverse conduction voltage of the withstand voltage transistor HVJT_T, thus lowering it to a specific voltage value. Furthermore, when there is a high-voltage signal at the drain of the withstand voltage transistor HVJT_T, it can be reverse-conducted earlier than other components, thus providing protection. In one embodiment, the trigger voltage reduction circuit 21 can also be designed not to reduce the reverse conduction voltage of the withstand voltage transistor HVJT_T in the operating mode, thereby maintaining the reverse conduction voltage of the withstand voltage transistor HVJT_T, i.e., keeping its ESD tolerance unchanged.

[0037] Please refer to Figure 4A and Figure 4B , Figure 4A This is a circuit diagram of a circuit system according to another embodiment of the present invention, and Figure 4B yes Figure 4A A schematic diagram of the semiconductor structure of the withstand transistor in the high-voltage protection circuit. Figure 4A In the high-voltage protection circuit 2 of circuit system 4, the trigger voltage reduction circuit 21 is implemented with a resistor R2, and the two ends of the resistor R2 are electrically connected to the ground voltage GND and the gate of the withstand voltage transistor HVJT_T, respectively. Correspondingly, in Figure 4B In this embodiment, one end of resistor R2 is electrically connected to the polysilicon electrode PLY, and the other end of resistor R2 is electrically connected to the P-type doped region NP2 and the first N-type doped region NP1. In this embodiment, the reverse conduction voltage of HVJT_T is reduced regardless of whether it is in electrostatic testing mode or operating mode.

[0038] Please refer to Figure 5A and Figure 5B , Figure 5A This is a circuit diagram of a circuit system according to another embodiment of the present invention, and Figure 5B yes Figure 5A A schematic diagram of the semiconductor structure of the withstand transistor in the high-voltage protection circuit. Figure 5AThe trigger voltage reduction circuit 21 in the high-voltage protection circuit 2 of circuit system 5 is implemented using a resistor R3 and a transistor N2. The gate of transistor N2 is electrically connected to one end of resistor R3, the drain of transistor N2 is electrically connected to the gate of the withstand voltage transistor HVJT_T, and the source of transistor N2 is electrically connected to ground voltage GND. Correspondingly, in Figure 5B In the transistor N2, the drain is electrically connected to the polysilicon electrode PLY, and the source is electrically connected to the P-type doped region PP1 and the first N-type doped region NP1. In electrostatic discharge (ESD) mode, the other end of resistor R3 is floating, thus reducing the reverse conduction voltage of the withstand voltage transistor HVJT_T; and in operating mode, the other end of resistor R3 is electrically connected to voltage VCC, so the reverse conduction voltage of HVJT_T remains almost constant.

[0039] In summary, the high-voltage protection circuit provided by this invention avoids the technical problem of the circuit to be protected conducting in reverse before the voltage-resistant transistor, thus effectively protecting the circuit. In one embodiment, it can also be designed to maintain the voltage-resistant transistor's tolerance to electrostatic discharge during operation. Furthermore, compared to existing technologies, the high-voltage protection circuit of this invention avoids the waste of area caused by excessively large semiconductor structures. In addition, the above-described architecture does not require an additional photomask and can be implemented using existing processes.

[0040] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A high-voltage protection circuit, characterized in that, The high-voltage protection circuit includes: A voltage-resistant transistor, which, when the voltage value of the high-voltage signal at the drain of the voltage-resistant transistor is greater than a certain voltage value, provides a discharge path for the high-voltage signal at the drain of the voltage-resistant transistor to flow to the source of the voltage-resistant transistor; and A trigger voltage reduction circuit is electrically connected between the gate of the withstand voltage transistor and the ground voltage to reduce the reverse conduction voltage of the withstand voltage transistor to the specific voltage value. The voltage-resistant transistor is formed of a semiconductor structure, and the semiconductor structure includes a high-voltage N-type well structure, a first epitaxial structure, a deep N-type well structure, and a second epitaxial structure in the horizontal direction. The high-voltage N-type well structure includes a P-type doped region and a first N-type doped region that are isolated and exposed in the horizontal direction. One end of the trigger voltage reduction circuit is electrically connected to the P-type doped region and the first N-type doped region. The high-voltage N-type well structure and the first epitaxial structure together include an exposed polysilicon electrode. The deep N-type well structure includes an exposed second N-type doped region. The polysilicon electrode is isolated from the first N-type doped region and the second N-type doped region in the horizontal direction and is electrically connected to the other end of the trigger voltage reduction circuit. The second N-type doped region is isolated from the second epitaxial structure in the horizontal direction. The first N-type doped region is the source of the voltage-resistant transistor, the second N-type doped region is the drain of the voltage-resistant transistor, and the polysilicon electrode is the gate of the voltage-resistant transistor.

2. The high-voltage protection circuit as described in claim 1, characterized in that, The trigger voltage reduction circuit includes a resistor, one end of which is electrically connected to the polysilicon electrode, and the other end of which is electrically connected to the P-type doped region and the first N-type doped region.

3. The high-voltage protection circuit as described in claim 1, characterized in that, The trigger voltage buck circuit includes a transistor and at least one resistor, wherein the gate of the transistor is electrically connected to one end of the resistor, the drain of the transistor is electrically connected to the polysilicon electrode, and the source of the transistor is electrically connected to the P-type doped region and the first N-type doped region.

4. The high-voltage protection circuit as described in claim 3, characterized in that, In an electrostatic test mode, the other end of the resistor is floating, and in the operating mode, the other end of the resistor is electrically connected to the voltage.

5. The high-voltage protection circuit as described in claim 1, characterized in that, The high-voltage N-type well structure includes a high-voltage P-type well, a first N-type well, a first isolator, a second isolator, a third isolator, the P-type doped region, the first N-type doped region, and a portion of the polysilicon electrode. The high-voltage P-type well is formed on a P-type substrate. The first N-type well is formed within the high-voltage P-type well. The P-type doped region and the first N-type doped region are formed within and exposed in the first N-type well. The portion of the polysilicon electrode is formed on and exposed in the high-voltage P-type well. The first isolator is formed above the first N-type well and located on one side of the P-type doped region in the horizontal direction. The second isolator is formed above the first N-type well and located between the other side of the P-type doped region in the horizontal direction and one side of the first N-type doped region in the horizontal direction. The third isolator is formed on the first N-type well and located between the other side of the first N-type doped region in the horizontal direction and one side of the polysilicon electrode in the horizontal direction.

6. The high-voltage protection circuit as described in claim 5, characterized in that, The first epitaxial structure includes another portion of the polysilicon electrode, a first N-type epitaxial layer, and a portion of the fourth isolation member. The first N-type epitaxial layer is adjacent to the high-voltage P-type well in the horizontal direction and is located on the P-type substrate. The other portion of the polysilicon electrode is located above the first N-type epitaxial layer. The polysilicon electrode is located between the third isolation member and the fourth isolation member in the horizontal direction. The portion of the fourth isolation member is formed on the first N-type epitaxial layer.

7. The high-voltage protection circuit as described in claim 6, characterized in that, The deep N-type well structure includes a second N-type doped region, a deep N-type well, a second N-type well, another portion of the fourth isolator, a portion of the fifth isolator, and a portion of the N-type buried layer. The deep N-type well is located on the P-type substrate and is adjacent to the first N-type epitaxial layer in the horizontal direction. The second N-type well is formed in the deep N-type well, and the second N-type doped region is formed in the second N-type well and exposed. The other portion of the fourth isolator is formed above the deep N-type well and the second N-type well. The portion of the fifth isolator is formed above the deep N-type well and the second N-type well. The second N-type doped region is located between the fourth and fifth isolators in the horizontal direction. The portion of the N-type buried layer is located above the P-type substrate and below the deep N-type well, and is adjacent to the deep N-type well in the horizontal direction.

8. The high-voltage protection circuit as described in claim 7, characterized in that, The second epitaxial structure includes another portion of the fifth spacer, the second epitaxial layer, and another portion of the N-type buried layer, wherein the other portion of the N-type buried layer is located above the P-type substrate and below the second epitaxial layer, the other portion of the fifth spacer is located above the second epitaxial layer, and the second epitaxial layer is adjacent to the deep N-type well in the horizontal direction.

9. A high-voltage protection circuit, characterized in that, The high-voltage protection circuit includes: A semiconductor structure has, in a horizontal direction, sequentially formed an exposed P-type doped region, a first N-type doped region, a polysilicon electrode, and a second N-type doped region. The P-type doped region and the first N-type doped region are isolated from each other in the horizontal direction. The first N-type doped region and the polysilicon electrode are isolated from each other in the horizontal direction. The polysilicon electrode and the second N-type doped region are also isolated from each other in the horizontal direction, thereby forming a non-parasitic voltage-degrading transistor. The first N-type doped region, the second N-type doped region, and the polysilicon electrode are respectively the source, drain, and gate of the voltage-degrading transistor. A trigger voltage reduction circuit is provided, one end of which is electrically connected to the P-type doped region and the first N-type doped region, and the other end of which is electrically connected to the polysilicon electrode, for reducing the reverse conduction voltage of the withstand voltage transistor to a specific voltage value. When the voltage value of the high-voltage signal on the drain of the voltage-resistant transistor is greater than the specific voltage value, the voltage-resistant transistor will conduct in reverse to provide a discharge path for the high-voltage signal to flow to the source of the voltage-resistant transistor.

10. A circuit system, characterized in that, The high-voltage protection circuit includes: The high-voltage protection circuit as described in any one of claims 1 to 9; The circuit to be protected is connected in parallel to the high-voltage protection circuit.

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