Data detection methods, equipment and communication systems

Abstract

This application relates to the field of communications and discloses a data detection method, device, and communication system. The method includes a first detection circuit and a second detection circuit receiving a first input signal; the first detection circuit acquires a first output signal based on the first input signal; the first output signal includes the first input signal and a first device bus connection method; the first detection circuit sends the first output signal to a data processing circuit; and the second detection circuit generates a blocking signal, causing the second detection circuit to be in a non-operating state. Specifically, the connection method between the first detection circuit and the connection port is the same as the connection method between the second device and the connection port, while the connection method between the second detection circuit and the connection port is different. Based on this, blocking signals are continuously generated in the detection circuit for abnormal bus relationships, preventing the output of incorrect bus connection methods to subsequent circuit modules and achieving accurate determination of the bus connection method.

Description

Technical Field

[0001] This application relates to the field of communications, specifically to a data detection method, device, and communication system. Background Technology

[0002] As the application requirements of RF front-end devices (power amplifiers, low-noise amplifiers, filters, etc.) become increasingly widespread, the complex control of these devices is also becoming more challenging. Therefore, the Mobile Industry Processor Interface (MIPI) has proposed an RFFE (RF Front-End) bus interface to connect multiple front-end devices to other front-end modules. A single RFFE bus can support one master device and up to 15 slave devices. When the master and slave devices communicate, each slave device detects the signals sent by the master device to obtain its bus connection mode and matches it with the bus connection mode corresponding to the slave device address (USID) in the 13-bit command frame sent by the master device. If the bus connection mode of the USID in the 13-bit command frame sent by the master device is the same as that of the slave device, the slave device receives and processes the data sent by the master device. This results in data that should only need to be processed by one slave device being processed by two slave devices. Therefore, the connection mode between different slave devices and the master device can be changed.

[0003] In some solutions, slave devices determine their bus connection type by detecting the SSC signal. However, if multiple slave devices determine their connection type based on the SSC signal to be the same as the bus connection type in the 13-bit command frame, all slave devices will execute the same 13-bit command frame, resulting in wasted resources.

[0004] To address the resource waste issue in the aforementioned solutions, some approaches involve using two detection circuits with different connection methods within the slave device to detect the 13-bit command frame and determine its bus connection mode. While this approach avoids the resource waste problem mentioned earlier by executing the same 13-bit command frame, it suffers from several drawbacks. When the 13-bit command frame sent by the master device is interfered with during transmission, resulting in data distortion and a frame that does not meet data characteristics, the correct detection circuit cannot determine the slave device's bus connection mode based on the 13-bit command frame. The incorrect detection circuit, upon receiving a certain number of subsequent pulses, will re-evaluate the slave device's bus connection mode and output an incorrect connection mode, thus affecting the accuracy of the bus connection mode determination. Summary of the Invention

[0005] In view of this, embodiments of this application provide a data detection method, device, and communication system. By setting two detection circuits in a first device (the first device mentioned in this application can be the slave device in this embodiment) to detect 13-bit command frames to obtain the bus connection mode of the slave device, the detection circuit for correct bus connection mode executes the bus relationship judgment process of the first device normally during the detection process, while the detection circuit for incorrect bus connection mode continuously generates SSC2 signals (blocking signals) to block the detection process of the error detection circuit. This avoids outputting incorrect bus connection mode to subsequent circuit modules and avoids redundant processing of data sent by the second device (master device) by the first device (slave device).

[0006] In a first aspect, embodiments of this application provide a data detection method, the method comprising: using a first device, the first device including a connection port, a data detection device, and a data processing circuit, the data detection device including a first detection circuit and a second detection circuit, wherein the connection method of the first detection circuit to the first device and the connection method of the connection port are the same as those of the second device, and the connection method of the second detection circuit to the master device and the connection method of the connection port to the second device are different; the first detection circuit and the second detection circuit receive a first input signal; the first detection circuit acquires a first output signal based on the first input signal; the first output signal includes the first input signal and the bus connection method of the slave device; the first detection circuit sends the first output signal to the data processing circuit; the second detection circuit generates a blocking signal, the blocking signal being used to put the second detection circuit into a non-operating state.

[0007] In this application, by blocking the detection process of the second detection circuit (error detection circuit), when the first detection circuit (correct detection circuit) fails to output the correct bus connection method judgment result, the second detection circuit will not perform the judgment again and output the incorrect bus connection method judgment result, thereby achieving accurate judgment of the bus connection method.

[0008] In one possible implementation of the first aspect described above, the first detection circuit includes a first instruction judgment unit; the first instruction judgment unit acquires a first output signal based on a first input signal.

[0009] It is understandable that the instruction judgment unit inside the first detection circuit that detects the correct bus connection method receives a 13-bit command frame and determines the bus connection method of the slave device based on the 13-bit command frame.

[0010] In one possible implementation of the first aspect described above, the first instruction determination unit obtains the first output signal based on the first input signal, and the first instruction determination unit outputs the first output signal when it determines that the first input signal meets the data characteristics.

[0011] It is understandable that the instruction judgment unit inside the first detection circuit that determines the bus connection mode of the first device determines the bus connection mode of the first device. Then, after the judgment circuit inside the instruction judgment unit determines that the data characteristics of the 13-bit command frame are correct, the 13-bit command frame and the judgment result of the bus connection mode are output to the data processing circuit.

[0012] In one possible implementation of the first aspect described above, the data characteristics include that the parity bit of the first input signal is correct and that the command sequence of the first input signal is consistent with a preset sequence.

[0013] In one possible implementation of the first aspect above, the first detection circuit further includes a first start signal detection unit, which further includes: the first start signal detection unit generates a start signal based on the high and low level changes of the first input signal, the start signal controls the normal detection process of the first detection circuit to be executed normally, and controls the first detection circuit to return to the default state after the first detection circuit ends the detection process.

[0014] It is understandable that after determining that the first detection circuit is a detection circuit with a correct bus connection, the SSC signal detection unit inside the first detection circuit generates the SSC1 signal (start signal), and the first detection circuit starts detection. The first detection circuit performs normal detection and judgment on the 13-bit command frame, that is, the first detection circuit is in normal working state.

[0015] In one possible implementation of the first aspect described above, the second detection circuit includes a second start signal detection unit; the second detection circuit generates a blocking signal by: the second start signal detection unit receiving a first input signal and generating a blocking signal based on the high / low level changes of the first input signal. The second start signal detection unit in the second detection circuit continuously generates an SSC2 signal during the detection process to block the detection process, preventing the second detection circuit from executing the complete detection procedure.

[0016] It is understandable that after determining that the second detection circuit is a detection circuit with an incorrect bus connection method, the SSC signal detection unit inside the second detection circuit continuously generates SSC2 signals (blocking signals) to block the detection and judgment of the 13-bit command frame by the second detection circuit, so that the second detection circuit cannot execute the complete detection process.

[0017] By blocking the operation of the error detection circuit, when the first detection circuit with a correct bus connection method cannot output the correct bus connection method judgment result, the second detection circuit with an incorrect bus connection method will not perform judgment again and output the incorrect bus connection method judgment result due to a certain number of subsequent pulses, thereby achieving accurate judgment of the bus connection method.

[0018] In one possible implementation of the first aspect described above, the second detection circuit includes a second instruction judgment unit; after the data processing circuit receives the first output signal, the first instruction judgment unit resets the first start signal generation circuit; and the second instruction judgment unit resets the second start signal generation circuit.

[0019] It is understandable that after the first bus relationship detection process of the first detection circuit with the correct bus connection mode is completed, the SSC signal detection unit of the first detection circuit controls the SSC signal to reset, so as to ensure that the SSC2 signal generated in the previous detection process will not affect the next bus connection mode judgment process.

[0020] In one possible implementation of the first aspect described above, the connection port includes a first clock signal terminal and a first data signal terminal; the first detection circuit includes a second clock signal terminal and a second data signal terminal; the second detection circuit includes a third clock signal terminal and a third data signal terminal; and the second device includes a fourth clock signal terminal and a fourth data signal terminal. The connection method between the first detection circuit and the connection port is the same as the connection method between the second device and the connection port. The connection method between the second detection circuit and the connection port is different from the connection method between the second device and the connection port, including: the first clock signal terminal is connected to the fourth clock signal terminal, and the first data signal terminal is connected to the fourth data signal terminal; the second clock signal terminal is connected to the fourth clock signal terminal, and the second data signal terminal is connected to the fourth data signal terminal; the third clock signal terminal is connected to the fourth data signal terminal, and the third data signal terminal is connected to the fourth clock signal terminal.

[0021] Secondly, embodiments of this application provide a device, which is a first device. The first device includes a connection port, a data detection device, and a data processing circuit. The data detection device includes a first detection circuit and a second detection circuit. The connection method between the first detection circuit and the first device, and the connection method between the connection port and the second device are the same. The connection method between the second detection circuit and the first device, and the connection method between the connection port and the second device are different. The first detection circuit is used to receive a first input signal. The second detection circuit is used to receive the first input signal. The first detection circuit is used to obtain a first output signal based on the first input signal. The first output signal includes the first input signal and the bus connection method of the first device. The first detection circuit is used to send the first output signal to the data processing circuit. The second detection circuit is used to generate a blocking signal, which is used to make the second detection circuit non-operating.

[0022] It is understandable that the first device is the slave device and the second device is the master device. The bus connection methods between different slave devices and master devices are different. The master device is responsible for sending 13-bit command frames and other data to the slave devices.

[0023] In one possible implementation of the second aspect described above, the first detection circuit includes an instruction determination unit; the first instruction determination unit is configured to acquire a first output signal based on a first input signal. The first instruction determination unit is configured to output the first output signal when it is determined that the first input signal satisfies the data characteristics.

[0024] In one possible implementation of the second aspect above, the connection port includes a first clock signal terminal and a first data signal terminal, wherein the first clock signal terminal is used to connect to the clock signal terminal of the second device, and the first data signal terminal is used to connect to the data signal terminal of the second device; the first detection circuit includes a second clock signal terminal and a second data signal terminal, wherein the second clock signal terminal is used to connect to the clock signal terminal of the second device, and the second data signal terminal is used to connect to the data signal terminal of the second device; the second detection circuit includes a third clock signal terminal and a third data signal terminal, wherein the third clock signal terminal is used to connect to the data signal terminal of the second device, and the third data signal terminal is used to connect to the clock signal terminal of the second device.

[0025] Thirdly, embodiments of this application provide a communication system, including: a second device and at least two first devices, wherein the second device sends a first input signal to the first devices. Attached Figure Description

[0026] Figure 1A According to some embodiments of this application, a schematic diagram of an RFFE bus interface connection is shown;

[0027] Figure 1B According to some embodiments of this application, a schematic diagram of an RFFE bus interface connection is shown;

[0028] Figure 2 According to some embodiments of this application, a flowchart for determining the bus connection mode of a slave device is shown;

[0029] Figure 3 According to some embodiments of this application, a schematic diagram of a detection circuit from a device is shown;

[0030] Figure 4A According to some embodiments of this application, a schematic diagram of the structure of an SSC detection unit is shown;

[0031] Figure 4B According to some embodiments of this application, a schematic diagram of another SSC detection unit is shown;

[0032] Figure 5A According to some embodiments of this application, a timing logic diagram of an SSC detection unit is shown;

[0033] Figure 5BAccording to some embodiments of this application, a timing logic diagram of another SSC detection unit is shown;

[0034] Figure 6 According to some embodiments of this application, a schematic diagram of the structure of an instruction judgment subunit is shown;

[0035] Figure 7A According to some embodiments of this application, a schematic diagram of an RFFE bus interface connection is shown;

[0036] Figure 7B According to some embodiments of this application, a schematic diagram of the structure of a data detection device is shown. Detailed Implementation

[0037] The illustrative embodiments of this application include, but are not limited to, data detection methods, devices, and communication systems.

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, some embodiments of this application will be described below in conjunction with the accompanying drawings and specific implementation methods.

[0039] It is understood that the data detection method of this application can be applied to radio frequency chips in devices such as mobile phones and laptops, and is not limited to these applications.

[0040] Figure 1A and Figure 1B The examples illustrate scenarios where two slave devices and one master device are connected to a single RFFE bus. Specifically, as shown... Figure 1A As shown, a master device 10, a slave device 11, and a slave device 12 are connected to the RF bus. The clock and data terminals of the master device 10 are connected to the clock and data terminals of the slave device 11, respectively, and the clock and data terminals of the master device 10 are connected to the clock and data terminals of the slave device 12, respectively. In other words, the bus connections of the two slave devices are corresponding connections. Figure 1B As shown, the clock and data terminals of the master device 10 are connected to the clock and data terminals of the slave device 11, respectively. The clock and data terminals of the master device 10 are cross-connected to the clock and data terminals of the slave device 12, respectively. In other words, the bus connection methods of the two slave devices are different.

[0041] It is understood that in this application, the slave device can be the first device mentioned in the embodiments of this application, and the master device can be the second device mentioned in this application.

[0042] As mentioned earlier, in some schemes, slave devices determine their bus connection mode by detecting the SSC signal. However, if multiple slave devices determine their connection mode based on the SSC signal to be the same as the bus connection mode in the 13-bit command frame, then all slave devices will execute the same 13-bit command frame, resulting in wasted resources.

[0043] To address the resource waste issue in the aforementioned solutions, some approaches involve using two detection circuits with different connection methods within the slave device to detect the 13-bit command frame and determine its bus connection mode. While this approach avoids the resource waste problem mentioned earlier by executing the same 13-bit command frame, it suffers from several drawbacks. When the 13-bit command frame sent by the master device is interfered with during transmission, resulting in data distortion and a frame that does not meet data characteristics, the correct detection circuit cannot determine the slave device's bus connection mode based on the 13-bit command frame. The incorrect detection circuit, upon receiving a certain number of subsequent pulses, will re-evaluate the slave device's bus connection mode and output an incorrect connection mode, thus affecting the accuracy of the bus connection mode determination.

[0044] In view of the above, some embodiments of this application propose a data detection method for use in a first device. The first device includes a connection port, a data detection device, and a data processing circuit. The data detection device includes a first detection circuit and a second detection circuit. The connection method between the first detection circuit and the connection port is the same as the connection method between the second device and the connection port, while the connection method between the second detection circuit and the connection port is different. The detection method includes: setting the first detection circuit and the second detection circuit in the slave device; the first detection circuit and the second detection circuit receiving a first input signal; and then the first detection circuit acquiring a first output signal based on the first input signal. The first output signal includes the first input signal and the bus connection method of the first device. The first detection circuit sends the first output signal to the data processing circuit, and the second detection circuit generates a blocking signal to disable the second detection circuit.

[0045] Based on the above scheme, the first detection circuit with correct bus connection will normally execute the bus relationship judgment process for the slave device during the detection process, while the second detection circuit with incorrect bus connection will continuously generate blocking signals to block the detection process of the second detection circuit. This avoids outputting incorrect bus connection information to subsequent circuit modules, thus achieving accurate determination of the bus connection method.

[0046] The data detection methods mentioned in the embodiments of this application are described below. Figure 2According to an embodiment of this application, a flowchart of a data detection method is shown, the method comprising:

[0047] S101: The first device receives the first input signal sent by the second device.

[0048] The first device mentioned in the embodiments of this application can be a slave device, the second device mentioned in this application can be a master device, and the first input signal can be a 13-bit command frame.

[0049] For example, Figure 1B In this process, the master device 10 sends a 13-bit command frame to the slave devices 11 and 12 via the clock and data terminals, and the slave devices 11 and 12 respectively receive the 13-bit command frame sent by the master device 10.

[0050] S102: The first detection circuit and the second detection circuit in the first device receive the first input signal.

[0051] In some embodiments, after the slave device receives a 13-bit command frame, the first detection circuit and the second detection circuit also receive a 13-bit command frame and detect the bus connection mode of the slave device through the 13-bit command frame.

[0052] For example, Figure 3 In the process, when a 13-bit command frame is received from device 31, the first detection circuit 312 and the second detection circuit 313 inside device 31 respectively detect the 13-bit command frame and determine the bus connection mode of device 31.

[0053] S103: The first detection circuit in the first device acquires the first output signal based on the first input signal and sends the first output signal to the data processing circuit.

[0054] In some embodiments, if the bus connection mode determined by the first detection circuit is correct based on the 13-bit command frame, then the first detection circuit is a bus connection mode correct detection circuit. The first detection circuit includes a first instruction judgment unit, which outputs a first output signal when it determines that the first input signal meets the data characteristics. The first detection circuit also includes a first start signal detection unit, which generates a start signal based on the high / low level changes of the first input signal. The start signal is used to maintain the first detection circuit in normal operating condition. Furthermore, the first instruction judgment unit can obtain the first output signal based on the first input signal; that is, the first instruction judgment unit can send the bus connection mode of the slave device obtained from the 13-bit command frame to the data processing circuit.

[0055] It is understood that data characteristics include the correctness of the parity check bit of the first input signal and the consistency between the command sequence of the first input signal and the preset sequence, etc., which are not limited here.

[0056] For example, Figure 3 In the process, the first detection circuit 312 of the slave device 31 determines that the bus connection mode of the slave device 31 is a corresponding connection, and the second detection circuit 313 determines that the bus connection mode of the slave device 31 is a cross connection. At this time, based on the 13-bit command frame, it is determined that the bus connection mode corresponding to the 13-bit command frame is a corresponding connection. Therefore, it can be determined that the first detection circuit 312 is a detection circuit with a correct bus connection mode, while the second detection circuit 313 is a detection circuit with an incorrect bus connection mode. Subsequently, the first start signal detection unit 3121 inside the first detection circuit 312 with a correct bus connection mode generates an SSC1 signal to ensure that the first detection circuit 312 works normally. The first detection circuit 312 can send the 13-bit command frame and the bus connection mode (corresponding connection) of the slave device 31 obtained based on the 13-bit command frame to the data processing circuit.

[0057] S104: The second detection circuit in the first device generates a blocking signal, causing the second detection circuit to be in a non-operating state.

[0058] In some embodiments, if the bus connection method determined by the second detection circuit is incorrect based on the 13-bit command frame, then the second detection circuit is a bus connection method error detection circuit. The second detection circuit includes a second start signal detection unit, which generates a blocking signal to shut down the working process of the second detection circuit.

[0059] For example, Figure 3 In the second detection circuit 313 with incorrect bus connection, the second start signal detection unit 3131 generates an SSC2 signal to ensure that the second detection circuit 313 stops detection.

[0060] It is understood that the second detection circuit includes a second start signal detection unit; the second detection circuit generates a blocking signal. Specifically, the second start signal detection unit receives the first input signal and generates a blocking signal based on the high and low level changes of the first input signal.

[0061] It is understood that a detection process ends when the first detection circuit, acting as a correct detection circuit, sends the first output signal to the data processing circuit, and the second detection circuit, acting as an error detection circuit, has stopped its detection process. At this time, the first instruction judgment unit of the first detection circuit resets the first detection circuit, and the second instruction judgment unit of the second detection circuit resets the second detection circuit, ensuring that the previous blocking signal will not affect the next time the master device sends the first input signal to the slave device, allowing the first and second detection circuits of the slave device to operate normally.

[0062] Based on some embodiments of this application, by setting up a correct detection circuit and an incorrect detection circuit with symmetrical structure but different connection methods in the slave device, the bus connection method of the slave device is detected. Only the bus connection method detected by the correct detection circuit is output as the bus connection method of the slave device. This bus connection method is then matched with the slave device address (USID) corresponding to that bus connection method in the 13-bit command frame sent by the master device, thereby enabling the slave device to obtain its own slave device address (USID). Furthermore, it ensures that if the data characteristics of the 13-bit command frame sent by the master device to the slave device are problematic, and the correct detection circuit cannot obtain the slave device's bus connection method based on the 13-bit command frame, the incorrect detection circuit will also be unable to re-determine the slave device's bus connection method based on a certain number of subsequent pulses, thus outputting an incorrect bus connection method as the slave device's bus connection method. This improves the overall stability of the data detection system while ensuring the accuracy of the bus determination result.

[0063] This application provides a device, which is a first device. The first device includes a connection port, a data detection device, and a data processing circuit. The data detection device includes a first detection circuit and a second detection circuit. The connection method between the first detection circuit and the connection port and the connection method between the second device and the connection port are the same. The connection method between the second detection circuit and the connection port and the connection method between the second device and the connection port are different.

[0064] A first detection circuit is used to receive a first input signal; a second detection circuit is used to receive the first input signal.

[0065] A first detection circuit is used to acquire a first output signal based on a first input signal; the first output signal includes the first input signal and the bus connection method of the first device.

[0066] The first detection circuit is used to send the first output signal to the data processing circuit;

[0067] The second detection circuit is used to generate a blocking signal, which is used to disable the second detection circuit.

[0068] The data detection device mentioned in this application will be described in detail below.

[0069] For example, Figure 3 A data detection device 310 is shown in the figure. For example... Figure 3 As shown, the data detection device 310 includes a first detection circuit 312 and a second detection circuit 313. The first detection circuit 312 includes a first start signal detection unit 3121 and a first instruction judgment unit 3122; the second detection circuit 313 includes a second start signal detection unit 3131 and a second instruction judgment unit 3132. The first start signal detection unit 3121 and the second start signal detection unit 3131 can output an SSC1 signal to control the normal detection process of the correct detection circuit and an SSC2 signal to hinder the detection process of the error detection circuit. The first instruction judgment unit 3122 and the second instruction judgment unit 3132 can determine whether the bus connection relationship of the detection circuit is correct and whether the data characteristics of the 13-bit command frame are satisfied, and control the reset of the first detection circuit 312 and the second detection circuit 313.

[0070] Furthermore, combined with Figure 3 The schematic diagram of the slave device 31 shown illustrates the detection method mentioned in this application by taking the bus connection method between the slave device 31 and the master device 30 and the bus connection method corresponding to the slave device address USID in the 13-bit command frame sent by the master device 30 as examples.

[0071] The master device 30 and slave device 31 are specifically connected as follows: the first clock signal terminal C311 and the first data signal terminal D311 are respectively connected to the second clock terminal C312 and the second data signal terminal D312 of the first detection circuit 312. The first clock signal terminal C311 and the first data signal terminal D311 are respectively connected to the third clock terminal C313 and the third data signal terminal D313 of the second detection circuit 313. The first clock signal terminal C311 and the first data signal terminal D311 are respectively connected to the fourth clock terminal C310 and the fourth data signal terminal D310 of the master device 30.

[0072] Specifically, when communication begins, the first detection circuit 312 and the second detection circuit 313 detect the 13-bit command frame sent by the master device 30 to obtain the bus connection mode of the slave device 31. The specific detection process is as follows: First, the master device 30 sends a 13-bit command frame to the slave device 31. The bus connection mode corresponding to this 13-bit command frame is a corresponding connection, and the clock value of this 13-bit command frame is 0, while the data value is 1. The second clock terminal C312 of the first detection circuit 312 receives a clock signal of 0, and the second data terminal D312 of the first detection circuit 312 receives the 13-bit command frame. Meanwhile, the third clock terminal C311 of the second detection circuit 313 receives the 13-bit command frame, and the third data terminal D311 of the second detection circuit 313 receives a clock signal of 0. Therefore, it can be determined that the bus connection mode of the slave device 31 is the same as the connection mode between the first detection circuit 312 and the first clock terminal C311 and the first data terminal D311 of the slave device 31, i.e., a corresponding connection mode.

[0073] Then, the first detection circuit 312 and the second detection circuit 313 respectively output the detection results to the data processing circuit 314. The data processing circuit 314 can judge the USID in the received 13-bit command frame based on the bus connection mode detected by the data detection device 310, so as to determine whether to execute the 13-bit command frame.

[0074] It is understood that in some embodiments, when the first detection circuit confirms that its bus connection method is the same as the bus connection method corresponding to the USID in the 13-bit command frame, that is, the first detection circuit is a detection circuit with a correct bus connection relationship. The first detection circuit executes the 13-bit command frame, obtains the bus connection method of the slave device 31, and sends the 13-bit command frame and the corresponding bus connection method as a first output signal to the data processing circuit 314.

[0075] The third data terminal D311 of the second detection circuit 313 receives the clock signal from the master device. Correspondingly, the third clock terminal C311 of the second detection circuit 313 receives the 13-bit command frame sent by the master device 30, thus determining that the bus connection mode of the slave device 31 is a cross connection. However, the bus connection mode corresponding to the 13-bit command frame is a corresponding connection, so the second detection circuit 313 is a bus connection mode error detection circuit. Consequently, the SSC detection unit 31221 inside the second detection circuit 313 generates an SSC2 signal to shut down the detection process of the second detection circuit 313.

[0076] It is understood that in other embodiments, the bus connection method corresponding to the slave device address USID in the 13-bit command frame sent by the master device 30 may also be a cross connection, which is not limited here.

[0077] It can be understood that the SSC1 signal is generated by the bus relationship correct detection circuit to ensure that the correct detection circuit can detect normally; while the SSC2 signal is generated by the bus relationship incorrect detection circuit to shut down the error detection circuit detection process, so that the error detection circuit cannot make abnormal judgments.

[0078] It is understandable that the SSC detection unit supports asynchronous reset of the SSC2 signal to ensure that the SSC2 signal after the previous communication will not affect the next communication.

[0079] It is understood that in some other embodiments, based on the different bus connection methods between the two detection circuits and the slave device 31, the first detection circuit 312 may be an error detection circuit, while the second detection circuit 313 may be a correct detection circuit, and this is not limited here.

[0080] The following is combined Figures 4A to 5B The schematic diagram of the SSC detection unit shown is a timing logic diagram, which further explains the generation principle of the SSC2 signal in the correct detection circuit and the error detection circuit in the device.

[0081] First, refer to Figure 4A and Figure 5A This explains the working principle of the first start signal detection unit 3121 in the first detection circuit 312, which generates only the SSC1 signal and not the SSC2 signal.

[0082] For example, such as Figure 4A The diagram shows the structure of the first start signal detection unit 3121 of the correct first detection circuit 312. The first start signal detection unit 3121 mainly includes: a first input terminal, a second input terminal, an SSC1 signal generation circuit 31211, an SSC2 signal generation circuit 31212, and an OR logic gate Y2. The first input terminal is connected to the data terminal C311 of the slave device 31, and the second input terminal is connected to the clock terminal D311 of the slave device 31.

[0083] The SSC1 signal generation circuit 31211 consists of two cascaded registers T1 and T2. Registers T1 and T2 are used to identify high-level pulses at the first input terminal and generate the SSC1 signal upon successful identification. Since the first detection circuit 312 is the correct detection circuit at this time, only the SSC1 signal generation circuit in the first start signal detection unit 3121 within the first detection circuit 312 operates and generates the SSC1 signal, ensuring that the first detection circuit 312 can correctly obtain the correct bus connection mode of the slave device 31 based on the 13-bit command frame.

[0084] further, Figure 5AA timing diagram of the first start signal detection unit 3121 in the first detection circuit 312 is shown.

[0085] Specifically, the first input terminal of the SSC2 signal generation circuit in the first start signal detection unit 3121 receives a data signal, and the second input terminal receives a clock signal. The data signal at the first input terminal is driven by the rising edge of the clock signal at the second input terminal. The frequency divider signal generated by the CLKN_DIV frequency divider module is flipped according to the falling edge of the clock signal at the second input terminal. Since the frequency divider signal CLKN_DIV extends the pulse width of the clock signal at the second input terminal, the pulse of the data signal at the first input terminal is the same as that of the CLKN_DIV frequency divider signal and they coincide in phase for half a clock signal period. Therefore, no additional SSC2 signal is generated in the first detection circuit 312.

[0086] Secondly, refer to Figure 4B and Figure 5B This explains the working principle of the second start signal detection unit 3131 in the second detection circuit 313 generating only the SSC2 signal.

[0087] For example, such as Figure 4B The diagram shows the structure of the second start signal detection unit 3131 of the second detection circuit 313. The structure of the second start signal detection unit 3131 is the same as that of the first start signal detection unit 3121 described above. The first input terminal is connected to the data terminal C311 of the slave device 31, and the second input terminal is connected to the clock terminal D311 of the slave device 31.

[0088] The SSC2 signal generation circuit 31212 consists of two cascaded registers T3 and T4 and a CLKN_DIV divider module. Registers T3 and T4 are used to identify the high-level pulse at the first input terminal, while the CLKN_DIV divider module generates a divider signal CLKN_DIV based on the falling edge of the second input terminal. This divider expands the pulse width of the second input signal, thereby generating the SSC2 signal to shut down the detection process of the error detection circuit 3122. Since the second detection circuit 313 is currently an error detection circuit, only the SSC2 signal generation circuit 31212 operates within the second start signal detection unit 3131 of the second detection circuit 313, generating the SSC2 signal to shut down the detection operation of the second detection circuit 313.

[0089] Furthermore, such as Figure 5B The timing diagram of the second start signal detection unit 3131 in the second detection circuit 313 shown.

[0090] Specifically, the first input terminal of the SSC2 detection circuit in the second start signal detection unit 3131 is connected to the clock terminal of the slave device 31, meaning the first input terminal receives a clock signal. The second input terminal is connected to the data terminal of the slave device 31, meaning the second input terminal receives a data signal. In other words, at this time, the data signal at the second input terminal serves as the clock signal, while the clock signal at the first input terminal serves as the data signal. Since the CLKN_DIV frequency divider signal is divided by two based on the falling edge of the second input data signal (as a clock signal), it expands the pulse width of the second input data signal (as a clock signal). The minimum pulse width of the second input data signal (as a clock signal) has the same period as the clock signal (as a data signal) of the first input. However, the pulse width of the CLKN_DIV frequency divider signal is twice or more than that of the clock signal (as a data signal) of the first input. Therefore, the low-level pulse width of the CLKN_DIV frequency divider signal contains at least one pulse of the clock signal (as a data signal) of the first input, causing the SSC2 signal generation circuit to generate the SSC2 signal.

[0091] It is understandable that the SSC2 signal generation circuit supports asynchronous reset of the SSC2 signal, which ensures that the SSC2 signal after the previous communication will not affect the next communication.

[0092] further, Figure 6 A schematic diagram of an instruction judgment unit is shown. The first instruction judgment unit 3122 mainly consists of a data acquisition subunit 31221 and a judgment subunit 31222. It can receive 13-bit command frames sent by the master device and judge the data characteristics of the 13-bit command frames. After judging that the data characteristics of the 13-bit command frames meet the conditions, it determines the bus connection mode of the slave device. In addition, since the bus connection modes of different detection circuits are different, the address used for addressing by the instruction judgment unit of different detection circuits is also different. Among them, the data acquisition subunit 31221 mainly consists of a counter 312211 and a shift register 312212. The data acquisition subunit 31221 is responsible for acquiring and detecting the received 13-bit command frames to determine the bus connection mode of the slave device. The judgment subunit 31222 can be used to judge whether the 13-bit command frame meets the preset data characteristics. After judging that the data characteristics of the 13-bit command frame meet the conditions, it matches the bus connection mode of the slave device with the bus connection mode corresponding to the slave device address USID in the 13-bit command frame. Thus, the USID is the slave device address of the slave device.

[0093] It is understandable that the instruction control unit can also control the SSC detection unit to perform asynchronous reset, so as to ensure that the SSC2 signal generated by the SSC2 signal generation circuit in a certain communication will not affect the next communication.

[0094] It is understandable that, since the two detection circuits are connected to the slave device 31 in different ways, the addresses used for addressing by the instruction judgment unit are also different, which can realize the addressing expansion of the instruction judgment unit.

[0095] It is understood that some embodiments disclose a method for determining the bus connection mode of the slave device based on the SSC signal. This is mainly achieved by the slave device receiving the SSC signal from the master device and then determining the high and low levels of the clock and data terminals of the slave device based on the SSC signal.

[0096] The following provides a detailed description of the technical solutions mentioned in some embodiments for determining the bus connection mode of slave devices based on SSC signals.

[0097] Specifically, the communication process between the master device 10 and the two slave devices mainly includes: the master device 10 sending an SSC signal to the slave devices connected to it via a bus to initiate communication. After receiving the SSC signal from the master device, the slave devices can determine their connection method based on the signals received at the clock and data ends.

[0098] It can be understood that the SSC signal is the start signal for the master device to begin communication with the slave device. The conditions for its generation are that the clock terminal of the master device is at a low level and the data terminal of the master device is a pulse signal, that is, the clock signal sent by the clock terminal of the master device is 0 and the data signal sent by the data terminal is 1.

[0099] For example, in Figure 1A In this context, for slave devices 11 and 12, if both their clock terminals C111 and C121 receive signals of 0, then slave devices 11 and 12 can determine that their clock terminals are connected to the clock terminal C101 of the master device 30. Similarly, if both their data terminals D111 and D121 receive signals of 1, then slave devices 11 and 12 can determine that their data terminals are connected to the data terminal D101 of the master device 10. Therefore, slave devices 11 and 12 can determine that their connections to the master device 10 are corresponding connections.

[0100] For example, in Figure 1BIn the above scenario, if the signals received by slave device 11 from its clock terminal C111 and data terminal D111 are 0 and 1 respectively, slave device 11 can determine that its own clock terminal C111 is connected to the clock terminal C101 of master device 10, and its data terminal D111 is connected to the data terminal D101 of master device 10. Therefore, slave device 11 can determine that its connection with master device 10 is a corresponding connection. Similarly, if the signals received by slave device 12 from its clock terminal C121 and data terminal D111 are 1 and 0 respectively, slave device 12 can determine that its own clock terminal C121 is connected to the data terminal D101 of master device 10, and its data terminal D121 is connected to the clock terminal C101 of master device 10. Therefore, slave device 12 can determine that its connection with master device 10 is a cross connection. Then, master device 10 sends a first input signal to slave device 10.

[0101] It is understood that the first input signal includes a 13-bit command frame, which consists of a 4-bit slave device address (USID), a 3-bit register write identifier (010), a 5-bit register address, and a 1-bit parity bit (P). The composition of the command frame will vary for different read and write instruction sequences. This embodiment of the application takes the 13-bit command frame of the write instruction as an example, and is not limited here.

[0102] Thus, after receiving the first input signal, the slave device can determine whether its bus connection method is the same as the bus connection method corresponding to the USID based on the USID in the 13-bit command frame of the first input signal. If they are the same, the slave device assumes that the 13-bit command frame is sent to itself for execution, and then executes the 13-bit command frame.

[0103] For example, for Figure 1B In the scenario shown, device 12 determines its bus connection mode as a cross connection based on the SSC signal. If the bus connection mode represented by the USID in the received 13-bit command frame is a cross connection, then the specific content in the 13-bit command frame is executed. If the bus connection mode represented by the USID in the received 13-bit command frame is the corresponding connection mode, then the specific content in the 13-bit command frame is not executed.

[0104] Understandably, in this scenario, the slave device relies on the connection method determined by the SSC signal to decide whether to execute the received 13-bit command frame. If multiple slave devices determine their connection method based on the SSC signal to be the same as the bus connection method in the 13-bit command frame, then all slave devices will execute the same 13-bit command frame, resulting in wasted resources. Conversely, if multiple slave devices determine their bus connection method based on the SSC signal to be different from the bus connection method in the 13-bit command frame, then there may be a situation where no slave device executes the 13-bit command frame sent by the master device.

[0105] For example, for Figure 1A In the scenario shown, both slave devices 11 and 12 are connected in a corresponding manner based on the SSC signal. Therefore, after receiving a 13-bit command frame from master device 10, if the bus connection method indicated by the USID in the received 13-bit command frame is a corresponding connection, both slave devices 11 and 12 will execute the specific content of the 13-bit command frame, resulting in resource waste. However, if the bus connection method indicated by the USID in the received 13-bit command frame is a cross-connection, neither slave device will execute the 13-bit command frame; that is, no slave device executes the 13-bit command frame sent by master device 10.

[0106] And for Figure 1B Although the connection method allows for differentiation of the different bus connection modes of slave devices 11 and 12 via the SSC signal, a problem arises if, before a master-slave communication, the clock signal at the clock terminal C111 and the data signal at the data terminal D111 of the master device 10 are both 0 (meaning a normal SSC signal cannot be generated to initiate communication), but a glitch occurs at the data terminal D111 of the master device 10, causing the master device 10's data signal to become 1, resulting in the master device 10 mistakenly triggering an SSC signal. Slave devices 11 and 12, upon receiving this SSC signal, will still perform checks to determine their own bus connection modes. However, because the SSC signal was sent due to the master device 10's mistaken triggering, no further 13-bit command frames will be sent. Therefore, slave devices 11 and 12 perform an unnecessary check.

[0107] The solution provided in this application detects the correct bus connection mode of the 13-bit command frame through the bus connection mode detection circuit in the two detection circuits of the slave device to obtain the correct bus connection mode of the slave device. This enables the slave device with the same bus connection mode as the USID in the 13-bit command frame to execute the 13-bit command frame, while the slave device with a different bus connection mode than the USID in the 13-bit command frame will not execute the 13-bit command frame. This solves the problem of resource waste caused by multiple slave devices executing the 13-bit command frame in the above solution.

[0108] It is understood that some embodiments disclose a method for determining the bus connection mode of the slave device based on a 13-bit command frame. This is mainly achieved by setting two detection circuits in the slave device to detect its bus connection mode, without needing to detect the SSC signal. The bus connection mode of the slave device can be determined by whether the clock and data terminals of the two detection circuits receive a clock signal or a 13-bit command frame, respectively.

[0109] The following is a detailed description of the technical solutions mentioned in some embodiments for determining the bus connection mode of the slave device based on the 13-bit command frame.

[0110] Specifically, the master device typically sends a clock signal via its clock input and a 13-bit command frame via its data input. The slave device's internal data signal detection unit has two detection circuits. One detection circuit's clock and data inputs are connected to the slave device's clock and data inputs respectively, while the other detection circuit's clock and data inputs are cross-connected to the slave device's clock and data inputs respectively. When the slave device's bus connection is a corresponding connection, the clock input of the detection circuit corresponding to the slave device's clock and data inputs will receive the clock signal, and the data input will receive the 13-bit command frame. Conversely, the clock input of the cross-connected detection circuit will receive the 13-bit command frame, and the data input will receive the clock signal. When the slave device's bus connection is a cross-connection, the clock input of the cross-connected detection circuit will receive the clock signal, and the data input will receive the 13-bit command frame. Similarly, the clock input of the detection circuit corresponding to the slave device's clock and data inputs will receive the 13-bit command frame, and the data input will receive the clock signal.

[0111] Therefore, by determining whether the clock and data terminals of the two detection circuits receive a clock signal or a 13-bit command frame, the bus connection method of the slave device can be confirmed.

[0112] Specifically, for example, such as Figure 7AAs shown, the bus connections of slave devices 21 and 22 to master device 20 are respectively a corresponding connection and a cross connection. Furthermore, slave devices 21 and 22 each have a data detection device 212 and a data detection device 222 internally. Data detection devices 212 and 222 can confirm the bus connection method of the slave devices through two internal detection circuits. The specific detection method of data detection device 212 will be explained below as an example.

[0113] like Figure 7B As shown, the data detection device 212 includes a first detection circuit 2121 and a second detection circuit 2122. The clock terminal C2121 and data terminal D2121 of the first detection circuit 2121 are connected to the clock terminal C211 and data terminal D211 of the slave device 21, respectively. The clock terminal C2122 of the second detection circuit 2122 is connected to the data terminal D211 of the slave device 21, and the data terminal D2121 is connected to the clock terminal C211 of the slave device 21.

[0114] Assuming Figure 7A Since slave device 21 and master device 20 are connected accordingly, when master device 20 sends a clock signal through clock terminal C211 and a 13-bit command frame through data terminal D211 to slave device 21, clock terminal C2121 of the first detection circuit 2121 receives the clock signal, and data terminal D2121 of the first detection circuit 2121 receives the 13-bit command frame. Similarly, clock terminal C2122 of the second detection circuit 2122 receives the 13-bit command frame, and data terminal D2122 of the first detection circuit 2121 receives the clock signal. Therefore, it can be determined that the bus connection method of slave device 21 is the same as the connection method between the first detection circuit 2121 and the clock terminal C211 and data terminal D211 of slave device 21, i.e., a corresponding connection method.

[0115] Then, the first detection circuit 2121 and the second detection circuit 2122 respectively output the detection results to the data processing circuit 2124. The data processing circuit 2124 can determine whether to execute the 13-bit command frame based on the bus connection mode detected by the data detection device 212 and the USID in the received 13-bit command frame.

[0116] Assuming that slave device 21 and master device 20 are cross-connected, when master device 20 sends a clock signal through clock terminal C201 and a 13-bit command frame through data terminal D201, the clock terminal C2122 of the second detection circuit 2122 is connected to the data terminal D211 of slave device 21, while the data terminal D511 of slave device 21 is connected to the clock terminal C201 of master device 20. Therefore, the clock terminal C2122 of the second detection circuit 2122 receives the clock signal sent by master device 20, and correspondingly, the data terminal D2122 of the second detection circuit 2122 receives the 13-bit command frame sent by master device 20. Thus, it can be determined that the bus connection mode of slave device 21 is the same as the connection mode between the second detection circuit 2122 and the clock terminal C211 and data terminal D211 of slave device, which is a cross-connection.

[0117] Then, the first detection circuit 2121 and the second detection circuit 2122 respectively output the detection results to the data signal processing circuit 2124. The data signal processing circuit 2124 can judge the USID in the received 13-bit command frame based on the bus connection mode detected by the data detection device 212 to determine whether to execute the 13-bit command frame.

[0118] However, in the above embodiments, if the 13-bit command frame sent by the master device is interfered with or distorted during transmission, and the 13-bit command frame does not meet the data characteristics (correct parity bit and command sequence as specified by the RFFE protocol), the detection circuit in the slave device's data detection device, which connects the data terminal to the master device's data terminal, will not determine the bus connection method based on the 13-bit command frame. Therefore, another detection circuit in the data detection device will re-acquire the clock signal and the 13-bit command frame. Since the data terminal of this detection circuit is connected to the master device's clock terminal, and the clock terminal is connected to the master device's data terminal, the output bus connection method is not the slave device's bus connection method, thus causing an error in determining the slave device's bus connection method.

[0119] For example, for Figure 7A and Figure 7B In the scenario shown, if the 13-bit command frame sent by the master device 20 is interfered with during transmission and does not meet the data characteristics, the first detection circuit 2121 will not determine the bus connection mode of the 13-bit command frame; only the second detection circuit 2122 can make the determination. The second detection circuit 2122 determines the bus connection mode to be a cross connection, but the connection mode between the slave device 21 and the master device 20 is a corresponding connection, so the determination result is incorrect.

[0120] The solution provided in this application uses a bus connection correctness detection circuit in one of the two detection circuits in the slave device to detect the 13-bit command frame to obtain the correct bus connection mode of the slave device. The bus connection error detection circuit stops detecting after determining it to be an error. This ensures that only the correct detection circuit can correctly detect the slave device's bus connection mode, thus solving the problem of inaccurate bus connection mode results caused by the error detection circuit detecting incorrect slave device bus connection modes in the aforementioned solutions.

[0121] This application provides a device, a first device, comprising a connection port, a data detection device, and a data processing circuit. The data detection device includes a first detection circuit and a second detection circuit. The first detection circuit and the connection port are connected in the same way as the second device and the connection port; the second detection circuit and the connection port are connected in a different way than the second device and the connection port.

[0122] A first detection circuit is used to receive a first input signal; a second detection circuit is used to receive the first input signal; the first detection circuit is used to obtain a first output signal based on the first input signal; the first output signal includes the first input signal and the bus connection method of the first device.

[0123] The first detection circuit is used to send a first output signal to the data processing circuit; the second detection circuit is used to generate a blocking signal, which is used to make the second detection circuit non-operating.

[0124] The first detection circuit includes a first instruction judgment unit;

[0125] The first instruction judgment unit is used to obtain the first output signal based on the first input signal;

[0126] The first instruction judgment unit is used to output the first output signal when it is determined that the first input signal meets the data characteristics.

[0127] The connection port includes a first clock signal terminal and a first data signal terminal; the first detection circuit includes a second clock signal terminal and a second data signal terminal; the second detection circuit includes a third clock signal terminal and a third data signal terminal; and the second device includes a fourth clock signal terminal and a fourth data signal terminal.

[0128] The connection method between the first detection circuit and the connection port is the same as that between the second device and the connection port. The connection method between the second detection circuit and the connection port differs from that between the second device and the connection port, including:

[0129] The first clock signal terminal is connected to the fourth clock signal terminal, and the first data signal terminal is connected to the fourth data signal terminal.

[0130] The second clock signal terminal is connected to the fourth clock signal terminal, and the second data signal terminal is connected to the fourth data signal terminal.

[0131] The third clock signal terminal is connected to the fourth data signal terminal, and the third data signal terminal is connected to the fourth clock signal terminal.

[0132] This application provides a communication system, including: a second device and at least two first devices, wherein the second device sends a first input signal to the first devices.

[0133] This application embodiment can also provide an electronic device, including the above-described communication system, wherein the electronic device can be any electronic device such as a mobile phone or a computer.

[0134] This application also provides a program product for implementing the data detection methods provided in the above embodiments.

[0135] Various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or combinations of these implementation methods. Embodiments of this application can be implemented as computer modules or module code executing on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0136] Module code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0137] Module code can be implemented using a high-level modular language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used to implement module code when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0138] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0139] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0140] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the term "comprising" or any other variations thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0141] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A data detection method for a first device, characterized in that, The first device includes a connection port, a data detection device, and a data processing circuit. The data detection device includes a first detection circuit and a second detection circuit. The connection method between the first detection circuit and the connection port is the same as the connection method between the second device and the connection port. The connection method between the second detection circuit and the connection port is different from the connection method between the second device and the connection port. The first detection circuit and the second detection circuit receive the first input signal; When the first detection circuit determines that the first input signal meets the data characteristics, it outputs a first output signal to the data processing circuit. The data characteristics include that the parity check bit of the first input signal is correct and that the command sequence of the first input signal is consistent with the preset sequence. The first output signal includes the first input signal and the bus connection mode of the first device. The second detection circuit generates a blocking signal, which is used to disable the second detection circuit.

2. The data detection method according to claim 1, characterized in that, The first detection circuit includes a first instruction judgment unit; When the first instruction judgment unit determines that the first input signal meets the data characteristics, it outputs the first output signal to the data processing circuit.

3. The data detection method according to claim 1, characterized in that, The first detection circuit further includes a first start signal detection unit, and also includes: The first start signal detection unit generates a start signal based on the high and low level changes of the first input signal, and the start signal is used to keep the first detection circuit in normal working state.

4. The data detection method according to claim 1, characterized in that, The second detection circuit includes a second start signal detection unit; The second detection circuit generates the blocking signal, including: The second start signal detection unit receives the first input signal and generates the blocking signal based on the high and low level changes of the first input signal.

5. The data detection method according to claim 2, characterized in that, The second detection circuit includes a second instruction judgment unit; After the data processing circuit receives the first output signal... The first instruction judgment unit resets the first detection circuit generation circuit; The second instruction judgment unit resets the second detection circuit generation circuit.

6. The data detection method according to claim 1, characterized in that, The connection port includes a first clock signal terminal and a first data signal terminal; the first detection circuit includes a second clock signal terminal and a second data signal terminal; the second detection circuit includes a third clock signal terminal and a third data signal terminal; and the second device includes a fourth clock signal terminal and a fourth data signal terminal. The connection method between the first detection circuit and the connection port is the same as the connection method between the second device and the connection port. The connection method between the second detection circuit and the connection port differs from the connection method between the second device and the connection port, including: The first clock signal terminal is connected to the fourth clock signal terminal, and the first data signal terminal is connected to the fourth data signal terminal; The second clock signal terminal is connected to the fourth clock signal terminal, and the second data signal terminal is connected to the fourth data signal terminal; The third clock signal terminal is connected to the fourth data signal terminal, and the third data signal terminal is connected to the fourth clock signal terminal.

7. A data detection device, characterized in that, The data detection device is a first device, which includes a connection port, a data detection unit, and a data processing circuit. The data detection unit includes a first detection circuit and a second detection circuit. The connection method between the first detection circuit and the connection port, and the connection method between the second device and the connection port, are the same. The connection method between the second detection circuit and the connection port is different from the connection method between the second device and the connection port; The first detection circuit and the second detection circuit are used to receive the first input signal; The first detection circuit is used to output a first output signal to the data processing circuit when it determines that the first input signal meets the data characteristics. The data characteristics include that the parity check bit of the first input signal is correct and that the command sequence of the first input signal is consistent with the preset sequence. The first output signal includes the first input signal and the bus connection mode of the first device. The second detection circuit is used to generate a blocking signal, which is used to put the second detection circuit into a non-operating state.

8. The device according to claim 7, characterized in that, The first detection circuit includes a first instruction judgment unit; The first instruction determination unit is used to output the first output signal to the data processing circuit when it determines that the first input signal meets the data characteristics.

9. The device according to claim 7, characterized in that, The connection port includes a first clock signal terminal and a first data signal terminal; the first detection circuit includes a second clock signal terminal and a second data signal terminal; the second detection circuit includes a third clock signal terminal and a third data signal terminal; and the second device includes a fourth clock signal terminal and a fourth data signal terminal. The connection method between the first detection circuit and the connection port is the same as the connection method between the second device and the connection port. The connection method between the second detection circuit and the connection port differs from the connection method between the second device and the connection port, including: The first clock signal terminal is connected to the fourth clock signal terminal, and the first data signal terminal is connected to the fourth data signal terminal; The second clock signal terminal is connected to the fourth clock signal terminal, and the second data signal terminal is connected to the fourth data signal terminal; The third clock signal terminal is connected to the fourth data signal terminal, and the third data signal terminal is connected to the fourth clock signal terminal.

10. A communication system, characterized in that, include: A second device, at least two first devices as described in claim 7, wherein the second device sends the first input signal to the first device.

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