Data transmission method based on serial transceiver, transceiver, medium and device

Abstract

The application provides a serial transceiver-based data transmission method, a transceiver, a medium and equipment, and the method comprises the following steps: a serial transceiver switches clock frequency in the process of transmitting frame data, sends clock frequency switching information to a sending end parallel-serial conversion unit, and repeatedly writes current frame data into a sending data buffer; the sending end parallel-serial conversion unit reads parallel valid data of a preset bit number in the current frame data, counts the read bit number through a counter, and after receiving the clock frequency switching information, judges whether the count value is equal to the preset bit number value; if yes, it is determined that the parallel valid data is serialized, and serial data is obtained; the receiving end serial-parallel conversion unit converts the serial data into parallel data, and after detecting a frame header in the parallel data, it is determined that the frame header is in the aligned frame data, and the frame data is written into a receiving data buffer. The application realizes switching of data transmission rate of the serial transceiver in the data transmission process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission method based on a serial transceiver, a transceiver, a medium and equipment. BACKGROUND

[0002] Figure 1 A structural schematic diagram of a serial transceiver provided according to the prior art is shown in FIG. 1. As shown in FIG. 1, the current serial transceiver includes a transceiver control unit, a sending data buffer, a sending end parallel-serial conversion unit, a receiving buffer, and a receiving end serial-parallel conversion unit. The transceiver control unit is responsible for clock generation, sending parallel data generation, receiving parallel data processing, and module overall control. The sending data buffer is responsible for buffering the parallel data to be sent. The sending end parallel-serial conversion unit is responsible for converting the parallel data read from the sending data buffer into serial data and sending the serial data out. The receiving end serial-parallel conversion unit is responsible for converting the received serial data into parallel data and then writing the parallel data into the receiving data buffer. The receiving data buffer is responsible for buffering the received parallel data. Figure 1 In the above application, the PLL (Phase-locked loops, a frequency and phase synchronization technology realized by using feedback control principle, which functions to keep the output clock of the circuit synchronized with the external reference clock) in the transceiver control unit generates a serial sending clock, a write sending buffer clock, and a read receiving buffer clock. The read sending buffer clock is generated by the serial sending clock. All the clocks can be divided into low-speed parallel clocks and high-speed serial clocks, which are in a fixed multiple relationship and change synchronously. The low-speed parallel clocks include the write sending buffer clock and the read receiving buffer clock. The high-speed serial clocks include the serial sending clock, the read sending buffer clock, the write receiving buffer clock, and the serial receiving clock.

[0003] In the traditional application scenario, the module needs to determine the frequencies of the parallel clock and the serial clock before transmitting data, and then performs data transmission. The clock frequency is generally not changed during the data transmission process. If the clock frequency needs to be changed, the serial transceiver needs to be powered off or reset, the clock frequency is changed, and then the module starts working again with the new clock frequency. Since the data transmission rate changes with the clock frequency, for the traditional serial transceiver, changing the clock frequency will cause data transmission errors and data disorder.

[0004] SUMMARY

[0005] Therefore, the present application aims to provide a data transmission method based on a serial transceiver, a transceiver, a medium and equipment to solve the problem of data transmission errors caused by data transmission rate switching in the traditional serial transceiver.

[0006] ​In order to achieve the above object, the application provides a data transmission method based on a serial transceiver, comprising the following steps:

[0007] In response to the serial transceiver receiving an instruction of changing the transmission rate during the process of transmitting frame data, switching the clock frequency based on the instruction, and sending the clock frequency switching information to the transmitting parallel-serial conversion unit and repeatedly writing the current frame data to the transmitting data buffer;

[0008] Reading the parallel valid data of a preset bit number in the current frame data by the transmitting parallel-serial conversion unit, counting the read bit number by a counter, and judging whether the count value is equal to the preset bit number value after receiving the clock frequency switching information;

[0009] In response to the count value being equal to the preset bit number value, determining that the parallel valid data is completed serializing to obtain serial data;

[0010] Converting the serial data into parallel data by the receiving serial-parallel conversion unit and performing frame header detection on the parallel data;

[0011] In response to detecting the frame header, determining that the frame data where the frame header is located is aligned, and writing the frame data into the receiving data buffer.

[0012] In some embodiments, the method further comprises:

[0013] In response to the count value being less than the preset bit number value, determining that the parallel valid data is not completed serializing, and confirming the ratio of the switched clock frequency to the original clock frequency according to the clock frequency switching factor in the clock frequency switching information;

[0014] In response to the ratio being greater than or equal to the preset bit number value, pausing reading the parallel valid data from the transmitting data buffer, and re-sending the parallel valid data to the transmitting parallel-serial conversion unit.

[0015] In some embodiments, the method further comprises:

[0016] In response to the ratio being less than the preset bit number value, continuing to send the data of the remaining bit number in the parallel valid data from the transmitting data buffer to the transmitting parallel-serial conversion unit.

[0017] In some embodiments, the method further comprises:

[0018] Multiplying the original clock frequency by the frequency multiplication factor in the clock frequency switching factor to obtain a frequency multiplication frequency, and dividing the frequency multiplication frequency by the frequency division factor in the clock frequency switching factor to obtain the switched clock frequency.

[0019] In some embodiments, the frame header detection on the parallel data comprises:

[0020] Performing the frame header detection on the bit-by-bit moved parallel data through a window of the preset bit number size.

[0021] In some embodiments, the method further comprises:

[0022] The frame data is processed by an 8B10B codec algorithm.

[0023] In some embodiments, the frame header detection on the parallel data comprises:

[0024] The frame header detection on the parallel data is performed by a data alignment module in the receiving end serial-parallel conversion unit based on a data alignment enable signal.

[0025] Another aspect of the present application further provides a serial transceiver, comprising:

[0026] A phase-locked loop configured to switch the clock frequency based on the instruction of the transmission rate change, and output clock frequency switching information, and repeatedly output the current frame data transmitted by the serial transceiver;

[0027] A sending data buffer configured to receive the repeated current frame data;

[0028] A sending end serial-parallel conversion unit configured to read parallel valid data of a preset bit number in the current frame data in the sending data buffer, count the read bit number by a counter, and after receiving the clock frequency switching information, determine whether the count value is equal to the preset bit number value, and in response to the count value being equal to the preset bit number value, determine that the parallel valid data is completed serialization, obtain serial data and output the serial data; and

[0029] A receiving end serial-parallel conversion unit configured to receive the serial data, convert the serial data into parallel data, perform frame header detection on the parallel data, and in response to detecting the frame header, determine that the frame data where the frame header is located is aligned, and write the frame data into a receiving data buffer.

[0030] Still another aspect of the present application further provides a computer readable storage medium storing computer program instructions, which, when executed by a processor, implement the above method.

[0031] Still another aspect of the present application further provides a computer device comprising a memory and a processor, the memory storing a computer program, which, when executed by the processor, executes the above method.

[0032] The present application has at least the following beneficial technical effects:

[0033] The serial transceiver-based data transmission method of the application realizes switching of the serial transceiver according to the requirement in the data transmission process, and can guarantee the accuracy of data transmission and reception, avoid data transmission errors, and improve the flexibility and safety of the serial transceiver. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the application, and for those skilled in the art, other embodiments can be obtained according to these drawings without creative labor.

[0035] Figure 1 The structural schematic diagram of the serial transceiver provided according to the prior art is shown in FIG. 1.

[0036] Figure 2 The schematic diagram of the serial transceiver-based data transmission method provided according to the embodiment of the application is shown in FIG. 2.

[0037] Figure 3 The structural schematic diagram of the serial transceiver for realizing the data transmission method provided according to the embodiment of the application is shown in FIG. 3.

[0038] Figure 4 The schematic diagram of the serial transceiver provided according to the embodiment of the application is shown in FIG. 4.

[0039] Figure 5 The schematic diagram of the computer readable storage medium for realizing the serial transceiver-based data transmission method provided according to the embodiment of the application is shown in FIG. 5.

[0040] Figure 6 The hardware structural schematic diagram of the computer device for executing the serial transceiver-based data transmission method provided according to the embodiment of the application is shown in FIG. 6. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the application more clear, the following will further describe the embodiments of the application in combination with specific embodiments and with reference to the drawings.

[0042] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two non-identical entities or non-identical parameters with the same name, and "first" and "second" are only for the convenience of description, and should not be understood as a limitation of the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, the process, method, system, product or device inherently includes other steps or units.

[0043] Based on the above purpose, a first aspect of the embodiments of the present application provides an embodiment of a data transmission method based on a serial transceiver. Figure 2 The embodiment of the data transmission method based on the serial transceiver provided by the present application is shown. As shown in the figure, Figure 2 The embodiment of the present application includes the following steps:

[0044] Step S10, in response to the serial transceiver receiving an instruction to change the transmission rate during the process of transmitting frame data, switching the clock frequency based on the instruction, and sending the clock frequency switching information to the sending end parallel-serial conversion unit, and repeatedly writing the current frame data to the sending data buffer;

[0045] Step S20, reading the parallel valid data of a preset number of bits in the current frame data by the sending end parallel-serial conversion unit, and counting the number of bits read by the counter, and after receiving the clock frequency switching information, judging whether the count value is equal to the preset bit number value;

[0046] Step S30, in response to the count value being equal to the preset bit number value, determining that the parallel valid data is completed serialization to obtain serial data;

[0047] Step S40, converting the serial data into parallel data by the receiving end serial-parallel conversion unit, and performing frame header detection on the parallel data;

[0048] Step S50, in response to detecting the frame header, determining that the frame data where the frame header is located is aligned, and writing the frame data into the receiving data buffer.

[0049] The data transmission method based on the serial transceiver of the embodiments of the present application realizes switching the data transmission rate of the serial transceiver according to the demand in the data transmission process, and can ensure the accuracy of data sending and receiving, avoid data transmission errors, improve the flexibility and safety of the serial transceiver; and without powering off the serial transceiver or stopping the data transmission, the data transmission rate can be switched arbitrarily, which is efficient and reliable, and widely applicable.

[0050] In some embodiments, the method further comprises: in response to the count value being less than the preset bit number value, determining that the parallel valid data is not serialized, and confirming a ratio of the switched clock frequency to the original clock frequency according to a clock frequency switching coefficient in the clock frequency switching information; and in response to the ratio being greater than or equal to the preset bit number value, suspending reading of the parallel valid data from the sending data buffer and resending the parallel valid data to the sending end parallel-serial conversion unit.

[0051] In some embodiments, the method further comprises: in response to the ratio being less than the preset bit number value, continuing to send the remaining bit number of data in the parallel valid data from the sending data buffer to the sending end parallel-serial conversion unit.

[0052] In some embodiments, the method further comprises: multiplying the original clock frequency by a frequency multiplication coefficient in the clock frequency switching coefficient to obtain a frequency multiplication frequency, and dividing the frequency multiplication frequency by a frequency division coefficient in the clock frequency switching coefficient to obtain the switched clock frequency.

[0053] In some embodiments, the frame header detection on the parallel data comprises: performing frame header detection on the parallel data moved bit by bit through a window of a preset bit number.

[0054] In some embodiments, the method further comprises: processing the frame data through an 8B10B encoding and decoding algorithm.

[0055] In the present embodiment, the 8B10B encoding and decoding algorithm can convert 8-bit data into 10-bit data.

[0056] In some embodiments, the frame header detection on the parallel data comprises: performing frame header detection on the parallel data by a data alignment module in the receiving end serial-parallel conversion unit based on a data alignment enable signal.

[0057] Figure 3 A structure diagram of a serial transceiver for implementing a data transmission method according to an embodiment of the present application is provided. As shown in FIG. 1, the serial transceiver comprises a sending end parallel-serial conversion unit 1, a sending data buffer 2, a clock frequency switching unit 3, a receiving end serial-parallel conversion unit 4, a receiving data buffer 5, and a clock frequency switching unit 6. Figure 3As shown, in order to solve the transmission error problem caused by data transmission rate switching in the traditional serial transceiver, a data transmission control module is added to the parallel-serial conversion unit at the sending end, and a data alignment module is added to the serial-parallel conversion unit at the receiving end. When it is necessary to switch the data transmission rate, the serial clock and the parallel clock output by the PLL (Phase-locked loops, a frequency and phase synchronization technology realized by using feedback control principle, which functions to keep the clock output by the circuit synchronized with the external reference clock) are changed first, and then the data transmission rate is changed. The transceiver control unit sends a clock frequency switching instruction signal and a clock frequency switching coefficient to the data transmission control module, so as to complete the control of the frequency switching device data and ensure the correct transmission of data. The transceiver control unit sends a data alignment enable signal to the data alignment module, and the data alignment module detects the received data. After the clock frequency is stable, the correct alignment data is detected, and then the subsequent data is transmitted. The following is an exemplary embodiment of the data transmission method based on the serial transceiver of the application:

[0058] 1) First, the data frame format is designed, taking N bytes as one frame, each frame including 1 byte of frame header and N-1 bytes of valid data. The 1 byte of frame header can be set to a fixed value for frame header detection during data misalignment. In order to make the frame header easy to detect, the data is processed by 8B10B encoding and decoding algorithm.

[0059] 2) When it is necessary to switch the data transmission rate, the PLL in the transceiver control unit changes the output serial clock and parallel clock first, and then writes repeated frame data to the sending data buffer, and then sends a clock frequency switching instruction signal and a clock frequency switching coefficient to the parallel-serial conversion unit at the sending end. The clock frequency switching instruction signal is used to indicate that the clock frequency is changed at this time. The clock frequency switching coefficient includes 32 bits of data, the first 16 bits of data are frequency multiplication coefficient, and the last 16 bits of data are frequency division coefficient, which indicates the specific clock change at this time. The switched clock frequency is the original clock frequency multiplied by the frequency multiplication coefficient, and then divided by the frequency division coefficient.

[0060] 3) The sending end parallel-to-serial conversion unit converts the n-bit (i.e. the preset bit number; if the data is processed by the 8B10B encoding algorithm, n is 10) parallel data read from the sending buffer into 1-bit serial data based on the counter. When the n-bit parallel data starts to enter the parallel-to-serial conversion state, the next n-bit parallel data is read from the sending buffer, and the transmission is waited for. When the sending clock frequency switching instruction signal is received, it is first determined whether the parallel-to-serial conversion counter value is equal to n. If it is equal to n, it indicates that the n-bit parallel data has been serialized. If the current counter value is less than n, it indicates that the n-bit parallel data has not been serialized. At this time, the frequency switching coefficient of the clock frequency switching coefficient is confirmed, and the frequency variation trend of the clock frequency after the frequency switching is determined. If the frequency is faster than n times, the reading speed of the sending buffer will also be accelerated. The reading of the sending buffer is suspended, and the n-bit parallel data needs to be re-sent at the new rate. If the frequency is faster than n times or slower, the reading speed of the sending buffer will not be accelerated, and the remaining data in the n-bit is continued to be sent.

[0061] 4) After the data transmission rate is switched, the data alignment enable signal is sent to the receiving end serial-to-parallel conversion unit. After the data alignment module detects that the data alignment enable signal is valid, the data alignment work is started. The bit-by-bit moving (i.e. bit-by-bit moving) parallel data is detected in each serial receiving clock cycle during the serial-to-parallel conversion, until the set frame header value is detected, it is determined that the data has been aligned, and the data alignment completion instruction signal is sent to the transceiver control unit. The repeated frame data during the data misalignment period is discarded and does not affect the transmission of other data.

[0062] 5) The serial-to-parallel conversion unit of the receiving end writes the frame header and the subsequent data determined to be aligned into the receiving data buffer.

[0063] This embodiment solves the transmission error problem caused by data transmission rate switching in serial transceivers. Traditional serial transceivers require changes to their internal serial and parallel clocks when the data transmission rate changes during data transmission. The PLL clock fluctuations after the change require relocking to stabilize, and this serial-to-parallel conversion can lead to data corruption and glitches, ultimately causing data transmission errors. Therefore, traditional serial transceivers cannot switch data transmission rates during data transmission. This embodiment processes the data during frequency changes based on different division and multiplication coefficients, ensuring accurate and stable data transmission. An effective frame format design and 8B10B encoding / decoding algorithm enable the frame header to be distinguishable from valid data, facilitating detection. A data alignment module performs alignment detection during frequency switching and performs a handshake with the transceiver control unit to ensure data accuracy. Data transmission rate switching can be performed during data transmission without power-off or interruption, ensuring high efficiency and reliability. This meets the application scenario requirements of serial transceivers that need to switch data rates during transmission, improving the flexibility of the serial transceiver.

[0064] A second aspect of the present invention also provides a serial transceiver. Figure 4 The diagram shown is a schematic representation of an embodiment of the serial transceiver provided by the present invention. Figure 4 As shown, a serial transceiver includes: a phase-locked loop 10, configured to switch the clock frequency based on instructions for changes in transmission rate, output clock frequency switching information, and repeatedly output the current frame data transmitted by the serial transceiver; a transmit data buffer 20, configured to receive repeated current frame data; a transmit-end parallel-to-serial conversion unit 30, configured to read a preset number of parallel valid data bits from the current frame data in the transmit data buffer, count the number of read bits using a counter, and after receiving clock frequency switching information, determine whether the count value is equal to the preset bit value, and in response to the count value being equal to the preset bit value, determine that the parallel valid data has been serialized, obtain serial data, and output it; and a receive-end serial-to-parallel conversion unit 40, configured to receive serial data, convert the serial data into parallel data, perform frame header detection on the parallel data, and in response to the detection of the frame header, determine that the frame data containing the frame header is aligned, and write the frame data into the receive data buffer.

[0065] The serial transceiver of this invention enables switching of data transmission rate according to demand during data transmission, while ensuring the accuracy of data sending and receiving, avoiding data transmission errors, and improving flexibility and security. Furthermore, it can switch data transmission rate arbitrarily without powering down or stopping data transmission, making it highly efficient, reliable, and applicable to a wide range of scenarios.

[0066] In some embodiments, the sending parallel-serial conversion unit 30 is further configured to, in response to the count value being less than the preset bit number value, determine that the parallel valid data is not serialized, and determine the ratio of the switched clock frequency to the original clock frequency according to the clock frequency switching factor in the clock frequency switching information; in response to the ratio being greater than or equal to the preset bit number value, suspend reading the parallel valid data from the sending data buffer, and resend the parallel valid data to the sending parallel-serial conversion unit.

[0067] In some embodiments, the sending parallel-serial conversion unit 30 is further configured to, in response to the ratio being less than the preset bit number value, continue sending the remaining bit number of data in the parallel valid data from the sending data buffer to the sending parallel-serial conversion unit.

[0068] In some embodiments, the sending parallel-serial conversion unit 30 is further configured to multiply the original clock frequency by the frequency multiplication factor in the clock frequency switching factor to obtain a frequency multiplication frequency, and divide the frequency multiplication frequency by the frequency division factor in the clock frequency switching factor to obtain the switched clock frequency.

[0069] In some embodiments, the receiving serial-parallel conversion unit 40 is further configured to perform frame header detection on the bit-moved parallel data through a window of a preset bit number size.

[0070] In some embodiments, the serial transceiver further comprises a transceiver control unit configured to process the frame data through an 8B10B encoding and decoding algorithm.

[0071] In some embodiments, the receiving serial-parallel conversion unit 40 comprises a data alignment module configured to perform frame header detection on the parallel data based on a data alignment enable signal.

[0072] The above embodiments process the data during the frequency change according to different frequency division factors and frequency multiplication factors, so that the sending data is accurate and stable; the frame format is effectively designed, and the data is encoded through an 8B10B encoding and decoding algorithm, so that the frame header can be distinguished from the valid data and is easy to detect; through the data alignment module, the data is aligned and detected during the frequency switching, and a handshake operation of data alignment with the transceiver control unit is performed, so that the data is accurate and reliable; the data transmission rate can be switched during the data transmission process, without power-off or stalling data transmission, which is efficient and reliable; the application scene requirement that the serial transceiver needs to switch the data rate during the transmission process is met, and the flexibility of the serial transceiver is improved.

[0073] A third aspect of the embodiments of the present application also provides a computer readable storage medium, Figure 5 A schematic diagram of a computer readable storage medium for implementing the data transmission method based on the serial transceiver according to the embodiments of the present application is shown. As shown in FIG. 6, the computer readable storage medium comprises a computer readable code for implementing the data transmission method based on the serial transceiver according to the embodiments of the present application. Figure 5As shown, the computer readable storage medium 3 stores computer program instructions 31. The computer program instructions 31, when executed by a processor, implement the method of any one of the above embodiments.

[0074] It should be understood that, in the case of not conflicting with each other, all the embodiments, features and advantages described above for the serial transceiver-based data transmission method according to the present application are equally applicable to the serial transceiver and the storage medium according to the present application.

[0075] A fourth aspect of the embodiments of the present application further provides a computer device, comprising a memory 402 and a processor 401, wherein the memory 402 stores a computer program, and the computer program is executed by the processor 401 to implement the method of any one of the above embodiments. Figure 6 As shown, the computer readable storage medium 3 stores computer program instructions 31. The computer program instructions 31, when executed by a processor, implement the method of any one of the above embodiments.

[0076] As shown, the computer readable storage medium 3 stores computer program instructions 31. The computer program instructions 31, when executed by a processor, implement the method of any one of the above embodiments. Figure 6 As shown, the computer readable storage medium 3 stores computer program instructions 31. The computer program instructions 31, when executed by a processor, implement the method of any one of the above embodiments. Figure 6 As shown, the computer device comprises a processor 401 and a memory 402, and can further comprise an input device 403 and an output device 404. The processor 401, the memory 402, the input device 403 and the output device 404 can be connected through a bus or other means, Figure 6 As shown, the computer readable storage medium 3 stores computer program instructions 31. The computer program instructions 31, when executed by a processor, implement the method of any one of the above embodiments.

[0077] The memory 402 is a non-volatile computer readable storage medium, which can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the program instructions / modules corresponding to the serial transceiver-based data transmission method in the embodiments of the present application. The memory 402 can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created by the use of the serial transceiver-based data transmission method, etc. In addition, the memory 402 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state memory device. In some embodiments, the memory 402 can optionally include a memory remotely arranged with respect to the processor 401, and these remote memories can be connected to the local modules through a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0078] The processor 401 performs various function applications and data processing of the server by running non-volatile software programs, instructions and modules stored in the memory 402, i.e. implements the serial transceiver-based data transmission method of the method embodiments.

[0079] Finally, it is to be appreciated that the computer readable storage medium (e.g., memory) of the present disclosure can be tangible and non-transitory computer readable storage medium. As an example and not by way of limitation, non-transitory computer readable storage media can include random access memory (RAM), read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), flash memory, compact disk (CD), digital versatile disc (DVD), magnetic disks, etc. As another example, computer readable storage medium can comprise computer readable storage media depicted as a group of disks and a group of chips. As yet another example, computer readable storage medium can comprise a combination of memory and chips.

[0080] Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0081] The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein can be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0082] The above are exemplary embodiments disclosed by the present application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the present application as defined by the claims. The functions, steps and / or actions of the method claims described herein need not be performed in any particular order. Furthermore, although elements of the embodiments disclosed by the present application can be described or claimed in individual form, unless explicitly restricted, they can also be implemented in multiple forms.

[0083] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The embodiment number of the embodiments disclosed by the present application is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0084] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary, and is not intended to imply that the scope of the embodiments disclosed by the present application (including the claims) is limited to these examples; under the idea of the embodiments disclosed by the present application, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes of the different aspects of the embodiments disclosed by the present application as above, which are not provided in detail for the sake of brevity. Therefore, any omission, modification, equivalent replacement, improvement, etc. made within the spirit and principles of the embodiments disclosed by the present application shall be included in the scope of protection of the embodiments disclosed by the present application.

Claims

1. A method of data transmission based on a serial transceiver, characterized in that, The method comprises the following steps: in response to the serial transceiver receiving an instruction of transmission rate change during transmission of frame data, switching the clock frequency based on the instruction, sending clock frequency switching information to the sending parallel-serial conversion unit, and repeatedly writing current frame data to the sending data buffer; reading a preset number of parallel valid data in the current frame data by the sending parallel-serial conversion unit, counting the number of read bits by a counter, and determining whether the count value is equal to the preset bit number value after receiving the clock frequency switching information; in response to the count value being equal to the preset bit number value, determining that the parallel valid data is completed serialization to obtain serial data; converting the serial data into parallel data by the receiving serial-parallel conversion unit, and performing frame header detection on the parallel data; in response to detecting the frame header, determining that the frame data where the frame header is located is aligned, and writing the frame data into the receiving data buffer; in response to the count value being less than the preset bit number value, determining that the parallel valid data is not completed serialization, and confirming the ratio of the switched clock frequency to the original clock frequency according to the clock frequency switching factor in the clock frequency switching information; in response to the ratio being greater than or equal to the preset bit number value, pausing reading the parallel valid data from the sending data buffer, and re-sending the parallel valid data to the sending parallel-serial conversion unit.

2. The method of claim 1, wherein, Further comprising: in response to the ratio being less than the preset bit number value, continuing to send the remaining bits of data in the parallel valid data from the sending data buffer to the sending parallel-serial conversion unit.

3. The method of claim 1, wherein, Further comprising: multiplying the original clock frequency by the frequency multiplication factor in the clock frequency switching factor to obtain a frequency multiplication frequency, and dividing the frequency multiplication frequency by the frequency division factor in the clock frequency switching factor to obtain the switched clock frequency.

4. The method of claim 1, wherein, The frame header detection on the parallel data comprises: performing frame header detection on the bit-shifted parallel data through a window of a preset bit size.

5. The method of claim 1, wherein, Further comprising: processing the frame data through an 8B10B encoding and decoding algorithm.

6. The method of claim 1, wherein, The frame header detection on the parallel data comprises: performing frame header detection on the parallel data by a data alignment module in the receiving serial-parallel conversion unit based on a data alignment enable signal.

7. A serial transceiver, characterized by comprising: a phase-locked loop configured to switch the clock frequency based on the instruction of transmission rate change, output clock frequency switching information, and repeatedly output current frame data transmitted by the serial transceiver; a sending data buffer configured to receive the repeatedly output current frame data; The sending end parallel-to-serial conversion unit is configured to read parallel valid data of a preset bit number in the current frame data in the sending data buffer, count the read bit number by using a counter, and after receiving the clock frequency switching information, determine whether the counted value is equal to the preset bit number value, and in response to the counted value being equal to the preset bit number value, determine that the parallel valid data is completed serializing to obtain serial data and output the serial data, and in response to the counted value being less than the preset bit number value, determine that the parallel valid data is not completed serializing, and according to a clock frequency switching coefficient in the clock frequency switching information, confirm a ratio of the switched clock frequency to the original clock frequency, and in response to the ratio being greater than or equal to the preset bit number value, pause reading the parallel valid data from the sending data buffer, and re-send the parallel valid data to the sending end parallel-to-serial conversion unit. And The receiving end serial-to-parallel conversion unit is configured to receive the serial data, convert the serial data into parallel data, perform frame header detection on the parallel data, and in response to detecting a frame header, determine that frame data where the frame header is located is aligned, and write the frame data into a receiving data buffer.

8. A computer-readable storage medium, characterized in that, The memory stores computer program instructions, and the computer program instructions are executed by the processor to implement the method in any one of claims 1-6. 9.A computer device, comprising a memory and a processor, and characterized in that, The memory stores a computer program, and the computer program is executed by the processor to execute the method in any one of claims 1-6.

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