Two-dimensional network-on-chip structure and routing method, device and storage medium thereof

Abstract

The application provides a two-dimensional network-on-chip structure and a routing method, device and equipment thereof and a storage medium, and relates to the technical field of communication. The two-dimensional network-on-chip structure comprises: a plurality of processing cores, any processing core comprising a routing node, the routing node comprising five input distributors and five output arbiters; any input distributor is used for sending a transmission request of a target data packet to a target output arbiter, the target output arbiter being determined based on a target routing direction, the target routing direction being determined based on destination address information of the target data packet and an X-Y dimension sequence routing strategy; the target output arbiter is used for responding to the transmission request to transmit the target data packet to a destination position corresponding to the target output arbiter, the destination position comprising one of four adjacent routing nodes or a pulse data packet codec interface. The application can better avoid the deadlock problem and improve the throughput of the two-dimensional network-on-chip structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a two-dimensional network-on-chip structure, a routing method, device and equipment thereof, and a storage medium. BACKGROUND

[0002] With the end of Moore's Law, in order to solve the communication problem between more and more processing cores on a single chip, the design idea of NoC (Network on Chip) architecture has developed rapidly.

[0003] At present, the communication mode between multiple processing cores in the NoC architecture mostly adopts routing technology. However, the current routing algorithm cannot well avoid deadlock, resulting in a decrease in the throughput of the NoC architecture. SUMMARY

[0004] The present application provides a routing method, device, electronic equipment and storage medium of a two-dimensional network-on-chip structure, to solve the defect of a decrease in the throughput in the prior art.

[0005] The present application provides a two-dimensional network-on-chip structure, comprising:

[0006] a plurality of processing cores, any processing core comprising a routing node, the routing node comprising five input distributors and five output arbiters;

[0007] The routing node is connected with four adjacent routing nodes corresponding to the routing node to form four routing directions of the routing node, and the four adjacent routing nodes comprise routing nodes of four adjacent processing cores corresponding to the any processing core.

[0008] The routing node is connected with a pulse data packet codec interface of the any processing core to form one routing direction of the routing node.

[0009] The five input distributors are used for receiving data packets sent by the four adjacent routing nodes and the pulse data packet codec interface, and the five output arbiters are used for sending data packets to the four adjacent routing nodes and the pulse data packet codec interface.

[0010] Any input distributor is used for sending a transmission request of a target data packet to a target output arbiter, the target output arbiter being determined based on a target routing direction, and the target routing direction being determined based on destination address information of the target data packet and an X-Y dimensional sequence routing strategy.

[0011] The target output arbiter is configured to respond to the transmission request to transmit the target data packet to a target destination corresponding to the target output arbiter, wherein the target destination comprises one of the four adjacent routing nodes or the pulse data packet codec interface.

[0012] The application further provides a routing method of a two-dimensional network-on-chip structure, the two-dimensional network-on-chip structure being the two-dimensional network-on-chip structure as described above, the method being applied to a first routing node, and the method comprising:

[0013] receiving a first target data packet sent by a second routing node, and determining a positional relationship between the second routing node and the first routing node in the two-dimensional network-on-chip structure, wherein the second routing node is an adjacent routing node of the first routing node;

[0014] determining a first target input distributor from five input distributors of the first routing node based on the positional relationship, and sending the first target data packet to the first target input distributor;

[0015] determining a first target routing direction based on destination address information of the first target data packet and an X-Y dimensional sequence routing strategy;

[0016] determining a first target output arbiter from the five output arbiters based on the first target routing direction;

[0017] sending, by the first target input distributor, a first transmission request of the first target data packet to the first target output arbiter;

[0018] responding, by the first target output arbiter, to the first transmission request to transmit the first target data packet to a first target destination corresponding to the first target output arbiter, wherein the first target destination comprises a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

[0019] According to the routing method of the two-dimensional network-on-chip structure provided by the application, the responding to the first transmission request comprises:

[0020] determining a responding time of the first transmission request based on a preset transmission request priority rule;

[0021] responding to the first transmission request based on the responding time;

[0022] The transmission request priority rule comprises at least one of the following:

[0023] The transmission request sent by the first input distributor has the highest priority, and the first input distributor is an input distributor corresponding to a pulse data packet codec interface;

[0024] The transmission request sent by the second input distributor has a higher priority than the transmission request sent by the third input distributor, the second input distributor is an input distributor corresponding to a first position relationship, the third input distributor is an input distributor corresponding to a second position relationship, the first position relationship is a same Y coordinate position on a two-dimensional network on chip, and the second position relationship is a same X coordinate position on the two-dimensional network on chip;

[0025] In a case where the first target output arbiter receives a third transmission request, the third transmission request is not responded, and the third transmission request meets a preset condition, a priority order of the first transmission request and the third transmission request is alternated in each response process, and the preset condition includes that a position relationship corresponding to the third transmission request and a position relationship corresponding to the first transmission request are both the first position relationship.

[0026] According to the two-dimensional network on chip structure provided by the application, a routing method of the two-dimensional network on chip structure is further provided.

[0027] In a case where it is determined based on multicast identification information of the first target data packet that the first target data packet needs to be copied, the first target data packet is copied to obtain a copy data packet, and the multicast identification information is used to determine whether a data packet needs to be copied.

[0028] Based on destination address information of the first target data packet, a third destination position is determined, and the third destination position is different from the first destination position.

[0029] The copy data packet is sent to the third destination position.

[0030] According to the routing method of the two-dimensional network on chip structure provided by the application, the multicast identification information includes identification bit values of a plurality of routing rounds, and a bit number of the multicast identification information is determined based on a number of the plurality of processing cores.

[0031] The first target data packet is determined whether to need to be copied based on the following steps:

[0032] Bit-by-bit analysis is performed on multicast identification information of the first target data packet to obtain an identification bit value of a current routing round.

[0033] Based on the identification bit value of the current routing round, it is determined whether the first target data packet needs to be copied.

[0034] According to the application, a routing method of a two-dimensional network-on-chip structure is provided, destination address information of the first target data packet comprises address bit values of multiple routing rounds, and the number of bits of the destination address information of the first target data packet is determined based on the number of the multiple processing cores.

[0035] The third destination position is determined based on the destination address information of the first target data packet.

[0036] The destination address information of the first target data packet is analyzed bit by bit to obtain address bit values of a current routing round.

[0037] The third destination position is determined based on a comparison result of the address bit values of the current routing round and source address information of the first routing node.

[0038] According to the application, a routing method of a two-dimensional network-on-chip structure is provided, destination address information of the first target data packet comprises address bit values of multiple routing rounds, and the number of bits of the destination address information of the first target data packet is determined based on the number of the multiple processing cores.

[0039] The second target data packet sent by the pulse data packet codec interface of the first routing node is received.

[0040] The second target input distributor corresponding to the pulse data packet codec interface of the first routing node is determined from the five input distributors of the first routing node, and the second target data packet is sent to the second target input distributor.

[0041] The second target routing direction is determined based on the destination address information of the second target data packet.

[0042] The second target output arbiter is determined from the five output arbiters of the first routing node based on the second target routing direction.

[0043] The second target data packet is sent to the second target output arbiter through the second target input distributor.

[0044] The second target data packet is transmitted to a second destination position corresponding to the second target output arbiter through the second target output arbiter in response to the second transmission request, and the second destination position comprises a fourth routing node adjacent to the first routing node or the pulse data packet codec interface of the first routing node.

[0045] The application further provides a routing device of a two-dimensional network-on-chip structure, the two-dimensional network-on-chip structure is as described above, the device is arranged in a first routing node, and the device comprises:

[0046] The data packet receiving module is configured to receive a first target data packet sent by a second routing node and determine a positional relationship between the second routing node and the first routing node on a two-dimensional network-on-chip, the second routing node being a neighboring routing node of the first routing node.

[0047] The distributor determining module is configured to determine a first target input distributor from five input distributors of the first routing node based on the positional relationship, and send the first target data packet to the first target input distributor.

[0048] The direction determining module is configured to determine a first target routing direction based on destination address information of the first target data packet and an X-Y dimensional sequential routing strategy.

[0049] The arbiter determining module is configured to determine a first target output arbiter from the five output arbiters based on the first target routing direction.

[0050] The request sending module is configured to send a first transmission request of the first target data packet to the first target output arbiter through the first target input distributor.

[0051] The request responding module is configured to respond to the first transmission request through the first target output arbiter, so as to transmit the first target data packet to a first target destination position corresponding to the first target output arbiter, the first target destination position including a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

[0052] The application further provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the routing method of the two-dimensional network-on-chip structure according to any one of the above when executing the program.

[0053] The application further provides a non-transitory computer readable storage medium, which stores a computer program executable by a processor, and the processor implements the routing method of the two-dimensional network-on-chip structure according to any one of the above when executing the program.

[0054] The application provides a two-dimensional network-on-chip structure, a routing method, device and equipment and a storage medium. BRIEF DESCRIPTION OF DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0056] Figure 1 A structural schematic diagram of the two-dimensional network-on-chip structure provided by the application;

[0057] Figure 2 One of the routing schematic diagrams of the two-dimensional network-on-chip structure provided by the application;

[0058] Figure 3 The second routing schematic diagram of the two-dimensional network-on-chip structure provided by the application;

[0059] Figure 4 The routing multicast schematic diagram of the two-dimensional network-on-chip structure provided by the application;

[0060] Figure 5 One of the flow schematic diagrams of the routing method of the two-dimensional network-on-chip structure provided by the application;

[0061] Figure 6 The second flow schematic diagram of the routing method of the two-dimensional network-on-chip structure provided by the application;

[0062] Figure 7 A structural schematic diagram of a routing device of a two-dimensional network-on-chip structure provided by the present application is shown in the figure;

[0063] Figure 8 A structural schematic diagram of an electronic device provided by the present application is shown in the figure. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0065] In the description of the embodiments of the present application, it should be noted that the orientations or positional relationships indicated by the terms “center”, “longitudinal”, “transverse”, “upper”, “lower”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “east”, “south”, “west”, “north”, “local” and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated thereby must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application. In addition, the terms “first”, “second”, “third” are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0066] In the description of the embodiments of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms “connected” and “connected” should be understood broadly, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0067] In the embodiments of the present application, unless otherwise explicitly specified and limited, the first feature is “on” or “under” the second feature, which can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature can be directly above or obliquely above the second feature, or only means that the horizontal height of the first feature is higher than that of the second feature. The first feature can be directly below or obliquely below the second feature, or only means that the horizontal height of the first feature is less than that of the second feature.

[0068] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the different embodiments or examples described in the present specification and the features of the different embodiments or examples can be combined and combined by those skilled in the art without contradiction. In addition, the term "a plurality of" means two or more.

[0069] In the past few decades, the processing power and integration of chips have doubled in 18 to 24 months according to the path of frequency multiplication and transistor scaling proposed by Moore's Law. In recent years, as Moore's Law approaches the end, the traditional path of relying on frequency scaling to improve chip operation speed has become unsustainable. Therefore, increasing the number of parallel processing cores on a single chip has become a reasonable choice.

[0070] Based on the above, in order to solve the communication problem between more and more processing cores on a single chip, similar to the organization structure of the brain, the design idea of NoC (Network on Chip) architecture commonly used for neural network calculation has developed rapidly. Common NoC topologies include 2D-Mesh structure, Tree structure, Ring structure, Star structure, Octagon structure, Spidergon structure, Torus structure and Butterfly structure. Among them, the 2D-Mesh structure is the most commonly used in neural network calculation.

[0071] And how to achieve higher communication efficiency based on the NoC architecture is an important issue at present. At present, the communication mode between multiple processing cores in the NoC architecture mostly adopts routing technology. However, the current routing algorithm cannot well avoid deadlock, resulting in low throughput of the NoC architecture. For example, the Tree structure is not as expandable and universal as the 2D-Mesh routing, and the on-chip communication bandwidth is low, especially when the number of processing cores of the on-chip network structure is less than 64, the average routing distance of the Tree structure is farther; and the 2D-Mesh structure does not realize the on-chip network routing algorithm that can avoid deadlock, which seriously restricts the throughput of the system.

[0072] In view of the above problems, the present application proposes the following embodiments. Figure 1 The structure diagram of the two-dimensional on-chip network structure provided by the present application is shown in Figure 1The two-dimensional on-chip network structure includes multiple processing cores 1, each processing core includes a routing node 11, and the routing node includes five input distributors 111 and five output arbiters 112.

[0073] Here, the input distributor 111 is used to send a data packet to be transmitted to the corresponding output arbiter 112. More specifically, the input distributor 111 is used to receive a data packet sent by one of the four adjacent routing nodes of the routing node 11, or to receive a data packet sent by the burst packet codec interface 12, and to send a transmission request for the data packet to the corresponding output arbiter 112.

[0074] Here, the output arbiter 112 is used to determine the transmission location of the data packet to be transmitted. More specifically, the output arbiter 112 is used to send the data packet to be transmitted to one of the four adjacent routing nodes of the routing node 11, or to send the data packet to be transmitted to the pulse packet codec interface 12, and to respond to transmission requests, thereby receiving the data packet sent by the input distributor 111 and transmitting the data packet to the location corresponding to the output arbiter 112.

[0075] In one embodiment, processing core 1 receives a data packet sent by another processing core. The data packet is first received by input distributor 111 in routing node 11 and then sent by input distributor 111 to output arbiter 112. Output arbiter 112 transmits the data packet to processing core 1 through pulse data packet codec interface 12.

[0076] In another embodiment, processing core 1 sends a data packet to another processing core. The data packet is first sent by pulse packet codec interface 12 to input distributor 111, which then sends the data packet to output arbiter 112. Output arbiter 112 then transmits the data packet to the other processing core via an adjacent routing node. The process of receiving the data packet by the other processing core is similar to that in the above embodiment and will not be repeated here.

[0077] The routing node 11 is connected to four adjacent routing nodes corresponding to the routing node 11 to form four routing directions of the routing node 11, and the four adjacent routing nodes include the routing nodes of the four adjacent processing cores corresponding to any one of the processing cores 1;

[0078] The routing node 11 is connected to the pulse data packet encoding and decoding interface 12 of any one of the processing cores 1 to form a routing direction of the routing node.

[0079] Here, the pulse packet codec interface 12 is an interface for the processing core 1 to communicate with the routing node 11 .

[0080] Here, the routing direction is the transmission direction of the data packet on the routing node 11. Since the routing node 11 is connected with four adjacent routing nodes in four directions, and is connected with the pulse data packet codec interface 12 of the any processing core 1 at the same time, i.e. connected with the pulse data packet codec interface 12 of the local core at the same time, the routing node 11 has five routing directions.

[0081] For the convenience of understanding, it is assumed that the four routing directions formed by the connection of the routing node 11 with the four adjacent routing nodes corresponding to the routing node 11 are east direction, west direction, south direction and north direction respectively, and the routing direction formed by the connection of the routing node 11 with the pulse data packet codec interface 12 of the any processing core 1 is local direction, based on which the routing directions of the routing node 11 have east direction, west direction, south direction, north direction and local direction. Correspondingly, the routing node 11 can be connected with the adjacent routing node in the east direction, the routing node 11 can be connected with the adjacent routing node in the west direction, the routing node 11 can be connected with the adjacent routing node in the south direction, the routing node 11 can be connected with the adjacent routing node in the north direction, and the routing node 11 can be connected with the pulse data packet codec interface 12 in the local direction.

[0082] For example, the routing direction can be described according to the relative position relationship between the routing node 11 and the four adjacent routing nodes. Referring to Figure 2 Taking a two-dimensional network-on-chip structure composed of 16 cores as an example, Figure 2 The node in the figure is a routing node, and the 4-bit destination address information of the data packet includes 2-bit X address and 2-bit Y address. For example, the X address is Figure 2 The core address 00, 01 in the figure, and the Y address is Figure 2 The core address 00, 01 in the figure. The two-dimensional network-on-chip structure can be described in the X-Y coordinate system. In the X-Y coordinate system, the four routing directions are east direction E in the direction of increasing X address, west direction W in the direction of decreasing X address, south direction S in the direction of increasing Y address, and north direction N in the direction of decreasing Y address.

[0083] It should be noted that the processing core 1 where the routing node 11 in the embodiment of the application is located is in the central region of the two-dimensional network-on-chip structure, i.e. the routing node 11 has four adjacent routing nodes. In addition, if the processing core where the routing node is located is in the edge region of the two-dimensional network-on-chip structure, i.e. the routing node has three adjacent routing nodes; if the processing core where the routing node is located is in the corner region of the two-dimensional network-on-chip structure, i.e. the routing node has two adjacent routing nodes.

[0084] The five input distributors are used for receiving data packets sent by the four adjacent routing nodes and the pulse data packet codec interface, and the five output arbitrators are used for sending data packets to the four adjacent routing nodes and the pulse data packet codec interface.

[0085] Any of the input distributors is used for sending a transmission request of a target data packet to a target output arbitrator, the target output arbitrator being determined based on a target routing direction, the target routing direction being determined based on destination address information of the target data packet and an X-Y dimensional sequence routing strategy.

[0086] There is one input distributor 111 and one output arbitrator 112 in each of the five routing directions of the routing node 11, that is, there is one input channel and one output channel corresponding to each routing direction, and one input distributor 111 can be deployed on the input channel and one output arbitrator 112 can be deployed on the output channel.

[0087] For ease of understanding, it is assumed that the four routing directions formed by the connection of the routing node 11 and the four adjacent routing nodes corresponding to the routing node 11 are east direction, west direction, south direction and north direction, and it is assumed that the routing direction formed by the connection of the routing node 11 and the pulse data packet codec interface 12 of the any processing core 1 is local direction. Referring to Figure 3 The data packet sent by the adjacent routing node in the west direction is input to the input distributor, and the input distributor can transmit the data packet to the output arbitrators corresponding to the routing directions of east direction, south direction, north direction and local direction; the data packet sent by the adjacent routing node in the east direction is input to the input distributor, and the input distributor can transmit the data packet to the output arbitrators corresponding to the routing directions of west direction, south direction, north direction and local direction; the data packet sent by the adjacent routing node in the north direction is input to the input distributor, and the input distributor can transmit the data packet to the output arbitrators corresponding to the routing directions of south direction and local direction; the data packet sent by the adjacent routing node in the south direction is input to the input distributor, and the input distributor can transmit the data packet to the output arbitrators corresponding to the routing directions of north direction and local direction; the data packet sent by the adjacent routing node in the local direction is input to the input distributor, and the input distributor can transmit the data packet to the output arbitrators corresponding to the routing directions of east direction, west direction, south direction, north direction and local direction.

[0088] The target output arbitrator is used for responding to the transmission request to transmit the target data packet to a destination position corresponding to the target output arbitrator, and the destination position includes one of the four adjacent routing nodes or the pulse data packet codec interface.

[0089] Here, the target data packet is a data packet to be transmitted by the input distributor. Destination address information of the target data packet is address information of a final transmission position of the target data packet, i.e. address information of a processing core to which the target data packet is finally transmitted. The destination address information is used to determine a routing direction of the target data packet. Referring to Figure 4 Taking a two-dimensional on-chip network structure composed of 16 cores as an example, the destination address information can be 4-bit information, such as 0000, 0100, 0001, 0010, etc. Figure 4 A in the above is 1000, 1100, the destination address information can be 0000, 0100, 0001, 0010, etc., further, the destination address information includes an X address and a Y address.

[0090] Specifically, after the target output arbiter responds to the transmission request, the target data packet corresponding to the transmission request is sent to the target output arbiter.

[0091] Considering that a condition for deadlock occurrence is that a routing node has a limited cache space, when the cache space of node A is full, a data packet sending request sent by node B to node A will not be responded, and the data packet of node B will wait until the cache space of node A is available, and then the data packet is sent, so that the cache space of node B is continuously occupied. If a "request-occupation" cache resource dependency loop is formed among multiple nodes, a so-called deadlock phenomenon occurs. Based on this, an embodiment of the present application adopts an X-Y dimensional sequence routing strategy to determine a routing direction.

[0092] Here, the X-Y dimensional sequence routing strategy is to describe a two-dimensional on-chip network structure in an X-Y coordinate system. The X-Y dimensional sequence routing strategy provides that a target data packet is first routed in an X-axis direction, and then routed in a Y-axis direction when an X address of the target address information is equal to an X address of the target data packet.

[0093] The two-dimensional network-on-chip structure provided by the embodiment of the present application comprises a plurality of processing cores, and a routing node in any processing core comprises five input distributors and five output arbiters, the five input distributors are used to receive data packets transmitted by pulse data packet codec interfaces of four adjacent routing nodes and the processing core, so that data packets in five directions can be received, and the target output arbiter is used to respond to a transmission request to transmit a target data packet to a destination position corresponding to the target output arbiter, the destination position comprises one of the four adjacent routing nodes or the pulse data packet codec interface, so that the five output arbiters can transmit data packets in five directions, thereby realizing parallel processing of five data packets, and finally improving the throughput of the two-dimensional network-on-chip structure; any input distributor is used to transmit a transmission request of a target data packet to a target output arbiter, the target output arbiter is determined based on a target routing direction, and the target routing direction is determined based on destination address information of the target data packet and an X-Y dimension sequence routing strategy, so that the target output arbiter can be determined from the five output arbiters based on the X-Y dimension sequence routing strategy, thereby better avoiding a deadlock problem, and finally improving the throughput of the two-dimensional network-on-chip structure.

[0094] Based on the two-dimensional network-on-chip structure described above, the present application further provides a routing method of the two-dimensional network-on-chip structure, which is applied to a first routing node. Further, the execution subject of the routing method can be a controller on an FPGA (Field Programmable Gate Array) or a controller on a CPU (central processing unit), and the embodiment of the present application does not limit this. Figure 5 One of the flowcharts of the routing method of the two-dimensional network-on-chip structure provided by the present application is shown in Figure 5 The routing method of the two-dimensional network-on-chip structure comprises the following steps.

[0095] In step 510, a first target data packet transmitted by a second routing node is received, and a positional relationship between the second routing node and the first routing node in the two-dimensional network-on-chip is determined, the second routing node being an adjacent routing node of the first routing node.

[0096] Here, the first routing node can be any routing node in the two-dimensional network-on-chip structure.

[0097] Here, the second routing node is an adjacent routing node of the first routing node, and based on the establishment of an X-Y coordinate system in the two-dimensional network-on-chip structure, the positional relationship between the first routing node and the second routing node in the two-dimensional network-on-chip structure can be determined.

[0098] The positional relationship between the first routing node and the second routing node includes a first positional relationship, a second positional relationship, a third positional relationship and a fourth positional relationship. The first positional relationship is a first input direction of the first routing node, the second positional relationship is a second input direction of the first routing node, the third positional relationship is a third input direction of the first routing node, and the fourth positional relationship is a fourth input direction of the first routing node.

[0099] In an embodiment, the first input direction is an east direction, the second input direction is a west direction, the third input direction is a south direction, and the fourth input direction is a north direction. Based on this, the first positional relationship is an east direction of the first routing node, the second positional relationship is a west direction of the first routing node, the third positional relationship is a south direction of the first routing node, and the fourth positional relationship is a north direction of the first routing node.

[0100] It should be noted that the processing core where the first routing node is located is in the central region of the two-dimensional network-on-chip structure, and the first routing node has four adjacent routing nodes. There are four possibilities for the positional relationship between the first routing node and the second routing node.

[0101] In step 520, based on the positional relationship, a first target input distributor is determined from the five input distributors of the first routing node, and the first target data packet is sent to the first target input distributor.

[0102] It should be noted that the five input distributors include an input distributor corresponding to the first positional relationship, an input distributor corresponding to the second positional relationship, an input distributor corresponding to the third positional relationship, an input distributor corresponding to the fourth positional relationship, and an input distributor corresponding to the fifth positional relationship. Here, the first target input distributor is determined according to the positional relationship between the first routing node and the first target data packet.

[0103] In an embodiment, the input distributor corresponding to the first positional relationship is an input distributor in the east direction of the first routing node, the input distributor corresponding to the second positional relationship is an input distributor in the west direction of the second routing node, the input distributor corresponding to the third positional relationship is an input distributor in the south direction of the third routing node, the input distributor corresponding to the fourth positional relationship is an input distributor in the north direction of the fourth routing node, and the input distributor corresponding to the fifth positional relationship is an input distributor in the local direction of the fifth routing node.

[0104] In step 530, based on the destination address information of the first target data packet and the X-Y dimensional order routing strategy, a first target routing direction is determined.

[0105] Here, the destination address information of the first target data packet can be the address information of one of the four adjacent routing nodes of the first routing node and the pulse data packet codec interface connected to the first routing node.

[0106] Here, the X-Y dimension sequence routing strategy first performs transmission in the X-axis direction and then performs transmission in the Y-axis direction according to the positional relationship between the first routing node and the second routing node. Specifically, the first performs transmission in the east-west direction, and then performs transmission in the south-north direction.

[0107] Here, the first target routing direction includes a first routing direction, a second routing direction, a third routing direction, a fourth routing direction, and a fifth routing direction. The first routing direction is the first output direction of the first routing node, the second routing direction is the second output direction of the first routing node, the third routing direction is the third output direction of the first routing node, the fourth routing direction is the fourth output direction of the first routing node, and the fifth routing direction is the fifth output direction of the first routing node.

[0108] In an embodiment, the first output direction is the east direction, the second output direction is the west direction, the third output direction is the south direction, the fourth output direction is the north direction, and the fifth output direction is the local direction. Based on this, the first routing direction is the east direction of the first routing node, the second routing direction is the west direction of the first routing node, the third routing direction is the south direction of the first routing node, the fourth routing direction is the north direction of the first routing node, and the fifth routing direction is the local direction of the first routing node.

[0109] Specifically, referring to Figure 3 , the target data packet is input from the west direction, and the first target routing direction can be the east, north, south, and local directions; the target data packet is input from the east direction, and the first target routing direction can be the west, north, south, and local directions; the target data packet is input from the north direction, and the first target routing direction can be the south and local directions; the target data packet is input from the south direction, and the first target routing direction can be the north and local directions; the target data packet is input from the local direction, and the first target routing direction can be the west, east, north, south, and local directions.

[0110] Step 540, determining a first target output arbiter from the five output arbiters based on the first target routing direction.

[0111] Here, the first target output arbiter includes a first output arbiter, a second output arbiter, a third output arbiter, a fourth output arbiter, and a fifth output arbiter.

[0112] In an embodiment, the first output arbiter is an output arbiter in an east direction of the first routing node, the second output arbiter is an output arbiter in a west direction of the first routing node, the third output arbiter is an output arbiter in a south direction of the first routing node, the fourth output arbiter is an output arbiter in a north direction of the first routing node, and the fifth output arbiter is an output arbiter in a local direction of the first routing node. Based on this, the first target output arbiter is the output arbiter in the east direction of the first routing node, the second routing direction is the output arbiter in the west direction of the first routing node, the third routing direction is the output arbiter in the south direction of the first routing node, the fourth routing direction is the output arbiter in the north direction of the first routing node, and the fifth routing direction is the output arbiter in the local direction of the first routing node.

[0113] At step 550, the first transmission request of the first target data packet is sent to the first target output arbiter through the first target input distributor.

[0114] At step 560, the first transmission request is responded to by the first target output arbiter, so as to transmit the first target data packet to a first target destination position corresponding to the first target output arbiter, wherein the first target destination position comprises a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

[0115] Referring to Figure 3 The west direction input distributor can send transmission requests to the output arbiters in the east, north, south, and local directions, i.e., four kinds of transmission requests; the east direction input distributor can send transmission requests to the output arbiters in the west, north, south, and local directions, i.e., four kinds of transmission requests; the north direction input distributor can send transmission requests to the output arbiters in the south and local directions, i.e., two kinds of transmission requests; the south direction input distributor can send transmission requests to the output arbiters in the north and local directions, i.e., two kinds of transmission requests; and the local direction input distributor can send transmission requests to the output arbiters in the east, south, west, north, and local directions, i.e., five kinds of transmission requests.

[0116] Here, responding to the transmission request is used to confirm whether the first target output arbiter can transmit data packets with the first target input distributor.

[0117] Here, the first target destination position comprises a routing node corresponding to the first output direction, a routing node corresponding to the second output direction, a routing node corresponding to the third output direction, a routing node corresponding to the fourth output direction, and a pulse data packet codec interface corresponding to the fifth output direction.

[0118] In an embodiment, the first output direction is an east direction, the second output direction is a west direction, the third output direction is a south direction, the fourth output direction is a north direction, and the fifth output direction is a local direction. Based on this, the first destination position can be a routing node corresponding to the east direction, a routing node corresponding to the west direction, a routing node corresponding to the south direction, a routing node corresponding to the north direction, or a pulse data packet coding interface corresponding to the local direction.

[0119] The routing method of the two-dimensional network-on-chip structure provided by the embodiment of the application includes the following steps: a first routing node receives a first target data packet sent by a second routing node, and determines a first target input distributor from five input distributors of the first routing node based on a positional relationship between the second routing node and the first routing node in the two-dimensional network-on-chip structure, and sends the first target data packet to the first target input distributor, so that data packets in five directions can be received; a first target routing direction is determined based on destination address information of the first target data packet and an X-Y dimension sequence routing strategy, and a first target output arbiter is determined from five output arbiters based on the first target routing direction, so that the target output arbiter can be determined from the five output arbiters based on the X-Y dimension sequence routing strategy, and a deadlock problem is better avoided, and the throughput of the two-dimensional network-on-chip structure is finally improved; a first transmission request of the first target data packet is sent to the first target output arbiter through the first target input distributor; the first transmission request is responded to through the first target output arbiter, so that the first target data packet is transmitted to a first destination position corresponding to the first target output arbiter, and the first destination position includes a third routing node adjacent to the first routing node or a pulse data packet coding interface of the first routing node, so that data packets in the five directions can be sent based on the five output arbiters, parallel processing of the five data packets is realized, and the throughput of the two-dimensional network-on-chip structure is finally improved.

[0120] Based on any of the above embodiments, considering that the condition for routing starvation to occur is that when the NoC network traffic is very large, the output channel is continuously in an occupied state, and the request from the input channel with the lowest priority will always wait until the other input channels no longer occupy the output channel, resulting in a sharp increase in routing delay of a specific channel and path, and a large increase in the risk of routing congestion. Based on this, in the method, in step 560, responding to the first transmission request includes:

[0121] Determining a response time of the first transmission request based on a preset transmission request priority rule.

[0122] Responding to the first transmission request based on the response time.

[0123] The transmission request priority rule includes at least one of the following:

[0124] The first input distributor has the highest priority of the transmission request, and the first input distributor is an input distributor corresponding to the pulse data packet codec interface.

[0125] The second input distributor has a higher priority of the transmission request than the third input distributor, the second input distributor is an input distributor corresponding to the first position relationship, and the third input distributor is an input distributor corresponding to the second position relationship.

[0126] In a case where the first target output arbiter receives a third transmission request, the third transmission request is not responded, and the third transmission request meets a preset condition, the priority order of the first transmission request and the third transmission request is alternated in each response process, and the preset condition includes that the position relationship corresponding to the third transmission request and the position relationship corresponding to the first transmission request are both the first position relationship.

[0127] Here, the input distributor corresponding to the pulse data packet codec interface is an input distributor of the local input channel.

[0128] In an embodiment, for the five output channels of east, west, south, north and local, the transmission request sent by the local input channel has the highest priority, so as to reduce the congestion of the local input channel, avoid the core circuit from pausing work, and improve the throughput.

[0129] Here, the second input distributor is an input distributor with the same Y coordinate, and the second input distributor is an input distributor with the same X coordinate.

[0130] In an embodiment, the first input distributor can be an input distributor in the east and west directions, and the second input distributor can be an input distributor in the south and north directions. For the south, north and local output channels, the request from the east and west input channels has a higher priority than the south and north input channels. Because the turning from the east and west input channels to the south and north output channels only occurs when the data packet ends the X direction routing and turns to the Y direction routing, and the turning from the east and west input channels to the local output channel only occurs when the source core and the target core of the data packet have the same Y address and end the X direction routing. The traffic of the two cases is small, the frequency of occupying the output arbiter is low, and the two cases can be processed preferentially.

[0131] It should be noted that the two cases with small traffic are because when the two cases occur, only the output arbiter in the local and Y directions is occupied.

[0132] Here, the third transmission request is a request sent by an input distributor on two input channels in the X axis, including a request received by an output channel in the south direction for input channels in the east and west directions; a request received by an output channel in the north direction for input channels in the east and west directions; and a request received by an output arbitrator in the local direction for input channels in the east and west directions.

[0133] In an embodiment, the first transmission request and the third transmission request are requests received by an output channel in the north direction from input channels in the east and west directions, and the first transmission request and the third transmission request are alternately responded, that is, the priority of the input channel of the last received request is lowered.

[0134] The routing method of the two-dimensional network-on-chip structure provided by the embodiment of the application has the highest priority for requests from local input channels, and ensures normal operation of the core circuit. The two cases of turning from the east and west input channels to the south and north output channels and turning from the east and west input channels to the local output channel are preferentially processed, and the two cases have smaller traffic and lower occupation frequency of the output arbitrator. The first transmission request and the third transmission request are alternately responded, and the same input channel is avoided from being always assigned a low priority. Through the above-mentioned means, the routing delay of a specific channel and path is further reduced, the risk of routing congestion is greatly reduced, and finally the routing starvation problem is solved.

[0135] Based on any of the above embodiments, the method further comprises:

[0136] In a case where it is determined, based on the multicast identification information of the first target data packet, that the first target data packet needs to be copied, copying the first target data packet to obtain a copied data packet, the multicast identification information being used to determine whether a data packet needs to be copied.

[0137] In an embodiment, taking a two-dimensional network-on-chip structure composed of 16 cores as an example, the multicast identification information can be 4-bit information. Referring to Figure 4 As shown in F in the figure, each bit of F identifies multicast of a corresponding bit of destination address information A. If F[i] is 1, it indicates that both A[i] = 0 and A[i] = 1 are target addresses. The routing module will analyze A and F bit by bit, and determine whether a data packet needs to be multicast copied according to the corresponding bit.

[0138] Based on the destination address information of the first target data packet, a third destination position is determined, the third destination position being different from the first destination position.

[0139] Here, the third destination position is a destination position of a copied data packet of the first target data packet.

[0140] In an embodiment, taking a two-dimensional network-on-chip structure composed of 16 cores as an example, the destination address information can be 4-bit information. Referring to Figure 4The core at address 1111 generates a data packet with A=1000 and F=0101. The second bit of F is 1 and the second bit of A is 0, so the data packet is copied and the third destination of the copied data packet is 1100.

[0141] The copied data packet is sent to the third destination.

[0142] In an embodiment, referring to Figure 4 For example, in a two-dimensional network-on-chip structure with 16 cores, when a data packet is routed to the core at address 1101, a copy of the data packet is generated and sent to the core at address 1100. Thus, the copied data packet is sent to the third destination.

[0143] The routing method of the two-dimensional network-on-chip structure provided by the embodiment of the application copies a first target data packet based on multicast identification information of the first target data packet to obtain a copied data packet, and sends the copied data packet to a third destination, thereby implementing a routing multicast strategy. As a solution to high-speed parallel data transmission, the routing multicast strategy can effectively alleviate the transmission burden of a communication link and improve the utilization rate of network bandwidth.

[0144] In any of the above embodiments, the multicast identification information includes identification bit values of multiple routing rounds, and the number of bits of the multicast identification information is determined based on the number of the multiple processing cores.

[0145] The first target data packet is determined whether to be copied based on the following steps:

[0146] The multicast identification information of the first target data packet is analyzed bit by bit to obtain an identification bit value of a current routing round.

[0147] Based on the identification bit value of the current routing round, it is determined whether the first target data packet needs to be copied.

[0148] Here, the multicast identification information includes identification bit values of multiple routing rounds, and the number of bits of the multicast identification information is determined based on the number of the multiple processing cores.

[0149] In an embodiment, for example, in a two-dimensional network-on-chip structure with 16 cores, the multicast identification information can be 4-bit information and the total routing round can be 4 times. Referring to Figure 4The core at address 1111 generates a data packet with destination address information A=1000 and multicast identification information F=0101. Analyzing A and F bit by bit, in the first routing round, the first bit of F is 0 and the first bit of A is 1, indicating that the data packet has reached the target address and no routing duplication is needed. In the second routing round, the second bit of F is 1 and the second bit of A is 0, indicating that the data packet needs to be duplicated, and the duplicated data packet enters the core at address 1011, and the second bit of F is cleared. In the third routing round, the two data packets are routed to the cores at addresses 1001 and 1101 respectively. In the fourth routing round, the fourth bit of F is 1 and the fourth bit of A is 0, indicating that the two data packets need to be duplicated to the cores at addresses 1000 and 1100 respectively. Thus, the data packet completes 1 / 4 duplication.

[0150] The routing method of the two-dimensional network-on-chip structure provided by the embodiment of the application determines the bit number of the multicast identification information based on the number of the plurality of processing cores, and then determines whether the first target data packet needs to be duplicated. The multicast duplication technology is finally realized, which can effectively alleviate the transmission burden of the communication link and improve the utilization rate of the network bandwidth.

[0151] In any of the above embodiments, the destination address information of the first target data packet includes address bit values of a plurality of routing rounds, and the bit number of the destination address information of the first target data packet is determined based on the number of the plurality of processing cores.

[0152] The third destination position is determined based on the destination address information of the first target data packet.

[0153] The destination address information of the first target data packet is analyzed bit by bit to obtain an address bit value of a current routing round.

[0154] The third destination position is determined based on a comparison result of the address bit value of the current routing round and source address information of the first routing node.

[0155] Here, the bit number of the destination address information of the first target data packet needs to be determined based on the number of the plurality of processing cores. In an embodiment, taking a two-dimensional network-on-chip structure composed of 16 cores as an example, the bit number of the destination address information of the first target data packet is 4.

[0156] The routing method of the two-dimensional network-on-chip structure provided by the embodiment of the application determines the address bit value of the current routing round based on the destination address information of the first target data packet, and provides support for determining the third destination position by comparing the address bit value of the routing round with the source address information of the first routing node, thereby realizing the multicast duplication technology, and finally effectively alleviating the transmission burden of the communication link and improving the utilization rate of the network bandwidth.

[0157] Based on any of the above embodiments, Figure 6 As shown in FIG. 2, the routing method of the two-dimensional network-on-chip structure provided by the present application comprises the following steps: Figure 6

[0158] In step 610, a second target data packet sent by the pulse data packet codec interface of the first routing node is received.

[0159] In step 620, a second target input distributor corresponding to the pulse data packet codec interface of the first routing node is determined from the five input distributors of the first routing node, and the second target data packet is sent to the second target input distributor.

[0160] Here, the second target data packet is a data packet sent by the first routing node in the local direction.

[0161] Here, the second target input distributor is an input distributor in the local direction of the first routing node.

[0162] Only one input distributor corresponds to the pulse data packet codec interface among the five input distributors.

[0163] In step 630, a second target routing direction is determined based on the destination address information of the second target data packet.

[0164] Here, the destination address information of the second target data packet can be the address information of one of the four adjacent routing nodes of the first routing node and the pulse data packet codec interface connected to the first routing node.

[0165] Here, the second target routing direction includes a first routing direction, a second routing direction, a third routing direction, a fourth routing direction, and a fifth routing direction. The first routing direction is the first output direction of the first routing node, the second routing direction is the second output direction of the first routing node, the third routing direction is the third output direction of the first routing node, the fourth routing direction is the fourth output direction of the first routing node, and the fifth routing direction is the fifth output direction of the first routing node.

[0166] In an embodiment, the first output direction is the east direction, the second output direction is the west direction, the third output direction is the south direction, the fourth output direction is the north direction, and the fifth output direction is the local direction. Based on this, the first routing direction is the east direction of the first routing node, the second routing direction is the west direction of the first routing node, the third routing direction is the south direction of the first routing node, the fourth routing direction is the north direction of the first routing node, and the fifth routing direction is the local direction of the first routing node.

[0167] ​Step 640, determining a second target output arbiter from the five output arbiters of the first routing node based on the second target routing direction.

[0168] Here, the second target output arbiter includes the first output arbiter, the second output arbiter, the third output arbiter, the fourth output arbiter, and the fifth output arbiter.

[0169] In an embodiment, the first output arbiter is an output arbiter in the east direction of the first routing node, the second output arbiter is an output arbiter in the west direction of the first routing node, the third output arbiter is an output arbiter in the south direction of the first routing node, the fourth output arbiter is an output arbiter in the north direction of the first routing node, and the fifth output arbiter is an output arbiter in the local direction of the first routing node. Based on this, the first target output arbiter is an output arbiter in the east direction of the first routing node, the second routing direction is an output arbiter in the west direction of the first routing node, the third routing direction is an output arbiter in the south direction of the first routing node, the fourth routing direction is an output arbiter in the north direction of the first routing node, and the fifth routing direction is an output arbiter in the local direction of the first routing node.

[0170] Step 650, sending a second transmission request of the second target data packet to the second target output arbiter through the second target input distributor.

[0171] Step 660, responding to the second transmission request through the second target output arbiter to transmit the second target data packet to a second target position corresponding to the second target output arbiter, the second target position including a fourth routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

[0172] In an embodiment, referring to Figure 3 The local direction input distributor can send transmission requests to output arbiters in the east, south, west, north, and local directions, i.e., five kinds of transmission requests.

[0173] Here, responding to the transmission request is used to confirm whether the second target output arbiter can transmit data packets with the second target input distributor.

[0174] Here, the second target position includes a routing node corresponding to the first output direction, a routing node corresponding to the second output direction, a routing node corresponding to the third output direction, a routing node corresponding to the fourth output direction, and a pulse data packet codec interface corresponding to the fifth output direction.

[0175] In an embodiment, the first output direction is an east direction, the second output direction is a west direction, the third output direction is a south direction, the fourth output direction is a north direction, and the fifth output direction is a local direction. Based on this, the first destination position can be a routing node corresponding to the east direction, a routing node corresponding to the west direction, a routing node corresponding to the south direction, a routing node corresponding to the north direction, or a pulse data packet codec interface corresponding to the local direction.

[0176] The routing device of the two-dimensional network-on-chip structure provided by the application is described below. The routing device of the two-dimensional network-on-chip structure described below can be referred to in correspondence with the routing method of the two-dimensional network-on-chip structure described above.

[0177] Figure 7 A structural schematic diagram of the routing device of the two-dimensional network-on-chip structure provided by the application is shown in FIG. 1. The routing device of the two-dimensional network-on-chip structure includes: Figure 7

[0178] The packet receiving module 710 is configured to receive a first target data packet sent by a second routing node and determine a positional relationship between the second routing node and the first routing node in the two-dimensional network-on-chip structure, where the second routing node is a neighboring routing node of the first routing node.

[0179] The distributor determining module 720 is configured to determine a first target input distributor from five input distributors of the first routing node based on the positional relationship and send the first target data packet to the first target input distributor.

[0180] The direction determining module 730 is configured to determine a first target routing direction based on destination address information of the first target data packet and an X-Y dimensional order routing strategy.

[0181] The arbiter determining module 740 is configured to determine a first target output arbiter from the five output arbiters based on the first target routing direction.

[0182] The request sending module 750 is configured to send a first transmission request of the first target data packet to the first target output arbiter through the first target input distributor.

[0183] The request response module 760 is configured to respond to the first transmission request through the first target output arbiter to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, where the first destination position includes a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

[0184] Figure 8 ​An example of a schematic diagram of a physical structure of an electronic device is shown in Figure 8 As shown, the electronic device can include a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 complete mutual communication through the communications bus 840. The processor 810 can invoke a logical instruction in the memory 830 to execute a routing method of a two-dimensional network-on-chip structure, the method including: receiving a first target data packet sent by a second routing node, and determining a positional relationship between the second routing node and the first routing node in a two-dimensional network-on-chip, the second routing node being a neighboring routing node of the first routing node; determining a first target input distributor from five input distributors of the first routing node based on the positional relationship, and sending the first target data packet to the first target input distributor; determining a first target routing direction based on destination address information of the first target data packet and an X-Y dimension sequence routing strategy; determining a first target output arbiter from the five output arbiters based on the first target routing direction; sending a first transmission request of the first target data packet to the first target output arbiter through the first target input distributor; and responding to the first transmission request through the first target output arbiter to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, the first destination position including a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

[0185] In addition, the logical instruction in the memory 830 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0186] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements a routing method of a two-dimensional network-on-chip structure as provided by any of the above methods, the method comprising: receiving a first target data packet sent by a second routing node, and determining a positional relationship between the second routing node and the first routing node in the two-dimensional network-on-chip, the second routing node being a neighboring routing node of the first routing node; determining a first target input distributor from five input distributors of the first routing node based on the positional relationship, and sending the first target data packet to the first target input distributor; determining a first target routing direction based on destination address information of the first target data packet and an X-Y dimensional sequence routing strategy; determining a first target output arbiter from the five output arbiters based on the first target routing direction; sending, by the first target input distributor, a first transmission request of the first target data packet to the first target output arbiter; and responding, by the first target output arbiter, to the first transmission request to transmit the first target data packet to a first destination position corresponding to the first target output arbiter, the first destination position comprising a third routing node adjacent to the first routing node or a pulse data packet codec interface of the first routing node.

[0187] The apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0188] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be implemented by means of software plus necessary universal hardware platforms, and of course can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0189] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A two-dimensional network-on-chip structure, characterized in that: include: a plurality of processing cores, each processing core including a routing node, wherein the routing node includes five input distributors and five output arbiters; The routing node is connected to four adjacent routing nodes corresponding to the routing node to form four routing directions of the routing node, and the four adjacent routing nodes include routing nodes of four adjacent processing cores corresponding to any one processing core; The routing node is connected to the pulse data packet codec interface of any one of the processing cores to form a routing direction of the routing node; The five input distributors are used to receive data packets sent by the four adjacent routing nodes and the pulse data packet codec interface, and the five output arbiters are used to send data packets to the four adjacent routing nodes and the pulse data packet codec interface; Any of the input distributors is used to send a transmission request of a target data packet to a target output arbitrator, wherein the target output arbitrator is determined based on a target routing direction, and the target routing direction is determined based on the destination address information of the target data packet and an XY dimensional order routing policy; The target output arbiter is used to respond to the transmission request to transmit the target data packet to a destination location corresponding to the target output arbiter, where the destination location includes one routing node among the four adjacent routing nodes or the pulse data packet encoding and decoding interface.

2. A routing method for a two-dimensional network-on-chip structure, characterized in that: The two-dimensional network-on-chip structure is the two-dimensional network-on-chip structure according to claim 1, and the method is applied to a first routing node, the method comprising: receiving a first target data packet sent by a second routing node, and determining a positional relationship between the second routing node and the first routing node in a two-dimensional network-on-chip, where the second routing node is an adjacent routing node of the first routing node; Based on the position relationship, determining a first target input distributor from the five input distributors of the first routing node, and sending the first target data packet to the first target input distributor; Determining a first target routing direction based on the destination address information of the first target data packet and an XY-dimensional order routing strategy; determining a first target output arbitrator from the five output arbitrators based on the first target routing direction; sending, through the first target input distributor, a first transmission request for the first target data packet to the first target output arbitrator; The first transmission request is responded to through the first target output arbitrator to transmit the first target data packet to a first destination location corresponding to the first target output arbitrator, wherein the first destination location includes a third routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

3. The routing method of the two-dimensional network-on-chip structure according to claim 2, characterized in that: The responding to the first transmission request comprises: Determining a response time for the first transmission request based on a preset transmission request priority rule; responding to the first transmission request based on the response time; The transmission request priority rule includes at least one of the following: The transmission request sent by the first input distributor has the highest priority, and the first input distributor is the input distributor corresponding to the pulse data packet encoding and decoding interface; The priority of the transmission request sent by the second input distributor is higher than the priority of the transmission request sent by the third input distributor, the second input distributor is the input distributor corresponding to the first positional relationship, and the third input distributor is the input distributor corresponding to the second positional relationship, the first positional relationship is that the Y coordinate positions on the two-dimensional on-chip network are the same, and the second positional relationship is that the X coordinate positions on the two-dimensional on-chip network are the same; When the first target output arbiter receives a third transmission request and the third transmission request is not responded to, and the third transmission request satisfies a preset condition, the priority order of the first transmission request and the third transmission request alternates in each response process, and the preset condition includes that the position relationship corresponding to the third transmission request and the position relationship corresponding to the first transmission request are both the first position relationship.

4. The routing method of the two-dimensional network-on-chip structure according to claim 2, characterized in that: Also includes: In a case where it is determined based on the multicast identification information of the first target data packet that the first target data packet needs to be copied, copying the first target data packet to obtain a copied data packet, wherein the multicast identification information is used to determine whether the data packet needs to be copied; determining a third destination location based on the destination address information of the first target data packet, where the third destination location is different from the first destination location; The copied data packet is sent to the third destination.

5. The routing method of the two-dimensional network-on-chip structure according to claim 4, characterized in that: The multicast identification information includes identification bit values ​​of multiple routing rounds, and the number of bits of the multicast identification information is determined based on the number of the multiple processing cores; The first target data packet is determined to be copied based on the following steps: Analyze the multicast identification information of the first target data packet bit by bit to obtain the identification bit value of the current routing round; Based on the identification bit value of the current routing round, it is determined whether the first target data packet needs to be copied.

6. The routing method of the two-dimensional network-on-chip structure according to claim 4, characterized in that: The destination address information of the first target data packet includes address bit values ​​of multiple routing rounds, and the number of bits of the destination address information of the first target data packet is determined based on the number of the multiple processing cores; The determining of the third destination location based on the destination address information of the first target data packet includes: Analyzing the destination address information of the first target data packet bit by bit to obtain the address bit value of the current routing round; A third destination location is determined based on a comparison result of the address bit value of the current routing round and the source address information of the first routing node.

7. The routing method of the two-dimensional network-on-chip structure according to claim 2, characterized in that: Also includes: receiving a second target data packet sent by the pulse data packet encoding and decoding interface of the first routing node; Determining a second target input distributor corresponding to the pulse data packet encoding and decoding interface of the first routing node from the five input distributors of the first routing node, and sending the second target data packet to the second target input distributor; determining a second target routing direction based on the destination address information of the second target data packet; determining a second target output arbiter from the five output arbiters of the first routing node based on the second target routing direction; sending, through the second target input distributor, a second transmission request for the second target data packet to the second target output arbitrator; The second transmission request is responded to through the second target output arbitrator to transmit the second target data packet to the second destination location corresponding to the second target output arbitrator, and the second destination location includes a fourth routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

8. A routing device for a two-dimensional network-on-chip structure, characterized in that: The two-dimensional network-on-chip structure is the two-dimensional network-on-chip structure according to claim 1, the device is deployed at a first routing node, and the device includes: a data packet receiving module, configured to receive a first target data packet sent by a second routing node, and determine a positional relationship between the second routing node and the first routing node in the two-dimensional network-on-chip, where the second routing node is an adjacent routing node of the first routing node; a distributor determining module, configured to determine a first target input distributor from the five input distributors of the first routing node based on the position relationship, and send the first target data packet to the first target input distributor; a direction determining module, configured to determine a first target routing direction based on the destination address information of the first target data packet and an XY dimensional order routing strategy; an arbitrator determining module, configured to determine a first target output arbitrator from the five output arbitrators based on the first target routing direction; a request sending module, configured to send a first transmission request of the first target data packet to the first target output arbitrator via the first target input distributor; a request response module, configured to respond to the first transmission request through the first target output arbitrator to transmit the first target data packet to a first destination location corresponding to the first target output arbitrator, wherein the first destination location includes a third routing node adjacent to the first routing node or a pulse data packet encoding and decoding interface of the first routing node.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the routing method of the two-dimensional network-on-chip structure according to any one of claims 2 to 7 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the routing method of the two-dimensional network-on-chip structure according to any one of claims 2 to 7 is implemented.

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