Weighted alternate paths in graphs for quantum computing

Abstract

A computer-implemented method for expanding a set of matching nodes in a partially-matched graph can include obtaining, by a computing system, a partially-matched graph having a matching set, the partially-matched graph including one or more edges and a plurality of nodes, the one or more edges having matching labels. The method can include obtaining at least two non-matching nodes. The method can include determining an alternating path from a first non-matching node of the at least two non-matching nodes to a second non-matching node of the at least two non-matching nodes, the alternating path including at least one edge of the one or more edges. The method can include reversing the matching labels of the at least one edge of the alternating path such that the at least two non-matching nodes are included in the matching set of the partially-matched graph.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of priority to U.S. Provisional Application Serial No. 63 / 121,027, entitled “Algorithm for Computing Cost of Weighted Alternating Paths in a Graph for Quantum Computing,” filed December 3, 2020, which is incorporated by reference herein. TECHNICAL FIELD

[0003] The present disclosure relates generally to algorithms for computing cost of weighted alternating paths in a graph, and more particularly to algorithms for computing cost of weighted alternating paths in an error graph of a quantum computing system. BACKGROUND

[0004] Quantum computing is a method of computing that leverages quantum effects such as ground states and entanglement of superpositions to perform some computations more efficiently than classical digital computers. In contrast to digital computers that store and manipulate information in the form of bits (e.g., “1” or “0”), quantum computing systems can use quantum bits (“qubits”) to manipulate information. A qubit can refer to a quantum device that enables superposition of multiple states (e.g., data in both “0” and “1” states), and / or to the superposition of data itself in multiple states. According to conventional terminology, a superposition of “0” and “1” states in a quantum system can be represented as |0> + b |1>, for example. The “0” and “1” states of a digital computer are analogous to the |0> and |1> ground states of a qubit, respectively. SUMMARY

[0005] Aspects and advantages of embodiments of the present disclosure will be set forth in part in the following description, or can be apparent from the description, or can be learned through practice of the embodiments.

[0006] One example aspect of the present disclosure relates to a computer-implemented method for expanding a set of matching nodes in a partially matching graph. The method can include obtaining, by a computing system comprising one or more computing devices, a partially matching graph having a matching set, the partially matching graph comprising one or more edges and a plurality of nodes, the one or more edges having matching labels. The method can include obtaining, by the computing system, at least two non-matching nodes. The method can include determining, by the computing system, an alternating path from a first non-matching node of the at least two non-matching nodes to a second non-matching node of the at least two non-matching nodes, the alternating path comprising at least one edge of the one or more edges. The method can include reversing, by the computing system, the matching labels of at least one edge of the alternating path such that the at least two non-matching nodes are included in the matching set of the partially matching graph.

[0007] In some implementations, at least one of the nodes can be a boundary node. A boundary node can have an invariant boundary status such that the boundary node is neither matched nor isolated. A boundary node can be matched any suitable number of times, such as zero or more times. In some implementations, the algorithms described herein can be configured such that alternating paths from unmatched nodes to boundary nodes are discovered. For example, to discover alternating paths, a boundary node can always act as an unmatched node because a boundary node is always available to be matched regardless of any pre-existing matches.

[0008] Another example aspect of the present disclosure relates to a method for error detection in a quantum computing system. The method can include obtaining, by a computing system comprising one or more computing devices, a matching graph comprising one or more edges and a plurality of nodes, the plurality of nodes corresponding to a plurality of qubits of a quantum computing system, the one or more edges having a matching label. The method can include obtaining, by the computing system, an error detection signal comprising a first endpoint and a second endpoint, the first endpoint and the second endpoint corresponding to a first qubit and a second qubit of the plurality of qubits. The method can include determining, by the computing system, an alternating path from the first endpoint to the second endpoint, the alternating path comprising at least one edge of the one or more edges. The method can include detecting, by the computing system, at least one error location in the quantum computing system based at least in part on the alternating path.

[0009] Another example aspect of the present disclosure relates to a quantum computing system. The quantum computing system can include quantum hardware comprising a plurality of qubits. The quantum hardware can include one or more classical processors. The one or more classical processors can be configured to perform operations. The operations can include obtaining a matching graph comprising one or more edges and a plurality of nodes, the plurality of nodes corresponding to the plurality of qubits, the one or more edges having a matching label. The operations can include obtaining an error detection signal comprising a first endpoint and a second endpoint, the first endpoint and the second endpoint corresponding to a first qubit and a second qubit of the plurality of qubits. The operations can include determining an alternating path from the first endpoint to the second endpoint, the alternating path comprising at least one edge of the one or more edges. The operations can include detecting at least one error location in the quantum hardware based at least in part on the alternating path.

[0010] Other aspects of the present disclosure relate to various systems, methods, apparatuses, non-transitory computer-readable mediums, computer-readable instructions, and computing devices.

[0011] These and other features, aspects, and advantages of various embodiments of the present disclosure will be better understood when considered with reference to the following description and appended claims. The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate example embodiments of the present disclosure and serve to explain the related principles. Attached Figure Description

[0012] A detailed description of embodiments for those skilled in the art will be set forth in the specification with reference to the accompanying drawings, in which:

[0013] Figure 1 Depicts an example quantum computing system according to an example embodiment of the present disclosure;

[0014] Figure 2 Depicting an example qubit grid according to an example embodiment of this disclosure;

[0015] Figure 3 Example diagrams depicting exemplary embodiments according to this disclosure;

[0016] Figure 4A and Figure 4B Example diagrams depicting error messages according to exemplary embodiments of the present disclosure;

[0017] Figure 5 A flowchart depicting an example method for expanding a set of matching nodes in a graph for partial matching, according to an example embodiment of the present disclosure;

[0018] Figure 6 A flowchart depicting an example method for error detection in a quantum computing system according to an example embodiment of the present disclosure; and

[0019] Figure 7 An example computing system is described according to an example embodiment of the present disclosure. Detailed Implementation

[0020] Example aspects of the present disclosure relate to systems and methods for extending a match of a partially matched graph (e.g., a match of matched and / or isolated nodes and / or a match set of edges) and / or computing a cost of a weighted alternating path in a graph. Specifically, the systems and methods described herein can be used for error detection of a quantum computing system including one or more qubits. A graph can include one or more nodes and / or one or more edges. Each edge can be shared by two nodes. For example, each edge can connect a first node to a second node. A graph (e.g., one or more edges) can have a match set (e.g., a set of nodes and / or edges) such that each edge is one of “matched” or “not matched.” Further, the match set can include nodes that are one of matched or isolated. Two nodes are considered matched if they share a matched edge. A node can share at most one matched edge with one other node. For example, a node can be linked to at most one matched edge according to constraints of the graph. As another example, a set of matched edges can be a set of edges that do not share a node or vertex with two edges. A node that does not have a matched edge is an isolated node. In some implementations, edges can be weighted edges. For example, each edge can have an associated weight.

[0021] It should be appreciated that example aspects of the present disclosure will be discussed with reference to match labels at nodes (e.g., matched nodes versus isolated nodes) and edges (e.g., matched edges versus not matched edges). In some implementations, only match labels can be used to represent matches, and a matched node can generally refer to a node that shares a matched edge. Thus, a pair of matched nodes can refer to two nodes of a matched edge. Additionally and / or alternatively, node labels can be applied to nodes indicating that the nodes are matched, isolated, and / or not matched.

[0022] According to example aspects of the present disclosure, one or more not matched nodes can be introduced and / or otherwise present in a graph. A match of a graph can be extended to include not matched nodes. As used herein, a “not matched node” refers to a node that is neither matched nor isolated, e.g., a node that is not currently included in a match set of a graph. For example, a partially matched graph can include one or more not matched nodes that are neither matched nor isolated when the graph is partially matched. Not matched nodes can only be connected to not matched edges, but can become matched or isolated in a solution of the partially matched graph. For example, a set of matched nodes and / or edges in a partially matched graph can be extended to include not matched nodes, e.g., by changing match labels of edges in the graph to include some or all of the not matched nodes. The set of nodes and / or edges with a match can be extended while satisfying one or more constraints of the match. As one example, a constraint can be that a node is either part of a matched pair with exactly one other node or is isolated. As another example, a constraint can be that each node can touch at most one matched edge.

[0023] Additionally and / or alternatively, the matching of the graph can be extended with reference to a cost function, e.g., to optimize (e.g., minimize and / or maximize) the cost function. For example, in some implementations, the cost function can be based at least in part on the edge weights of the matching edges. For example, the cost function can seek to minimize the sum of the edge weights of the set of matching edges. The cost function can reward lower edge weights and / or penalize higher edge weights when an edge is included in the matching set. As another example, the cost function can be chosen to minimize the cost of an alternating path from a first unmatched node to a second unmatched node.

[0024] Example aspects of the present disclosure can include an algorithm for computing a reassignment of matching labels that extends a partial matching of a graph given the graph and the partial matching (e.g., an assignment of matching labels that covers a subset of the nodes and / or edges in the graph). The algorithm can extend the partial matching to a complete matching through one or more iterations of the algorithm. For example, the algorithm can repeat the iterations several times until each node and / or edge in the graph has an assignment of matching and / or isolation to provide a complete matching of the graph.

[0025] In particular, the algorithm can include finding alternating paths, such as minimum cost alternating paths, and / or the cost of an alternating path from one unmatched node to another node, such as a second unmatched node. As used herein, an alternating path is a sequence of edges and / or nodes that alternate between being labeled as unmatched and matched. In particular, if the matching labels of the edges along an alternating path that terminates at an unmatched node are reversed, the matching is still valid and includes the unmatched node in addition to each existing matched node. If the alternating path spans two unmatched nodes, both of the unmatched nodes are included in the new matching when the matching labels are reversed. Further, the total cost of the matching edges changes with the cost of the alternating path. In some implementations, the cost of the alternating path can be the sum of the weights of all unmatched edges in the path minus the sum of the weights of all matched edges in the path. Thus, by augmenting the minimum cost path, the unmatched nodes are included in the matching with the lowest total cost increase. This can be repeated to find a globally optimal weighted matching. In some implementations, the path cost can be determined by constructing a tree rooted at the unmatched node. Then, for each node reachable through the graph, a minimum cost alternating path to the node and a path (tree) to the node can be established. This can prevent the formation of cycles, which is beneficial for quantum computing applications. In some implementations, the tree can be generated by a Bellman-Ford algorithm modified to avoid cycles when generating the tree. For example, the algorithm can be modified so that nodes that are ancestors of the current node are not visited as candidates for the next node in the tree.

[0026] According to example aspects of the present disclosure, the algorithm can be applied to error detection in a quantum computing system. For example, the algorithm can be implemented by an error detection and / or error correction system for identifying errors in a quantum computation. For example, in some implementations, the nodes of the matching graph can correspond to locations of one or more qubits in a quantum computing system. The existing matching graph can be a matching graph from a previous point in time. As one example, the one or more qubits can be arranged in a grid or array of qubits. For example, the nodes in the graph can correspond to coordinates of qubits within the array of qubits. The weights of the edges in the graph can correspond to a likelihood of an error at a point in the quantum computing system. These weights can be learned from historical usage data of the quantum computing system, estimated from simulation or design, or established by any other suitable method. For example, higher weights can be assigned to points that are less likely to have an error, such that the minimum cost path is also the path that is most likely to have an error. The weights can be pre-existing at the time of quantum computer runtime.

[0027] In some implementations, the grid of qubits can include one or more computational qubits and one or more ancilla qubits. For example, in some implementations, the grid of qubits can be an interleaved grid of ancilla qubits and computational qubits. The computational qubits can perform computations for evaluating one or more quantum algorithms. Additionally and / or alternatively, the ancilla qubits can be configured to monitor parity of the quantum computing system (e.g., the computational qubits) to detect errors in the quantum computing system.

[0028] For example, in some implementations, the computing system can receive error information including coordinates describing endpoints of a mismatched parity. For example, the coordinates can correspond to locations of ancilla qubits in the grid of qubits that detected a mismatched parity. In some cases, the error information can be received in real-time, e.g., in time slices and / or continuously. For example, each time slice can correspond to a set of quantum gate operations at each qubit of a plurality of qubits. The error information can be received with a precision on the order of microseconds (e.g., half a microsecond). For example, in some embodiments, the computing system can receive error information including pairs of endpoints of a mismatched parity in real-time.

[0029] Systems and methods according to example aspects of the present disclosure can support resolving a minimum cost alternating path between pairs of endpoints. The minimum cost alternating path can indicate a most likely source of an error that caused a mismatched parity at the endpoints. Thus, the minimum cost alternating path can indicate a location of a computational qubit that had an error occur. For example, the minimum cost alternating path can include an erratic qubit. In some cases, these errors can propagate through a quantum computation, so timely detection and / or correction can be beneficial.

[0030] For purposes of illustration, example aspects of the present disclosure are described herein with respect to quantum computing applications and error detection. Example aspects of the present disclosure can be beneficial for evaluating errors in quantum computing systems. Moreover, the general problem of weighted matching in the figures can be useful in other applications, including many engineering disciplines. In accordance with the present disclosure, example aspects of the present disclosure can be applied to such other applications.

[0031] Systems and methods in accordance with example aspects of the present disclosure can provide a number of technical effects and benefits, including but not limited to improvements to computing technology, e.g., quantum computing technology. For example, example aspects of the present disclosure can provide for reduced evaluation time of error information, particularly for smaller graphs, e.g., graphs including a number of nodes on the order of the number of qubits in an example quantum computing system. This can be particularly beneficial in quantum computing applications that can require small graph problems to be solved quickly. For example, it can be desirable to solve two-terminal error information problems as quickly as possible to meet the precise timing requirements of a quantum computing control system, e.g., quickly enough that errors can be considered and / or corrected. Particularly in these cases, systems and methods in accordance with example aspects of the present disclosure can have reduced evaluation time as compared to some existing methods, e.g., the Blossom algorithm.

[0032] Example embodiments of the present disclosure will now be discussed in greater detail. As used herein, the term “about,” used in conjunction with a numerical value, means within 20% of the numerical value.

[0033] Figure 1 An example quantum computing system 100 is depicted. Example system 100 is an example of a system on one or more classical computers or quantum computing devices at one or more locations in which systems, components, and techniques described below can be implemented. Using the disclosure provided herein, one of ordinary skill in the art will appreciate that other quantum computing structures or systems can be used without departing from the scope of the present disclosure.

[0034] System 100 includes one or more classical processors 104 in data communication with quantum hardware 102. Quantum hardware 102 includes components for performing quantum computations. For example, quantum hardware 102 includes a quantum system 110, a control device 112, and a readout device 114 (e.g., a readout resonator). Quantum system 110 can include one or more multi-level quantum subsystems, e.g., a register of qubits. In some implementations, the multi-level quantum subsystems can include superconducting qubits, e.g., flux qubits, charge qubits, transmon qubits, gmon qubits, etc.

[0035] The type of multi-level quantum subsystem utilized by the system 100 can vary. For example, in some cases, it can be convenient to include one or more readout devices 114 attached to one or more superconducting qubits (e.g., transmon qubits, flux qubits, gmon qubits, xmon qubits, or other qubits). In other cases, ion traps, photonic devices, or superconducting cavities can be used (e.g., from which states can be prepared without requiring qubits). Other examples of implementations of multi-level quantum subsystems include magnetic flux qubits, silicon quantum dots, or phosphorus quantum bits.

[0036] The quantum circuit can be constructed and applied to a register of qubits included in the quantum system 110 through a plurality of control lines coupled to one or more control devices 112. Example control devices 112 operating on the register of qubits can be used to implement quantum gates or quantum circuits having a plurality of quantum gates, such as Pauli gates, Hadamard gates, controlled not (CNOT) gates, controlled phase gates, T gates, multi-qubit quantum gates, coupler quantum gates, and the like. The one or more control devices 112 can be configured to operate on the quantum system 110 through one or more respective control parameters (e.g., one or more physical control parameters). For example, in some implementations, the multi-level quantum subsystem can be a superconducting qubit, and the control device 112 can be configured to provide control pulses to the control lines to generate a magnetic field to adjust the frequency of the qubit.

[0037] The quantum hardware 102 can also include a readout device 114 (e.g., a readout resonator). Measurement results 108 obtained via the measurement device can be provided to the classical processor 104 for processing and analysis. In some implementations, the quantum hardware 102 can include a quantum circuit, and the control device 112 and the readout device 114 can implement one or more quantum logic gates operating on the quantum system 102 through physical control parameters (e.g., microwave pulses) sent through wires included in the quantum hardware 102. Other examples of control devices include arbitrary waveform generators, where a DAC (digital-to-analog converter) creates the signal.

[0038] Readout device 114 can be configured to perform quantum measurements on quantum system 110 and send the measurement result 108 to classical processor 104. Furthermore, quantum hardware 102 can be configured to receive data from classical processor 104 specifying physical control qubit parameter values ​​106. Quantum hardware 102 can use the received physical control qubit parameter values ​​106 to update the actions of control device 112 and readout device 114 on quantum system 110. For example, quantum hardware 102 can receive data specifying new values ​​representing the voltage strength of one or more DACs included in control device 112 and can update the actions of the DACs on quantum system 110 accordingly. Classical processor 104 can be configured to initialize quantum system 110 to an initial quantum state, for example, by sending data specifying an initial set of parameters 106 to quantum hardware 102.

[0039] The readout device 114 can use the impedance difference to measure the state of an element (e.g., a qubit) in a quantum system, specifically the |0> and |1> states. For example, due to the nonlinearity of the qubit, the resonant frequency of the readout resonator can exhibit different values ​​when the qubit is in state |0> or state |1>. Therefore, the microwave pulse reflected from the readout device 114 carries an amplitude and phase shift depending on the qubit state. In some implementations, a Purcell filter can be used in conjunction with the readout device 114 to block microwave propagation at the qubit frequency.

[0040] Figure 2 An example qubit grid 200 is depicted according to an example embodiment of this disclosure. For example... Figure 2 As shown, the qubit grid 200 can be an interleaved qubit grid of one or more auxiliary qubits 202 (shown as solid circles) and / or one or more computation qubits 204 (shown as unshaded circles). The auxiliary qubits 202 can be configured to measure errors (e.g., parity) in the output of the computation qubits 204. For example, some of the computation qubits 204 may have a time series of quantum gate operations defining a quantum algorithm spanning some or all of the computation qubits 204. Errors in the execution of these quantum gate operations can propagate through the qubit grid 200 and are eventually detected at the auxiliary qubits 202 via parity checks. Error information, including endpoints corresponding to the coordinates of the auxiliary qubits 202 responsible for error detection, is then generated and / or transmitted to a control system for error detection and / or correction.

[0041] Figure 3 Example Figure 300 depicts an exemplary embodiment according to the present disclosure. Figure 300 includes nodes 302 and edges 304. According to an exemplary aspect of the present disclosure, node 302 may correspond to an auxiliary qubit in a quantum computing system. Figure 3As shown, nodes 302 can be connected by edges 304. Some or all of edges 304 can be associated with computational qubits 305. For example, according to example aspects of the present disclosure, if error information is received that includes two nodes 302 as endpoints, the computational qubit 305 responsible for the error can be associated with (e.g., matched to) the edge 304 of the least cost alternate path between the two nodes.

[0042] Figure 4A and Figure 4B Example graphs 400, 450 including error information are depicted in accordance with example embodiments of the present disclosure. For example, Figure 4A Example graph 400 is depicted including error endpoints 402, 404, 406, and 408. Graph 400 can include nodes 410 and edges 420. Nodes can correspond to ancilla qubits. Additionally and / or alternatively, some or all of edges 420 can represent computational qubits. For example, in some implementations, each edge 420 can represent a single computational qubit. Additionally and / or alternatively, in some implementations, an edge can represent an error that affects more than one qubit (e.g., an ancilla qubit and a computational qubit). As shown, each node 410 can be connected to one or more other nodes 410 by edges 420. In some implementations, each edge 420 can have an associated weight. Endpoints 402, 404, 406, and 408 can correspond to ancilla qubits that detected an error, such as a parity check failure.

[0043] Figure 4B Example graph 450 is depicted including a greater number of endpoints 452 than graph 400. For example, graph 450 illustrates how the complexity of solving for error locations can increase as the number of endpoints 452 increases. For example, as can be appreciated from a comparison of Figure 4A and Figure 4B Solving graph 400 (e.g., assigning match edges to it) can be easier than solving graph 450, which includes a greater number of endpoints 452. For example, it can be easily inferred (without considering weights) that edge 422 can match endpoints 402 and 404, and edge 424 is most likely to match endpoints 406 and 408. However, as can be appreciated from a comparison of Figure 4B Assigning matches to graph 450 can be computationally more complex.

[0044] Example aspects of the present disclosure can support determining a match of graph 400 and / or graph 450. For example, systems and methods according to example aspects of the present disclosure can assign a match label of “match” or “no match” (or other similar binary quality) to edges 420 such that each endpoint (e.g., 402-408) is included in a match. For example, systems and methods according to example aspects of the present disclosure can find a minimum cost alternating path from a first no-match node (e.g., a first endpoint) to a second no-match node (e.g., a second endpoint). For example, the minimum cost alternating path can include edges corresponding to qubits that most likely caused an erroneous endpoint. The match label along the alternating path can be reversed, resulting in a new optimal (e.g., lowest cost) match that includes the no-match nodes. This can be repeated until an overall optimal (e.g., most likely) solution is obtained. In this way, the propagation of errors and / or multiple errors through a system can be continuously considered while the quantum computing system is running.

[0045] Figure 5 A flow diagram depicting an example method 500 for expanding a set of matching nodes in a graph of a partial match according to example embodiments of the present disclosure is depicted. While the steps are depicted in a particular order for purposes of illustration and discussion, Figure 5 Steps are depicted in a particular order, but methods of the present disclosure are not limited to the particular order or arrangement specified. Individual steps of method 500 can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present disclosure.

[0046] Method 500 can include, at 502, obtaining (e.g., by a computing system including one or more computing devices) a graph of a partial match including one or more edges and a plurality of nodes. The one or more edges can have a match. For example, a match label can be assigned to the one or more edges indicating whether an edge is matched or not matched. For example, in some implementations, for each edge, the match can be or include a match label indicating one of a matched edge having a match condition or a no-match edge having a no-match condition. The graph can define matched nodes and / or edges according to some constraints. For example, in some implementations, the graph is matched such that each node of the plurality of nodes touches at most one matched edge.

[0047] In some implementations, each of the one or more edges can include a weight. For example, in some implementations, such as implementations in which the graph corresponds to a plurality of qubits, each edge can be weighted based on a likelihood of an error at that edge. For example, in some implementations, edge weights can be established based at least in part on prior analysis and / or simulation of a quantum computing system. In some implementations, the weight can be inversely related to the likelihood of an error. For example, edges with a low likelihood of an error can have a high weight.

[0048] The method 500 can include, at 504, obtaining (e.g., by the computing system) at least two mismatched nodes. For example, the at least two mismatched nodes can be new nodes, e.g., nodes that were not in the graph prior to obtaining the at least two mismatched nodes. Additionally and / or alternatively, the at least two mismatched nodes can be existing nodes with updated status, e.g., nodes that have switched from a prior match (e.g., a matched and / or mismatched) to a mismatched. In some implementations, the at least two mismatched nodes can be or can include endpoints (e.g., a first endpoint and / or a second endpoint) included in error information from a quantum computing system.

[0049] The method 500 can include, at 506, determining, by the computing system, an alternating path from a first mismatched node of the at least two mismatched nodes to a second mismatched node of the at least two mismatched nodes. The alternating path can include at least one edge of the one or more edges. For example, the alternating path can alternate between matched edges and mismatched edges. As an example, the order of edges from the first mismatched node to the second mismatched node can alternate between matched edges and mismatched edges. In some implementations, for an alternating path with only one edge, the edge can be either matched or mismatched.

[0050] In some implementations, the alternating path can be a minimum cost alternating path. For example, in some implementations, the cost of the alternating path can be a sum of mismatched weights of mismatched edges in the alternating path, where the sum of mismatched weights is subtracted from a sum of matched weights of matched edges in the alternating path. For example, in implementations of quantum computing error detection, an alternating path according to this cost function can thus correspond to a most likely error path.

[0051] In some implementations, determining an alternating path from a first of the at least two mismatched nodes to a second of the at least two mismatched nodes includes determining, by the computing system, a tree having a plurality of alternating paths from the first mismatched node to each of the plurality of nodes, and selecting the alternating path from the tree. For example, a tree of alternating paths from the selected mismatched pattern to each node in the graph can be determined. Additionally and / or alternatively, the alternating path can be a minimum cost alternating path. Thus, an alternating path to the second mismatched node can be selected. The tree of alternating paths advantageously avoids cycles, which is particularly beneficial in quantum computing applications. For example, in some implementations, no alternating path of the plurality of alternating paths can include a cycle. In two or more instances, a cycle can be present in a path that uses a single edge. As another example, a cycle can occur two or more times in a path that includes a single node. The tree of alternating paths can be determined by any suitable algorithm. For example, in some implementations, determining the tree including the plurality of alternating paths is performed by applying the Bellman-Ford algorithm. The Bellman-Ford algorithm can be modified to prevent cycles from being formed, such as by only selecting paths that do not include cycles. For example, the algorithm can be prevented from accessing nodes that are ancestors of the current node.

[0052] The method 500 can include, at 508, reversing the match labels of at least one edge of the alternating path. For example, once the alternating path is identified, the match labels of each edge along the alternating path can be reversed. For example, a match edge along the alternating path can be reversed to a mismatch edge, and / or a mismatch edge along the alternating path can be reversed to a match edge. In accordance with example aspects of the present disclosure, reversing the match labels along the alternating path from the first mismatched node to the second mismatched node can extend the match set of the graph to include the mismatched nodes while maintaining validity for the existing nodes. Moreover, if the minimum cost alternating path is reversed, the new match can be the overall optimal match (e.g., as defined by the cost function).

[0053] Figure 6 A flow diagram depicting an example method 600 for error detection in a quantum computing system in accordance with example embodiments of the present disclosure is depicted. While the steps are depicted in a particular order for the purposes of illustration and discussion, Figure 6 The method 600 is depicted with steps performed in a particular order, but the methods of the present disclosure are not limited to the particular illustrated order or arrangement. The various steps of the method 600 can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of the present disclosure.

[0054] The method 600 can include, at 602, obtaining (e.g., by a computing system including one or more computing devices) a matching graph including one or more edges and a plurality of nodes. The one or more edges can have a match. For example, a match label can be assigned to the one or more edges indicating whether an edge is a matching edge or a non-matching edge. For example, in some implementations, for each edge, the match can be or can include a match label indicating one of a matching edge having a matching condition or a non-matching edge having a non-matching condition. The graph can define matching nodes and / or edges according to some constraints. For example, in some implementations, the graph is matched such that each node of the plurality of nodes touches at most one matching edge.

[0055] The plurality of nodes can correspond to a plurality of qubits of a quantum computing system. For example, in some implementations, the plurality of qubits can correspond to a staggered grid of qubits. The staggered grid can include a plurality of computational qubits staggered with a plurality of ancilla qubits. For example, each node can correspond to an ancilla qubit. Additionally and / or alternatively, each edge of the one or more edges can correspond to a computational qubit. Figure 2 An example qubit grid is illustrated in FIG. 1. Any suitable qubit grid and / or other plurality of qubits can be employed in accordance with example aspects of the present disclosure.

[0056] In some implementations, each edge of the one or more edges can include a weight. For example, in some implementations, each edge can be weighted based on a likelihood of error at the edge and / or a node (e.g., qubit) of the edge. For example, in some implementations, edge weights can be established based at least in part on prior analysis and / or simulation of the quantum computing system. In some implementations, the weight can be inversely related to the likelihood of error. For example, an edge with a low likelihood of error can have a high weight.

[0057] The method 600 can include, at 604, obtaining (e.g., by the computing system) error detection signals that describe first and second endpoints. For example, in some implementations, the first and / or second endpoints can be mismatched nodes in a matching graph. The first and second endpoints can correspond to first and second qubits of the plurality of qubits. For example, in some implementations, each of the first and second endpoints corresponds to a ancilla qubit. The computing system can receive error information that includes coordinates of endpoints that describe a mismatched parity. For example, the endpoints can correspond to locations of ancilla qubits in a grid of qubits where a mismatched parity was detected. In some cases, the error information including the endpoints can be received in real-time, e.g., in time slices and / or continuously. For example, each time slice can correspond to a set of quantum gate operations at each qubit of the plurality of qubits. The error information can be received with precision on the order of microseconds. For example, in some embodiments, the computing system can receive error information including pairs of endpoints of a mismatched parity in real-time.

[0058] The method 600 can include, at 606, determining (e.g., by the computing system) an alternating path from the first endpoint to the second endpoint. The alternating path can include at least one edge of the one or more edges. For example, the alternating path can alternate between matching edges and mismatched edges. For example, the order of edges from the first endpoint to the second endpoint can alternate between matching edges and mismatched edges. In some implementations, for an alternating path having only one edge, the edge can be either matching or mismatched.

[0059] In some implementations, the alternating path can be a minimum cost alternating path. For example, in some implementations, the cost of the alternating path can be a sum of mismatched weights of mismatched edges in the alternating path, where the sum of mismatched weights is subtracted by a sum of matching weights of matching edges in the alternating path. For example, in implementations of quantum computing error detection, the alternating path according to this cost function can thus correspond to the most likely error path.

[0060] In some implementations, determining an alternate path from a first endpoint of the at least two endpoints to a second endpoint of the at least two endpoints includes determining, by the computing system, a tree having a plurality of alternate paths from the first endpoint to each of the plurality of nodes, and selecting an alternate path from the tree. For example, a tree of alternate paths from the selected mismatched pattern to each node in the graph can be determined. Additionally and / or alternatively, the alternate path can be a least cost alternate path. Thus, an alternate path to the second endpoint can be selected. The tree of alternate paths advantageously avoids cycles, which is particularly beneficial in quantum computing applications. For example, in some implementations, none of the plurality of alternate paths can include a cycle. The tree of alternate paths can be determined by any suitable algorithm. For example, in some implementations, determining the tree including the plurality of alternate paths is performed by applying the Bellman-Ford algorithm. The Bellman-Ford algorithm can be modified to prevent formation of cycles, such as by only selecting paths that do not include cycles.

[0061] The method 600 can include, at 608, detecting, (e.g., by the computing system) at least one error location in the quantum computing system based at least in part on the alternate path. For example, the alternate path can be compared to the plurality of qubits to identify a location of an error in the quantum computation. As one example, a matching edge can indicate an unstable qubit. Thus, the location of the error can correspond to, for example, a qubit index, coordinate, and / or other identifier.

[0062] In some implementations, the method 600 can further include, at 610, correcting, by the computing system, a quantum measurement from the at least one error location at the quantum computing system. For example, in some implementations, the quantum algorithm in which the error exists can be rerun to correct the error. As another example, in some implementations, a measurement value from the error location can be corrected and the quantum algorithm can continue to be evaluated with the corrected value.

[0063] Figure 7 A block diagram of an example computing system 1000 that can be used for implementing systems and methods in accordance with example embodiments of the present disclosure, such as the systems discussed with reference to FIGS. 1-4, is depicted. The system 1000 includes a control system 1010 and a quantum computing system 1030 communicatively coupled by a network 1050. One or more aspects of any of the methods described herein can be implemented on the control system 1010 and / or the quantum computing system 1030. Figure 1

[0064] ​The control system 1010 can include any type of computing device (e.g., a classical computing device). The control system 1010 includes one or more processors 1012 and a memory 1014. The one or more processors 1012 can include any suitable processing device (e.g., a processor core, a microprocessor, an ASIC, a FPGA, a controller, a microcontroller, etc.) and can be one processor or a plurality of processors that are operatively connected. The memory 1014 can include one or more non-transitory computer-readable storage media, such as, for example, RAM, ROM, EEPROM, EPROM, flash memory devices, magnetic disks, etc. and combinations thereof. The memory 1014 can store data 1016 (e.g., qubit parameters, measurements, etc.) and instructions 1018 that are executed by the processor 1012 to cause the control system 1010 to perform operations such as, for example, one or more aspects of any of the methods disclosed herein. According to example embodiments of the present disclosure, the control system 1010 can be configured to process error information 1020 obtained by measuring an output of a quantum system (e.g., the quantum system 1040) to identify errors in a quantum computation.

[0065] The quantum computing system 1030 includes one or more processors 1032 and a memory 1034. The one or more processors 1032 can include suitable processing devices (e.g., a processor core, a microprocessor, an ASIC, a FPGA, a controller, a microcontroller, etc.) and can be one processor or a plurality of processors that are operatively connected. The memory 1034 can include one or more non-transitory computer-readable storage media, such as, for example, RAM, ROM, EEPROM, EPROM, flash memory devices, magnetic disks, etc. and combinations thereof. The memory 1034 can store data 1036 and instructions 1038 that are executed by the processor 1032 to cause the quantum computing system 1030 to perform operations such as, for example, implementing a quantum circuit having one or more quantum gates on a quantum system 1040 having a plurality of qubits and obtaining associated measurements (e.g., error information 1020). The quantum computing system 1030 can be similar to the quantum computing system discussed and described with reference to Figure 1 The quantum computing system discussed and described. Other suitable quantum computing systems can be used without departing from the scope of the present disclosure.

[0066] The network 1050 can be any type of communications network, such as a local area network (e.g., an intranet), a wide area network (e.g., the Internet), or some combination thereof, and can include any number of wired or wireless links. In general, communications over the network 1050 can be carried out using various communication protocols (e.g., TCP / IP, HTTP, SMTP, FTP), encodings or formats (e.g., HTML, XML), and / or protection schemes (e.g., VPN, secure HTTP, SSL), via any type of wired and / or wireless connection. In some implementations, the network 1050 can be omitted, such that control system 1010 and quantum computing system 1030 are in direct signal communication.

[0067] The digital, classical, and / or quantum subject matter described in this specification can be implemented in digital electronic circuitry, suitable quantum circuitry, or more generally quantum computing systems, in tangible non-transitory computer- readable medium whether or not the quantum subject matter is implemented with quantum computer software or firmware, in digital and / or quantum computer hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. The term “quantum computing system” can include, but is not limited to, a quantum computer / computing system, a quantum information processing system, a quantum cryptography system, or a quantum simulator.

[0068] Implementations of the digital and / or quantum subject matter described in this specification can be implemented as one or more digital and / or quantum computer program(s), i.e., one or more modules of digital and / or quantum computer program instructions encoded on a tangible non-transitory storage medium for execution by, or to control the operation of, data processing apparatus. The digital and / or quantum computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, one or more qubits / qubit structures, or a combination of one or more of them. Alternatively or additionally, the program instructions can be encoded on an artificially generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, that is generated to encode digital and / or quantum information for transmission to the appropriate receiver apparatus for execution by a data processing apparatus.

[0069] The terms quantum information and quantum data refer to information or data carried by, held or stored by a quantum system, where the smallest non-trivial system is a qubit, i.e., a system that defines a unit of quantum information. It is to be understood that the term “qubit” encompasses all quantum systems that can be suitably approximated in the corresponding context as a two-level system. Such quantum systems can include multi-level systems, e.g., having two or more energy levels. For example, such systems can include atoms, electrons, photons, ions, or superconducting qubits. In many implementations, the computational basis states are identified with the ground state and the first excited state, however it is to be understood that other setups identifying the computational states with higher-level excited states (e.g., qubits) are possible.

[0070] The term “data processing apparatus” refers to digital and / or quantum data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing digital and / or quantum data, including by way of example, a programmable digital processor, a programmable quantum processor, a digital computer, a quantum computer, or multiple digital and quantum processors or computers, and combinations thereof. The apparatus can also be, or further include, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit), or a quantum simulator, i.e., a quantum data processing apparatus designed to simulate or produce information about a particular quantum system. In particular, a quantum simulator is a special-purpose quantum computer that does not possess the ability to perform general quantum computation. The apparatus can optionally include, in addition to the hardware, code that creates an execution environment for digital and / or quantum computer programs, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0071] A digital or classical computer program (which can also be referred to or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a digital computing environment. A quantum computer program (which can also be referred to or described as a program, software, a software application, a module, a software module, a script, or code) can be written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be translated into a suitable quantum programming language, or it can be written in a quantum programming language (e.g., QCL, Quipper, Cirq, etc.).

[0072] A digital and / or quantum computer program can, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that is used by the operating system to store an application program, in a file that is dedicated to storing computer programs (e.g., a file that is encoded with a proprietary format that is used to store one or more programs in a single file for execution by the digital and / or quantum computer), or in multiple coordinated files (e.g., files that store one or more modules, subprograms, or portions of code). A digital and / or quantum computer program can be deployed to be executed by one digital or one quantum computer, or alternatively, can be deployed to be executed by multiple digital and / or quantum computers that are functioning collectively.

[0073] The processes and logic flows described in this specification can be performed by one or more programmable digital and / or quantum computers, operating with one or more digital and / or quantum processors, executing one or more digital and / or quantum computer programs to perform functions by operating on input digital and quantum data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA or an ASIC, or a quantum simulator, or by a combination of special purpose logic circuitry or a quantum simulator and one or more programmed digital and / or quantum computers.

[0074] For a system of one or more digital and / or quantum computers or processors, “configured to” or “operable to” perform particular operations or actions means that the system has installed on it software, firmware, hardware, or a combination of them that in operation cause the system to perform the operations or actions. For one or more digital and / or quantum computer programs to be configured to perform particular operations or actions means that the one or more programs include instructions that operate on digital and / or quantum data to cause the apparatus to perform the operations or actions. Quantum computers can receive instructions from digital computers that, when executed by the quantum computing apparatus, cause the apparatus to perform operations or actions.

[0075] Digital and / or quantum computers suitable for the execution of a digital and / or quantum computer program can be based on general or special purpose digital and / or quantum microprocessors, or both, or any other kind of central digital and / or quantum processing unit. Generally, a central digital and / or quantum processing unit will receive instructions and digital and / or quantum data from a read only memory or from a random access memory or a quantum system suitable for transmitting quantum data (e.g., photons) or both, or from a combination thereof. The digital and / or quantum computer programs can be deployed in any memory or transmission media by the digital and / or quantum computer.

[0076] Some example elements of a digital and / or quantum computer are a central processing unit for performing instructions and one or more memory devices for storing instructions and digital and / or quantum data. The central processing unit and the memory can be supplemented or incorporated into by special purpose logic circuitry or quantum simulators. Generally, a digital and / or quantum computer will also include, or be operatively coupled to (to receive digital and / or quantum data therefrom, or to transmit digital and / or quantum data thereto, or both) one or more mass storage devices for storing digital and / or quantum data (such as magnetic, magneto-optical or optical disks, or quantum systems suitable for storing quantum information). A digital and / or quantum computer need not however have such devices.

[0077] Digital and / or quantum computer readable media suitable for storing digital and / or quantum computer program instructions and digital and / or quantum data include all forms of non-volatile digital and / or quantum memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices; magnetic disk such as a internal hard disks or removable disks; magneto-optical disk; CD-ROM and DVD-ROM disks; and quantum systems such as trapped atoms or electrons. It is to be understood that quantum memory is a device capable of storing quantum data with high fidelity, high efficiency, and for long periods of time, for example, using light-matter interfaces for transmission, and matter for storing and preserving quantum features of the data (e.g., superposition or quantum coherence).

[0078] The control of the various systems described in this specification, or portions of them, can be implemented in a digital and / or quantum computer program product that includes instructions that are stored in one or more tangible, non-transitory, machine-readable storage media and that are executable on one or more digital and / or quantum processing devices. The systems described in this specification, or portions of them, can each be implemented as an apparatus, method, or electronic system that can include one or more digital and / or quantum processing devices and memory storing executable instructions to perform the operations described in this specification.

[0079] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what can be claimed, but rather as descriptions of features that can be specific to particular implementations. Some features are described in independent claims to protect combinations of features. Dependent claims can refer to particular combinations of features. While specific implementations can have been described in some detail, it will be appreciated that various modifications and alterations can be made to the implementations and features described herein. Accordingly, it is not intended that the scope of the claims be limited by the scope of the disclosure. For example, while the subject matter has been described in language specific to structural features, it is to be understood that the subject matter defined in the claims can be embodied under different structural regimes and / or regimes including hardware and software. Moreover, various functions can be described in the claims as being performed by one or more entities. However, there are often aspects of the functions that can be performed by a different entity than is described in the claims. Accordingly, the claims are not to be construed as limited to the specific implementations described herein, but are to be construed in accordance with the appended claims, along with their full scope of equivalents.

[0080] Similarly, while operations are described in a particular, sequential order, this should not be understood as requiring such an order unless specifically stated, and that other operations be performed between two described operations. In some cases, multitasking and parallel processing can be advantageous. Moreover, the separation of various system modules and components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0081] Specific implementations of the subject matter have been described. Other implementations can be within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures can not require the particular order shown, or sequential execution of steps, to achieve desirable results. In some cases, multitasking and parallel processing can be advantageous.

Claims

1. A computer-implemented method for expanding a set of matching nodes in a partially matched graph, the method comprising: obtaining, by a computing system comprising one or more computing devices, a partially matched graph having a matching set, the partially matched graph comprising one or more edges and a plurality of nodes, the one or more edges having matching labels; obtaining, by the computing system, at least two unmatched nodes; determining, by the computing system, an alternating path from a first unmatched node of the at least two unmatched nodes to a second unmatched node of the at least two unmatched nodes, the alternating path comprising at least one edge of the one or more edges, wherein a cost of the alternating path comprises a sum of unmatched weights of unmatched edges in the alternating path, wherein the sum of unmatched weights is reduced by a sum of matching weights of matching edges in the alternating path; and reversing, by the computing system, matching labels of at least one edge of the alternating path such that the at least two unmatched nodes are included in the matching set of the partially matched graph.

2. The method of claim 1, wherein, determining the alternating path from the first unmatched node of the at least two unmatched nodes to the second unmatched node of the at least two unmatched nodes comprises: determining, by the computing system, a tree comprising a plurality of alternating paths from the first unmatched node to each node of the plurality of nodes; and selecting the alternating path from the tree.

3. The method of claim 2, wherein, determining, by the computing system, the tree comprising the plurality of alternating paths is performed by applying a Bellman-Ford algorithm to the partially matched graph.

4. The method of claim 2 or 3, wherein, none of the plurality of alternating paths comprise a cycle.

5. The method of any one of claims 1 to 3, wherein, each edge of the one or more edges comprises a weight.

6. The method of any one of claims 1 to 3, wherein, the alternating path comprises a minimum cost alternating path.

7. The method of any one of claims 1 to 3, wherein, the matching labels indicate one of a matching edge having a matching condition or an unmatched edge having an unmatched condition, and wherein the alternating path alternates between matching edges and unmatched edges.

8. The method of any one of claims 1 to 3, wherein, matching the graph such that each node of the plurality of nodes is contacted to at most one matching edge.

9. The method of any of claims 1 to 3, wherein, at least one of the at least two unmatched nodes comprises a boundary node.

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