Short-wave full-band radio frequency sampling device and method based on zero intermediate frequency technology

Abstract

The application discloses a short-wave full-band radio frequency sampling device and method based on a zero intermediate frequency technology, which comprises an AD sampling chip and a digital processing module. The method is as follows: the A / D sampling chip completes the sampling of the short-wave full-band radio frequency signal of 2-30 MHz through a sampling rate which is at least greater than 2 times of the highest frequency of the signal, and directly converts the collected analog radio frequency signal into a digital radio frequency signal; the digital radio frequency signal is distributed to multiple digital processing modules for parallel capturing of the full-band signal; the digital processing module adopts an FPGA chip, and the useful signal captured by the digital processing module is sent to a signal processing device through a service port for demodulation processing. The application can efficiently and reliably realize the analog-digital conversion of the full-band radio frequency signal, and greatly simplifies the hardware of a channel machine, thereby reducing the system cost, power consumption and equipment volume.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a shortwave full-band radio frequency sampling device and method based on zero intermediate frequency technology. Background Technology

[0002] In shortwave communication systems, most receivers currently use an intermediate frequency (IF) digitization scheme, which retains the receiver's radio frequency and analog mixing stages and performs digitization at a relatively low and fixed IF frequency. This scheme has a complex hardware structure, limited software functionality, and poor scalability.

[0003] Zero-IF (zero-intermediate-frequency) reception technology refers to the direct conversion of RF signals to analog baseband I / Q signals without conversion to an intermediate frequency (IF), followed by demodulation. Zero-IF technology includes two methods: segmented RF sampling and full-band RF sampling. Segmented RF sampling divides the shortwave full-band into several bands using an analog bandpass filter. Each band uses an analog converter (AD) chip to digitize the signal within its effective bandwidth, converting the RF signal within that band into a digital signal. This method uses more AD conversion chips and has a more complex hardware structure. Full-band RF sampling moves the sampling AD chip closer to the antenna, digitizing the RF signal as early as possible, representing a significant step towards the ideal goal of software-defined radio and an inevitable trend in shortwave reception technology development. Although zero-IF technology has been developing for many years and has been adopted by some types of paging and GSM mobile phones, current zero-IF technology cannot meet the high-performance requirements of circuits.

[0004] In summary, current radio frequency sampling devices have drawbacks such as complex hardware structure, high cost, and poor reliability. Furthermore, the complex hardware of the channel unit will introduce design noise, increase the combined tone interference of the receiver, and result in high system power consumption and large size. Summary of the Invention

[0005] The purpose of this invention is to provide a shortwave full-band radio frequency sampling device and method based on zero intermediate frequency technology, which can efficiently and reliably realize analog-to-digital conversion of full-band radio frequency signals. By greatly simplifying the hardware of the channel unit, the system cost is reduced while the system power consumption and device size are also reduced.

[0006] The technical solution to achieve the purpose of this invention is: a shortwave full-band radio frequency sampling device based on zero intermediate frequency technology, including an AD sampling chip and a digital processing module;

[0007] The A / D sampling chip completes the sampling of the entire shortwave frequency band RF signal from 2MHz to 30MHz by a sampling rate at least twice the highest frequency of the signal, and directly converts the acquired analog RF signal into a digital RF signal. The digital RF signal is then distributed to multiple digital processing modules for parallel acquisition of the entire frequency band signal.

[0008] The digital processing module uses an FPGA chip, and the useful signals captured by the digital processing module are sent to the signal processing equipment for demodulation processing through the service port.

[0009] Furthermore, the input front end of the AD sampling chip is equipped with a protection circuit, a filtering circuit, an attenuation control circuit, a low-noise amplifier, and a filter, wherein:

[0010] Protection circuitry is used to prevent large signals from damaging the receiver.

[0011] The filtering circuit uses a bandpass filter of 1.5 to 32 MHz to suppress non-shortwave frequency interference signals.

[0012] The attenuation control circuit contains two 10dB attenuation networks. When the input signal exceeds the threshold, the two attenuators are connected one after the other to suppress the signal exceeding the threshold.

[0013] Low-noise amplifier, employing a high-linearity low-noise amplifier in the shortwave band;

[0014] The filter performs anti-aliasing filtering.

[0015] Furthermore, the AD sampling chip uses the BLAD16D125 analog-to-digital converter, with a sampling rate of up to 125MHz, 16-bit data output, a working bandwidth of 300MHz, and a signal-to-noise ratio (SNR) of 78.2dB.

[0016] Furthermore, the AD sampling chip uses a 64-pin QFN package and can operate in an industrial-grade temperature range of -40°C to 85°C.

[0017] Furthermore, the FPGA chip processes the data and transmits the digital signal remotely via a 6.125Gbps optical fiber.

[0018] Furthermore, the sampling device is installed indoors or at the base of the antenna, and software maintenance and status queries are performed via a fiber optic interface.

[0019] Furthermore, the FPGA chip includes a digitally controlled oscillator (NCO), a digital multiplier, and a digital filter.

[0020] A shortwave full-band radio frequency sampling method based on zero intermediate frequency (IF) technology is described below:

[0021] The A / D sampling chip completes the sampling of the entire shortwave frequency band RF signal from 2MHz to 30MHz by a sampling rate at least twice the highest frequency of the signal, and directly converts the acquired analog RF signal into a digital RF signal. The digital RF signal is then distributed to multiple digital processing modules for parallel acquisition of the entire frequency band signal.

[0022] The digital processing module uses an FPGA chip, and the useful signals captured by the digital processing module are sent to the signal processing equipment for demodulation processing through the service port.

[0023] Furthermore, the input front end of the AD sampling chip is equipped with a protection circuit, a filtering circuit, an attenuation control circuit, a low-noise amplifier, and a filter, wherein:

[0024] Protection circuitry is used to prevent large signals from damaging the receiver.

[0025] The filtering circuit uses a bandpass filter of 1.5 to 32 MHz to suppress non-shortwave frequency interference signals.

[0026] The attenuation control circuit contains two 10dB attenuation networks. When the input signal exceeds the threshold, the two attenuators are connected one after the other to suppress the signal exceeding the threshold.

[0027] Low-noise amplifier, employing a high-linearity low-noise amplifier in the shortwave band;

[0028] The filter performs anti-aliasing filtering.

[0029] Furthermore, the AD sampling chip uses the BLAD16D125 analog-to-digital converter, with a sampling rate of up to 125MHz, 16-bit data output, a working bandwidth of 300MHz, and a signal-to-noise ratio (SNR) of 78.2dB.

[0030] Compared with the prior art, the significant advantages of this invention are:

[0031] (1) The radio frequency sampling module is based on the zero intermediate frequency shortwave full-band technology solution, which reduces the number of filters and AD chips, reduces the complexity of the equipment, reduces the cost, and improves the reliability;

[0032] (2) Compared with intermediate frequency digitization, zero intermediate frequency technology can greatly simplify the hardware of the channel machine. With the reduction of components such as mixer and independent frequency synthesis circuit, the design noise introduced by the system is reduced, the combined tone interference of the receiver is reduced, and the power consumption and equipment size are also reduced. Attached Figure Description

[0033] Figure 1 This is a structural diagram of the protection circuit.

[0034] Figure 2 This is a block diagram of a full-band radio frequency sampling receiver architecture.

[0035] Figure 3 This is a block diagram of the radio frequency sampling module. Detailed Implementation

[0036] Shortwave full-band RF sampling is a relatively ideal software radio architecture. This scheme performs shortwave band filtering on the shortwave full-band RF signal at the RF front end, and then directly digitizes the RF signal, converting it directly into a digital signal. A single AD chip can meet the requirements of shortwave full-band sampling, reducing equipment complexity, improving sampling reliability, and creating conditions for subsequent digital domain processing.

[0037] This invention provides a shortwave full-band radio frequency sampling device based on zero intermediate frequency technology, comprising an AD sampling chip and a digital processing module;

[0038] The A / D sampling chip completes the sampling of the entire shortwave frequency band RF signal from 2MHz to 30MHz by a sampling rate at least twice the highest frequency of the signal, and directly converts the acquired analog RF signal into a digital RF signal. The digital RF signal is then distributed to multiple digital processing modules for parallel acquisition of the entire frequency band signal.

[0039] The digital processing module uses an FPGA chip, and the useful signals captured by the digital processing module are sent to the signal processing equipment for demodulation processing through the service port.

[0040] Furthermore, the input front end of the AD sampling chip is equipped with a protection circuit, a filtering circuit, an attenuation control circuit, a low-noise amplifier, and a filter, wherein:

[0041] Protection circuitry is used to prevent large signals from damaging the receiver.

[0042] Combination Figure 1 Under normal use, the receiver can handle a maximum signal strength of 25 dBm. To prevent damage from rapid surges in strong signals exceeding this maximum, a discharge tube is used in the circuit design to suppress the pulse signal. First, a varistor is connected in parallel with the discharge tube. Second, a suitable transmission line is left between the discharge tube and V1 during wiring to reduce the voltage level. Simultaneously, a two-stage protection circuit is employed: the discharge tube FU1 as the first stage, and the semiconductor overvoltage protection V1 as the second stage, to ensure the receiver is not damaged by strong signal interference.

[0043] The filtering circuit uses a bandpass filter of 1.5 to 32 MHz to suppress non-shortwave frequency interference signals.

[0044] The attenuation control circuit contains two 10dB attenuation networks. When the input signal exceeds the threshold, the two attenuators are connected one after the other to suppress the signal exceeding the threshold.

[0045] Low-noise amplifier, employing a high-linearity low-noise amplifier in the shortwave band;

[0046] The filter performs anti-aliasing filtering.

[0047] Furthermore, the AD sampling chip uses the BLAD16D125 analog-to-digital converter, with a sampling rate of up to 125MHz, 16-bit data output, a working bandwidth of 300MHz, and a signal-to-noise ratio (SNR) of 78.2dB.

[0048] Furthermore, the AD sampling chip uses a 64-pin QFN package and can operate in an industrial-grade temperature range of -40°C to 85°C.

[0049] Furthermore, the FPGA chip processes the data and transmits the digital signal remotely via a 6.125Gbps optical fiber.

[0050] Furthermore, the sampling device is installed indoors or at the base of the antenna, and software maintenance and status queries are performed via a fiber optic interface.

[0051] Furthermore, the FPGA chip includes a digitally controlled oscillator (NCO), a digital multiplier, and a digital filter.

[0052] This invention discloses a shortwave full-band radio frequency sampling method based on zero intermediate frequency (IF) technology, as detailed below:

[0053] The A / D sampling chip completes the sampling of the entire shortwave frequency band RF signal from 2MHz to 30MHz by a sampling rate at least twice the highest frequency of the signal, and directly converts the acquired analog RF signal into a digital RF signal. The digital RF signal is then distributed to multiple digital processing modules for parallel acquisition of the entire frequency band signal.

[0054] The digital processing module uses an FPGA chip, and the useful signals captured by the digital processing module are sent to the signal processing equipment for demodulation processing through the service port.

[0055] Furthermore, the input front end of the AD sampling chip is equipped with a protection circuit, a filtering circuit, an attenuation control circuit, a low-noise amplifier, and a filter, wherein:

[0056] Protection circuitry is used to prevent large signals from damaging the receiver.

[0057] The filtering circuit uses a bandpass filter of 1.5 to 32 MHz to suppress non-shortwave frequency interference signals.

[0058] The attenuation control circuit contains two 10dB attenuation networks. When the input signal exceeds the threshold, the two attenuators are connected one after the other to suppress the signal exceeding the threshold.

[0059] Low-noise amplifier, employing a high-linearity low-noise amplifier in the shortwave band;

[0060] The filter performs anti-aliasing filtering.

[0061] Furthermore, the AD sampling chip uses the BLAD16D125 analog-to-digital converter, with a sampling rate of up to 125MHz, 16-bit data output, a working bandwidth of 300MHz, and a signal-to-noise ratio (SNR) of 78.2dB.

[0062] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0063] Example

[0064] The full-band RF sampling receiver directly performs 2-30MHz bandpass filtering, low-noise amplification, and anti-aliasing filtering on the RF signal. Then, the ADC directly performs analog-to-digital conversion to sample the signal. Next, a digital down-conversion module performs spectrum shifting and sampling rate conversion. Finally, the baseband processing section demodulates the signal. Figure 2 As shown, this can greatly simplify the hardware of the channel machine.

[0065] Shortwave full-band RF sampling technology utilizes high-speed, high-resolution AD sampling chips to sample shortwave RF signals ranging from 2MHz to 29.999MHz at a sampling rate at least twice the highest signal frequency (30MHz). Analog RF signals are directly converted to digital RF signals, which are then distributed to multiple digital processing modules for parallel acquisition across the entire frequency band. The captured useful signals are sent to signal processing equipment for demodulation via the service port. This centralized acquisition of digital RF signals and centralized demodulation of baseband signals significantly improves the utilization efficiency of device resources, enabling parallel reception across the entire frequency band and enhancing the equipment's service processing capabilities.

[0066] Full-band RF sampling receivers eliminate the need for analog mixers, local oscillators, and intermediate frequency filters, significantly simplifying the receiver's hardware circuitry. This reduces equipment costs, power consumption, and size, while also greatly improving stability and reliability. The ADC chip directly digitizes the RF signal, enabling subsequent digitization and software-based processing. Software running on the signal processing chip implements many of the receiver's analog component functions; for example, an NCO (Digital Controlled Oscillator) replaces the frequency synthesizer, a digital multiplier replaces the analog mixer, and digital filters replace LC filters, crystal filters, and other analog filtering circuits.

[0067] In principle, the ADC chip for the RF sampling module should ideally be selected with a wide processing bandwidth, high sampling rate, high resolution, and high conversion bit depth. Higher resolution requires a smaller input signal amplitude, less demand on the analog front-end amplification, and a higher conversion bit depth results in a higher A / D dynamic range. However, this also leads to higher power consumption and higher operating temperature for the ADC. After comprehensive consideration, the BLAD16D125 analog-to-digital converter is chosen for the RF sampling module. It boasts a sampling rate of up to 125MHz, 16-bit data output, a 300MHz operating bandwidth, and a signal-to-noise ratio (SNR) of 78.2dB. The chip uses a 64-pin QFN package for enhanced heat dissipation, allowing the system to operate within an industrial-grade temperature range of -40°C to 85°C even without a heatsink. This chip also offers a spurious-free dynamic range (SFDR) of up to -95dBc, providing a significant advantage for improving the dynamic range of the shortwave full-band receiver.

[0068] Therefore, the RF sampling module mainly consists of an A / D sampling chip and an FPGA chip. The RF sampling module is primarily used to sample RF signals across the entire 2–30MHz frequency band and digitize the analog signals. After processing by the FPGA, the digital signals are transmitted remotely via a 6.125Gbps fiber optic cable. The RF acquisition unit can be placed indoors or at the base of the antenna, and software maintenance and status queries can be performed via the fiber optic interface. The receiving RF front-end employs input protection, filtering, attenuation control, and amplification circuits. Input protection prevents damage to the receiver from large signals. The filtering circuit uses a 1.5–32MHz bandpass filter to suppress non-shortwave frequency interference signals. The attenuation control circuit includes two 10dB attenuation networks; when the input signal is too large, the two attenuators are connected sequentially to suppress the large signal. The amplifier uses a high-linearity, low-noise amplifier in the shortwave band, which effectively improves the overall sensitivity of the device. The block diagram of the RF sampling module is shown below. Figure 3 As shown.

[0069] This invention's RF sampling module is based on a zero-IF shortwave full-band technology solution, reducing the number of filters and AD chips, thus lowering equipment complexity, reducing costs, and improving reliability. It significantly simplifies the channel receiver hardware; the reduction in components such as mixers and independent frequency synthesis circuits lowers system design noise, reduces receiver combinatorial interference, and also reduces power consumption and device size.

Claims

1. A short wave full band radio frequency sampling device based on zero intermediate frequency technology, characterized in that, The AD sampling chip and a digital processing module are included; The AD sampling chip completes sampling of the full-band radio frequency signal of the short wave frequency band of 2-30 MHz through a sampling rate of at least 2 times of the highest frequency of the signal, and directly converts the collected analog radio frequency signal into a digital radio frequency signal, and the digital radio frequency signal is distributed to multiple digital processing modules for parallel capture of the full-band signal; The digital processing module adopts an FPGA chip, and the useful signal captured by the digital processing module is sent to a signal processing device through a service port for demodulation processing; The input front end of the AD sampling chip is provided with a protection circuit, a filter circuit, an attenuation control circuit, a low noise amplifier and a filter, wherein: The protection circuit is used to avoid damage of a large signal to the receiver; The filter circuit adopts a 1.5-32 MHz band-pass filter to complete suppression of the non-short wave frequency interference signal; The attenuation control circuit includes two 10 dB attenuation networks, and when the input signal exceeds a threshold, the two attenuation networks are connected one by one to suppress the signal exceeding the threshold; The low noise amplifier adopts a high linearity low noise amplifier of the short wave frequency band; The filter performs anti-aliasing filter processing; The AD sampling chip adopts a BLAD16D125 analog-to-digital converter, the sampling rate can reach 125 MHz, the 16-bit data output, the working bandwidth is 300 MHz, and the signal-to-noise ratio SNR is 78.2 dB; The AD sampling chip adopts a 64-pin QFN package and can work in an industrial temperature range of-40-85 degrees Celsius; The FPGA chip processes the digital signal and transmits the digital signal remotely through an optical fiber with a rate of 2.5 Gbps; The sampling device is arranged indoors or at the root of an antenna, and software maintenance and state query are performed through an optical fiber interface; The FPGA chip is provided with a digital control oscillator NCO, a digital multiplier and a digital filter.

2. A short wave full band radio frequency sampling method based on zero intermediate frequency technology, characterized in that, Specifically as follows: The AD sampling chip completes sampling of the full-band radio frequency signal of the short wave frequency band of 2-30 MHz through a sampling rate of at least 2 times of the highest frequency of the signal, and directly converts the collected analog radio frequency signal into a digital radio frequency signal, and the digital radio frequency signal is distributed to multiple digital processing modules for parallel capture of the full-band signal; The digital processing module adopts an FPGA chip, and the useful signal captured by the digital processing module is sent to a signal processing device through a service port for demodulation processing; The input front end of the AD sampling chip is provided with a protection circuit, a filter circuit, an attenuation control circuit, a low noise amplifier and a filter, wherein: The protection circuit is used to avoid damage of a large signal to the receiver; The filter circuit adopts a 1.5-32 MHz band-pass filter to complete suppression of the non-short wave frequency interference signal; The attenuation control circuit includes two 10 dB attenuation networks, and when the input signal exceeds a threshold, the two attenuation networks are connected one by one to suppress the signal exceeding the threshold; The low noise amplifier adopts a high linearity low noise amplifier of the short wave frequency band; The filter performs anti-aliasing filter processing; AD sampling chip adopts BLAD16D125 analog-digital converter, sampling rate can reach 125MHz, 16bit data output, working bandwidth 300MHz, signal noise ratio SNR is 78.2dB.

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