Multi-channel broadband signal transmitting and receiving device based on RFSOC (Radio Frequency System On Chip)

Abstract

The invention belongs to the technical field of signal generation and acquisition, and particularly relates to an RFSOC-based multichannel broadband signal transmitting and receiving device, which comprises an upper computer unit, an intermediate frequency signal transmitting and receiving unit, a down-conversion unit and a local oscillator unit, and is characterized in that the upper computer unit, the intermediate frequency signal transmitting and receiving unit, the down-conversion unit and the local oscillator unit cooperatively realize signal transmission and acquisition; the upper computer unit adopts an ARM chip, communicates with the intermediate frequency signal transceiving unit through a PCIE interface, and is used for parameter configuration, flow control, state monitoring and collected data storage. The integration level can be greatly improved, complex external connection and compatible debugging are omitted, software and hardware design is remarkably simplified, and the maintenance cost is reduced; different application scenes can be adapted without changing a hardware circuit, so that the configuration flexibility is greatly improved; the power consumption is reduced, and the application requirements of miniaturization and light weight are better met; and the requirements of multi-channel synchronous transceiving and high-precision signal processing can be met.

Description

Technical Field

[0001] This invention belongs to the field of signal generation and acquisition technology, specifically relating to a multi-channel broadband signal transceiver device based on RFSOC. Background Technology

[0002] In scenarios requiring multi-channel, broadband signal transmission and reception, such as radar detection, communication transmission, and electronic testing and measurement, it is used to realize the generation, transmission, reception, and acquisition processing of high-frequency signals. As core hardware, signal transceivers need to meet key requirements such as multi-channel synchronous operation, broadband signal coverage, and high sampling rate acquisition / transmission to ensure the accuracy of signal processing and the efficiency of the system. Currently, mainstream signal transceivers in the industry usually adopt an independent architecture design, that is, they select independent analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and field-programmable gate arrays (FPGAs) chips, and connect and integrate the chips through external hardware circuits to form a complete signal transceiver system. Specifically, existing stand-alone signal transceiver devices require dedicated power supply circuits, interface matching circuits, and timing synchronization circuits for each ADC, DAC, and FPGA chip, and then complex PCB routing to achieve data transmission and control signal interaction between the chips. To achieve multi-channel signal processing, multiple independent ADC / DAC chips and corresponding driver circuits also need to be configured, making the hardware structure of the entire device extremely cumbersome. However, the extensive use of independent chips and supporting circuits results in bulky and heavy devices, failing to meet the miniaturization and lightweight requirements of applications such as drones and portable testing equipment. Furthermore, the interface protocols and timing requirements of each independent chip differ, requiring significant effort for compatibility debugging. The fixed connection method of the hardware circuits also makes subsequent maintenance and upgrades difficult. Key parameters such as signal sampling rate, output frequency, and number of channels depend on the physical design of the hardware circuits. Adjusting operating parameters or adapting to different application scenarios often requires redesigning the hardware circuits, making it impossible to quickly switch functions through software configuration. Finally, the independent operation of multiple chips and the operation of complex supporting circuits generate significant power consumption, increasing energy consumption and potentially affecting the system's operational stability due to overheating issues. Therefore, there is an urgent need for a signal transceiver device that can solve the above-mentioned technical problems. Summary of the Invention

[0003] The purpose of this invention is to provide a multi-channel broadband signal transceiver based on RFSOC, which can significantly improve integration, eliminate complex external connections and compatibility debugging, significantly simplify hardware and software design, and reduce maintenance costs; it can adapt to different application scenarios without modifying the hardware circuit, greatly improving configuration flexibility; and it reduces power consumption, making it more suitable for miniaturized and lightweight applications; it can meet the requirements of multi-channel synchronous transmission and reception and high-precision signal processing, and is suitable for signal transmission and reception applications in multiple fields such as radar, communication, and test and measurement.

[0004] The specific technical solution adopted by this invention is as follows: A multi-channel broadband signal transceiver based on RFSOC includes a host computer unit, an intermediate frequency signal transceiver unit, a down-conversion unit, and a local oscillator unit. The host computer unit, intermediate frequency signal transceiver unit, down-conversion unit, and local oscillator unit work together to achieve signal transmission and acquisition.

[0005] The host computer unit uses an ARM chip and communicates with the intermediate frequency signal transceiver unit through a PCIE interface. It is used for parameter configuration, process control, status monitoring and data acquisition and storage. The configuration parameters include chip configuration, signal playback settings and signal acquisition settings. The intermediate frequency signal transceiver unit uses Xilinx's ZU47DRRFSOC chip as its core, integrating a parameter calculation module, a baseband signal generation module, an RFSOC hard core module, a packaging module, and a PCIE interface module. The RFSOC chip has a built-in 8-channel ADC, an 8-channel DAC, a digital up-converter, and a digital down-converter. The downconversion unit receives 8 channels of 0~10GHz radio frequency signals from external input, generates intermediate frequency signals through radio frequency downconversion processing, and transmits them to the intermediate frequency signal transceiver unit. The local oscillator unit generates a 100MHz reference clock and a down-conversion clock by multiplying the frequency of the crystal oscillator and the phase-locked loop, providing a synchronous clock reference for the intermediate frequency signal transceiver unit and the down-conversion unit.

[0006] The intermediate frequency signal transceiver unit also includes a multi-channel phase calibration module, and the local oscillator unit also includes a clock distribution submodule; The multi-channel phase calibration module communicates with the RFSOC hard core module and the parameter calculation module. It uses the reference signal injection method combined with cross-correlation calculation to calculate the phase difference of each channel and generate phase compensation coefficients. The clock distribution submodule uses a clock tree distribution network to transmit synchronous clocks and timing pulses to multi-channel and expansion boards via the LVDS differential signal interface.

[0007] The PCIe interface adopts the PCIe 4.0 x8 protocol and uses a data fragmentation transmission mechanism to adapt to the high sampling rate data transmission requirements.

[0008] The local oscillator unit and the parameter calculation module communicate via the SPI protocol; the DDS circuit of the baseband signal generation module adopts a 32-bit phase accumulator; the DDC module adopts a cascaded structure formed by a CIC decimation filter and an FIR low-pass filter.

[0009] It also includes a scenario-based function module, which allows switching between radar scenario sub-modules and communication scenario sub-modules; The radar scene submodule includes a pulse compression module and a multi-target detection module. The pulse compression module uses matched filtering and sidelobe suppression techniques, and the multi-target detection module uses the CFAR algorithm. The communication scenario submodule includes a modulation and demodulation unit and a channel coding module. The modulation and demodulation unit supports QPSK / 16QAM / 64QAM modulation, and the channel coding module uses LDPC coding.

[0010] It also includes a fault monitoring and redundancy module, which detects signal amplitude and phase changes in each channel; the intermediate frequency signal transceiver unit is configured with 4GB DDR4 local cache.

[0011] It also includes an electromagnetic compatibility optimization submodule, which employs a metal EMI shield, a power supply π-type filter circuit, a digital signal interface RC absorption circuit, and a single-point grounding design for digital ground and analog ground.

[0012] The technical effects achieved by this invention are as follows: This invention employs an RFSOC chip integrating an 8-channel ADC, an 8-channel DAC, and a DUC / DDC module, replacing the traditional discrete architecture of independent ADCs, DACs, and FPGAs. This significantly improves integration, eliminates complex external connections and compatibility debugging, simplifies hardware and software design, and reduces maintenance costs. Furthermore, it supports flexible configuration of chip parameters, signal types, sampling rates, and other key indicators via software, adapting to different application scenarios without modifying hardware circuitry, greatly enhancing configuration flexibility. The integrated design effectively reduces device size and weight, lowers power consumption, and better suits miniaturized and lightweight application requirements. It can achieve 0~10GHz wideband signal coverage, supports dual sampling rates of 250MHz / 1000MHz, meets the needs of multi-channel synchronous transmission and reception and high-precision signal processing, and is suitable for signal transmission and reception applications in radar, communication, test and measurement, and other fields. Attached Figure Description

[0013] Fig. 1 This is a system diagram of Embodiment 1 of the present invention; Fig. 2 This is a flowchart of Embodiment 1 of the present invention. Detailed Implementation

[0014] To make the objectives and advantages of this invention clearer, the invention will be specifically described below with reference to embodiments. It should be understood that the following text is merely used to describe one or more specific embodiments of the invention and does not strictly limit the scope of protection specifically claimed by the invention.

[0015] Example 1: like Figs. 1-2 As shown, a multi-channel broadband signal transceiver based on RFSOC includes a host computer unit, an intermediate frequency signal transceiver unit, a down-conversion unit, and a local oscillator unit. The host computer unit, the intermediate frequency signal transceiver unit, the down-conversion unit, and the local oscillator unit work together to achieve signal transmission and acquisition. The host computer unit uses an ARM chip and communicates with the intermediate frequency (IF) signal transceiver unit via a PCIe interface. It is used for parameter configuration, process control, status monitoring, and data acquisition and storage, controlling the down-conversion attenuation and frequency of the RF module. Simultaneously, it can monitor the status of the IF board and the RF serial port, and configure parameters including chip configuration, signal playback settings, and signal acquisition settings. The host computer unit is configured as follows: 1. Chip configuration: Clock Configuration: Sets the internal / external reference configuration for the clock; Output frequency: This setting specifies the device's output frequency. The device does not have an upconversion function; the radio frequency signal is output via RFSoc, up to a maximum of 10GHz. Input intermediate frequency point: This sets the intermediate frequency point of the device. Since the equipped RF center frequency is 100MHz, write 100 here. This value should match the center frequency point of the RF being used.

[0016] Configuration distribution: Distribute clock internal / external reference type and AD / DA reset; Clock reconfiguration: Send out the output frequency and input intermediate frequency and reset the AD and DA converters; Reset: Forced reset of AD and DA; 2. Signal playback settings: Signal type: You can choose from three signal types: continuous wave, monopulse, and linear frequency modulation; Pulse Width: When the signal type is selected as "Single Pulse" or "Linear Frequency Modulation", the pulse width needs to be set; Bandwidth: When the signal type is selected as "linear frequency modulation", the bandwidth needs to be set; Repetition period: When the signal type is selected as "single pulse" and "linear frequency modulation", the repetition period needs to be set; Delay time: Sets the delay of the signal relative to the rising edge of the trigger; 3. Signal Acquisition: Sampling rate: The current device is designed with sampling rates of 1x and 4x, where 1x is 250MHz and 4x is 1000MHz; Gate delay: The delay time of the acquisition gate relative to its trigger. Gate time: Acquisition duration; The intermediate frequency (IF) transceiver unit utilizes the Xilinx ZU47DRRFSOC chip, integrating a parameter calculation module, baseband signal generation module, RFSOC hard core module, packetization module, and PCIe interface module. The RFSOC chip incorporates an 8-channel ADC, an 8-channel DAC, a digital up-converter (DUC), and a digital down-converter (DDC), enabling operation at high sampling rates up to 10GHz. It features high integration, simple hardware design, flexible software configuration, small size, light weight, and low power consumption. The IF transceiver unit receives operating parameters from the host computer unit via the PCIe interface module and transmits them to the parameter calculation module. The parameter calculation module parses the parameters, extracting waveform control words, sampling gate control words, and RF receive control words, which are then configured for the baseband signal generation module, packetization module, and external local oscillator, respectively. The baseband signal generation module generates eight baseband transmit signals according to the set waveform control word using a DDS lookup table, and transmits them to the RFSOC hard core module. The RFSOC hard core module receives the baseband transmit signals generated by the baseband signal generation module, performs digital up-conversion processing according to the preset bandwidth parameters and RF frequency points, and then performs digital-to-analog conversion to obtain the RF transmit signal, which is then output to the outside at the maximum frequency. The RFSOC module also has the functions of ADC acquisition and digital down-conversion. It performs ADC acquisition on the intermediate frequency signal transmitted from the down-conversion unit and performs digital down-conversion processing according to the set bandwidth. The baseband acquisition signal is transmitted to the packetization module. The packetization module packages the baseband acquisition signal according to the set gate timing and transmits it to the PCIE interface module, and then to the host computer unit. The host computer unit is responsible for the final data storage of the acquired data. The downconversion unit receives 8 channels of 0~10GHz radio frequency signals from external input, generates intermediate frequency signals through radio frequency downconversion processing, and transmits them to the intermediate frequency signal transceiver unit; The local oscillator unit generates a 100MHz reference clock and down-conversion clock by multiplying the frequency of the crystal oscillator and the phase-locked loop, providing a synchronous clock reference for the intermediate frequency signal transceiver unit and the down-conversion unit.

[0017] Example 2: This embodiment is a further technical improvement based on Embodiment 1, and its technical effects and features are as follows: The intermediate frequency signal transceiver unit also includes a multi-channel phase calibration module, and the local oscillator unit also includes a clock distribution submodule; The multi-channel phase calibration module communicates with the RFSOC hard core module and parameter calculation module. It uses the reference signal injection method combined with cross-correlation calculation to calculate the phase difference of each channel and generate phase compensation coefficients to realize phase deviation detection and compensation of multi-channel ADC / DAC. The clock distribution submodule uses a clock tree distribution network to transmit synchronous clocks and timing pulses to multi-channel and expansion boards through the LVDS differential signal interface, ensuring timing consistency between boards.

[0018] This multi-channel coherent synchronization implementation employs a phase calibration algorithm. It utilizes a reference signal injection method to synchronously inject a 100MHz standard reference signal into eight ADC / DAC channels. The multi-channel phase calibration module calculates the phase difference between each channel and the reference signal through cross-correlation operations, generates phase compensation coefficients, and sends them to the timing control unit of the RFSOC hard core module to adjust the sampling / output timing of each channel in real time. After calibration, the phase difference of the multi-channel is controlled within ±0.3°, and the timing deviation is small. It utilizes a dynamic calibration mechanism to support two modes: periodic self-calibration and real-time monitoring calibration. Periodic self-calibration can be set with an adjustable period of 1 to 60 minutes. Real-time monitoring calibration collects phase data from each channel through a dedicated monitoring channel, and automatically triggers calibration when the phase deviation exceeds 0.1°. It can achieve expansion synchronization between boards. When the system is expanded to multiple RFSOC boards, the motherboard outputs a synchronization timing pulse through the clock distribution submodule, which is triggered by the rising edge and the pulse width can be 10ns. The board receives and locks the pulse through the LVDS interface to achieve a small clock synchronization error between multiple boards. The PCIe interface uses the PCIe 4.0 x8 protocol and employs a data fragmentation transmission mechanism to adapt to the requirements of high sampling rate data transmission. The data frame structure is designed as follows: The frame header, parameter / data area, and parity bit work together to ensure data transmission integrity. For the data transmission requirements of 8 channels and 16-bit width at a sampling rate of 1000MHz, a data fragmentation transmission mechanism is used to avoid bandwidth bottlenecks.

[0019] The local oscillator unit and the parameter calculation module communicate via the SPI protocol; the DDS circuit of the baseband signal generation module uses a 32-bit phase accumulator; the DDC module adopts a cascaded structure formed by a CIC decimation filter and an FIR low-pass filter, which improves the image rejection ratio and increases channel selectivity compared to the previous one.

[0020] Specifically as follows: The host computer unit sends out calibration instructions, including calibration mode and period parameters. After the parameter calculation module parses the instructions, it triggers the multi-channel phase calibration module to start. The multi-channel phase calibration module injects a reference signal, collects response data from each channel, and calculates the phase deviation and compensation coefficient. The compensation coefficients are transmitted to the RFSOC hard core module via the internal bus to adjust the sampling / output timing of each channel's ADC / DAC; After calibration, the multi-channel phase calibration module feeds back the calibration results, including the phase deviation values ​​of each channel and the calibration status, to the host computer. The host computer stores the calibration log and displays it in real time. Example 3: This embodiment is a further technical improvement based on Embodiments 1 and 2, and its technical effects and features are as follows: It also includes a scenario-based function module, which allows switching between radar scenario sub-modules and communication scenario sub-modules; The radar scene submodule includes a pulse compression module and a multi-target detection module. The pulse compression module uses matched filtering and sidelobe suppression technology to compress the linear frequency modulated signal. The multi-target detection module uses the CFAR algorithm and the constant false alarm rate (CFAR) detection algorithm, which significantly improves the target detection probability compared to the previous one. The communication scenario submodule includes a modulation and demodulation unit and a channel coding module. The modulation and demodulation unit supports three digital modulation methods: QPSK, 16QAM, and 64QAM, which reduces the modulation error rate. The demodulation uses a coherent demodulation algorithm. The channel coding module uses LDPC coding, which has a greater gain than before.

[0021] This module adopts a dynamic power management strategy. Idle channels of the RFSOC chip automatically shut down the corresponding ADC / DAC modules, and the clock frequency is dynamically adjusted according to the sampling rate, thereby reducing overall power consumption. It also includes a fault monitoring and redundancy module, which detects abrupt changes in the amplitude and phase of each channel signal to determine the fault of the ADC / DAC channel; the intermediate frequency signal transceiver unit is equipped with a 4GB DDR4 local cache. When the communication between the host computer and the intermediate frequency unit is interrupted, the acquired data is automatically cached and transmitted in the original order after the communication is restored. It also reserves one redundant channel. When any working channel fails, it automatically switches to the redundant channel to ensure continuous operation of the system.

[0022] It also includes an electromagnetic compatibility optimization submodule, which employs a metal EMI shield, a power supply π-type filter circuit, a digital signal interface RC absorption circuit, and a single-point grounding design for digital and analog grounds.

[0023] Specifically as follows: Taking a radar scenario as an example: The host computer unit selects the radar scene and configures parameters such as pulse compression ratio and CFAR detection type; The scene-based function module of the intermediate frequency signal transceiver unit is switched to the radar scene sub-module, and the baseband signal generation module generates a linear frequency modulated signal. The transmission process is the same as in Example 2. In the receiving process, the baseband acquisition signal output by the packet module is first transmitted to the pulse compression module for processing, and then the target information is extracted by the multi-target detection module. The target information, including target distance and speed, is uploaded to the host computer along with the original data. The host computer displays the target trajectory and stores the data in real time.

[0024] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. A multi-channel wideband signal transceiver based on RFSOC, characterized by, The application relates to a radar signal acquisition and emission device, which comprises a host computer unit, an intermediate frequency signal transceiving unit, a frequency down-conversion unit and a local oscillator unit, and the host computer unit, the intermediate frequency signal transceiving unit, the frequency down-conversion unit and the local oscillator unit cooperatively realize signal emission and collection. The host computer unit adopts an ARM chip, communicates with the intermediate frequency signal transceiving unit through a PCIE interface, is used for parameter configuration, flow control, state monitoring and collection data storage, and the configuration parameters include chip configuration, signal playing setting and signal collection setting. The intermediate frequency signal transceiving unit core adopts an Xilinx ZU47DRRFSOC chip, integrates a parameter solving module, a baseband signal generating module, an RFSOC hard core module, a packing module and a PCIE interface module, the RFSOC chip is internally provided with 8-channel ADC, 8-channel DAC, a digital up-converter and a digital down-converter. The frequency down-conversion unit receives external input 8-channel 0-10GHz radio frequency signals, generates intermediate frequency signals through radio frequency down-conversion processing and transmits the intermediate frequency signals to the intermediate frequency signal transceiving unit. The local oscillator unit generates 100MHz reference clock and down-conversion clock through crystal oscillator and phase-locked loop frequency multiplication, and provides synchronous clock reference for the intermediate frequency signal transceiving unit and the frequency down-conversion unit.

2. The RFSOC-based multi-channel wideband signal transceiver device according to claim 1, wherein: The intermediate frequency signal transceiving unit further comprises a multi-channel phase calibration module, and the local oscillator unit further comprises a clock distribution sub-module. The multi-channel phase calibration module communicates with the RFSOC hard core module and the parameter solving module, adopts a reference signal injection method combined with cross-correlation operation to calculate the phase difference of each channel, and generates a phase compensation coefficient. The clock distribution sub-module adopts a clock tree distribution network, transmits synchronous clock and timing pulse to the multi-channel and expansion board through an LVDS differential signal interface.

3. The RFSOC-based multi-channel wideband signal transceiver device of claim 1, wherein: The PCIE interface adopts PCIE4.0x8 protocol, adopts a data fragmentation transmission mechanism to adapt high sampling rate data transmission demand.

4. The RFSOC-based multi-channel wideband signal transceiver device of claim 3, wherein: The local oscillator unit communicates with the parameter solving module through an SPI protocol; the DDS circuit of the baseband signal generating module adopts a 32-bit phase accumulator; and the DDC module adopts a cascade structure formed by a CIC decimation filter and a FIR low-pass filter.

5. The RFSOC-based multi-channel wideband signal transceiver device of claim 4, wherein: Further comprising a scene function module, which switches and configures a radar scene sub-module or a communication scene sub-module; The radar scene sub-module comprises a pulse compression module and a multi-target detection module, the pulse compression module adopts matching filtering and sidelobe suppression technology, and the multi-target detection module adopts a CFAR algorithm; The communication scene sub-module comprises a modulation and demodulation unit and a channel coding module, the modulation and demodulation unit supports QPSK / 16QAM / 64QAM modulation, and the channel coding module adopts LDPC coding.

6. The RFSOC-based multi-channel wideband signal transceiver device of claim 5, wherein: Further comprising a fault monitoring and redundancy module, which detects signal amplitude and phase mutation of each channel; the intermediate frequency signal transceiving unit is configured with 4GB DDR4 local cache.

7. The RFSOC-based multi-channel wideband signal transceiver device of claim 6, wherein: Further comprising an electromagnetic compatibility optimization sub-module, which adopts a metal EMI shielding cover, a power supply end pi-type filtering circuit, a digital signal interface RC absorption circuit and a digital ground and analog ground single-point grounding design.

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