Circuit for background light suppression

Abstract

A circuit (SBI, 500) for background light suppression for a light travel time sensor (22) is described, the sensor operating according to the phase measurement principle and the light travel time pixel of which has an integration node or diode (Ga, Gb, diode_a, diode_b) for accumulating charge, the circuit having an input stage (50), an operational amplifier (OP) and an SBI current source (SQ), wherein the input stage (50) has a bypass and common mode circuit (SBP, SVcm), the signal of the integration node (Ga, Gb, diode_a, diode_b) is guided to the operational amplifier (OP) via the bypass and common mode circuit, and the operational amplifier (OP) can Switching to maximum detection or common mode operation, wherein the operational amplifier (OP) is designed so that a gate voltage (gate_cs) for an SBI current source (SQ) is generated based on a signal switched by an input stage (50) to an integral node (Ga, Gb, diode_a, diode_b) of the operational amplifier (OP), wherein the SBI current source (SQ) has a first current source (SQ1) for maximum detection operation and a second current source and a third current source (SQ2a, SQ2b) for common mode operation, wherein the current sources (SQ1, SQ2a, SQ2b) can be connected to the integral node (Ga, Gb, diode_a, diode_b) via a switch (S).

Description

Technical Field

[0001] The present invention relates to circuits for background light suppression. Background Art

[0002] In this article, the term light propagation time or time-of-flight camera or time-of-flight camera system is intended to specifically include systems that obtain distance based on the phase shift of emitted and received radiation. In particular, a PMD camera with a photomixing detector (PMD), such as described in DE 197 04 496 A1, is suitable as a time-of-flight or TOF camera.

[0003] Furthermore, so-called suppressed background illumination (SBI) circuits are known from DE 10 2004 016 626 A1, DE 10 2005 056 774 A1 and DE 10 2014 214 733 A1, which extend the dynamics of the pixels by suppressing the background light individually for each pixel. Summary of the Invention

[0004] The object of the present invention is to optimize a circuit for background light suppression with regard to functionality and space-saving arrangement.

[0005] This object is achieved by the circuit according to the invention.

[0006] According to the present invention, a circuit for background light suppression is provided for a time-of-flight sensor operating according to the phase measurement principle and whose time-of-flight pixels include an integration node or a diode for accumulating charge.

[0007] The invention comprises an input stage, an operational amplifier and an SBI current source, wherein the input stage comprises a bypass and a common-mode switch, a signal from an integral node is provided to the operational amplifier via the bypass and the common-mode switch, and the operational amplifier can be switched to a maximum value detection or a common-mode operation via the bypass and the common-mode switch.

[0008] wherein the operational amplifier is configured such that a gate voltage of the SBI current source is generated based on a signal switched to an integral node of the operational amplifier via an input stage node,

[0009] The SBI current source includes a first current source for a maximum detection mode and a second current source and a third current source for a common mode operation, wherein the current source can be connected to the integration node via a switch.

[0010] This SBI circuit has the advantage that a suitable SBI mode can always be found for different applications.

[0011] Advantageously, the second current source is configured as a low current source and the third current source is configured as a high current source.

[0012] This approach has the advantage that different compensation currents can be used depending on the background light present.

[0013] It is particularly useful if the operational amplifier has a differential input stage and a second branch consisting of transistors connected to the SBI threshold voltage, wherein, depending on the operating mode, the inputs pa and pb are either connected together to the common mode voltage or individually to the diode voltage.

[0014] Likewise, it would be advantageous to provide a time-of-flight pixel with the aforementioned circuitry for background light suppression, and to construct a time-of-flight sensor with a corresponding time-of-flight pixel.

[0015] It is also useful to provide a time-of-flight camera comprising the aforementioned circuit or a plurality of the aforementioned time-of-flight pixels, and in particular it is advantageous to design a time-of-flight camera for TOF operation and combined TOF and triangulation operation, wherein background light suppression is performed in maximum detection mode and in TOF and triangulation operation in common mode operation.

[0016] The time-of-flight camera is suitably configured such that, in common mode operation, switching between the second current source and the third current source is performed in dependence on external light incident on the time-of-flight sensor.

[0017] This process advantageously enables an adequate response to different application conditions, such that a safe operation of the time-of-flight camera is permanently guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings schematically show:

[0019] Figure 1 : Time-of-flight camera system;

[0020] Figure 2 : modulation integral of generated carriers;

[0021] Figure 3 : Cross section of a PMD time-of-flight sensor with potential distribution;

[0022] Figure 4 : the change of the integrated voltage at the time-of-flight pixel over time;

[0023] Figure 5 : Potential curves at the time-of-flight pixel with and without SBI;

[0024] Figure 6 : Circuits for charge compensation known in the prior art;

[0025] Figure 7 : Voltage curve of the maximum value detector SBI;

[0026] Figure 8 : Common mode SBI voltage curve;

[0027] Figure 9 : a block diagram of a circuit according to the present invention; and

[0028] Figure 10 : Input stage of the operational amplifier. DETAILED DESCRIPTION

[0029] In the following description of the preferred embodiments, the same reference numerals denote the same or corresponding components.

[0030] Figure 1 A measurement situation is shown for optical distance measurement using a time-of-flight camera, as is known, for example, from DE 197 04 496 A1.

[0031] The time-of-flight camera system 1 comprises a transmitting unit or lighting module 10 comprising an illumination device 12 and associated beam shaping optics 15 and a receiving unit or time-of-flight camera 20 comprising receiving optics 25 and a time-of-flight sensor 22 .

[0032] The time-of-flight sensor 22 comprises at least one time-of-flight pixel, preferably also a pixel array, and is specifically configured as a PMD sensor. The receiving optics 25 generally consists of several optical elements to improve the imaging characteristics. The beam shaping optics 15 of the transmitting unit 10 can be configured as a reflector or lens optics, for example. In a very simplified embodiment, the optical elements on both the receiving side and the transmitting side can also be omitted.

[0033] The measurement principle of this arrangement is essentially based on the fact that starting from the phase shift of the emitted and received light, the propagation time of the received light and therefore the distance traveled by the received light can be determined. For this purpose, the light source 12 and the time-of-flight sensor 22 are jointly provided with a base phase position via the modulator 30. In the example shown, a phase shifter 35 is further provided between the modulator 30 and the light source 12, by means of which the base phase of the modulation signal M0 of the light source 12 is shifted. Can be set at a limited phase position For typical phase measurements, it is preferable to use the phase position 90°, 180° and 270°.

[0034] According to the set modulation signal, the light source 12 emits a signal with a first phase position p1 or The intensity modulation signal S p1 In the case shown, the signal S p1 Or electromagnetic radiation is reflected by the object 40 and is phase shifted accordingly due to the distance traveled At the second phase position Impact time-of-flight sensor 22, as the received signal S p2 In the time-of-flight sensor 22, the modulation signal M0 and the received signal S p2 Frequency mixing, wherein the phase shift or object distance d is determined from the resulting signal.

[0035] Furthermore, the system comprises a modulation controller 27 which changes the phase position of the modulation signal M0 according to the measurement task at hand. and / or adjusting the modulation frequency via the frequency oscillator 38 .

[0036] Preferably, the illumination source or light source 12 is an infrared light emitting diode. Of course, other radiation sources in other frequency ranges are conceivable, in particular light sources in the visible frequency range.

[0037] Figure 2 The basic principle of phase measurement is schematically shown in FIG. The upper curve shows the time course of the modulation signal M0, with which the lighting device 12 and the time-of-flight sensor 22 are driven. The light reflected by the object 40 is measured according to its flight time t L Phase shift Impact time-of-flight sensor 22, as the received signal S p2 The time-of-flight sensor 22 accumulates the photogenerated charge q in the phase position of the modulation signal M0 in the first accumulation gate Ga and in the phase position M0+180° shifted by 180° in the second accumulation gate Gb over a plurality of modulation cycles. The phase shift can be determined based on the ratio of the charges qa and qb accumulated in the first gate Ga and the second gate Gb. And thus the distance d of the object can be determined.

[0038] Figure 3 A cross-section of a pixel of a photomixing detector, such as that known from DE 197 04 496 C2, is shown. Modulated photogates Gam, G0, Gbm form the photosensitive region of the PMD pixel. Depending on the voltage applied to the modulation gates Gam, G0, Gbm, the photogenerated charge q is directed to one or the other accumulation gate / integration node Ga, Gb or diodes diode_a, diode_b, respectively. The integration node can be configured as a gate or a diode.

[0039] Figure 3 b shows the potential curve, where the charge q flows in the direction of the first integrating gate Ga, and according to Figure 3The potential of c allows charge q to flow in the direction of the second integrating node Gb. The potential is predetermined by the applied modulation signal. Depending on the application, the modulation frequency is preferably in the range of 1 to 100 MHz. For example, a modulation frequency of 1 MHz produces a time period of one microsecond, resulting in a corresponding change in the modulation potential every 500 nanoseconds.

[0040] Figure 3 A also shows a readout unit 400, which may already be a part of a PMD time-of-flight sensor configured in CMOS form. The integration nodes Ga and Gb in the form of capacitors or diodes integrate the light-generated charge in multiple modulation cycles. In a known manner, the voltage provided at gates Ga and Gb can then be, for example, tapped with high impedance via the readout unit 400. The integration time is preferably selected so that for the expected amount of light, the time-of-flight sensor or integration node and / or photosensitive area will not cause saturation.

[0041] Figure 4 shows the voltage U provided at the integration nodes Ga, Gb during phase measurement a 、U b Typical time characteristics of the reset node. DRS Initially, the voltage drops due to the accumulated photoelectrons at the integration nodes Ga and Gb. The voltages at the integration nodes Ga and Gb drop to different degrees. int At the end, the voltage U provided at the integration nodes Ga and Gb is read. a 、U b . Two voltages U a 、U b The voltage difference ΔU corresponds in a known manner to the difference Δq of the charges q accumulated at the integration nodes Ga, Gb. int It is preferred that no integrating node Ga, Gb reaches its saturation potential U during normal exposure. s For greater signal strengths, a so-called SBI circuit can be provided for signal compensation. Such a circuit is known, for example, from DE 10 2004 016 626 A1 or DE 10 2005 056 774 A1.

[0042] Figure 5 The signal U provided at the integration nodes Ga, Gb and diodes a, b respectively during the measurement is shown. a 、U b After reset, a reset voltage U with a positive potential is provided at the integration nodes Ga, Gb. RESIn the example shown, charge compensation should not be effective at the start of the measurement at start time t0. As the number of collected carriers or photoelectrons increases, the voltage U at the integration nodes Ga, Gb increases. a 、U b reduce.

[0043] If the charge at the integration nodes Ga, Gb is not compensated in the further process, the potential U at the integration nodes Ga, Gb a 、U b Further decreases, as shown by the dotted line. In the case shown, the second integration node Gb is at the saturation time t s Reaching saturation potential U sat , after which the integration node saturates and the phase reference provided for the accumulated charge or voltage is lost. Saturation occurs when no further carriers can accumulate due to an insufficient potential gradient in the semiconductor or when leaving the readout range of the readout device 400. Distance values determined after this point in time are erroneous.

[0044] In order to prevent or delay such saturation, it is known, for example from DE 10 2005 056 774 A1, to SBI (In this case, at the first time point t1), charge compensation is achieved at the two integration nodes Ga and Gb. k The compensation current i is applied to both the integration nodes Ga and Gb. k For example, (U a 、U b ) is determined by the slope of the larger potential drop and, if necessary, adjusted by the compensation factor k.

[0045]

[0046] It is also possible to preferably control the control system according to the electric variable i provided at the integration node Ga, Gb a 、i b 、U a 、U b Provide compensation current i k Such a control system is known, for example, from DE 10 2004 016 626 A1 and in particular from DE 10 2005 056 774 A1, which is explicitly mentioned in different variants in this document. A characteristic feature of such a control system is that the compensation current i k Specified by the control system so that the SBI potential limit U is reached first SBI The potential of the integration node remains constant.

[0047] This process in Figure 5The charge accumulation is shown in the solid line. k In the example shown, the second integration node Gb has the largest potential drop and reaches the SBI potential limit U first. SBI By using the SBI control system, it is now possible to set the compensation current i k , so that the potential at the integration node Gb remains substantially constant. The first integration node Ga is provided with a compensation current i of the same magnitude. k , and is thus quasi-overcompensated, so that the potential increases with the start of compensation. This overcompensation can continue until the first integration node Ga reaches a reference potential U substantially predetermined by the circuit design. com .

[0048] Figure 6 An example of an SBI circuit 500 for charge compensation, known from DE 10 2005 056 774 A1, is shown. Preferably, the SBI circuit 500 is an integral part of the readout device 400. However, in principle, a design independent of the readout device 400 is also conceivable. In this example and in the following examples, the illustrated switches or transistors M1 to M7 are designed as PMOS transistors.

[0049] Of course, the embodiment is not limited to a PMOS structure, but can also be designed as an NMOS structure. In the circuit, only the potential distribution changes. In the NMOS design, the power supply voltage is at the negative GND potential instead of the positive U DD potential, and the reference potential is at U DD The relationship with respect to other potentials changes accordingly.

[0050] The SBI circuit 500 , in combination with the control transistor M7 and the first and second input transistors M1 and M2 , forms a source follower with two inputs, by means of which the first and second SBI current transistors M3 and M4 are driven.

[0051] At the start of the measurement, the gate potential is usually set so that the transistors M1 to M6 are closed. S Preferably, it is already present at the gate of transistor M7. However, no current flows through transistor M7, since transistors M1 and M2 are still closed.

[0052] The source terminals of the transistors M3, M4 and M7 are connected to the supply voltage U DD A reset potential U is provided at the source terminals of the reset transistors M5 and M6. RES , and the reset switch potential U RES _N to drive the gate.

[0053] The potential U of the integration nodes Ga and Gb a 、U b are respectively connected to the storage device 300, which is preferably configured as a source follower. In addition, the potential U of the integration node Ga, Gb a 、U b Also provided at the gates of the SBI input transistors M1, M2.

[0054] If any of the integration nodes Ga, Gb does not reach the SBI threshold U during the measurement SBI , then the SBI input transistors M1 and M2 and the SBI current transistors M3 and M4 remain closed and there is no charge compensation. After the measurement is completed, the reset switch signal U RES_N The integration nodes Ga and Gb are connected to the reset potential U through the reset switches M5 and M6. RES , and the integration nodes Ga and Gb are reset to this potential.

[0055] If during the integration period, the voltage U at one of the integration nodes Ga, Gb a 、U b Reaching SBI threshold U SBI , then one of the SBI input transistors M1 or M2 is turned on, so that the current I7 flows from U through the control transistor M7. DD Flows to ground GND. The input transistors M1 and M2 with lower gate potential determine the output voltage of the source follower. The output voltage is used to drive the two SBI current transistors M3 and M4, which then act as current sources to provide the same magnitude of compensation current i to the two integration nodes Ga and Gb. k .

[0056] When the SBI threshold is reached, the compensation current i k is equal in magnitude to the photocurrent of the deeper channel or integration node Ga, Gb, which reaches the SBI threshold first. Figure 5 As shown, the second integration node Gb first reaches the SBI threshold U SBI , the second switching transistor M2 determines the output voltage of the source follower and thus determines the compensation current i k .

[0057] SBI switching threshold U SBI It is optional within certain specifications and depends primarily on the following factors.

[0058]

[0059] Among them, U S : Control voltage, U th_min_a,b: Effective SBI threshold voltage at SBI input transistors M1 and M2; n: Technology-related fitting parameter, U T : Temperature-related voltage component; I 0_M3,4 : Transfer current across transistor M3 or M4.

[0060] The drain current I D Or compensation current i k is derived in a known manner from the following formula.

[0061]

[0062] Where, I0: transfer current of transistor, U GS : Gate-source voltage, U th : Threshold voltage, U T : Temperature-dependent voltage component.

[0063] SBI insertion threshold U SBI Mainly determined by the size of the SBI and pixel circuit in the chip design. In the ready-to-use state, it can be used to adjust the SBI threshold U SBI The only parameter is essentially the control voltage U at transistor M7 S However, it is variable only within certain limits due to interactions with other potentials. S Small changes in U are usually accompanied by large changes in the source current (subthreshold region). This leads to a modification of the control characteristics of the SBI circuit and, especially for large pixel matrices, may lead to an unacceptable increase in the total current consumption due to the increase in the drain current I7. Therefore, via the control voltage U S SBI threshold U SBI Regulation is only reasonably possible within small limits.

[0064] Typically, SBI circuits are designed as maximum value detectors, as previously described, or as common mode SBI, and usually include a generally limited extraneous photocurrent range.

[0065] The background light suppression circuit or SBI circuit according to the present invention combines the functions of a maximum value detector and a common mode detector and significantly extends the extraneous photocurrent range of the switchable current source used.

[0066] The SBI circuit according to the invention is particularly suitable for different ambient light situations, from little ambient light to direct ambient light, and can therefore also be used under difficult operating conditions, such as direct ambient light illumination at a short distance.

[0067] Figure 7 and Figure 8 The maximum detector operation is shown ( Figure 7) and common mode operation ( Figure 8 )'s voltage characteristics at the two diode nodes diode_a and diode_b.

[0068] like Figure 9 An advantage of the illustrated SBI circuit according to the present invention is that operational amplifier OP can be used for both the maximum detector and common-mode operation. Switching between the two functions is accomplished by switching the input transistors or input switches SE of operational amplifier OP in input stage 50. This eliminates the need for two separate circuits, thereby reducing the required space and current consumption on the chip.

[0069] Additionally, the proposed SBI circuit has a wide dynamic range since it is suitable for both high and low extraneous photocurrents due to the switchable current source SQ.

[0070] The corresponding current range can be selected by switching the SBI current source SQ. In addition, the SBI circuit can be switched between maximum detector and common mode operation by an external signal.

[0071] The possible extraneous photocurrent range in which the maximum value detector operates is fixed and lies, for example, between 1 nA and 1 μA.

[0072] In common mode operation, the current range can be changed by changing the current source. For example, a low current source SQ2a can be provided for a current range of 50nA to 10μA, and a high current source SQ2b can be provided for a current range of 1μA to 100μA.

[0073] Moreover, due to different current ranges, different sizes of current source transistors are advantageous. For low currents, the gate should preferably be designed with a small width and a large length. This size design prevents the transistor from entering the subthreshold region.

[0074] For larger currents, the width should be larger and the gate length should be smaller to prevent the transistor from saturating at low operating voltages. At the same time, the operational amplifier OP's control of the transistor and the stability of the control loop must be considered over all current ranges.

[0075] like Figure 9 As shown, the SBI circuit 500 is generally composed of three components, namely, an input stage 50, an operational amplifier OP, and an SBI current source SQ having switchable current sources SQ1, SQ2a, and SQ2b.

[0076] The input stage 50 includes two reset switches SR, preferably two PMOS switches, which pull the two diode nodes diode_a and diode_b to a defined reset voltage vreset when the SBI circuit 500 is in the reset mode.

[0077] If common mode operation is activated, such as Figure 9 As shown, a common mode voltage Vcm is derived from the two diode voltages diode_a and diode_b via two capacitors in the input stage and is forwarded uniformly to the inputs p_a and p_b of the operational amplifier OP via two common mode switches SVcm.

[0078] If maximum detector operation is selected, the two bypass transistors / switches SBP are activated, which switch the diode voltages diode_a and diode_b to the inputs p_a and p_b of the operational amplifier, respectively. In this case, the common-mode switch SVcm is open.

[0079] The operational amplifier OP is used to generate the loop gain required for control and drive the SBI current source SQ. The inputs p_a and p_b of the OPV are selectively switched to common mode or to separate diode voltages diode_a and diode_b by switches in the input stage.

[0080] The operational amplifier OP is preferably designed as a folded cascode operational amplifier with a differential input stage. The OP circuit has an internal common-mode feedback (CMFB) which drives the current source of the folded cascode stage of the operational amplifier and thus controls the common mode.

[0081] The output stage of the operational amplifier OP is preferably constituted by a PMOS source follower, which drives the gates of the SBI current sources SQ1 , SQ2 , thereby regulating the SBI currents I_sbi_a and I_sbi_b accordingly.

[0082] The generation of the bias voltages for the operational amplifier OP is preferably done externally in a separate bias block. This allows biasing several SBIs simultaneously, which further reduces the required area and current consumption.

[0083] The SBI current source SQ includes an SBI current source SQ1 for maximum value detector operation and SBI current sources SQ2a and SQ2b for common mode operation, which provide compensation currents I_sbi_a and I_sbi_b to diodes diode_a, diode_b and thus compensate for extraneous photocurrent.

[0084] The gates of current sources SQ1, SQ2a, and SQ2b are driven by the output stage of an operational amplifier (PMOS source follower), thereby determining the compensation currents I_sbi_a and I_sbi_b of the current sources.

[0085] Due to the current requirements of different applications, different current sources are used for the maximum detector SBI and common mode SBI, which differ in gate size and current output. For maximum detection operation, time-of-flight applications are generally considered. Common mode operation is preferably suitable for triangulation applications with or without parallel time-of-flight operation.

[0086] The current sources SQ2a and SQ2b of the common mode SBI can be switched between a small current source array of low current source SQ2a for low extraneous light conditions and a large current source array of high current source SQ2b for high extraneous light conditions depending on the situation (low or high extraneous light).

[0087] For maximum detector operation, such switching is usually not provided for current source SQ1, since the outgoing photocurrent is usually much lower there.

[0088] In the power-off / off or standby mode, preferably by switching the off Switching the gate to the operating voltage VDD de-energizes the current source (PMOS), allowing only low leakage current to flow. An additional PMOS switch S with low leakage current isolates the unused current source from the diode nodes diode_a and diode_b, so that no undesirable coupling occurs between the maximum detector and the common mode SBI.

[0089] The SBI circuit proposed here preferably also has a comparator (not shown here) which monitors the common mode voltage Vcm or the gate voltage Gate_cs of the current source and thus indicates when the SBI circuit is active. The reference voltage for the comparator is generated externally in a separate block.

[0090] This architecture enables the realization of a highly robust, low-noise, and flexible SBI circuit with a wide dynamic range and the ability to deliver high currents even under difficult operating conditions. At the same time, the circuit is characterized by low current consumption and low SBI asymmetry.

[0091] On the other hand, there is the circuit of the differential input stage of the operational amplifier. Figure 10 As shown, the input stage consists of four transistors N1-N4, two of which are cross-connected (inputs pa and pb).

[0092] These four transistors form one branch of the differential input stage. The other branch consists of transistor N5, whose gate is connected to the given SBI threshold voltage vsbi. Depending on the operating mode (common mode or maximum detector), inputs pa and pb are connected together to the derived common mode Vcm or individually to the diode voltages diode_a and diode_b. The cross-coupling of these four transistors achieves high symmetry in the input stage, which ultimately leads to low input offset in the circuit. This presupposes that this symmetry is also implemented in the layout.

[0093] Reference Signs List

[0094] 1Time-of-Flight Camera System

[0095] 10 Lighting equipment, transmitters

[0096] 20 receivers, time-of-flight camera

[0097] 12 light sources

[0098] 22 Time of Flight Sensors

[0099] 30 modulators

[0100] Propagation time-dependent phase shift

[0101] Phase position

[0102] Reference Phase

[0103] M0 modulation signal

[0104] p1 first phase

[0105] p2 second phase

[0106] S p1 The transmission signal S with a first phase p2 Integration node for receiving signals Ga and Gb with a second phase

[0107] U a 、U b Voltage at the integration node

[0108] d Object distance

[0109] 300 storage devices

[0110] 400 readout circuit

[0111] 500SBI circuit, charge compensation equipment U com Reference potential

[0112] U SBI SBI threshold

[0113] U RES Reset voltage

[0114] U RES_N Reset switch potential

[0115] U DD Power supply voltage

[0116] U S Control voltage

[0117] U th Threshold voltage

[0118] U sat Saturation potential

[0119] M1..Switch / Transistor

[0120] M1, M2 SBI input transistors

[0121] M3, M4 SBI current transistor

[0122] M5, M6 reset switch

[0123] M7 controls the transistor

[0124] M8, M9 hold transistors

Claims

1. A background light suppression circuit (SBI, 500) for a time-of-flight sensor (22) operating according to the phase measurement principle and whose time-of-flight pixels comprise integrating nodes or diodes (Ga, Gb, diode_a, diode_b) for accumulating charge; comprising an input stage (50), an operational amplifier (OP) and an SBI current source (SQ), in, The input stage (50) includes a bypass and common-mode switch (SBP, SVCm), the signal of the integration node (Ga, Gb, diode_a, diode_b) is supplied to the operational amplifier (OP) via the bypass and common-mode switch, and the operational amplifier (OP) can be switched to a maximum detection operation or a common-mode operation via the bypass and common-mode switch, wherein the operational amplifier (OP) is configured to generate a gate voltage (gate_cs) for the SBI current source (SQ) based on the signal switched to the integration node (Ga, Gb, diode_a, diode_b) of the operational amplifier (OP) via the input stage (50), The SBI current source (SQ) includes a first current source (SQ1) for the maximum value detection operation and a second current source and a third current source (SQ2a, SQ2b) for the common mode operation. The current sources (SQ1, SQ2a, SQ2b) can be connected to the integration nodes (Ga, Gb, diode_a, diode_b) via switches (S).

2. The circuit according to claim 1, wherein The second current source (SQ2a) is configured as a low current source, and the third current source (SQ2b) is configured as a high current source.

3. A circuit according to any one of the preceding claims, wherein The operational amplifier comprises a differential input stage and a second branch consisting of a transistor (N5) connected to an SBI threshold voltage (vsbi), Here, inputs pa and pb are connected together to a common-mode voltage (Vcm) or individually to diode voltages (diode_a, diode_b), depending on the operating mode.

4. A time-of-flight pixel comprising a background light suppression circuit (500) according to any one of the preceding claims. 5 . A time-of-flight sensor comprising the circuit according to claim 1 or comprising a plurality of time-of-flight pixels according to claim 4 . A time-of-flight camera comprising the time-of-flight sensor according to claim 5 .

7. A time-of-flight camera according to claim 6, configured for TOF operation and combined TOF and triangulation operation, in, Background light suppression in the TOF operation occurs in the maximum detection operation as well as the TOF and triangulation operations in the common mode operation.

8. The time-of-flight camera according to claim 7, configured such that, in the common-mode operation, switching between the second current source and the third current source (SQ2a, SQ2b) is effected in dependence on external light incident on the time-of-flight sensor.

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