Display panel and display device

Abstract

Embodiments of the present invention disclose a display panel and a display device. The display panel includes a pixel circuit and a light-emitting element; in the pixel circuit, a driving module includes a driving transistor, the gate of the driving transistor is connected to a first node; a reset module includes a first sub-transistor and a second sub-transistor, the connection node between the first sub-transistor and the second sub-transistor is a second node; a compensation module includes a third sub-transistor and a fourth sub-transistor, the connection node between the third sub-transistor and the fourth sub-transistor is a third node; in a first stage, the first dual-gate transistor and the second dual-gate transistor are both turned off, and the first node, the second node, and the third node satisfy (V2-V1)×(V1-V3)>0. The embodiment of the present invention solves the problem of the potential change of the first node caused by the leakage current of the transistor, can ensure that the voltage of the first node is relatively stable, maintain the stability of the brightness of the light-emitting element, and improve the display effect of the display panel.

Description

[0001] This application is a divisional application of the patent with the application date of May 17, 2021, application number: 202110536427.3, and invention name: Display panel and display device. Technical Field

[0002] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light-Emitting Diodes (OLEDs), with their advantages of low power consumption, low cost, self-luminescence, wide viewing angles, and fast response times, have become a research hotspot in the display field. Electronic display products utilize varying refresh rates for different application scenarios. For example, a higher refresh rate is used for dynamic images to ensure smooth display, while a lower refresh rate is used for static images to reduce power consumption.

[0004] When electronic products using organic self-luminous technology display at a low refresh rate, the gate potential of the driving transistor in the existing pixel circuit will change due to leakage problems of other switches, causing the brightness of the light-emitting element to continuously decrease and then increase when driving it, resulting in unstable display brightness of the display panel, affecting the display effect and user experience. Summary of the Invention

[0005] The present invention provides a display panel and a display device to stabilize the potential of a gate of a driving transistor in a pixel circuit, maintain the stability of the brightness of a light-emitting element, and improve the display effect of the display panel.

[0006] In a first aspect, an embodiment of the present invention provides a display panel, including:

[0007] Pixel circuits and light-emitting elements;

[0008] The pixel circuit includes a driving module, a reset module and a compensation module;

[0009] The driving module is used to provide a driving current for the light emitting element, and the driving module includes a driving transistor, wherein the gate of the driving transistor is connected to the first node;

[0010] The reset module is used to provide a reset signal for the gate of the driving transistor, the reset module includes a first dual-gate transistor, the first dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a second node;

[0011] The compensation module is used to compensate for the threshold voltage of the driving transistor, and the compensation module includes a second dual-gate transistor, the second dual-gate transistor includes a third sub-transistor and a fourth sub-transistor, and the connection node between the third sub-transistor and the fourth sub-transistor is a third node; wherein,

[0012] The working process of the pixel circuit includes a first stage. In the first stage, the first dual-gate transistor and the second dual-gate transistor are both turned off, the voltage of the first node is V1, the voltage of the second node is V2, and the voltage of the third node is V3, wherein (V2-V1)×(V1-V3)>0.

[0013] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display device as described in any one of the first aspects.

[0014] In this embodiment, the voltage between the first node and the third node is set to satisfy (V2-V1)×(V1-V3)>0, which can ensure that the voltage of the first node is between the voltage of the second node and the voltage of the third node. In this case, even if there is a voltage difference between the first node and the second node and the third node, the two voltage differences are of different positive and negative values, and the direction of the leakage current of the sub-transistor between the nodes caused by the voltage difference is different. For the first node, the leakage current will flow from the second node through the first node to the third node, or from the third node through the first node to the second node. Compared with the prior art where both the second node and the third node flow leakage current into the first node, the embodiment of the present invention can ensure that the voltage of the first node is relatively stable. The embodiment of the present invention solves the problem in the prior art that the transistor leakage current caused by the scan signal and the capacitor causes the potential of the first node to change. By changing the node voltage difference, the influence of the leakage current on the first node is reduced, and the voltage of the first node is relatively stable, thereby maintaining the stability of the brightness of the light-emitting element and improving the display effect of the display panel, especially under low-frequency driving. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a schematic structural diagram of a pixel circuit in an existing display panel provided by an embodiment of the present invention;

[0016] Figure 2 This is a schematic structural diagram of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present invention;

[0017] Figure 3 is a timing diagram of driving signals of a pixel circuit provided by an embodiment of the present invention;

[0018] Figure 4 This is a schematic structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0019] Figure 5 This is a structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0020] Figure 6 This is a structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0021] Figure 7 This is a structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0022] Figure 8 This is a structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention;

[0023] Figure 9 is a schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0025] Figure 1 is a schematic diagram of the structure of a pixel circuit in an existing display panel provided by an embodiment of the present invention, with reference to Figure 1 As described in the background technology section, the first node N1 in the existing pixel circuit 10 is connected to the gate of the driving transistor T3, one end of the first dual-gate transistor T1, and one end of the second dual-gate transistor T2. Those skilled in the art will appreciate that the pixel circuit may include a reset phase, a data write phase, and a light-emitting phase. In the reset phase, the first dual-gate transistor T1 provides a reset signal Vref to reset the potential of the first node N1. In the data write phase, the second dual-gate transistor T2 writes a data signal data to the first node N1 and simultaneously compensates the threshold voltage of the driving transistor T3 to the potential of the first node N1. In the light-emitting phase, the driving transistor T3 drives the light-emitting element 20 to emit light using the data signal stored in the gate, i.e., the first node N1, and after threshold compensation.

[0026] It should be noted that the dual-gate transistor in this pixel circuit includes two sub-transistors, and a capacitor is connected in parallel between the node connecting the two sub-transistors and their gates. It is understood that when the two sub-transistors are turned on or off by a scan signal, one of the capacitor plates also receives the scan signal. Due to the charging and discharging principles of capacitor plates, the charge on the two plates of the capacitor affects each other. That is, when one plate receives a scan signal, it affects the potential of the other plate, causing the potential of the connection node between the two sub-transistors to be affected. Taking the first dual-gate transistor T1 shown in the figure as a P-type dual-gate transistor as an example, the connection node between the first sub-transistor T11 and the second sub-transistor T12 in the first dual-gate transistor T1 is the second node N2. During the light-emitting phase, the gate of the first dual-gate transistor T1 receives the first scan signal S1 (a high-level signal) and is turned off. At this time, the second capacitor C2 raises the potential of the second node N2 due to this high-level signal, causing the potential of the second node N2 to be greater than the potential of the first node N1. This causes leakage current in the second sub-transistor T12 during this phase, and the potential of the first node N1 to increase. Similarly, the second dual-gate transistor T2, also a P-type transistor, will have the same effect on the first node N1 during this light-emitting phase. The potential of the third node N3 is raised due to the influence of the third capacitor C3 and the second scan signal S2 (a high-level signal), causing the potential of the third node N3 to be greater than the potential of the first node N1. The third sub-transistor T23 in the second dual-gate transistor T2 also generates leakage current, causing the potential of the first node N1 to increase. Ultimately, the potential of the first node N1 will be affected by the potentials of the second node N2 and the third node N3, causing the sub-transistor to generate leakage current, thereby affecting the potential of the first node N1. Experiments have found that during this phase, when the driving transistor T3 drives the light-emitting element 20 to illuminate, the brightness of the light-emitting element 20 will continuously decrease and then gradually recover due to the changes in the first node N1, resulting in unstable brightness of the light-emitting element 20.

[0027] Based on the above problem, an embodiment of the present invention provides a display panel. The display panel includes: a pixel circuit and a light-emitting element; the pixel circuit includes a driving module, a reset module, and a compensation module; the driving module is used to provide a driving current for the light-emitting element, the driving module includes a driving transistor, and the gate of the driving transistor is connected to a first node; the reset module is used to provide a reset signal to the gate of the driving transistor, the reset module includes a first dual-gate transistor, the first dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a second node; the compensation module is used to compensate for the threshold voltage of the driving transistor, the compensation module includes a second dual-gate transistor, the second dual-gate transistor includes a third sub-transistor and a fourth sub-transistor, and the connection node between the third sub-transistor and the fourth sub-transistor is a third node; wherein the operation process of the pixel circuit includes a first stage, in the first stage, the first dual-gate transistor and the second dual-gate transistor are both turned off, the voltage of the first node is V1, the voltage of the second node is V2, and the voltage of the third node is V3, wherein (V2-V1)×(V1-V3)>0.

[0028] In this embodiment, the voltage of the first node-the third node is set to satisfy (V2-V1)×(V1-V3)>0, which can ensure that V2>V1 while V3<V1, or, V3>V1 while V2<V1. In other words, this embodiment can ensure that the voltage of the first node is between the voltage of the second node and the voltage of the third node. At this time, even if there is a voltage difference between the first node and the second node and the third node respectively, the two voltage differences are of different positive and negative values, and the direction of the leakage current of the sub-transistor between the nodes caused by the voltage difference is different. For the first node, the leakage current will flow from the second node through the first node until it flows to the third node, or from the third node through the first node until it flows to the second node. It can be understood that compared with the prior art in which both the second node and the third node flow leakage current into the first node, the embodiment of the present invention can ensure that the voltage of the first node is relatively stable. Therefore, in the pixel circuit provided by the embodiment of the present invention, on the basis of satisfying the relationship (V2-V1)×(V1-V3)>0, even if the voltages of the second node and the third node change due to the scanning signal and the capacitor, it will not have much impact on the voltage of the first node, thereby ensuring the relative stability of the voltage of the first node.

[0029] The above is the core concept of the present invention. The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0030] Figure 2This is a schematic diagram of the structure of a pixel circuit and a light-emitting element in a display panel provided by an embodiment of the present invention, with reference to Figure 2 The display panel includes: a pixel circuit 10 and a light-emitting element 20; the pixel circuit 10 includes a driving module 11, a reset module 12 and a compensation module 13; the driving module 11 is used to provide a driving current for the light-emitting element 20, the driving module 11 includes a driving transistor T3, and the gate of the driving transistor T3 is connected to the first node N1; the reset module 12 is used to provide a reset signal for the gate of the driving transistor T3, the reset module 12 includes a first dual-gate transistor T1, the first dual-gate transistor T1 includes a first sub-transistor T11 and a second sub-transistor T12, and the connection node between the first sub-transistor T11 and the second sub-transistor T12 is the second node N 2; the compensation module 13 is used to compensate for the threshold voltage of the driving transistor T3, and the compensation module 13 includes a second dual-gate transistor T2, and the second dual-gate transistor T2 includes a third sub-transistor T23 and a fourth sub-transistor T24, and the connection node between the third sub-transistor T23 and the fourth sub-transistor T24 is a third node N3; wherein, the operation process of the pixel circuit 10 includes a first stage, in which the first dual-gate transistor T1 and the second dual-gate transistor T2 are both turned off, the voltage of the first node N1 is V1, the voltage of the second node N2 is V2, and the voltage of the third node N3 is V3, wherein (V2-V1)×(V1-V3)>0.

[0031] Furthermore, in the pixel circuit, the reset module 12 is connected between the reset signal terminal Vref and the gate of the driving transistor T3, one end of the first dual-gate transistor T1 is connected to the reset signal terminal Vref, and the other end is connected to the gate of the driving transistor T3; the compensation module 13 is connected between the gate of the driving transistor T3 and the drain of the driving transistor T3, one end of the second dual-gate transistor T2 is connected to the gate of the driving transistor T3, and the other end is connected to the drain of the driving transistor T3.

[0032] In addition, in this embodiment, the pixel circuit 10 is connected to the first power supply voltage signal terminal PVDD for receiving the first power supply voltage signal, which is a constant high-level signal. The gate of the first dual-gate transistor T1 is connected to the first scan signal line S1 for receiving the first scan signal. The pixel circuit 10 includes a second capacitor C2, wherein the first plate of the second capacitor C2 is connected to the first scan signal line S1 and the second plate is connected to the second node N2. The gate of the second dual-gate transistor T2 is connected to the second scan signal line S2 for receiving the second scan signal. The pixel circuit 10 includes a third capacitor C3, wherein the first plate of the third capacitor C3 is connected to the second scan signal line S2 and the second plate is connected to the third node N3.

[0033] Figure 3This is a timing diagram of the driving signal of the pixel circuit provided by the embodiment of the present invention. Figure 2 and Figure 3 The functional modules and driving process of the pixel circuit in the embodiment of the present invention are introduced. It should be noted that the transistors T1-T7 in the pixel circuit of this embodiment are illustratively P-type transistors. When the control signal provided to their gates is at a high level, the transistors are turned off, and when the control signal is at a low level, the transistors are turned on. In addition to the driving module 11, the reset module 12, and the compensation module 13, the pixel circuit also includes a light control module 14, an initialization module 15, and a data writing module 16. The light control module 14 includes a first light control module 141 and a second light control module 142. The first light control module 141 includes a fifth transistor T5, the second light control module 142 includes a sixth transistor T6, the initialization module 15 includes a seventh transistor T7, and the data writing module 16 includes a fourth transistor T4. The gates of the fifth transistor T5 and the sixth transistor T6 are both connected to the light control signal terminal EM; one end of the seventh transistor T7 is connected to the initialization signal terminal Vini, and the other end is connected to the anode of the light-emitting element 20; one end of the fourth transistor T4 is connected to the data signal terminal Vdata, and the other end is connected to the driving module 11, i.e., the first end of the driving transistor T3. In addition, other connection relationships between functional modules or transistors such as Figure 2 As shown, no further details are given here.

[0034] Those skilled in the art will appreciate that the driving process of this pixel circuit includes an initialization (reset) phase ta, a data writing phase tb, and a light-emitting phase tc. During the initialization (reset) phase ta, the first scanning signal S1 transitions from a high level to a low level, at which point the first dual-gate transistor T1 turns on, and the reset signal Vref is written to the first node N1. Simultaneously, the fourth scanning signal S4 transitions from a high level to a low level, at which point the seventh transistor T7 turns on, and the initialization signal Vini is written to the anode of the light-emitting element 20. This initialization (reset) phase is used to reset or initialize the first node N1 and the anode of the light-emitting element 20 to avoid the influence of the voltage signal written in the previous frame.

[0035] During the data writing (threshold capture) phase tb, the third scan signal S3 transitions from a high level to a low level, turning on the fourth transistor T4. Simultaneously, the second scan signal S2 transitions from a high level to a low level, turning on the second dual-gate transistor T2. The data signal Vdata flows sequentially through the fourth transistor T4, the drive transistor T3, and the second dual-gate transistor T2 into the first node N1. Since the voltage at the fourth node N4 is Vdata, when the voltage at the first node N1 reaches Vdata-Vth (Vth is the threshold voltage of the drive transistor T3), the drive transistor T3 turns off. In other words, during this phase, the threshold-compensated data voltage signal Vdata-Vth is written to the first node N1.

[0036] During the light-emitting phase tc, the light-emitting control signal EM transitions from a high level to a low level. At this point, the fifth transistor T5 and the sixth transistor T6 are turned on, forming a path from the first power supply voltage signal terminal PVDD to the second power supply voltage signal terminal PVEE. The light-emitting element 20 emits light, and the magnitude of the light-emitting current is controlled by the gate potential of the driving transistor T3. Since the voltage stored at the first node N1 in the previous phase is Vdata-Vth, and the voltage at the third node N3 is slightly higher than the second power supply voltage signal terminal PVEE, the current passing through the driving transistor T3 is I=K(N2-N1-Vth)=K(PVDD-Vdata). It can be understood that the greater the voltage stored at the first node N1, the greater the light-emitting current and the greater the brightness of the light-emitting element 20. The voltage at the first node N1 affects the brightness of the light-emitting element 20.

[0037] Based on the driving process of the above-mentioned pixel circuit, it should be noted that in the embodiment of the present invention, in the first stage, the voltage between the first node N1 and the third node N3 satisfies (V2-V1)×(V1-V3)>0, wherein the first stage is the time period when the first dual-gate transistor T1 and the second dual-gate transistor T2 are turned off. As can be seen from the driving process of the above pixel circuit, there is at least a light-emitting stage during which the first dual-gate transistor T1 and the second dual-gate transistor T2 need to be turned off. In this embodiment, the voltage between the first node N1 and the third node N3 is set to satisfy (V2-V1)×(V1-V3)>0 to prevent the shutdown signal from affecting the second node N2 and the third node N3 when the first dual-gate transistor T1 and the second dual-gate transistor T2 are turned off, thereby affecting the voltage of the first node N1.

[0038] Specifically, when V2>V1 and V3<V1, a voltage difference exists across the second sub-transistor T12 between the second node N2 and the first node N1 due to V2>V1. If leakage occurs in the second sub-transistor T12, the leakage current will flow from the second node N2 to the first node N1. Simultaneously, because V3<V1, a voltage difference exists across the third sub-transistor T23 between the third node N3 and the first node N1. If leakage occurs in the third sub-transistor T23, the leakage current will flow from the first node N1 to the third node N3. At this point, the voltage at the first node N1 is less affected by the transistor leakage current and can remain essentially stable. When V2<V1 and V3>V1, a voltage difference exists across the second sub-transistor T12 between the second node N2 and the first node N1 due to V2<V1. If leakage occurs in the second sub-transistor T12, the leakage current will flow from the first node N1 to the second node N2. At the same time, because V3>V1, a voltage difference exists across the third sub-transistor T23 between the third node N3 and the first node N1. If leakage current occurs in the third sub-transistor T23, the leakage current will flow from the third node N3 to the first node N1. At this time, the voltage at the first node N1 is less affected by the transistor leakage current and can remain basically stable.

[0039] Based on the same principle, it can be understood that when both the first dual-gate transistor T1 and the second dual-gate transistor T2 are N-type transistors, the voltage at the first node N1 will also be affected by the second node N2 and the third node N3. Specifically, because the gates of the first and second dual-gate transistors T1 and T2 are low-level signals when they are turned off, the potentials of the second and third nodes N2 and N3 will be lower than the potential of the first node N1 through the influence of capacitance, causing leakage current to flow from the second sub-transistor T12 to the second node N2 and from the first node N1 to the third node N3, respectively, resulting in a decrease in the potential of the first node N1. In this case, in this embodiment, the voltage between the first node N1 and the third node N3 is set to satisfy (V2-V1)×(V1-V3)>0, which can also ensure that V2>V1 and V3<V1, or V2<V1 and V3>V1. In this case, the leakage current between the first node N1, the second node N2, and the third node N3 flows from the second node N2 to the third node N3 via the first node N1, or from the third node N3 to the second node N2 via the first node N1. Obviously, in this case, the first node N1 is less affected by the transistor leakage current, and the voltage can also remain basically stable.

[0040] To achieve that the voltage between the first node N1 and the third node N3 satisfies (V2-V1)×(V1-V3)>0, continue to refer to Figure 1 In one embodiment of the present invention, the voltage between the first node N1 and the third node N3 can optionally satisfy V2 < V1 < V3. Specifically, the pixel circuit 10 can include a first capacitor C1, wherein a first plate of the first capacitor C1 is connected to the first power supply voltage signal terminal PVDD, and a second plate is connected to the second node N2.

[0041] It can be understood that, since the second node N2 in the pixel circuit of this embodiment is electrically connected to the first power supply voltage signal terminal PVDD via the first capacitor C1, and the first power supply voltage signal terminal PVDD is a constant high-level signal, the potential of the second node N2 in the first phase is simultaneously affected by the charge and discharge of the capacitor plates of the first capacitor C1 and the second capacitor C2. Specifically, in this first phase, the first scanning signal S1 transitions from a low level VGL to a high level VGH, turning off the first dual-gate transistor T1. Simultaneously, the first capacitor C1 and the second capacitor C2 are connected in series. Since the first capacitor C1 is connected to a constant high-level signal, it can be seen that the potential of the second node N2, V2 = (VGH - VGL) × C2 / (C1 + C2) + Vref1. It can be seen from the formula that compared with not setting the first capacitor C1, the potential of the second node N2 will be appropriately reduced at this time, so that the potential of the first node N1 is between the potentials of the second node N2 and the third node N3, that is, V2<V1<V3, thereby avoiding the leakage current from the second node N2 to the first node N1, affecting the change of the potential of the first node N1, and thus ensuring the relative stability of the brightness of the light-emitting element 20.

[0042] Furthermore, in the embodiment of the present invention, the first capacitor C1 and the second capacitor C2 may be configured to satisfy the relationship: C1 > C2. According to the above-described potential formula for the second potential N2, the larger the first capacitor C1, the smaller the potential V2 of the second node N2. In this case, the potential of the second node N2 can be minimized, allowing the leakage current of the second sub-transistor T12 to flow toward the second node N2, thereby preventing the potential of the first node N1 from changing.

[0043] Further optionally, in the embodiment of the present invention, the second capacitor C2 and the third capacitor C3 may be set to satisfy: C2≤C3. Figure 2 As shown, illustratively, since the second dual-gate transistor T2 is a P-type transistor, in the first phase, the second scan signal S2 transitions from a low level to a high level, turning off the second dual-gate transistor T2. At this point, under the action of the third capacitor C3, the second scan signal S2 raises the potential of the third node N3. Since the relationship between voltage U, capacitance C, and charge Q is: U = Q / C, the larger the capacitance C, the smaller the voltage U. Therefore, in this embodiment, setting C2 ≤ C3 ensures that the potential of the third node N3 is raised higher, thereby ensuring that V1 < V3 is satisfied for the first node N1 and the third node N3.

[0044] In summary, Figure 2 In the illustrated embodiment, a first capacitor C1 may be optionally provided between the first power supply voltage signal terminal PVDD and the second node N2, and the first capacitor C1 may be provided to be greater than the second capacitor C2, while the second capacitor C2 may be provided to be greater than or equal to the third capacitor C3, so as to achieve that the voltage between the first node N1 and the third node N3 satisfies V2<V1<V3, thereby causing the leakage current between the first node N1 and the third node N3 to flow from the third node N3 through the first node N1 to the second node N2, thereby preventing the first node N1 from receiving excessive leakage current and causing the potential to rise, thereby affecting the stability of the light-emitting brightness of the light-emitting element.

[0045] In another embodiment of the present invention, the voltages between the first node N1 and the third node N3 may also be optionally set to satisfy V2 < V1 < V3. Figure 4 is a schematic structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, with reference to Figure 4 In this embodiment, one end of the first sub-transistor T11 is optionally connected to the reset signal terminal Vref, and the other end is connected to the second node N2. In the first stage, the first sub-transistor T11 remains in the on state and the second sub-transistor T12 remains in the off state.

[0046] It can be understood that if the first sub-transistor T11 is set to remain in the on state in the first stage, the second node N2 will always receive the signal of the reset signal terminal Vref in this stage, and the potential of the second node N2 will be the low-level reset signal. At this time, the potential V2 of the second node N2 is lower than the potential V1 of the first node N1.

[0047] Specifically, in order to achieve the above-mentioned first sub-transistor T11 being kept in the turned-on state in the first stage, as shown in FIG. Figure 4 As shown, in this embodiment, the gate of the first sub-transistor T11 can be connected to the reset signal line Vref to receive the reset signal. It will be appreciated that because the first sub-transistor T11 is a P-type transistor and the reset signal line Vref is a low-level signal, when the gate of the first sub-transistor T11 is connected to the reset signal line Vref, the first sub-transistor T11 remains in an on state under the control of the effective reset signal. This ensures that the second node N2 receives the reset signal in the first phase, and the potential of the second node N2 is lower than that of the first node N1.

[0048] Figure 5 This is a schematic diagram of the structure of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, based on the same concept, such as Figure 5The pixel circuit shown also includes an initialization module 15, which is connected between the initialization signal terminal Vini and the light-emitting element 20 to provide an initialization signal for the light-emitting element 20; wherein the gate of the first sub-transistor T11 can be set to be connected to the initialization signal line Vini to receive the initialization signal.

[0049] What is similar is that the effective signals of the initialization signal line Vini and the reset signal Vref are both low-level signals. In order to ensure that the first sub-transistor T11 is in the turned-on state in the first stage and the second node N2 receives the reset signal Vref, the low-level initialization signal can also be used to control the first sub-transistor T11 to remain in the turned-on state. That is, as mentioned above, the gate of the first sub-transistor T11 can be set to be connected to the initialization signal terminal Vini.

[0050] In addition to the above embodiment in which the pixel circuit structure can be changed to make the potential of the first node N1-third node N3 satisfy V2<V1<V3, other embodiments of the present invention can also set the potential of the first node N1-third node N3 to satisfy V2>V1>V3.

[0051] Figure 6 This is a structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, with reference to Figure 6 First, in the pixel circuit, the gate of the first dual-gate transistor T1 is connected to the first scanning signal line S1 for receiving the first scanning signal; wherein, the pixel circuit 10 includes a second capacitor C2, the first plate of the second capacitor C2 is connected to the first scanning signal line S1, and the second plate is connected to the second node N2. The gate of the second dual-gate transistor T2 is connected to the second scanning signal line S2 for receiving the second scanning signal; wherein, the pixel circuit 10 includes a third capacitor C3, the first plate of the third capacitor C3 is connected to the second scanning line S2, and the second plate is connected to the third node N3. wherein, the pixel circuit 10 can be set to be connected to the first power supply voltage signal terminal PVDD for receiving the first power supply voltage signal, the first power supply voltage signal being a constant high level signal; wherein, the pixel circuit 10 includes a first capacitor C1, the first plate of the first capacitor C1 is connected to the first power supply voltage signal terminal PVDD, and the second plate is connected to the third node N3.

[0052] Similarly, the two substrates of the first capacitor C1 are respectively connected to the first power supply voltage signal and the third node N3, so that the first capacitor C1 and the third capacitor C3 form a series structure. Since one end of the first capacitor C1 is connected to the first power supply voltage signal end PVDD (constant high-level signal), compared with not setting the first capacitor C1, the potential of the third node N3 at this time will be appropriately reduced, and the potential of the first node N1 will be located between the potentials of the third node N3 and the second node N2, that is, V2>V1>V3, thereby avoiding leakage current from the third node N3 to the first node N1, affecting the change in the potential of the first node N1, and thus ensuring the relative stability of the brightness of the light-emitting element 20.

[0053] Similarly, based on the principle that the larger the first capacitor C1, the lower the potential V3 of the third node N3, in this embodiment, the first capacitor C1 and the third capacitor C3 can be configured to satisfy the relationship: C1 > C3. This minimizes the potential of the third node N3, allowing the leakage current of the third sub-transistor T23 to flow toward the third node N3, thereby preventing the potential of the first node N1 from changing.

[0054] Furthermore, according to U=Q / C, the larger the capacitance C, the smaller the voltage U. Therefore, the second capacitor C2 and the third capacitor C3 can be set to satisfy: C2 ≥ C3. This ensures that the potential of the second node N2 is higher, thereby making the first node N1 and the second node N2 satisfy V1<V2.

[0055] In another embodiment of the present invention, the voltages between the first node N1 and the third node N3 may also be set to satisfy V2>V1>V3. Figure 7 This is a structural diagram of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, with reference to Figure 7 In this embodiment, one end of the fourth sub-transistor T24 is optionally connected to the third node N3, and the other end is connected to the drain of the driving transistor T3. In the first stage, the fourth sub-transistor T24 remains in the on state and the third sub-transistor T23 remains in the off state.

[0056] Similarly, the fourth sub-transistor T24 is set to remain in the on state in the first stage. In this stage, the third node N3 is always equal to the drain potential of the driving transistor T3. Because when the first dual-gate transistor T1 and the second dual-gate transistor T2 are both turned off, that is, when the reset module 12 and the compensation module 13 are both turned off, the pixel circuit 10 is in the light-emitting stage, and the driving transistor T3 is in a non-saturated state in the light-emitting stage, so that the drain potential of the driving transistor T3 is generally at a lower potential (the driving transistor is a P-type transistor). At this time, the third node N3 is at a lower potential, so that the potential of the third node N3 is lower than the potential of the first node N1.

[0057] Specifically, in order to achieve the fourth sub-transistor T24 being kept turned on in the first stage, as shown in FIG. Figure 7 As shown, in this embodiment, the gate of the fourth sub-transistor T24 can be connected to the reset signal line Vref to receive the reset signal. It can be understood that because the fourth sub-transistor T24 is a P-type transistor and the reset signal line Vref is a low-level signal, when the gate of the fourth sub-transistor T24 is connected to the reset signal line Vref, the fourth sub-transistor T24 remains in an on state under the control of the effective reset signal. This ensures that the potential of the third node N3 remains consistent with the drain potential of the driving transistor T3 during the first phase, and the potential of the third node N3 is lower than the potential of the first node N1.

[0058] Figure 8 This is a schematic diagram of the structure of a pixel circuit and a light-emitting element in another display panel provided by an embodiment of the present invention, based on the same concept, such as Figure 8 The pixel circuit shown also includes an initialization module 15, which is connected between the initialization signal terminal Vini and the light-emitting element 20 and is used to provide an initialization signal for the light-emitting element 20; wherein the gate of the fourth sub-transistor T24 is connected to the initialization signal line Vini and receives the initialization signal.

[0059] What is similar is that the effective signals of the initialization signal line Vini and the reset signal Vref are both low-level signals. In order to ensure that the fourth sub-transistor T24 is in the on state in the first stage and the potential of the third node N3 is kept consistent with the drain potential of the driving transistor T3, the low-level initialization signal Vini can also be used to control the fourth sub-transistor T24 to remain in the on state. That is, as mentioned above, the gate of the fourth sub-transistor T24 can be set to be connected to the initialization signal terminal Vini.

[0060] Based on the various embodiments described above, the present invention further defines the transmission time of leakage current flowing from the second node N2 and the third node N3 to the first node N1. Specifically, in the first stage, the leakage current transmission time between the second node N2 and the first node N1 is t1, and the leakage current transmission time between the third node N3 and the first node N1 is t2. The smaller of t1 and t2 is t0, the frame refresh frequency of the display panel is MHz, and t0 ≥ 1 / MHz.

[0061] It can be understood that the display panel's frame refresh frequency is MHz, and the duration of one frame is 1 / M. In this embodiment, the smaller of the leakage current transmission time from the second node N2 to the first node N1 and the leakage current transmission time from the third node N3 to the first node N1 is set to be greater than or equal to the duration of one frame of the display panel, that is, t0 is set to ≥ 1 / M. Therefore, during the light-emitting phase of one frame, the first node N1 always participates in the leakage current process of the second node N2 and the leakage current process of the third node N3. That is, the leakage current flows from the second node N2 through the first node N1 and then into the third node N3, or the leakage current flows from the third node N3 through the first node N1 and then into the second node N2. At this time, the first node N1 is always in a leakage current equilibrium state, and the potential of the first node N1 changes relatively little or even remains unchanged, thereby ensuring stable luminance of the light-emitting element.

[0062] Furthermore, in the embodiment of the present invention, 0≤|t1-t2|≤t0×1 / 5 can be set. In this case, the difference between t1 and t2 is relatively small, which can ensure that t0 is relatively large during the entire pixel driving process, thereby extending the leakage current balancing time of the first node N1. Accordingly, the frame refresh frequency MHz of the display panel can be reduced, thereby facilitating the display panel to achieve low-frequency driving display.

[0063] An embodiment of the present invention further provides a display device, Figure 9 The figure shows a schematic diagram of a display device provided by an embodiment of the present invention, wherein the display device 2 may include any one of the display panels 1 provided by the above embodiments. Moreover, since the display device is made of the above display panel, it has the same or corresponding technical effects as the above display panel. It should be noted that the display device also includes other devices for supporting the normal operation of the display device. Specifically, the display device can be a mobile phone, tablet, computer, television, wearable smart device, etc., and the embodiment of the present invention does not limit it.

[0064] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will appreciate that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations, and substitutions are possible for those skilled in the art without departing from the scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a reset module; The driving module includes a driving transistor; The reset module is used to provide a reset signal for the gate of the driving transistor, the reset module includes a first dual-gate transistor, the first dual-gate transistor includes a first sub-transistor and a second sub-transistor, and the connection node between the first sub-transistor and the second sub-transistor is a second node; The pixel circuit is connected to the first power supply voltage signal terminal and is used to receive the first power supply voltage signal, and the first power supply voltage signal is a high level signal; wherein, The pixel circuit includes a first capacitor, a first plate of the first capacitor is connected to the first power supply voltage signal terminal, and a second plate of the first capacitor is connected to the second node; The gate of the first dual-gate transistor is connected to the first scanning signal line for receiving a first scanning signal; The pixel circuit includes a second capacitor, a first plate of the second capacitor is connected to the first scanning signal line, and a second plate is connected to the second node; wherein, The first capacitor C1 and the second capacitor C2 satisfy: C1>C2.

2. The display panel according to claim 1, wherein: The reset module is connected between the reset signal terminal and the gate of the driving transistor. One end of the first dual-gate transistor is connected to the reset signal terminal, and the other end is connected to the gate of the driving transistor.

3. The display panel according to claim 1, wherein: One end of the first sub-transistor is connected to the reset signal terminal, and the other end is connected to the second node; The operation process of the pixel circuit includes a first stage. In the first stage, the first sub-transistor remains in an on state, and the second sub-transistor remains in an off state.

4. The display panel according to claim 3, wherein: The pixel circuit further includes an initialization module, which is connected between the initialization signal terminal and the light-emitting element and is used to provide an initialization signal to the light-emitting element; wherein, The gate of the first sub-transistor is connected to a reset signal line to receive the reset signal; or, The gate of the first sub-transistor is connected to the initialization signal line to receive the initialization signal.

5. The display panel according to claim 1, wherein: The pixel circuit includes a compensation module connected between the gate of the driving transistor and the drain of the driving transistor; The compensation module includes a second dual-gate transistor, the second dual-gate transistor includes a third sub-transistor and a fourth sub-transistor, and a connection node between the third sub-transistor and the fourth sub-transistor is a third node.

6. The display panel according to claim 5, wherein: The gate of the second dual-gate transistor is connected to the second scan signal line for receiving a second scan signal; The pixel circuit includes a third capacitor, a first plate of the third capacitor is connected to the second scanning signal line, and a second plate is connected to the third node; wherein, The second capacitor C2 and the third capacitor C3 satisfy: C2≤C3.

7. The display panel according to claim 5, wherein: One end of the fourth sub-transistor is connected to the third node, and the other end is connected to the drain of the driving transistor; The operation process of the pixel circuit includes a first stage. In the first stage, the fourth sub-transistor remains in an on state, and the third sub-transistor remains in an off state.

8. The display panel according to claim 7, wherein: The pixel circuit further includes an initialization module, which is connected between the initialization signal terminal and the light-emitting element and is used to provide an initialization signal to the light-emitting element; wherein, The gate of the fourth sub-transistor is connected to the reset signal line to receive the reset signal; or, The gate of the fourth sub-transistor is connected to the initialization signal line to receive the initialization signal.

9. A display panel, characterized in that: include: Pixel circuits and light-emitting elements; The pixel circuit includes a driving module and a compensation module; The driving module includes a driving transistor; The compensation module is connected between the gate of the driving transistor and the drain of the driving transistor, the compensation module includes a second dual-gate transistor, the second dual-gate transistor includes a third sub-transistor and a fourth sub-transistor, and the connection node between the third sub-transistor and the fourth sub-transistor is a third node; The pixel circuit is connected to the first power supply voltage signal terminal and is used to receive the first power supply voltage signal, and the first power supply voltage signal is a high level signal; wherein, The pixel circuit includes a first capacitor, a first plate of the first capacitor is connected to the first power supply voltage signal terminal, and a second plate of the first capacitor is connected to the third node; The gate of the second dual-gate transistor is connected to the second scan signal line for receiving a second scan signal; The pixel circuit includes a third capacitor, a first plate of the third capacitor is connected to the second scanning signal line, and a second plate is connected to the third node; wherein, The first capacitor C1 and the third capacitor C3 satisfy: C1>C3.

10. The display panel according to claim 9, wherein: One end of the fourth sub-transistor is connected to the third node, and the other end is connected to the drain of the driving transistor; The operation process of the pixel circuit includes a first stage. In the first stage, the fourth sub-transistor remains in an on state, and the third sub-transistor remains in an off state.

11. The display panel according to claim 10, wherein: The pixel circuit further includes an initialization module, which is connected between the initialization signal terminal and the light-emitting element and is used to provide an initialization signal to the light-emitting element; wherein, The gate of the fourth sub-transistor is connected to the reset signal line to receive the reset signal; or, The gate of the fourth sub-transistor is connected to the initialization signal line to receive the initialization signal.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

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