A semiconductor structure and a method of fabricating the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate; a first dielectric layer on the substrate, the first dielectric layer comprising a first sidewall and a second sidewall oppositely arranged and extending upwards in a direction protruding from a plane of the substrate, and a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall; a first channel layer, the first channel layer comprising at least a first sub-portion covering the first surface and a second sub-portion covering the first sidewall; a second channel layer, the second channel layer comprising at least a third sub-portion covering the second surface and a fourth sub-portion covering the second sidewall; and a gate layer, the gate layer covering part of the first channel layer and part of the second channel layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is an important semiconductor device used for data storage or program storage during electronic device operation for data processing. However, as DRAM continues to evolve towards miniaturization and high integration, many factors still exist in the fabrication process that can degrade the performance of semiconductor devices. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, the semiconductor structure comprising:

[0004] Substrate;

[0005] A first dielectric layer located on the substrate, the first dielectric layer including a first sidewall and a second sidewall disposed opposite to each other and extending upward in a direction protruding from the plane of the substrate, and a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall;

[0006] The first channel layer includes at least a first sub-part covering the first surface and a second sub-part covering the first sidewall;

[0007] The second channel layer includes at least a third sub-section covering the second surface and a fourth sub-section covering the second sidewall;

[0008] A gate layer that covers a portion of the first channel layer and a portion of the second channel layer.

[0009] In some embodiments, the first channel layer further includes a fifth sub-section adjacent to the first sidewall and covering the substrate surface; the second channel layer further includes a sixth sub-section adjacent to the second sidewall and covering the substrate surface.

[0010] In some embodiments, a first included angle α1 exists between the first sub-section and the second sub-section of the first channel layer, 0° < α1 < 180°; a second included angle α2 exists between the second sub-section and the fifth sub-section, 0° < α2 < 180°; a third included angle α3 exists between the third sub-section and the fourth sub-section of the second channel layer, 0° < α3 < 180°; and a fourth included angle α4 exists between the fourth sub-section and the sixth sub-section, 0° < α4 < 180°.

[0011] In some embodiments, the first included angle α1 is the same as the third included angle α3, and the second included angle α2 is the same as the fourth included angle α4; or...

[0012] The first included angle α1, the second included angle α2, the third included angle α3 and the fourth included angle α4 are all 90°.

[0013] In some embodiments, the semiconductor structure further includes:

[0014] A first electrode located on one side of the first channel layer and on the substrate, and a second electrode located on the first dielectric layer;

[0015] A third electrode located on one side of the second channel layer and on the substrate, and a fourth electrode located on the first dielectric layer.

[0016] In some embodiments, the gate layer includes a first gate layer and a second gate layer, wherein the first gate layer covers the first channel layer between the first electrode and the second electrode; and the second gate layer covers the second channel layer between the third electrode and the fourth electrode.

[0017] In some embodiments, the semiconductor structure further includes:

[0018] Spacer layers, wherein the spacer layers are located between the first electrode and the first gate layer, between the second electrode and the first gate layer, between the first channel layer and the second channel layer, between the second gate layer and the fourth electrode, and between the third electrode and the second gate layer; and / or,

[0019] A protective layer that at least covers the surfaces of the gate layer, the first channel layer, the second channel layer, the second electrode, and the fourth electrode.

[0020] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising:

[0021] A substrate is provided, on which a first dielectric layer is formed, the first dielectric layer including a first sidewall and a second sidewall disposed opposite to each other and extending upward in a direction protruding from the plane of the substrate, and a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall;

[0022] A channel material layer is formed covering the substrate, the first sidewall, the second sidewall and the surface of the first dielectric layer, and a conductive material layer is formed covering the surface of the channel material layer;

[0023] An etching process is performed on the conductive material layer and the channel material layer, and the remaining conductive material layer constitutes the gate layer; the remaining channel material layer constitutes the first channel layer and the second channel layer respectively; wherein, the first channel layer includes at least a first sub-part covering the first surface and a second sub-part covering the first sidewall, and the second channel layer includes at least a third sub-part covering the second surface and a fourth sub-part covering the second sidewall.

[0024] In some embodiments, an etching process is performed on the channel material layer and the conductive material layer, including:

[0025] Remove a portion of the conductive material layer located above the first sidewall and above the second sidewall to form the gate layer;

[0026] The portion of the channel material layer located between the first surface and the second surface is removed to form a first channel layer and a second channel layer in the same process step; wherein the first channel layer includes a first sub-part covering the first surface, a second sub-part covering the first sidewall, and a fifth sub-part adjacent to the first sidewall and covering the substrate surface, and the second channel layer includes a third sub-part covering the second surface, a fourth sub-part covering the second sidewall, and a sixth sub-part adjacent to the second sidewall and covering the substrate surface.

[0027] In some embodiments, a first included angle α1 exists between the first sub-section and the second sub-section of the first channel layer, 0° < α1 < 180°; a second included angle α2 exists between the second sub-section and the fifth sub-section, 0° < α2 < 180°; a third included angle α3 exists between the third sub-section and the fourth sub-section of the second channel layer, 0° < α3 < 180°; and a fourth included angle α4 exists between the fourth sub-section and the sixth sub-section, 0° < α4 < 180°.

[0028] The semiconductor structure and its fabrication method provided in this disclosure include: a substrate; a first dielectric layer on the substrate, the first dielectric layer including a first sidewall and a second sidewall disposed opposite to each other and extending upward in a direction protruding from the plane of the substrate, and a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall; a first channel layer, the first channel layer including at least a first sub-portion covering the first surface and a second sub-portion covering the first sidewall; a second channel layer, the second channel layer including at least a third sub-portion covering the second surface and a fourth sub-portion covering the second sidewall; and a gate layer, the gate layer covering a portion of the first channel layer and a portion of the second channel layer. Thus, in this disclosure, a first channel layer and a second channel layer are respectively disposed on both sides of the first dielectric layer, and the first channel layer covers one sidewall and a portion of the surface of the first dielectric layer, and the second channel layer covers the other sidewall and a portion of the surface of the first dielectric layer. This allows the lengths of the two channel layers to change with the height of the first dielectric layer, facilitating flexible adjustment of the lengths of the two channel layers. It is understood that two transistors can be obtained by setting other structures based on two channel layers. Since the extension direction of the two channel layers in the semiconductor structure provided in this disclosure embodiment can include a portion extending upward in a direction protruding from the substrate plane, at least a portion of the channel layer can have a certain angle with the plane of the substrate, thereby effectively reducing the area occupied by the segment on the substrate plane (compared to planar transistors). This allows the semiconductor structure provided in this disclosure embodiment to have a higher transistor density, thereby significantly reducing the area of ​​the array region.

[0029] Details of one or more embodiments of this disclosure are set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification and drawings. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;

[0032] Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0033] Figure 3This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure;

[0034] Figure 4 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0035] Figures 5 to 14 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment;

[0036] Figure 15 This is a schematic diagram of the structure of the gate dielectric layer during its formation process, as provided in another embodiment of this disclosure. Detailed Implementation

[0037] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0038] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0039] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0043] Transistor structures are crucial components of semiconductor devices, typically comprising a channel layer, a gate dielectric layer, a gate structure, and source / drain regions located on either side of the gate structure. In practice, this is achieved by forming a stack of multiple material layers on a substrate. Subsequently, the gate structure and gate dielectric layer are obtained by etching these stacked material layers. Then, further process steps can be performed to obtain the source / drain regions and other structures.

[0044] However, in the process of fabricating transistor structures, there is still a problem that makes it difficult to increase transistor density.

[0045] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0046] This disclosure provides a semiconductor structure, which includes:

[0047] Substrate;

[0048] A first dielectric layer located on a substrate includes a first sidewall and a second sidewall disposed opposite to each other and extending upward in a direction protruding from the plane of the substrate, and a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall;

[0049] The first channel layer includes at least a first sub-section covering the first surface and a second sub-section covering the first sidewall;

[0050] The second channel layer includes at least a third sub-section covering the second surface and a fourth sub-section covering the second sidewall;

[0051] A gate layer that covers a portion of the first channel layer and a portion of the second channel layer.

[0052] Thus, in this embodiment, a first channel layer and a second channel layer are respectively disposed on both sides of the first dielectric layer. The first channel layer covers one sidewall and part of the surface of the first dielectric layer, and the second channel layer covers the other sidewall and part of the surface of the first dielectric layer. This allows the lengths of the two channel layers to change with the height of the first dielectric layer, which is beneficial for flexible adjustment of the lengths of the two channel layers. It is understood that two transistors can be obtained by setting other structures based on the two channel layers. Since the extension direction of the two channel layers in the semiconductor structure provided in this embodiment can include a portion extending upward along the direction protruding from the substrate plane, at least a portion of any channel layer can have a certain angle with the plane of the substrate. This can effectively reduce the area occupied by the segment on the substrate plane (compared to planar transistors), allowing the semiconductor structure provided in this embodiment to have a higher transistor density, thereby significantly reducing the area of ​​the array region.

[0053] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0054] Figure 1 This is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; Figure 2 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure; Figure 3 This is a schematic diagram of another semiconductor structure provided in an embodiment of the present disclosure.

[0055] like Figure 1 , Figure 2 and Figure 3 As shown, the semiconductor structure includes:

[0056] Substrate 10;

[0057] A first dielectric layer 11 is located on the substrate 10. The first dielectric layer 11 includes a first sidewall S1 and a second sidewall S2 that are disposed opposite to each other and extend upward in a direction protruding from the plane of the substrate 10, as well as a first surface S3 adjacent to the first sidewall S1 and a second surface S4 adjacent to the second sidewall S1.

[0058] The first channel layer 13 includes at least a first sub-part P1 covering the first surface S3 and a second sub-part P2 covering the first sidewall S1.

[0059] The second channel layer 14 includes at least a third sub-part P3 covering the second surface S4 and a fourth sub-part P4 covering the second sidewall S2.

[0060] Gate layer G covers a portion of the first channel layer 13 and a portion of the second channel layer 14.

[0061] Understandably, a first transistor structure can be obtained by adding other structures (such as a first electrode D1 and a second electrode D2) based on the first channel layer 13 and the gate layer G. Similarly, a second transistor structure can be obtained by adding other structures (such as a third electrode D3 and a fourth electrode D4) based on the second channel layer 14 and the gate layer G.

[0062] Here, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 10 is a silicon substrate.

[0063] In some embodiments, the material of the first dielectric layer 11 includes, but is not limited to, at least one or a combination of oxides, nitrides, oxynitrides, etc. In some specific embodiments, the material of the first dielectric layer 11 may be silicon nitride. It is understood that the first dielectric layer 11 can provide an isolation effect between the first transistor structure and the second transistor structure.

[0064] Here, the first plane S3 and the second plane S4 can both be composed of a portion of the upper surface of the first dielectric layer 11, and the first plane S3 and the second plane S4 are in a state of separation.

[0065] In some embodiments, the aspect ratio of the first dielectric layer 11 is between 1:10 and 10:1 (including endpoint values).

[0066] In some embodiments, the materials of the first channel layer 13 and the second channel layer 14 may be oxide semiconductor materials, including but not limited to at least one of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0067] In some specific embodiments, the materials of the first channel layer 13 and the second channel layer 14 include, but are not limited to, indium gallium zinc oxide (IGZO), such as materials with the chemical formula InGaZnO4. The thickness of the first channel layer 13 and the second channel layer 14 can be between 1 nm and 20 nm, such as 5 nm, 10 nm, 15 nm, 18 nm, etc.

[0068] In some embodiments, the ratio of indium (In), gallium (Ga), and zinc (Zn) can be 1:1:1 or 2:2:1, etc. However, it is not limited to this, and the ratio of indium (In), gallium (Ga), and zinc (Zn) can also be other suitable ratios.

[0069] Optionally, the oxide semiconductor material can be an undoped oxide semiconductor material or a doped oxide semiconductor material. Specifically, the dopant used to dope the oxide semiconductor material is one or more of boron, nitrogen, phosphorus and arsenic, or one or more of helium, neon, argon, krypton and xenon, or hydrogen; but it is not limited to these, and the dopant can also be a combination of the above materials as needed.

[0070] Oxide semiconductor materials can be formed by sputtering, coating, printing, evaporation, PCVD, PLD, ALD, or MBE methods.

[0071] Understandably, when the oxide semiconductor material is indium gallium zinc oxide (IGZO), the semiconductor device has the advantages of fast access speed, low cutoff current, and low power consumption.

[0072] In this embodiment of the present disclosure, the first dielectric layer 11 not only provides an isolation effect between the first channel layer 13 and the second channel layer 14, but also allows for adjustment of the length of the two channel layers.

[0073] Understandably, since the first dielectric layer 11 can be obtained by regrowing a new material layer on the substrate 10 and then performing a patterning process, the dimensions of the first dielectric layer 11 in each direction, such as height, length, width, and the angle between its first sidewall S1 and second sidewall S2 and the substrate 10, can be controlled as needed.

[0074] Optionally, in some embodiments, the angle between the first sidewall S1 and the substrate 10 can be between 0° and 180°, and the angle between the second sidewall S2 and the substrate 10 can also be between 0° and 180°, such that when the length of the first sidewall S1 and the second sidewall S2 of the first dielectric layer 11 is L1, its orthographic projection size on the substrate 10 can be greater than or equal to 0 and less than L1. Furthermore, when the angle between the first sidewall S1 and the substrate 10, or the angle between the second sidewall S2 and the substrate 10, is close to or equal to 90°, the orthographic projection size of the first sidewall S1 and the second sidewall S2 on the substrate will not substantially occupy the substrate's planar dimensions. It is understood that when other structures are further conformally disposed on the sidewalls of the first dielectric layer 11, the occupancy of these structures on the substrate 10's planar dimensions will also fall within the aforementioned numerical range.

[0075] It is understood that, in the embodiments of this disclosure, in the first dielectric layer 11, in addition to the adjustable angle between the first sidewall S1 and the second sidewall S2 and the substrate, the angle and range between the first sidewall S1 and the first surface S3 can also be set with reference to the angle range between the first sidewall S1 and / or the second sidewall S2 and the substrate. Optionally, in some embodiments, the angle range of the former can also be between 0° and 180°; the angle range between the second sidewall S2 and the second surface S4 can also be between 0° and 180°.

[0076] Similarly, when the length of the first surface S3 and the second surface S4 of the first dielectric layer 11 is L2, its orthographic projection size on the substrate 10 can be between 0 and L2. When the angle between the two sidewalls and the substrate 10 is small, and the angle between the first sidewall S1 and the first surface S3 or the angle between the second sidewall S2 and the second surface S4 is close to or equal to 90°, the orthographic projection size of the first surface S3 and the second surface S4 on the substrate 10 will not significantly occupy the planar size of the substrate 10. It is understandable that when other structures are subsequently disposed on the first surface S3 or the second surface S4 of the first dielectric layer 11, the occupancy of these structures on the planar size of the substrate 10 will also fall within the aforementioned range.

[0077] In some embodiments, the first channel layer 13 further includes a fifth sub-section P5 adjacent to the first sidewall S1 and covering the surface of the substrate 10; the second channel layer 14 further includes a sixth sub-section P6 adjacent to the second sidewall S2 and covering the surface of the substrate 10.

[0078] Since the included angles between the first sidewall S1, the second sidewall S2, the first surface S3, the second surface S4, and the substrate in the first dielectric layer can be various as described above, the included angles between the portions of the channel layer covering the first dielectric layer 11 can also be similar. It is understood that in some embodiments, there is a first included angle α1 between the first sub-part P1 and the second sub-part P2 of the first channel layer 13, 0° < α1 < 180°; there is a second included angle α2 between the second sub-part P2 and the fifth sub-part P5, 0° < α2 < 180°; there is a third included angle α3 between the third sub-part P3 and the fourth sub-part P4 of the second channel layer 14, 0° < α3 < 180°; and there is a fourth included angle α4 between the fourth sub-part P4 and the sixth sub-part P6, 0° < α4 < 180°.

[0079] In some embodiments, the first included angle α1 is the same as the third included angle α3, and the second included angle α2 is the same as the fourth included angle α4; or...

[0080] The first included angle α1, the second included angle α2, the third included angle α3, and the fourth included angle α4 are all 90°.

[0081] Continue to refer to Figures 1 to 3 As can be seen, the second sub-section P2 and the first sub-section P1 in the first channel layer 13 respectively cover one sidewall (first sidewall S1) and part of the upper surface (first surface S3) of the first dielectric layer 11, and the fourth sub-section P4 and the third sub-section P3 in the second channel layer 14 respectively cover the other sidewall (second sidewall S2) and part of the upper surface (second surface S4) of the first dielectric layer 11. The portions of the two channel layers located on the sidewall and part of the upper surface of the first dielectric layer 11 greatly reduce the occupancy of the two channel layers on the planar dimensions of the substrate 10 (compared to planar transistors), enabling the semiconductor structure provided in this embodiment to have a higher transistor density, thereby significantly reducing the area of ​​the array region.

[0082] In some embodiments, when the first included angle α1, the second included angle α2, the third included angle α3, and the fourth included angle α4 are all 90°, compared with planar transistors, the density of the transistor structure in the semiconductor structure provided by the present disclosure embodiments can be doubled, and the area of ​​the array region can be reduced by 50%.

[0083] In any of the above embodiments, the semiconductor structure further includes:

[0084] A first electrode D1 located on one side of the first channel layer 13 and on the substrate 10, and a second electrode D2 located on the first dielectric layer 11;

[0085] The third electrode D3 is located on the side of the second channel layer 14 and on the substrate 10, and the fourth electrode D4 is located on the first dielectric layer 11.

[0086] Continue to refer to Figure 1 and Figure 2 It can be seen that the arrangement of the fifth sub-part P5 in the first channel layer 13 and the sixth sub-part P6 in the second channel layer 14 are conducive to realizing the connection between the first channel layer 13 and the first electrode D1, and to realizing the connection between the second channel layer 14 and the third electrode D3.

[0087] In some embodiments, a second dielectric layer 12 is further disposed between the substrate 10 and the first dielectric layer 11, and the first electrode D1 and the third electrode D3 may be disposed in the second dielectric layer 12.

[0088] In practice, the material of the second dielectric layer 12 includes, but is not limited to, oxides, such as silicon oxide. It is understood that the arrangement of the second dielectric layer 12 can provide electrical isolation between the first electrode D1 and the third electrode D3.

[0089] Understandably, in embodiments where the first electrode D1 and the third electrode D3 are disposed in the second dielectric layer 12, the first electrode D1 and the third electrode D3, while serving to make electrical connections between the two channel layers, do not sacrifice the coverage area of ​​the gate layer G on the second sub-part P2 and the fourth sub-part P4. Therefore, the channel length and the gate length are not shortened. In this case, the first dielectric layer 11 does not need to be deliberately increased in height to take into account the placement of the first electrode D1 and the third electrode D3, which is beneficial to ensuring the stability and reliability of the semiconductor structure.

[0090] It should be noted that, although in Figure 1 and Figure 2 The diagram shows the first electrode D1 located on the side of the first channel layer 13 adjacent to the substrate. However, this is not the only embodiment. In some other embodiments, the first electrode D1 may also be located on the side of the first channel layer 13 adjacent to the gate layer G. In this case, simply increasing the thickness of the first dielectric layer 11 is sufficient to obtain an example where the first electrode D1 is located on the side of the first channel layer 12 adjacent to the gate layer G without reducing the channel length. Similarly, the third electrode D3 may also be located on the side of the second channel layer 14 adjacent to the gate layer G.

[0091] However, this is not the only one; in some embodiments, such as Figure 3 As shown, the first channel layer 13 may not include the fifth sub-section P5, and the second channel layer 14 may not include the sixth sub-section P6. Furthermore, the first dielectric layer 11 can have a larger height and a smaller width. Compared to other embodiments, this embodiment allows for the placement of a greater number of transistor structures on a substrate 10 with the same planar dimensions (i.e., increased transistor density), which helps to further improve the integration of the semiconductor structure and further reduce the area of ​​the array region.

[0092] comprehensive Figures 1 to 3 As can be seen from the semiconductor structure provided in this embodiment, a first channel layer 13 and a second channel layer 14 are respectively provided on both sides of the first dielectric layer 11. The size and angle of the first dielectric layer 11 in each direction can be adjusted according to actual needs, so as to meet the length adjustment requirements of the first channel layer 13 and the second channel layer 14. Thus, a transistor structure that meets the design or usage requirements can be obtained, which has high flexibility and high integration.

[0093] In some embodiments, by adjusting the size of the first dielectric layer 11 provided in this disclosure, the length of the obtained first channel layer 13 can range from 1 nm to 1000 nm (inclusive), for example, from 1 nm to 10 nm (inclusive), from 10 nm to 100 nm (inclusive), from 100 nm to 500 nm (inclusive), or from 500 nm to 1000 nm. Similarly, the length of the obtained second channel layer 14 can also range from 1 nm to 1000 nm (inclusive), for example, from 1 nm to 10 nm (inclusive), from 10 nm to 100 nm (inclusive), from 100 nm to 500 nm (inclusive), or from 500 nm to 1000 nm.

[0094] In some embodiments, the shapes of the first channel layer 13 and the second channel layer 14 located on both sides of the same first dielectric layer 11 may be the same or different. In some specific embodiments, the shapes of the first channel layer 13 and the second channel layer 14 may be any combination of the channel layer shapes provided in any of the above embodiments.

[0095] Continue to refer to Figure 1 , Figure 2 and Figure 3 As shown, in some embodiments, the gate layer G includes a first gate layer G1 and a second gate layer G2. The first gate layer G1 covers the first channel layer 13 between the first electrode D1 and the second electrode D2; the second gate layer G2 covers the second channel layer 13 between the third electrode D3 and the fourth electrode D4.

[0096] In some embodiments, the semiconductor structure further includes:

[0097] Spacer layer 15 is located between the first electrode D1 and the first gate layer G1, between the second electrode D2 and the first gate layer G1, between the first channel layer 13 and the second channel layer 14, between the second gate layer G2 and the fourth electrode D4, and between the third electrode D3 and the second gate layer G2.

[0098] Understandably, the first gate layer G1, the first channel layer 13, the first electrode D1, and the second electrode D2 can constitute the first transistor structure. Similarly, the second gate layer G2, the second channel layer 14, the third electrode D3, and the fourth electrode D4 can constitute the second transistor structure.

[0099] In some embodiments, the semiconductor structure further includes a protective layer 16, which at least covers the surfaces of the gate layer G, the first channel layer 13, the second channel layer 14, the second electrode D2, and the fourth electrode D4.

[0100] Here, the material of the protective layer 16 may include, but is not limited to, insulating materials, such as oxides, nitrides, and oxynitrides. Optionally, in some embodiments, the material of the protective layer 16 may be silicon nitride. The presence of the protective layer helps prevent substances such as hydrogen or water contained in the environment from entering the channel layer during subsequent use or storage of the semiconductor structure, thereby contributing to a more stable threshold voltage for the first transistor structure and the second transistor structure.

[0101] Optionally, in some embodiments, the materials of the first electrode D1, the second electrode D2, the third electrode D3, and the fourth electrode D4 include, but are not limited to, at least one or a combination of aluminum, copper, molybdenum, gold, tungsten, and materials commonly used in IGZO transistors.

[0102] In some embodiments, the semiconductor structure may further include a gate dielectric layer 17 located between the first gate layer G1 and the first channel layer 13 and between the second gate layer G2 and the second channel layer 14.

[0103] Optionally, in some embodiments, the material of the gate dielectric layer 17 includes, but is not limited to, oxides, oxynitrides, or high-k dielectric materials, such as silicon oxide (SiO2), hafnium oxide (HfO2), silicon nitride (Si3N4), and silicon oxynitride (SiO2). x N y One of the following, combinations thereof, or other suitable dielectric materials: tantalum oxide (Ta2O5), titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), cerium oxide (CeO2).

[0104] In some embodiments, the thickness of the gate dielectric layer 17 can be flexibly adjusted as needed to obtain transistor structures with different electrical properties. It is understood that in some embodiments, the thickness of the gate dielectric layer 17 near the first sidewall S1 may have the same or different values ​​as the thickness of the gate dielectric layer 17 near the second sidewall S2. In practice, this can be flexibly adjusted as needed, and no specific limitations are imposed here.

[0105] This disclosure also provides a memory, which may include the semiconductor structure provided in any of the above embodiments. It is understood that because the semiconductor structure provided in this disclosure can have high integration density, small array area, and stable electrical performance, the memory containing this semiconductor structure also achieves a higher integration density (corresponding to a smaller volume) and better stability and reliability.

[0106] This disclosure provides a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the method includes the following steps:

[0107] Step S101: Provide a substrate and form a first dielectric layer on the substrate. The first dielectric layer includes a first sidewall and a second sidewall that are disposed opposite to each other and extend upward in a direction protruding from the plane of the substrate, as well as a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall.

[0108] Step S102: Form a channel material layer covering the substrate, the first sidewall, the second sidewall and the surface of the first dielectric layer, and form a conductive material layer covering the surface of the channel material layer;

[0109] Step S103: Perform an etching process on the conductive material layer and the channel material layer. The remaining conductive material layer constitutes the gate layer. The remaining channel material layers constitute the first channel layer and the second channel layer, respectively. The first channel layer includes at least a first sub-part covering the first surface and a second sub-part covering the first sidewall. The second channel layer includes at least a third sub-part covering the second surface and a fourth sub-part covering the second sidewall.

[0110] It should be understood that, although Figure 4 The steps are shown sequentially as indicated by the arrows, but they are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order in which these steps are performed; they can be executed in other orders. Figure 4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0111] Figures 5 to 14 A process flow diagram of the method for fabricating a semiconductor structure provided in this disclosure embodiment; Figure 15 This is a schematic diagram of the structure of the gate dielectric layer during its formation process, as provided in another embodiment of this disclosure.

[0112] The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings.

[0113] First, execute step S101, as follows: Figures 5 to 7 As shown, a substrate 10 is provided, and a first dielectric layer 11 is formed on the substrate 10. The first dielectric layer 11 includes a first sidewall S1 and a second sidewall S2 that are disposed opposite to each other and extend upward in a direction protruding from the plane of the substrate 10, as well as a first surface S3 adjacent to the first sidewall S1 and a second surface S4 adjacent to the second sidewall S2.

[0114] Here, substrate 10 can be a semiconductor substrate; the material of the semiconductor substrate specifically includes elemental semiconductor materials (e.g., silicon (Si) substrates, germanium (Ge) substrates, etc.), or III-V compound semiconductor materials (e.g., gallium nitride (GaN) substrates, gallium arsenide (GaAs) substrates, indium phosphide (InP) substrates, etc.), or II-VI compound semiconductor materials, or organic semiconductor materials, or other semiconductor materials known in the art. In a specific embodiment, substrate 10 is a silicon substrate.

[0115] In some embodiments, the material of the first dielectric layer 11 includes, but is not limited to, at least one or a combination of oxides, nitrides, oxynitrides, etc. In some specific embodiments, the material of the first dielectric layer 11 may be silicon nitride. It is understood that the first dielectric layer 11 can provide isolation between different transistor structures subsequently obtained.

[0116] The first dielectric layer 11 can be formed using one or more thin film deposition processes; specifically, the thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof.

[0117] Here, the first surface S3 and the second surface S4 can both be composed of a portion of the upper surface of the first dielectric layer 11, and the first plane S3 and the second plane S4 are separated.

[0118] In some embodiments, the aspect ratio of the first dielectric layer 11 is between 1:10 and 10:1 (including endpoint values).

[0119] Understandably, since the first dielectric layer 11 can be obtained by regrowing a new material layer on the substrate 10 and then performing a patterning process, the dimensions of the first dielectric layer 11 in each direction, such as height, length, width, and the angle between its first sidewall S1 and second sidewall S2 and the substrate 10, can be controlled as needed.

[0120] Optionally, in some embodiments, the angle between the first sidewall S1 and the substrate 10 can be between 0° and 180°, and the angle between the second sidewall S2 and the substrate 10 can also be between 0° and 180°, such that when the length of the first sidewall S1 and the second sidewall S2 of the first dielectric layer 11 is L1, its orthographic projection size on the substrate 10 can be greater than or equal to 0 and less than L1. Furthermore, when the angle between the first sidewall S1 and the substrate 10 or the angle between the second sidewall S2 and the substrate 10 is close to or equal to 90°, the orthographic projection size of the first sidewall S1 and the second sidewall S2 on the substrate will not substantially occupy the substrate's planar dimensions. It is understood that when other structures (such as the first trench layer 13 and the second trench layer 14 in subsequent step S103) are subsequently disposed on the sidewalls of the first dielectric layer 11, the occupancy of these structures on the substrate 10's planar dimensions will also fall within the aforementioned numerical range.

[0121] It is understood that, in the embodiments of this disclosure, in the first dielectric layer 11, in addition to the adjustable angle between the first sidewall S1 and the second sidewall S2 and the substrate 10, the angle and range between the first sidewall S1 and the first surface S3 can also be set with reference to the angle range between the first sidewall S1 and / or the second sidewall S2 and the substrate 10. Optionally, in some embodiments, the angle range of the former can also be between 0° and 180°; the angle range between the second sidewall S2 and the second surface S4 can also be between 0° and 180°.

[0122] Similarly, when the length of the first surface S3 and the second surface S4 of the first dielectric layer 11 is L2, its orthographic projection size on the substrate 10 can be between 0 and L2. When the angle between the two sidewalls and the substrate 10 is small, and the angle between the first sidewall S1 and the first surface S3 or the angle between the second sidewall S2 and the second surface S4 is close to or equal to 90°, the orthographic projection size of the first surface S3 and the second surface S4 on the substrate 10 will not significantly occupy the planar size of the substrate 10. It is understandable that when other structures (such as the first trench layer 13 and the second trench layer 14 in subsequent step S103) are formed on the first surface S3 or the second surface S4 of the first dielectric layer 11, the occupancy of the planar size of the substrate 10 by such structures will also fall within the above-mentioned numerical range.

[0123] Understandably, in some embodiments, the inclination of the first sidewall S1 and the second sidewall S2 located on both sides of the same first dielectric layer 11 relative to the surface of the substrate 10 may be the same or different. Similarly, the angle between the first surface S3 and the first sidewall S1 located on the upper surface of the first dielectric layer 11 and the angle between the second surface S4 and the second sidewall S2 may be the same or different, and can be flexibly selected according to the actual situation, without specific limitations here.

[0124] In some specific embodiments, the first sidewall S1, the second sidewall S2, the first surface S3, and the second surface S4 can be any combination of the included angle values ​​provided in any of the above embodiments.

[0125] In some embodiments, before forming the first dielectric layer 11, the preparation method may further include: forming a second dielectric layer 12 and a first electrode D1 and a third electrode D3 located on the second dielectric layer.

[0126] Next, proceed with step S102, as follows: Figures 8 to 11 As shown, a channel material layer 13a is formed covering the substrate 10, the first sidewall S1, the second sidewall S2 and the surface of the first dielectric layer 11, and a conductive material layer Ga is formed covering the surface of the channel material layer 13a.

[0127] Here, the material of the channel material layer 13a includes, but is not limited to, indium gallium zinc oxide (IGZO), such as a material with the chemical formula InGaZnO4. In some embodiments, the ratio of indium (In), gallium (Ga), and zinc (Zn) can be 1:1:1 or 2:2:1, etc.

[0128] Optionally, the oxide semiconductor material can be an undoped oxide semiconductor material or a doped oxide semiconductor material. Specifically, the dopant used to dope the oxide semiconductor material is one or more of boron, nitrogen, phosphorus and arsenic, or one or more of helium, neon, argon, krypton and xenon, or hydrogen; but it is not limited to these, and the dopant can also be a combination of the above materials as needed.

[0129] Oxide semiconductor materials can be formed by sputtering, coating, printing, evaporation, PCVD, PLD, ALD, or MBE methods.

[0130] Understandably, when the oxide semiconductor material is indium gallium zinc oxide (IGZO), the semiconductor device has the advantages of fast access speed, low cutoff current, and low power consumption.

[0131] In this step, the channel material layer 13a can be used to simultaneously form the first channel layer 13 and the second channel layer 14 after undergoing a series of subsequent operations (including but not limited to etching operations).

[0132] It is understandable that in some embodiments, such as Figure 9 As shown, after forming the channel material layer 13a, the preparation method may further include:

[0133] A gate dielectric layer 17 is formed, which covers portions of the channel material layer 13a located on the first sidewall S1 and the second sidewall S2 of the first dielectric layer 11.

[0134] However, this is not the only possibility; the relationship between the gate dielectric layer 17 and the channel material layer 13a can also be other, for example:

[0135] In other embodiments, such as Figure 15 As shown, after forming the channel material layer 13a, the preparation method may further include:

[0136] A gate dielectric layer 17 is formed. The gate dielectric layer 17 may include a first sub-layer 171 covering the channel material layer 13a located on the upper surface of a portion of the first dielectric layer 11, a second sub-layer 172 located on the sidewall of the first dielectric layer 11, and a third sub-layer 173 located on the substrate 10.

[0137] Compared to the previous embodiment, this embodiment, after performing the subsequent step S103, allows the obtained first channel layer 13 and second channel layer 14 to have a larger channel length. Therefore, while maintaining the required channel length, Figure 15 The illustrated embodiments can be used with Figure 9 The embodiment shown has a first dielectric layer 11 structure with a lower thickness, which is beneficial for obtaining a semiconductor structure with a smaller height to achieve better stability while meeting the performance requirements of the application.

[0138] Optionally, in some embodiments, the thickness of the gate dielectric layer 17 can be flexibly adjusted as needed to obtain transistor structures with different electrical properties. It is understood that in some embodiments, the thickness of the gate dielectric layer 17 near the first sidewall S1 can have the same or different values ​​as the thickness of the gate dielectric layer 17 near the second sidewall S2. In practice, this can be flexibly adjusted as needed, and no specific limitations are imposed here.

[0139] In some embodiments, such as Figure 10 As shown, after forming the gate dielectric layer 17, the fabrication method further includes:

[0140] A spacer layer 15 is formed above the first electrode D1 and the third electrode D3 and covers the portion of the channel material layer 13a covering the surface of the substrate 10. One end of the spacer layer 15 is in contact with the end of the gate dielectric layer 17 adjacent to the second dielectric layer 12, so as to produce an electrical isolation effect between the first electrode D1 and the subsequently formed conductive material layer Ga, and between the third electrode D3 and the subsequently formed conductive material layer Ga.

[0141] Finally, proceed with step S103, as follows: Figures 12 to 13 As shown, an etching process is performed on the conductive material layer Ga and the channel material layer 13a, and the remaining conductive material layer Ga constitutes the gate layer G; the remaining channel material layer 13a constitutes the first channel layer 13 and the second channel layer 14 respectively; wherein, the first channel layer 13 includes at least a first sub-part P1 covering the first surface S3 and a second sub-part P2 covering the first sidewall S1, and the second channel layer 14 includes at least a third sub-part P3 covering the second surface S4 and a fourth sub-part P4 covering the second sidewall S2.

[0142] In some embodiments, an etching process is performed on the channel material layer 13a and the conductive material layer Ga, including:

[0143] Remove a portion of the conductive material layer Ga located above the first sidewall S1 and the second sidewall S2 to form the gate layer G (see details). Figure 12 );

[0144] A portion of the channel material layer 13a located between the first surface S3 and the second surface S4 is removed to form the first channel layer 13 and the second channel layer 14 in the same process step. The first channel layer 13 includes a first sub-part P1 covering the first surface S3, a second sub-part P2 covering the first sidewall S1, and a fifth sub-part P5 adjacent to the first sidewall S1 and covering the surface of the substrate 10. The second channel layer 14 includes a third sub-part P3 covering the second surface S4, a fourth sub-part P4 covering the second sidewall S2, and a sixth sub-part P6 adjacent to the second sidewall S2 and covering the surface of the substrate 10 (see details). Figure 13 ).

[0145] Continue to refer to Figure 12 As can be seen, in some embodiments, forming the gate layer G includes:

[0146] Remove a portion of the conductive material layer Ga located above the first sidewall S1 and the second sidewall S2 to form the first opening H1;

[0147] A spacer layer 15 is formed in the first opening H1. The spacer layer 15 separates the conductive material layers Ga located on both sides of the first dielectric layer 11 into two electrically isolated parts to form a gate layer G. The part of the conductive material layer Ga located on the first sidewall S1 can be defined as the first gate G1, and the part of the conductive material layer Ga located on the second sidewall S2 can be defined as the second gate G2.

[0148] Continue to refer to Figure 13 As can be seen, in some embodiments, forming the first trench layer 13 and the second trench layer 14 includes:

[0149] A portion of the channel material layer 13a located between the first surface S3 and the second surface S4 is removed to form the second opening H2;

[0150] A spacer layer 15 is formed within the second opening H2 to achieve the formation of the first channel layer 13 and the second channel layer 14 in the same process step.

[0151] In this step, the conductive material layer Ga remaining above the first surface S3 can be used as the second electrode D2 of the first transistor, while the conductive material layer Ga remaining above the second surface S4 can be used as the fourth electrode D4 of the second transistor.

[0152] Understandably, the first channel layer 13, the first electrode D1, and part of the gate layer G can constitute a first transistor structure. Simultaneously, the second channel layer 14, the third electrode D3, part of the gate layer G, and the fourth electrode D4 can form a second transistor structure.

[0153] In the fabrication method provided in this disclosure, obtaining two channel layers (first channel layer 13 and second channel layer 14) can be achieved in the same process step, effectively reducing the number of etching processes and greatly improving the efficiency of the etching process, which is beneficial to improving production efficiency and reducing production costs. At the same time, the reduction in the number of etching steps is conducive to obtaining a good etching profile in the fabricated structure, thereby improving the yield and reliability of the final semiconductor structure.

[0154] In addition, in the preparation method provided in this embodiment, the channel layer is formed by covering the first dielectric layer 11 with a covering material, so that there is no need to perform the operation of filling the gap with a large aspect ratio during the operation, and therefore there is no phenomenon of semiconductor performance degradation due to poor material filling performance.

[0155] In some embodiments, a first included angle α1 exists between the first sub-part P1 and the second sub-part P2 of the first channel layer 13, where 0° < α1 < 180°; a second included angle α2 exists between the second sub-part P2 and the fifth sub-part P3, where 0° < α2 < 180°; a third included angle α3 exists between the third sub-part P3 and the fourth sub-part P4 of the second channel layer 14, where 0° < α3 < 180°; and a fourth included angle α4 exists between the fourth sub-part P4 and the sixth sub-part P6, where 0° < α4 < 180°.

[0156] In some embodiments, the first included angle α1 is the same as the third included angle α3, and the second included angle α2 is the same as the fourth included angle α4; or...

[0157] The first included angle α1, the second included angle α2, the third included angle α3, and the fourth included angle α4 are all 90°.

[0158] Continue to refer to Figure 13 As can be seen, the second sub-section P2 and the first sub-section P1 in the first channel layer 13 respectively cover one sidewall (first sidewall S1) and part of the upper surface (first surface S3) of the first dielectric layer 11, and the fourth sub-section P4 and the third sub-section P3 in the second channel layer 14 respectively cover the other sidewall (second sidewall S2) and part of the upper surface (second surface S4) of the first dielectric layer 11. The portions of the two channel layers located on the sidewall and part of the upper surface of the first dielectric layer 11 greatly reduce the occupancy of the two channel layers on the planar dimensions of the substrate 10 (compared to planar transistors), enabling the semiconductor structure provided in this embodiment to have a higher transistor density, thereby significantly reducing the area of ​​the array region.

[0159] In some embodiments, when the first included angle α1, the second included angle α2, the third included angle α3, and the fourth included angle α4 are all 90°, compared with planar transistors, the density of the transistor structure in the semiconductor structure provided by the present disclosure embodiments can be doubled, and the area of ​​the array region can be reduced by 50%.

[0160] In some embodiments, after forming the first channel layer 13 and the second channel layer 14, the fabrication method may further include forming a protective layer 16, wherein the material of the protective layer 16 may be silicon nitride. The presence of the protective layer helps prevent substances such as hydrogen or water contained in the environment from entering the channel layer during subsequent use or storage of the semiconductor structure, thereby helping the first transistor structure and the second transistor structure to have a more stable threshold voltage.

[0161] It is understood that the transistor structure included in the semiconductor structure provided in this disclosure can be applied to DRAM structures or any other semiconductor device requiring a transistor structure, especially those requiring a high-density transistor structure. In some possible embodiments, the semiconductor structure provided in this disclosure may also be applicable to TFTs DRAM containing IGZO material, DRAM structures with a 2TOC structure, etc. Specific selection can be made according to actual needs, and no specific limitations are made here.

[0162] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor structure fabrication method provided in this disclosure belong to the same concept as the embodiments of the semiconductor structure; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0163] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; A first dielectric layer located on the substrate, the first dielectric layer including a first sidewall and a second sidewall disposed opposite to each other and extending upward in a direction protruding from the plane of the substrate, and a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall; The first channel layer includes at least a first sub-part covering the first surface and a second sub-part covering the first sidewall; The second channel layer includes at least a third sub-section covering the second surface and a fourth sub-section covering the second sidewall; A gate layer that covers a portion of the first channel layer and a portion of the second channel layer; A first electrode located on one side of the first channel layer and on the substrate, and a second electrode located on the first dielectric layer; A third electrode located on one side of the second channel layer and on the substrate, and a fourth electrode located on the first dielectric layer.

2. The semiconductor structure according to claim 1, characterized in that, The first channel layer further includes a fifth sub-section adjacent to the first sidewall and covering the substrate surface; the second channel layer further includes a sixth sub-section adjacent to the second sidewall and covering the substrate surface.

3. The semiconductor structure according to claim 2, characterized in that, There is a first included angle α1 between the first sub-section and the second sub-section of the first channel layer, where 0° < α1 < 180°; there is a second included angle α2 between the second sub-section and the fifth sub-section, where 0° < α2 < 180°; there is a third included angle α3 between the third sub-section and the fourth sub-section of the second channel layer, where 0° < α3 < 180°; and there is a fourth included angle α4 between the fourth sub-section and the sixth sub-section, where 0° < α4 < 180°.

4. The semiconductor structure according to claim 3, characterized in that, The first included angle α1 is the same as the third included angle α3, and the second included angle α2 is the same as the fourth included angle α4; or, The first included angle α1, the second included angle α2, the third included angle α3 and the fourth included angle α4 are all 90°.

5. The semiconductor structure according to claim 1, characterized in that, The gate layer includes a first gate layer and a second gate layer, wherein the first gate layer covers the first channel layer between the first electrode and the second electrode; and the second gate layer covers the second channel layer between the third electrode and the fourth electrode.

6. The semiconductor structure according to claim 5, characterized in that, The semiconductor structure also includes: Spacer layers, wherein the spacer layers are located between the first electrode and the first gate layer, between the second electrode and the first gate layer, between the first channel layer and the second channel layer, between the second gate layer and the fourth electrode, and between the third electrode and the second gate layer; and / or, A protective layer that at least covers the surfaces of the gate layer, the first channel layer, the second channel layer, the second electrode, and the fourth electrode.

7. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A substrate is provided on which a first electrode, a third electrode, and a first dielectric layer are formed. The first dielectric layer includes a first sidewall and a second sidewall disposed opposite to each other and extending upward in a direction protruding from the plane of the substrate, and a first surface adjacent to the first sidewall and a second surface adjacent to the second sidewall. A channel material layer is formed covering the substrate, the first sidewall, the second sidewall and the surface of the first dielectric layer, and a conductive material layer is formed covering the surface of the channel material layer; An etching process is performed on the conductive material layer and the channel material layer, and the remaining conductive material layer constitutes the gate layer; the remaining channel material layers respectively constitute the first channel layer and the second channel layer; wherein, the first channel layer includes at least a first sub-part covering the first surface and a second sub-part covering the first sidewall, the second channel layer includes at least a third sub-part covering the second surface and a fourth sub-part covering the second sidewall, the first electrode is located on one side of the first channel layer, and the third electrode is located on one side of the second channel layer; The second and fourth electrodes are formed on the first dielectric layer.

8. The preparation method according to claim 7, characterized in that, An etching process is performed on the channel material layer and the conductive material layer, including: Remove a portion of the conductive material layer located above the first sidewall and above the second sidewall to form the gate layer; The portion of the channel material layer located between the first surface and the second surface is removed to form a first channel layer and a second channel layer in the same process step; wherein the first channel layer includes a first sub-part covering the first surface, a second sub-part covering the first sidewall, and a fifth sub-part adjacent to the first sidewall and covering the substrate surface, and the second channel layer includes a third sub-part covering the second surface, a fourth sub-part covering the second sidewall, and a sixth sub-part adjacent to the second sidewall and covering the substrate surface.

9. The preparation method according to claim 8, characterized in that, There is a first included angle α1 between the first sub-section and the second sub-section of the first channel layer, where 0° < α1 < 180°; there is a second included angle α2 between the second sub-section and the fifth sub-section, where 0° < α2 < 180°; there is a third included angle α3 between the third sub-section and the fourth sub-section of the second channel layer, where 0° < α3 < 180°; and there is a fourth included angle α4 between the fourth sub-section and the sixth sub-section, where 0° < α4 < 180°.

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